riscv 4 core integration
diff --git a/openlane/Read.me b/openlane/Read.me
index c0c9895..6842b23 100644
--- a/openlane/Read.me
+++ b/openlane/Read.me
@@ -1,3 +1,2 @@
-ycr2_mintf harden with riscduino/openlane:mpw4 (mpw5 version not able to root due to conjuestion)
-Rest of the cores & top-level are harden with riscduino/openlane:mpw5 docker
+harden with riscduino/openlane:mpw5 docker
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index 4c64993..be6ef95 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -3,6 +3,8 @@
#S
h_reset_n 000 0 2
+cpu_core_rst_n\[3\]
+cpu_core_rst_n\[2\]
cpu_core_rst_n\[1\]
cpu_core_rst_n\[0\]
cpu_intf_rst_n
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 6cb3902..39a4885 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -44,7 +44,7 @@
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $proj_dir/../../verilog/rtl//yifive/ycr2c/src/top/ycr2_top_wb.sv \
+ $proj_dir/../../verilog/rtl//yifive/ycr4c/src/top/ycr4_top_wb.sv \
$proj_dir/../../verilog/rtl/user_project_wrapper.v"
@@ -73,8 +73,9 @@
$proj_dir/../../verilog/gl/pinmux.v \
$proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \
$proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/ycr2_mintf.v \
+ $proj_dir/../../verilog/gl/ycr_intf.v \
$proj_dir/../../verilog/gl/ycr_core_top.v \
+ $proj_dir/../../verilog/gl/ycr4_iconnect.v \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
@@ -84,8 +85,9 @@
$lef_root/wb_interconnect.lef \
$lef_root/uart_i2c_usb_spi_top.lef \
$lef_root/wb_host.lef \
- $lef_root/ycr2_mintf.lef \
+ $lef_root/ycr_intf.lef \
$lef_root/ycr_core_top.lef \
+ $lef_root/ycr4_iconnect.lef \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
@@ -95,14 +97,15 @@
$gds_root/wb_interconnect.gds \
$gds_root/uart_i2c_usb_spi_top.gds \
$gds_root/wb_host.gds \
- $gds_root/ycr2_mintf.gds \
+ $gds_root/ycr_intf.gds \
$gds_root/ycr_core_top.gds \
+ $gds_root/ycr4_iconnect.gds \
$::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ]
set ::env(GLB_RT_MAXLAYER) 6
set ::env(RT_MAX_LAYER) {met5}
@@ -127,15 +130,15 @@
met2 150 150 833.1 566.54,\
met3 150 150 833.1 566.54,\
- li1 900 150 1583.1 566.54,\
- met1 900 150 1583.1 566.54,\
- met2 900 150 1583.1 566.54,\
- met3 900 150 1583.1 566.54,\
+ li1 950 150 1633.1 566.54,\
+ met1 950 150 1633.1 566.54,\
+ met2 950 150 1633.1 566.54,\
+ met3 950 150 1633.1 566.54,\
- li1 150 800 833.1 1216.54,\
- met1 150 800 833.1 1216.54,\
- met2 150 800 833.1 1216.54,\
- met3 150 800 833.1 1216.54,\
+ li1 150 650 833.1 1066.54,\
+ met1 150 650 833.1 1066.54,\
+ met2 150 650 833.1 1066.54,\
+ met3 150 650 833.1 1066.54,\
met5 0 0 2920 3520"
set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index b9d6ef1..b281fb9 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,14 +1,17 @@
-u_qspi_master 2250 700 N
-u_uart_i2c_usb_spi 2250 1400 N
-u_pinmux 2250 2300 N
+u_qspi_master 2250 650 N
+u_uart_i2c_usb_spi 2250 1350 N
+u_pinmux 2250 2150 N
-u_riscv_top.i_core_top_0 150 1500 N
-u_riscv_top.i_core_top_1 950 1500 N
-u_riscv_top.u_mintf 925 700 N
+u_riscv_top.i_core_top_0 50 1400 N
+u_riscv_top.i_core_top_1 1200 1400 FN
+u_riscv_top.i_core_top_2 50 2400 N
+u_riscv_top.i_core_top_3 1200 2400 FN
+u_riscv_top.u_connect 725 1400 N
+u_riscv_top.u_intf 950 650 N
u_icache_2kb 150 150 N
-u_dcache_2kb 900 150 N
-u_tsram0_2kb 150 800 N
+u_dcache_2kb 950 150 N
+u_tsram0_2kb 150 650 N
-u_intercon 1850 700 N
+u_intercon 1850 650 N
u_wb_host 1750 100 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 097c11b..882273d 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -70,7 +70,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 320 1800"
+set ::env(DIE_AREA) "0 0 300 1800"
# If you're going to use multiple power domains, then keep this disabled.
@@ -82,7 +82,7 @@
set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) "0.20"
-set ::env(CELL_PAD) "10"
+set ::env(CELL_PAD) "8"
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index f4bd653..565b205 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -147,7 +147,7 @@
#W
-ch_data_out\[36\] 0750 0 2
+ch_data_out\[36\] 000 0 2
ch_data_out\[35\]
ch_data_out\[34\]
ch_data_out\[33\]
@@ -172,7 +172,7 @@
ch_clk_out\[0\]
-m1_wbd_stb_i 0950 0 2
+m1_wbd_stb_i 100 0 2
m1_wbd_we_i
m1_wbd_adr_i\[31\]
m1_wbd_adr_i\[30\]
@@ -279,7 +279,7 @@
m1_wbd_err_o
m1_wbd_cyc_i
-m2_wbd_stb_i 1150 0 2
+m2_wbd_stb_i 300 0 2
m2_wbd_we_i
m2_wbd_adr_i\[31\]
m2_wbd_adr_i\[30\]
@@ -397,7 +397,7 @@
m2_wbd_err_o
m2_wbd_cyc_i
-m3_wbd_stb_i 1350 0 2
+m3_wbd_stb_i 500 0 2
m3_wbd_we_i
m3_wbd_adr_i\[31\]
m3_wbd_adr_i\[30\]
@@ -700,7 +700,7 @@
s1_wbd_ack_i
s1_wbd_cyc_o
-ch_data_in\[36\] 1400 0 2
+ch_data_in\[36\] 1500 0 2
ch_data_in\[35\]
ch_data_in\[34\]
ch_data_in\[33\]
@@ -724,7 +724,7 @@
ch_data_out\[12\]
ch_clk_out\[3\]
-s2_wbd_stb_o 1500 0 2
+s2_wbd_stb_o 1600 0 2
s2_wbd_we_o
s2_wbd_adr_o\[7\]
s2_wbd_adr_o\[6\]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index fbd79bd..d443c79 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -56,12 +56,12 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 2200"
+set ::env(DIE_AREA) "0 0 390 1900"
#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) "10"
+set ::env(CELL_PAD) "12"
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg
index 7d1ffa2..28d1e97 100644
--- a/openlane/ycr4_iconnect/pin_order.cfg
+++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -1,6 +1,1385 @@
#BUS_SORT
#MANUAL_PLACE
+#W
+sram0_clk0 000 0 2
+sram0_csb0
+sram0_web0
+sram0_addr0\[8\]
+sram0_addr0\[7\]
+sram0_addr0\[6\]
+sram0_addr0\[5\]
+sram0_addr0\[4\]
+sram0_addr0\[3\]
+sram0_addr0\[2\]
+sram0_addr0\[1\]
+sram0_addr0\[0\]
+sram0_wmask0\[3\]
+sram0_wmask0\[2\]
+sram0_wmask0\[1\]
+sram0_wmask0\[0\]
+sram0_din0\[31\]
+sram0_din0\[30\]
+sram0_din0\[29\]
+sram0_din0\[28\]
+sram0_din0\[27\]
+sram0_din0\[26\]
+sram0_din0\[25\]
+sram0_din0\[24\]
+sram0_din0\[23\]
+sram0_din0\[22\]
+sram0_din0\[21\]
+sram0_din0\[20\]
+sram0_din0\[19\]
+sram0_din0\[18\]
+sram0_din0\[17\]
+sram0_din0\[16\]
+sram0_din0\[15\]
+sram0_din0\[14\]
+sram0_din0\[13\]
+sram0_din0\[12\]
+sram0_din0\[11\]
+sram0_din0\[10\]
+sram0_din0\[9\]
+sram0_din0\[8\]
+sram0_din0\[7\]
+sram0_din0\[6\]
+sram0_din0\[5\]
+sram0_din0\[4\]
+sram0_din0\[3\]
+sram0_din0\[2\]
+sram0_din0\[1\]
+sram0_din0\[0\]
+sram0_dout0\[31\]
+sram0_dout0\[30\]
+sram0_dout0\[29\]
+sram0_dout0\[28\]
+sram0_dout0\[27\]
+sram0_dout0\[26\]
+sram0_dout0\[25\]
+sram0_dout0\[24\]
+sram0_dout0\[23\]
+sram0_dout0\[22\]
+sram0_dout0\[21\]
+sram0_dout0\[20\]
+sram0_dout0\[19\]
+sram0_dout0\[18\]
+sram0_dout0\[17\]
+sram0_dout0\[16\]
+sram0_dout0\[15\]
+sram0_dout0\[14\]
+sram0_dout0\[13\]
+sram0_dout0\[12\]
+sram0_dout0\[11\]
+sram0_dout0\[10\]
+sram0_dout0\[9\]
+sram0_dout0\[8\]
+sram0_dout0\[7\]
+sram0_dout0\[6\]
+sram0_dout0\[5\]
+sram0_dout0\[4\]
+sram0_dout0\[3\]
+sram0_dout0\[2\]
+sram0_dout0\[1\]
+sram0_dout0\[0\]
+
+
+sram0_clk1 110 0 2
+sram0_csb1
+sram0_addr1\[8\]
+sram0_addr1\[7\]
+sram0_addr1\[6\]
+sram0_addr1\[5\]
+sram0_addr1\[4\]
+sram0_addr1\[3\]
+sram0_addr1\[2\]
+sram0_addr1\[1\]
+sram0_addr1\[0\]
+sram0_dout1\[31\]
+sram0_dout1\[30\]
+sram0_dout1\[29\]
+sram0_dout1\[28\]
+sram0_dout1\[27\]
+sram0_dout1\[26\]
+sram0_dout1\[25\]
+sram0_dout1\[24\]
+sram0_dout1\[23\]
+sram0_dout1\[22\]
+sram0_dout1\[21\]
+sram0_dout1\[20\]
+sram0_dout1\[19\]
+sram0_dout1\[18\]
+sram0_dout1\[17\]
+sram0_dout1\[16\]
+sram0_dout1\[15\]
+sram0_dout1\[14\]
+sram0_dout1\[13\]
+sram0_dout1\[12\]
+sram0_dout1\[11\]
+sram0_dout1\[10\]
+sram0_dout1\[9\]
+sram0_dout1\[8\]
+sram0_dout1\[7\]
+sram0_dout1\[6\]
+sram0_dout1\[5\]
+sram0_dout1\[4\]
+sram0_dout1\[3\]
+sram0_dout1\[2\]
+sram0_dout1\[1\]
+sram0_dout1\[0\]
+
+core0_uid\[1\] 0200 00 2
+core0_uid\[0\]
+core0_imem_req_ack
+core0_imem_req
+core0_imem_cmd
+core0_imem_addr\[31\]
+core0_imem_addr\[30\]
+core0_imem_addr\[29\]
+core0_imem_addr\[28\]
+core0_imem_addr\[27\]
+core0_imem_addr\[26\]
+core0_imem_addr\[25\]
+core0_imem_addr\[24\]
+core0_imem_addr\[23\]
+core0_imem_addr\[22\]
+core0_imem_addr\[21\]
+core0_imem_addr\[20\]
+core0_imem_addr\[19\]
+core0_imem_addr\[18\]
+core0_imem_addr\[17\]
+core0_imem_addr\[16\]
+core0_imem_addr\[15\]
+core0_imem_addr\[14\]
+core0_imem_addr\[13\]
+core0_imem_addr\[12\]
+core0_imem_addr\[11\]
+core0_imem_addr\[10\]
+core0_imem_addr\[9\]
+core0_imem_addr\[8\]
+core0_imem_addr\[7\]
+core0_imem_addr\[6\]
+core0_imem_addr\[5\]
+core0_imem_addr\[4\]
+core0_imem_addr\[3\]
+core0_imem_addr\[2\]
+core0_imem_addr\[1\]
+core0_imem_addr\[0\]
+core0_imem_bl\[2\]
+core0_imem_bl\[1\]
+core0_imem_bl\[0\]
+core0_imem_rdata\[31\]
+core0_imem_rdata\[30\]
+core0_imem_rdata\[29\]
+core0_imem_rdata\[28\]
+core0_imem_rdata\[27\]
+core0_imem_rdata\[26\]
+core0_imem_rdata\[25\]
+core0_imem_rdata\[24\]
+core0_imem_rdata\[23\]
+core0_imem_rdata\[22\]
+core0_imem_rdata\[21\]
+core0_imem_rdata\[20\]
+core0_imem_rdata\[19\]
+core0_imem_rdata\[18\]
+core0_imem_rdata\[17\]
+core0_imem_rdata\[16\]
+core0_imem_rdata\[15\]
+core0_imem_rdata\[14\]
+core0_imem_rdata\[13\]
+core0_imem_rdata\[12\]
+core0_imem_rdata\[11\]
+core0_imem_rdata\[10\]
+core0_imem_rdata\[9\]
+core0_imem_rdata\[8\]
+core0_imem_rdata\[7\]
+core0_imem_rdata\[6\]
+core0_imem_rdata\[5\]
+core0_imem_rdata\[4\]
+core0_imem_rdata\[3\]
+core0_imem_rdata\[2\]
+core0_imem_rdata\[1\]
+core0_imem_rdata\[0\]
+core0_imem_resp\[1\]
+core0_imem_resp\[0\]
+
+core0_dmem_req_ack 0350 0 2
+core0_dmem_req
+core0_dmem_cmd
+core0_dmem_width\[1\]
+core0_dmem_width\[0\]
+core0_dmem_addr\[31\]
+core0_dmem_addr\[30\]
+core0_dmem_addr\[29\]
+core0_dmem_addr\[28\]
+core0_dmem_addr\[27\]
+core0_dmem_addr\[26\]
+core0_dmem_addr\[25\]
+core0_dmem_addr\[24\]
+core0_dmem_addr\[23\]
+core0_dmem_addr\[22\]
+core0_dmem_addr\[21\]
+core0_dmem_addr\[20\]
+core0_dmem_addr\[19\]
+core0_dmem_addr\[18\]
+core0_dmem_addr\[17\]
+core0_dmem_addr\[16\]
+core0_dmem_addr\[15\]
+core0_dmem_addr\[14\]
+core0_dmem_addr\[13\]
+core0_dmem_addr\[12\]
+core0_dmem_addr\[11\]
+core0_dmem_addr\[10\]
+core0_dmem_addr\[9\]
+core0_dmem_addr\[8\]
+core0_dmem_addr\[7\]
+core0_dmem_addr\[6\]
+core0_dmem_addr\[5\]
+core0_dmem_addr\[4\]
+core0_dmem_addr\[3\]
+core0_dmem_addr\[2\]
+core0_dmem_addr\[1\]
+core0_dmem_addr\[0\]
+core0_dmem_wdata\[31\]
+core0_dmem_wdata\[30\]
+core0_dmem_wdata\[29\]
+core0_dmem_wdata\[28\]
+core0_dmem_wdata\[27\]
+core0_dmem_wdata\[26\]
+core0_dmem_wdata\[25\]
+core0_dmem_wdata\[24\]
+core0_dmem_wdata\[23\]
+core0_dmem_wdata\[22\]
+core0_dmem_wdata\[21\]
+core0_dmem_wdata\[20\]
+core0_dmem_wdata\[19\]
+core0_dmem_wdata\[18\]
+core0_dmem_wdata\[17\]
+core0_dmem_wdata\[16\]
+core0_dmem_wdata\[15\]
+core0_dmem_wdata\[14\]
+core0_dmem_wdata\[13\]
+core0_dmem_wdata\[12\]
+core0_dmem_wdata\[11\]
+core0_dmem_wdata\[10\]
+core0_dmem_wdata\[9\]
+core0_dmem_wdata\[8\]
+core0_dmem_wdata\[7\]
+core0_dmem_wdata\[6\]
+core0_dmem_wdata\[5\]
+core0_dmem_wdata\[4\]
+core0_dmem_wdata\[3\]
+core0_dmem_wdata\[2\]
+core0_dmem_wdata\[1\]
+core0_dmem_wdata\[0\]
+core0_dmem_rdata\[31\]
+core0_dmem_rdata\[30\]
+core0_dmem_rdata\[29\]
+core0_dmem_rdata\[28\]
+core0_dmem_rdata\[27\]
+core0_dmem_rdata\[26\]
+core0_dmem_rdata\[25\]
+core0_dmem_rdata\[24\]
+core0_dmem_rdata\[23\]
+core0_dmem_rdata\[22\]
+core0_dmem_rdata\[21\]
+core0_dmem_rdata\[20\]
+core0_dmem_rdata\[19\]
+core0_dmem_rdata\[18\]
+core0_dmem_rdata\[17\]
+core0_dmem_rdata\[16\]
+core0_dmem_rdata\[15\]
+core0_dmem_rdata\[14\]
+core0_dmem_rdata\[13\]
+core0_dmem_rdata\[12\]
+core0_dmem_rdata\[11\]
+core0_dmem_rdata\[10\]
+core0_dmem_rdata\[9\]
+core0_dmem_rdata\[8\]
+core0_dmem_rdata\[7\]
+core0_dmem_rdata\[6\]
+core0_dmem_rdata\[5\]
+core0_dmem_rdata\[4\]
+core0_dmem_rdata\[3\]
+core0_dmem_rdata\[2\]
+core0_dmem_rdata\[1\]
+core0_dmem_rdata\[0\]
+core0_dmem_resp\[1\]
+core0_dmem_resp\[0\]
+
+core0_debug\[48\] 0500 0 2
+core0_debug\[47\]
+core0_debug\[46\]
+core0_debug\[45\]
+core0_debug\[44\]
+core0_debug\[43\]
+core0_debug\[42\]
+core0_debug\[41\]
+core0_debug\[40\]
+core0_debug\[39\]
+core0_debug\[38\]
+core0_debug\[37\]
+core0_debug\[36\]
+core0_debug\[35\]
+core0_debug\[34\]
+core0_debug\[33\]
+core0_debug\[32\]
+core0_debug\[31\]
+core0_debug\[30\]
+core0_debug\[29\]
+core0_debug\[28\]
+core0_debug\[27\]
+core0_debug\[26\]
+core0_debug\[25\]
+core0_debug\[24\]
+core0_debug\[23\]
+core0_debug\[22\]
+core0_debug\[21\]
+core0_debug\[20\]
+core0_debug\[19\]
+core0_debug\[18\]
+core0_debug\[17\]
+core0_debug\[16\]
+core0_debug\[15\]
+core0_debug\[14\]
+core0_debug\[13\]
+core0_debug\[12\]
+core0_debug\[11\]
+core0_debug\[10\]
+core0_debug\[9\]
+core0_debug\[8\]
+core0_debug\[7\]
+core0_debug\[6\]
+core0_debug\[5\]
+core0_debug\[4\]
+core0_debug\[3\]
+core0_debug\[2\]
+core0_debug\[1\]
+core0_debug\[0\]
+
+core0_timer_irq 0600 0 2
+core0_timer_val\[63\]
+core0_timer_val\[62\]
+core0_timer_val\[61\]
+core0_timer_val\[60\]
+core0_timer_val\[59\]
+core0_timer_val\[58\]
+core0_timer_val\[57\]
+core0_timer_val\[56\]
+core0_timer_val\[55\]
+core0_timer_val\[54\]
+core0_timer_val\[53\]
+core0_timer_val\[52\]
+core0_timer_val\[51\]
+core0_timer_val\[50\]
+core0_timer_val\[49\]
+core0_timer_val\[48\]
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+
+core0_irq_lines\[15\]
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+
+core2_uid\[1\] 1200 00 2
+core2_uid\[0\]
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+core2_imem_req
+core2_imem_cmd
+core2_imem_addr\[31\]
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+core2_dmem_req_ack 1350 0 2
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+core2_debug\[0\]
+
+core2_timer_irq 1600 0 2
+core2_timer_val\[63\]
+core2_timer_val\[62\]
+core2_timer_val\[61\]
+core2_timer_val\[60\]
+core2_timer_val\[59\]
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+
+core2_irq_lines\[15\]
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+
+#E
+core1_uid\[1\] 0200 00 2
+core1_uid\[0\]
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+core1_imem_req
+core1_imem_cmd
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+
+core1_dmem_req_ack 0350 0 2
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+core1_debug\[48\] 0500 0 2
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+
+core1_timer_irq 600 0 2
+core1_timer_val\[63\]
+core1_timer_val\[62\]
+core1_timer_val\[61\]
+core1_timer_val\[60\]
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+core1_timer_val\[15\]
+core1_timer_val\[14\]
+core1_timer_val\[13\]
+core1_timer_val\[12\]
+core1_timer_val\[11\]
+core1_timer_val\[10\]
+core1_timer_val\[9\]
+core1_timer_val\[8\]
+core1_timer_val\[7\]
+core1_timer_val\[6\]
+core1_timer_val\[5\]
+core1_timer_val\[4\]
+core1_timer_val\[3\]
+core1_timer_val\[2\]
+core1_timer_val\[1\]
+core1_timer_val\[0\]
+core1_irq_lines\[15\]
+core1_irq_lines\[14\]
+core1_irq_lines\[13\]
+core1_irq_lines\[12\]
+core1_irq_lines\[11\]
+core1_irq_lines\[10\]
+core1_irq_lines\[9\]
+core1_irq_lines\[8\]
+core1_irq_lines\[7\]
+core1_irq_lines\[6\]
+core1_irq_lines\[5\]
+core1_irq_lines\[4\]
+core1_irq_lines\[3\]
+core1_irq_lines\[2\]
+core1_irq_lines\[1\]
+core1_irq_lines\[0\]
+core1_irq_soft
+
+core3_uid\[1\] 1200 00 2
+core3_uid\[0\]
+core3_imem_req_ack
+core3_imem_req
+core3_imem_cmd
+core3_imem_addr\[31\]
+core3_imem_addr\[30\]
+core3_imem_addr\[29\]
+core3_imem_addr\[28\]
+core3_imem_addr\[27\]
+core3_imem_addr\[26\]
+core3_imem_addr\[25\]
+core3_imem_addr\[24\]
+core3_imem_addr\[23\]
+core3_imem_addr\[22\]
+core3_imem_addr\[21\]
+core3_imem_addr\[20\]
+core3_imem_addr\[19\]
+core3_imem_addr\[18\]
+core3_imem_addr\[17\]
+core3_imem_addr\[16\]
+core3_imem_addr\[15\]
+core3_imem_addr\[14\]
+core3_imem_addr\[13\]
+core3_imem_addr\[12\]
+core3_imem_addr\[11\]
+core3_imem_addr\[10\]
+core3_imem_addr\[9\]
+core3_imem_addr\[8\]
+core3_imem_addr\[7\]
+core3_imem_addr\[6\]
+core3_imem_addr\[5\]
+core3_imem_addr\[4\]
+core3_imem_addr\[3\]
+core3_imem_addr\[2\]
+core3_imem_addr\[1\]
+core3_imem_addr\[0\]
+core3_imem_bl\[2\]
+core3_imem_bl\[1\]
+core3_imem_bl\[0\]
+core3_imem_rdata\[31\]
+core3_imem_rdata\[30\]
+core3_imem_rdata\[29\]
+core3_imem_rdata\[28\]
+core3_imem_rdata\[27\]
+core3_imem_rdata\[26\]
+core3_imem_rdata\[25\]
+core3_imem_rdata\[24\]
+core3_imem_rdata\[23\]
+core3_imem_rdata\[22\]
+core3_imem_rdata\[21\]
+core3_imem_rdata\[20\]
+core3_imem_rdata\[19\]
+core3_imem_rdata\[18\]
+core3_imem_rdata\[17\]
+core3_imem_rdata\[16\]
+core3_imem_rdata\[15\]
+core3_imem_rdata\[14\]
+core3_imem_rdata\[13\]
+core3_imem_rdata\[12\]
+core3_imem_rdata\[11\]
+core3_imem_rdata\[10\]
+core3_imem_rdata\[9\]
+core3_imem_rdata\[8\]
+core3_imem_rdata\[7\]
+core3_imem_rdata\[6\]
+core3_imem_rdata\[5\]
+core3_imem_rdata\[4\]
+core3_imem_rdata\[3\]
+core3_imem_rdata\[2\]
+core3_imem_rdata\[1\]
+core3_imem_rdata\[0\]
+core3_imem_resp\[1\]
+core3_imem_resp\[0\]
+
+core3_dmem_req_ack 1350 0 2
+core3_dmem_req
+core3_dmem_cmd
+core3_dmem_width\[1\]
+core3_dmem_width\[0\]
+core3_dmem_addr\[31\]
+core3_dmem_addr\[30\]
+core3_dmem_addr\[29\]
+core3_dmem_addr\[28\]
+core3_dmem_addr\[27\]
+core3_dmem_addr\[26\]
+core3_dmem_addr\[25\]
+core3_dmem_addr\[24\]
+core3_dmem_addr\[23\]
+core3_dmem_addr\[22\]
+core3_dmem_addr\[21\]
+core3_dmem_addr\[20\]
+core3_dmem_addr\[19\]
+core3_dmem_addr\[18\]
+core3_dmem_addr\[17\]
+core3_dmem_addr\[16\]
+core3_dmem_addr\[15\]
+core3_dmem_addr\[14\]
+core3_dmem_addr\[13\]
+core3_dmem_addr\[12\]
+core3_dmem_addr\[11\]
+core3_dmem_addr\[10\]
+core3_dmem_addr\[9\]
+core3_dmem_addr\[8\]
+core3_dmem_addr\[7\]
+core3_dmem_addr\[6\]
+core3_dmem_addr\[5\]
+core3_dmem_addr\[4\]
+core3_dmem_addr\[3\]
+core3_dmem_addr\[2\]
+core3_dmem_addr\[1\]
+core3_dmem_addr\[0\]
+core3_dmem_wdata\[31\]
+core3_dmem_wdata\[30\]
+core3_dmem_wdata\[29\]
+core3_dmem_wdata\[28\]
+core3_dmem_wdata\[27\]
+core3_dmem_wdata\[26\]
+core3_dmem_wdata\[25\]
+core3_dmem_wdata\[24\]
+core3_dmem_wdata\[23\]
+core3_dmem_wdata\[22\]
+core3_dmem_wdata\[21\]
+core3_dmem_wdata\[20\]
+core3_dmem_wdata\[19\]
+core3_dmem_wdata\[18\]
+core3_dmem_wdata\[17\]
+core3_dmem_wdata\[16\]
+core3_dmem_wdata\[15\]
+core3_dmem_wdata\[14\]
+core3_dmem_wdata\[13\]
+core3_dmem_wdata\[12\]
+core3_dmem_wdata\[11\]
+core3_dmem_wdata\[10\]
+core3_dmem_wdata\[9\]
+core3_dmem_wdata\[8\]
+core3_dmem_wdata\[7\]
+core3_dmem_wdata\[6\]
+core3_dmem_wdata\[5\]
+core3_dmem_wdata\[4\]
+core3_dmem_wdata\[3\]
+core3_dmem_wdata\[2\]
+core3_dmem_wdata\[1\]
+core3_dmem_wdata\[0\]
+core3_dmem_rdata\[31\]
+core3_dmem_rdata\[30\]
+core3_dmem_rdata\[29\]
+core3_dmem_rdata\[28\]
+core3_dmem_rdata\[27\]
+core3_dmem_rdata\[26\]
+core3_dmem_rdata\[25\]
+core3_dmem_rdata\[24\]
+core3_dmem_rdata\[23\]
+core3_dmem_rdata\[22\]
+core3_dmem_rdata\[21\]
+core3_dmem_rdata\[20\]
+core3_dmem_rdata\[19\]
+core3_dmem_rdata\[18\]
+core3_dmem_rdata\[17\]
+core3_dmem_rdata\[16\]
+core3_dmem_rdata\[15\]
+core3_dmem_rdata\[14\]
+core3_dmem_rdata\[13\]
+core3_dmem_rdata\[12\]
+core3_dmem_rdata\[11\]
+core3_dmem_rdata\[10\]
+core3_dmem_rdata\[9\]
+core3_dmem_rdata\[8\]
+core3_dmem_rdata\[7\]
+core3_dmem_rdata\[6\]
+core3_dmem_rdata\[5\]
+core3_dmem_rdata\[4\]
+core3_dmem_rdata\[3\]
+core3_dmem_rdata\[2\]
+core3_dmem_rdata\[1\]
+core3_dmem_rdata\[0\]
+core3_dmem_resp\[1\]
+core3_dmem_resp\[0\]
+
+core3_debug\[48\] 1500 0 2
+core3_debug\[47\]
+core3_debug\[46\]
+core3_debug\[45\]
+core3_debug\[44\]
+core3_debug\[43\]
+core3_debug\[42\]
+core3_debug\[41\]
+core3_debug\[40\]
+core3_debug\[39\]
+core3_debug\[38\]
+core3_debug\[37\]
+core3_debug\[36\]
+core3_debug\[35\]
+core3_debug\[34\]
+core3_debug\[33\]
+core3_debug\[32\]
+core3_debug\[31\]
+core3_debug\[30\]
+core3_debug\[29\]
+core3_debug\[28\]
+core3_debug\[27\]
+core3_debug\[26\]
+core3_debug\[25\]
+core3_debug\[24\]
+core3_debug\[23\]
+core3_debug\[22\]
+core3_debug\[21\]
+core3_debug\[20\]
+core3_debug\[19\]
+core3_debug\[18\]
+core3_debug\[17\]
+core3_debug\[16\]
+core3_debug\[15\]
+core3_debug\[14\]
+core3_debug\[13\]
+core3_debug\[12\]
+core3_debug\[11\]
+core3_debug\[10\]
+core3_debug\[9\]
+core3_debug\[8\]
+core3_debug\[7\]
+core3_debug\[6\]
+core3_debug\[5\]
+core3_debug\[4\]
+core3_debug\[3\]
+core3_debug\[2\]
+core3_debug\[1\]
+core3_debug\[0\]
+
+core3_timer_irq 1600 0 2
+core3_timer_val\[63\]
+core3_timer_val\[62\]
+core3_timer_val\[61\]
+core3_timer_val\[60\]
+core3_timer_val\[59\]
+core3_timer_val\[58\]
+core3_timer_val\[57\]
+core3_timer_val\[56\]
+core3_timer_val\[55\]
+core3_timer_val\[54\]
+core3_timer_val\[53\]
+core3_timer_val\[52\]
+core3_timer_val\[51\]
+core3_timer_val\[50\]
+core3_timer_val\[49\]
+core3_timer_val\[48\]
+core3_timer_val\[47\]
+core3_timer_val\[46\]
+core3_timer_val\[45\]
+core3_timer_val\[44\]
+core3_timer_val\[43\]
+core3_timer_val\[42\]
+core3_timer_val\[41\]
+core3_timer_val\[40\]
+core3_timer_val\[39\]
+core3_timer_val\[38\]
+core3_timer_val\[37\]
+core3_timer_val\[36\]
+core3_timer_val\[35\]
+core3_timer_val\[34\]
+core3_timer_val\[33\]
+core3_timer_val\[32\]
+core3_timer_val\[31\]
+core3_timer_val\[30\]
+core3_timer_val\[29\]
+core3_timer_val\[28\]
+core3_timer_val\[27\]
+core3_timer_val\[26\]
+core3_timer_val\[25\]
+core3_timer_val\[24\]
+core3_timer_val\[23\]
+core3_timer_val\[22\]
+core3_timer_val\[21\]
+core3_timer_val\[20\]
+core3_timer_val\[19\]
+core3_timer_val\[18\]
+core3_timer_val\[17\]
+core3_timer_val\[16\]
+core3_timer_val\[15\]
+core3_timer_val\[14\]
+core3_timer_val\[13\]
+core3_timer_val\[12\]
+core3_timer_val\[11\]
+core3_timer_val\[10\]
+core3_timer_val\[9\]
+core3_timer_val\[8\]
+core3_timer_val\[7\]
+core3_timer_val\[6\]
+core3_timer_val\[5\]
+core3_timer_val\[4\]
+core3_timer_val\[3\]
+core3_timer_val\[2\]
+core3_timer_val\[1\]
+core3_timer_val\[0\]
+
+core3_irq_lines\[15\]
+core3_irq_lines\[14\]
+core3_irq_lines\[13\]
+core3_irq_lines\[12\]
+core3_irq_lines\[11\]
+core3_irq_lines\[10\]
+core3_irq_lines\[9\]
+core3_irq_lines\[8\]
+core3_irq_lines\[7\]
+core3_irq_lines\[6\]
+core3_irq_lines\[5\]
+core3_irq_lines\[4\]
+core3_irq_lines\[3\]
+core3_irq_lines\[2\]
+core3_irq_lines\[1\]
+core3_irq_lines\[0\]
+core3_irq_soft
+
#S
core_icache_req_ack 000 0 2
core_icache_req
@@ -286,13 +1665,12 @@
core_dmem_resp\[1\]
core_dmem_resp\[0\]
-cfg_icache_pfet_dis 0300 0 2
+cfg_icache_pfet_dis
cfg_icache_ntag_pfet_dis
cfg_dcache_pfet_dis
cfg_dcache_force_flush
-#E
-core_debug_sel\[1\] 000 0 2
+core_debug_sel\[1\] 300 0 2
core_debug_sel\[0\]
riscv_debug\[63\]
riscv_debug\[62\]
@@ -359,1316 +1737,25 @@
riscv_debug\[1\]
riscv_debug\[0\]
-core_clk 150 0 2
+core_irq_lines_i\[15\]
+core_irq_lines_i\[14\]
+core_irq_lines_i\[13\]
+core_irq_lines_i\[12\]
+core_irq_lines_i\[11\]
+core_irq_lines_i\[10\]
+core_irq_lines_i\[9\]
+core_irq_lines_i\[8\]
+core_irq_lines_i\[7\]
+core_irq_lines_i\[6\]
+core_irq_lines_i\[5\]
+core_irq_lines_i\[4\]
+core_irq_lines_i\[3\]
+core_irq_lines_i\[2\]
+core_irq_lines_i\[1\]
+core_irq_lines_i\[0\]
+core_irq_soft_i
+
+core_clk
rtc_clk
pwrup_rst_n
cpu_intf_rst_n
-
-core0_uid\[1\] 0200 00 2
-core0_uid\[0\]
-core0_imem_req_ack
-core0_imem_req
-core0_imem_cmd
-core0_imem_addr\[31\]
-core0_imem_addr\[30\]
-core0_imem_addr\[29\]
-core0_imem_addr\[28\]
-core0_imem_addr\[27\]
-core0_imem_addr\[26\]
-core0_imem_addr\[25\]
-core0_imem_addr\[24\]
-core0_imem_addr\[23\]
-core0_imem_addr\[22\]
-core0_imem_addr\[21\]
-core0_imem_addr\[20\]
-core0_imem_addr\[19\]
-core0_imem_addr\[18\]
-core0_imem_addr\[17\]
-core0_imem_addr\[16\]
-core0_imem_addr\[15\]
-core0_imem_addr\[14\]
-core0_imem_addr\[13\]
-core0_imem_addr\[12\]
-core0_imem_addr\[11\]
-core0_imem_addr\[10\]
-core0_imem_addr\[9\]
-core0_imem_addr\[8\]
-core0_imem_addr\[7\]
-core0_imem_addr\[6\]
-core0_imem_addr\[5\]
-core0_imem_addr\[4\]
-core0_imem_addr\[3\]
-core0_imem_addr\[2\]
-core0_imem_addr\[1\]
-core0_imem_addr\[0\]
-core0_imem_bl\[2\]
-core0_imem_bl\[1\]
-core0_imem_bl\[0\]
-core0_imem_rdata\[31\]
-core0_imem_rdata\[30\]
-core0_imem_rdata\[29\]
-core0_imem_rdata\[28\]
-core0_imem_rdata\[27\]
-core0_imem_rdata\[26\]
-core0_imem_rdata\[25\]
-core0_imem_rdata\[24\]
-core0_imem_rdata\[23\]
-core0_imem_rdata\[22\]
-core0_imem_rdata\[21\]
-core0_imem_rdata\[20\]
-core0_imem_rdata\[19\]
-core0_imem_rdata\[18\]
-core0_imem_rdata\[17\]
-core0_imem_rdata\[16\]
-core0_imem_rdata\[15\]
-core0_imem_rdata\[14\]
-core0_imem_rdata\[13\]
-core0_imem_rdata\[12\]
-core0_imem_rdata\[11\]
-core0_imem_rdata\[10\]
-core0_imem_rdata\[9\]
-core0_imem_rdata\[8\]
-core0_imem_rdata\[7\]
-core0_imem_rdata\[6\]
-core0_imem_rdata\[5\]
-core0_imem_rdata\[4\]
-core0_imem_rdata\[3\]
-core0_imem_rdata\[2\]
-core0_imem_rdata\[1\]
-core0_imem_rdata\[0\]
-core0_imem_resp\[1\]
-core0_imem_resp\[0\]
-
-core0_dmem_req_ack 0400 0 2
-core0_dmem_req
-core0_dmem_cmd
-core0_dmem_width\[1\]
-core0_dmem_width\[0\]
-core0_dmem_addr\[31\]
-core0_dmem_addr\[30\]
-core0_dmem_addr\[29\]
-core0_dmem_addr\[28\]
-core0_dmem_addr\[27\]
-core0_dmem_addr\[26\]
-core0_dmem_addr\[25\]
-core0_dmem_addr\[24\]
-core0_dmem_addr\[23\]
-core0_dmem_addr\[22\]
-core0_dmem_addr\[21\]
-core0_dmem_addr\[20\]
-core0_dmem_addr\[19\]
-core0_dmem_addr\[18\]
-core0_dmem_addr\[17\]
-core0_dmem_addr\[16\]
-core0_dmem_addr\[15\]
-core0_dmem_addr\[14\]
-core0_dmem_addr\[13\]
-core0_dmem_addr\[12\]
-core0_dmem_addr\[11\]
-core0_dmem_addr\[10\]
-core0_dmem_addr\[9\]
-core0_dmem_addr\[8\]
-core0_dmem_addr\[7\]
-core0_dmem_addr\[6\]
-core0_dmem_addr\[5\]
-core0_dmem_addr\[4\]
-core0_dmem_addr\[3\]
-core0_dmem_addr\[2\]
-core0_dmem_addr\[1\]
-core0_dmem_addr\[0\]
-core0_dmem_wdata\[31\]
-core0_dmem_wdata\[30\]
-core0_dmem_wdata\[29\]
-core0_dmem_wdata\[28\]
-core0_dmem_wdata\[27\]
-core0_dmem_wdata\[26\]
-core0_dmem_wdata\[25\]
-core0_dmem_wdata\[24\]
-core0_dmem_wdata\[23\]
-core0_dmem_wdata\[22\]
-core0_dmem_wdata\[21\]
-core0_dmem_wdata\[20\]
-core0_dmem_wdata\[19\]
-core0_dmem_wdata\[18\]
-core0_dmem_wdata\[17\]
-core0_dmem_wdata\[16\]
-core0_dmem_wdata\[15\]
-core0_dmem_wdata\[14\]
-core0_dmem_wdata\[13\]
-core0_dmem_wdata\[12\]
-core0_dmem_wdata\[11\]
-core0_dmem_wdata\[10\]
-core0_dmem_wdata\[9\]
-core0_dmem_wdata\[8\]
-core0_dmem_wdata\[7\]
-core0_dmem_wdata\[6\]
-core0_dmem_wdata\[5\]
-core0_dmem_wdata\[4\]
-core0_dmem_wdata\[3\]
-core0_dmem_wdata\[2\]
-core0_dmem_wdata\[1\]
-core0_dmem_wdata\[0\]
-core0_dmem_rdata\[31\]
-core0_dmem_rdata\[30\]
-core0_dmem_rdata\[29\]
-core0_dmem_rdata\[28\]
-core0_dmem_rdata\[27\]
-core0_dmem_rdata\[26\]
-core0_dmem_rdata\[25\]
-core0_dmem_rdata\[24\]
-core0_dmem_rdata\[23\]
-core0_dmem_rdata\[22\]
-core0_dmem_rdata\[21\]
-core0_dmem_rdata\[20\]
-core0_dmem_rdata\[19\]
-core0_dmem_rdata\[18\]
-core0_dmem_rdata\[17\]
-core0_dmem_rdata\[16\]
-core0_dmem_rdata\[15\]
-core0_dmem_rdata\[14\]
-core0_dmem_rdata\[13\]
-core0_dmem_rdata\[12\]
-core0_dmem_rdata\[11\]
-core0_dmem_rdata\[10\]
-core0_dmem_rdata\[9\]
-core0_dmem_rdata\[8\]
-core0_dmem_rdata\[7\]
-core0_dmem_rdata\[6\]
-core0_dmem_rdata\[5\]
-core0_dmem_rdata\[4\]
-core0_dmem_rdata\[3\]
-core0_dmem_rdata\[2\]
-core0_dmem_rdata\[1\]
-core0_dmem_rdata\[0\]
-core0_dmem_resp\[1\]
-core0_dmem_resp\[0\]
-
-core0_debug\[48\] 0600 0 2
-core0_debug\[47\]
-core0_debug\[46\]
-core0_debug\[45\]
-core0_debug\[44\]
-core0_debug\[43\]
-core0_debug\[42\]
-core0_debug\[41\]
-core0_debug\[40\]
-core0_debug\[39\]
-core0_debug\[38\]
-core0_debug\[37\]
-core0_debug\[36\]
-core0_debug\[35\]
-core0_debug\[34\]
-core0_debug\[33\]
-core0_debug\[32\]
-core0_debug\[31\]
-core0_debug\[30\]
-core0_debug\[29\]
-core0_debug\[28\]
-core0_debug\[27\]
-core0_debug\[26\]
-core0_debug\[25\]
-core0_debug\[24\]
-core0_debug\[23\]
-core0_debug\[22\]
-core0_debug\[21\]
-core0_debug\[20\]
-core0_debug\[19\]
-core0_debug\[18\]
-core0_debug\[17\]
-core0_debug\[16\]
-core0_debug\[15\]
-core0_debug\[14\]
-core0_debug\[13\]
-core0_debug\[12\]
-core0_debug\[11\]
-core0_debug\[10\]
-core0_debug\[9\]
-core0_debug\[8\]
-core0_debug\[7\]
-core0_debug\[6\]
-core0_debug\[5\]
-core0_debug\[4\]
-core0_debug\[3\]
-core0_debug\[2\]
-core0_debug\[1\]
-core0_debug\[0\]
-
-core0_timer_irq
-core0_timer_val\[63\]
-core0_timer_val\[62\]
-core0_timer_val\[61\]
-core0_timer_val\[60\]
-core0_timer_val\[59\]
-core0_timer_val\[58\]
-core0_timer_val\[57\]
-core0_timer_val\[56\]
-core0_timer_val\[55\]
-core0_timer_val\[54\]
-core0_timer_val\[53\]
-core0_timer_val\[52\]
-core0_timer_val\[51\]
-core0_timer_val\[50\]
-core0_timer_val\[49\]
-core0_timer_val\[48\]
-core0_timer_val\[47\]
-core0_timer_val\[46\]
-core0_timer_val\[45\]
-core0_timer_val\[44\]
-core0_timer_val\[43\]
-core0_timer_val\[42\]
-core0_timer_val\[41\]
-core0_timer_val\[40\]
-core0_timer_val\[39\]
-core0_timer_val\[38\]
-core0_timer_val\[37\]
-core0_timer_val\[36\]
-core0_timer_val\[35\]
-core0_timer_val\[34\]
-core0_timer_val\[33\]
-core0_timer_val\[32\]
-core0_timer_val\[31\]
-core0_timer_val\[30\]
-core0_timer_val\[29\]
-core0_timer_val\[28\]
-core0_timer_val\[27\]
-core0_timer_val\[26\]
-core0_timer_val\[25\]
-core0_timer_val\[24\]
-core0_timer_val\[23\]
-core0_timer_val\[22\]
-core0_timer_val\[21\]
-core0_timer_val\[20\]
-core0_timer_val\[19\]
-core0_timer_val\[18\]
-core0_timer_val\[17\]
-core0_timer_val\[16\]
-core0_timer_val\[15\]
-core0_timer_val\[14\]
-core0_timer_val\[13\]
-core0_timer_val\[12\]
-core0_timer_val\[11\]
-core0_timer_val\[10\]
-core0_timer_val\[9\]
-core0_timer_val\[8\]
-core0_timer_val\[7\]
-core0_timer_val\[6\]
-core0_timer_val\[5\]
-core0_timer_val\[4\]
-core0_timer_val\[3\]
-core0_timer_val\[2\]
-core0_timer_val\[1\]
-core0_timer_val\[0\]
-
-core1_uid\[1\] 1200 00 2
-core1_uid\[0\]
-core1_imem_req_ack
-core1_imem_req
-core1_imem_cmd
-core1_imem_addr\[31\]
-core1_imem_addr\[30\]
-core1_imem_addr\[29\]
-core1_imem_addr\[28\]
-core1_imem_addr\[27\]
-core1_imem_addr\[26\]
-core1_imem_addr\[25\]
-core1_imem_addr\[24\]
-core1_imem_addr\[23\]
-core1_imem_addr\[22\]
-core1_imem_addr\[21\]
-core1_imem_addr\[20\]
-core1_imem_addr\[19\]
-core1_imem_addr\[18\]
-core1_imem_addr\[17\]
-core1_imem_addr\[16\]
-core1_imem_addr\[15\]
-core1_imem_addr\[14\]
-core1_imem_addr\[13\]
-core1_imem_addr\[12\]
-core1_imem_addr\[11\]
-core1_imem_addr\[10\]
-core1_imem_addr\[9\]
-core1_imem_addr\[8\]
-core1_imem_addr\[7\]
-core1_imem_addr\[6\]
-core1_imem_addr\[5\]
-core1_imem_addr\[4\]
-core1_imem_addr\[3\]
-core1_imem_addr\[2\]
-core1_imem_addr\[1\]
-core1_imem_addr\[0\]
-core1_imem_bl\[2\]
-core1_imem_bl\[1\]
-core1_imem_bl\[0\]
-core1_imem_rdata\[31\]
-core1_imem_rdata\[30\]
-core1_imem_rdata\[29\]
-core1_imem_rdata\[28\]
-core1_imem_rdata\[27\]
-core1_imem_rdata\[26\]
-core1_imem_rdata\[25\]
-core1_imem_rdata\[24\]
-core1_imem_rdata\[23\]
-core1_imem_rdata\[22\]
-core1_imem_rdata\[21\]
-core1_imem_rdata\[20\]
-core1_imem_rdata\[19\]
-core1_imem_rdata\[18\]
-core1_imem_rdata\[17\]
-core1_imem_rdata\[16\]
-core1_imem_rdata\[15\]
-core1_imem_rdata\[14\]
-core1_imem_rdata\[13\]
-core1_imem_rdata\[12\]
-core1_imem_rdata\[11\]
-core1_imem_rdata\[10\]
-core1_imem_rdata\[9\]
-core1_imem_rdata\[8\]
-core1_imem_rdata\[7\]
-core1_imem_rdata\[6\]
-core1_imem_rdata\[5\]
-core1_imem_rdata\[4\]
-core1_imem_rdata\[3\]
-core1_imem_rdata\[2\]
-core1_imem_rdata\[1\]
-core1_imem_rdata\[0\]
-core1_imem_resp\[1\]
-core1_imem_resp\[0\]
-
-core1_dmem_req_ack 1400 0 2
-core1_dmem_req
-core1_dmem_cmd
-core1_dmem_width\[1\]
-core1_dmem_width\[0\]
-core1_dmem_addr\[31\]
-core1_dmem_addr\[30\]
-core1_dmem_addr\[29\]
-core1_dmem_addr\[28\]
-core1_dmem_addr\[27\]
-core1_dmem_addr\[26\]
-core1_dmem_addr\[25\]
-core1_dmem_addr\[24\]
-core1_dmem_addr\[23\]
-core1_dmem_addr\[22\]
-core1_dmem_addr\[21\]
-core1_dmem_addr\[20\]
-core1_dmem_addr\[19\]
-core1_dmem_addr\[18\]
-core1_dmem_addr\[17\]
-core1_dmem_addr\[16\]
-core1_dmem_addr\[15\]
-core1_dmem_addr\[14\]
-core1_dmem_addr\[13\]
-core1_dmem_addr\[12\]
-core1_dmem_addr\[11\]
-core1_dmem_addr\[10\]
-core1_dmem_addr\[9\]
-core1_dmem_addr\[8\]
-core1_dmem_addr\[7\]
-core1_dmem_addr\[6\]
-core1_dmem_addr\[5\]
-core1_dmem_addr\[4\]
-core1_dmem_addr\[3\]
-core1_dmem_addr\[2\]
-core1_dmem_addr\[1\]
-core1_dmem_addr\[0\]
-core1_dmem_wdata\[31\]
-core1_dmem_wdata\[30\]
-core1_dmem_wdata\[29\]
-core1_dmem_wdata\[28\]
-core1_dmem_wdata\[27\]
-core1_dmem_wdata\[26\]
-core1_dmem_wdata\[25\]
-core1_dmem_wdata\[24\]
-core1_dmem_wdata\[23\]
-core1_dmem_wdata\[22\]
-core1_dmem_wdata\[21\]
-core1_dmem_wdata\[20\]
-core1_dmem_wdata\[19\]
-core1_dmem_wdata\[18\]
-core1_dmem_wdata\[17\]
-core1_dmem_wdata\[16\]
-core1_dmem_wdata\[15\]
-core1_dmem_wdata\[14\]
-core1_dmem_wdata\[13\]
-core1_dmem_wdata\[12\]
-core1_dmem_wdata\[11\]
-core1_dmem_wdata\[10\]
-core1_dmem_wdata\[9\]
-core1_dmem_wdata\[8\]
-core1_dmem_wdata\[7\]
-core1_dmem_wdata\[6\]
-core1_dmem_wdata\[5\]
-core1_dmem_wdata\[4\]
-core1_dmem_wdata\[3\]
-core1_dmem_wdata\[2\]
-core1_dmem_wdata\[1\]
-core1_dmem_wdata\[0\]
-core1_dmem_rdata\[31\]
-core1_dmem_rdata\[30\]
-core1_dmem_rdata\[29\]
-core1_dmem_rdata\[28\]
-core1_dmem_rdata\[27\]
-core1_dmem_rdata\[26\]
-core1_dmem_rdata\[25\]
-core1_dmem_rdata\[24\]
-core1_dmem_rdata\[23\]
-core1_dmem_rdata\[22\]
-core1_dmem_rdata\[21\]
-core1_dmem_rdata\[20\]
-core1_dmem_rdata\[19\]
-core1_dmem_rdata\[18\]
-core1_dmem_rdata\[17\]
-core1_dmem_rdata\[16\]
-core1_dmem_rdata\[15\]
-core1_dmem_rdata\[14\]
-core1_dmem_rdata\[13\]
-core1_dmem_rdata\[12\]
-core1_dmem_rdata\[11\]
-core1_dmem_rdata\[10\]
-core1_dmem_rdata\[9\]
-core1_dmem_rdata\[8\]
-core1_dmem_rdata\[7\]
-core1_dmem_rdata\[6\]
-core1_dmem_rdata\[5\]
-core1_dmem_rdata\[4\]
-core1_dmem_rdata\[3\]
-core1_dmem_rdata\[2\]
-core1_dmem_rdata\[1\]
-core1_dmem_rdata\[0\]
-core1_dmem_resp\[1\]
-core1_dmem_resp\[0\]
-
-core1_debug\[48\] 1600 0 2
-core1_debug\[47\]
-core1_debug\[46\]
-core1_debug\[45\]
-core1_debug\[44\]
-core1_debug\[43\]
-core1_debug\[42\]
-core1_debug\[41\]
-core1_debug\[40\]
-core1_debug\[39\]
-core1_debug\[38\]
-core1_debug\[37\]
-core1_debug\[36\]
-core1_debug\[35\]
-core1_debug\[34\]
-core1_debug\[33\]
-core1_debug\[32\]
-core1_debug\[31\]
-core1_debug\[30\]
-core1_debug\[29\]
-core1_debug\[28\]
-core1_debug\[27\]
-core1_debug\[26\]
-core1_debug\[25\]
-core1_debug\[24\]
-core1_debug\[23\]
-core1_debug\[22\]
-core1_debug\[21\]
-core1_debug\[20\]
-core1_debug\[19\]
-core1_debug\[18\]
-core1_debug\[17\]
-core1_debug\[16\]
-core1_debug\[15\]
-core1_debug\[14\]
-core1_debug\[13\]
-core1_debug\[12\]
-core1_debug\[11\]
-core1_debug\[10\]
-core1_debug\[9\]
-core1_debug\[8\]
-core1_debug\[7\]
-core1_debug\[6\]
-core1_debug\[5\]
-core1_debug\[4\]
-core1_debug\[3\]
-core1_debug\[2\]
-core1_debug\[1\]
-core1_debug\[0\]
-
-core1_timer_irq
-core1_timer_val\[63\]
-core1_timer_val\[62\]
-core1_timer_val\[61\]
-core1_timer_val\[60\]
-core1_timer_val\[59\]
-core1_timer_val\[58\]
-core1_timer_val\[57\]
-core1_timer_val\[56\]
-core1_timer_val\[55\]
-core1_timer_val\[54\]
-core1_timer_val\[53\]
-core1_timer_val\[52\]
-core1_timer_val\[51\]
-core1_timer_val\[50\]
-core1_timer_val\[49\]
-core1_timer_val\[48\]
-core1_timer_val\[47\]
-core1_timer_val\[46\]
-core1_timer_val\[45\]
-core1_timer_val\[44\]
-core1_timer_val\[43\]
-core1_timer_val\[42\]
-core1_timer_val\[41\]
-core1_timer_val\[40\]
-core1_timer_val\[39\]
-core1_timer_val\[38\]
-core1_timer_val\[37\]
-core1_timer_val\[36\]
-core1_timer_val\[35\]
-core1_timer_val\[34\]
-core1_timer_val\[33\]
-core1_timer_val\[32\]
-core1_timer_val\[31\]
-core1_timer_val\[30\]
-core1_timer_val\[29\]
-core1_timer_val\[28\]
-core1_timer_val\[27\]
-core1_timer_val\[26\]
-core1_timer_val\[25\]
-core1_timer_val\[24\]
-core1_timer_val\[23\]
-core1_timer_val\[22\]
-core1_timer_val\[21\]
-core1_timer_val\[20\]
-core1_timer_val\[19\]
-core1_timer_val\[18\]
-core1_timer_val\[17\]
-core1_timer_val\[16\]
-core1_timer_val\[15\]
-core1_timer_val\[14\]
-core1_timer_val\[13\]
-core1_timer_val\[12\]
-core1_timer_val\[11\]
-core1_timer_val\[10\]
-core1_timer_val\[9\]
-core1_timer_val\[8\]
-core1_timer_val\[7\]
-core1_timer_val\[6\]
-core1_timer_val\[5\]
-core1_timer_val\[4\]
-core1_timer_val\[3\]
-core1_timer_val\[2\]
-core1_timer_val\[1\]
-core1_timer_val\[0\]
-
-#W
-sram0_clk0 000 0 2
-sram0_csb0
-sram0_web0
-sram0_addr0\[8\]
-sram0_addr0\[7\]
-sram0_addr0\[6\]
-sram0_addr0\[5\]
-sram0_addr0\[4\]
-sram0_addr0\[3\]
-sram0_addr0\[2\]
-sram0_addr0\[1\]
-sram0_addr0\[0\]
-sram0_wmask0\[3\]
-sram0_wmask0\[2\]
-sram0_wmask0\[1\]
-sram0_wmask0\[0\]
-sram0_din0\[31\]
-sram0_din0\[30\]
-sram0_din0\[29\]
-sram0_din0\[28\]
-sram0_din0\[27\]
-sram0_din0\[26\]
-sram0_din0\[25\]
-sram0_din0\[24\]
-sram0_din0\[23\]
-sram0_din0\[22\]
-sram0_din0\[21\]
-sram0_din0\[20\]
-sram0_din0\[19\]
-sram0_din0\[18\]
-sram0_din0\[17\]
-sram0_din0\[16\]
-sram0_din0\[15\]
-sram0_din0\[14\]
-sram0_din0\[13\]
-sram0_din0\[12\]
-sram0_din0\[11\]
-sram0_din0\[10\]
-sram0_din0\[9\]
-sram0_din0\[8\]
-sram0_din0\[7\]
-sram0_din0\[6\]
-sram0_din0\[5\]
-sram0_din0\[4\]
-sram0_din0\[3\]
-sram0_din0\[2\]
-sram0_din0\[1\]
-sram0_din0\[0\]
-sram0_dout0\[31\]
-sram0_dout0\[30\]
-sram0_dout0\[29\]
-sram0_dout0\[28\]
-sram0_dout0\[27\]
-sram0_dout0\[26\]
-sram0_dout0\[25\]
-sram0_dout0\[24\]
-sram0_dout0\[23\]
-sram0_dout0\[22\]
-sram0_dout0\[21\]
-sram0_dout0\[20\]
-sram0_dout0\[19\]
-sram0_dout0\[18\]
-sram0_dout0\[17\]
-sram0_dout0\[16\]
-sram0_dout0\[15\]
-sram0_dout0\[14\]
-sram0_dout0\[13\]
-sram0_dout0\[12\]
-sram0_dout0\[11\]
-sram0_dout0\[10\]
-sram0_dout0\[9\]
-sram0_dout0\[8\]
-sram0_dout0\[7\]
-sram0_dout0\[6\]
-sram0_dout0\[5\]
-sram0_dout0\[4\]
-sram0_dout0\[3\]
-sram0_dout0\[2\]
-sram0_dout0\[1\]
-sram0_dout0\[0\]
-
-
-sram0_clk1 0110 0 2
-sram0_csb1
-sram0_addr1\[8\]
-sram0_addr1\[7\]
-sram0_addr1\[6\]
-sram0_addr1\[5\]
-sram0_addr1\[4\]
-sram0_addr1\[3\]
-sram0_addr1\[2\]
-sram0_addr1\[1\]
-sram0_addr1\[0\]
-sram0_dout1\[31\]
-sram0_dout1\[30\]
-sram0_dout1\[29\]
-sram0_dout1\[28\]
-sram0_dout1\[27\]
-sram0_dout1\[26\]
-sram0_dout1\[25\]
-sram0_dout1\[24\]
-sram0_dout1\[23\]
-sram0_dout1\[22\]
-sram0_dout1\[21\]
-sram0_dout1\[20\]
-sram0_dout1\[19\]
-sram0_dout1\[18\]
-sram0_dout1\[17\]
-sram0_dout1\[16\]
-sram0_dout1\[15\]
-sram0_dout1\[14\]
-sram0_dout1\[13\]
-sram0_dout1\[12\]
-sram0_dout1\[11\]
-sram0_dout1\[10\]
-sram0_dout1\[9\]
-sram0_dout1\[8\]
-sram0_dout1\[7\]
-sram0_dout1\[6\]
-sram0_dout1\[5\]
-sram0_dout1\[4\]
-sram0_dout1\[3\]
-sram0_dout1\[2\]
-sram0_dout1\[1\]
-sram0_dout1\[0\]
-
-
-core2_uid\[1\] 0200 00 2
-core2_uid\[0\]
-core2_imem_req_ack
-core2_imem_req
-core2_imem_cmd
-core2_imem_addr\[31\]
-core2_imem_addr\[30\]
-core2_imem_addr\[29\]
-core2_imem_addr\[28\]
-core2_imem_addr\[27\]
-core2_imem_addr\[26\]
-core2_imem_addr\[25\]
-core2_imem_addr\[24\]
-core2_imem_addr\[23\]
-core2_imem_addr\[22\]
-core2_imem_addr\[21\]
-core2_imem_addr\[20\]
-core2_imem_addr\[19\]
-core2_imem_addr\[18\]
-core2_imem_addr\[17\]
-core2_imem_addr\[16\]
-core2_imem_addr\[15\]
-core2_imem_addr\[14\]
-core2_imem_addr\[13\]
-core2_imem_addr\[12\]
-core2_imem_addr\[11\]
-core2_imem_addr\[10\]
-core2_imem_addr\[9\]
-core2_imem_addr\[8\]
-core2_imem_addr\[7\]
-core2_imem_addr\[6\]
-core2_imem_addr\[5\]
-core2_imem_addr\[4\]
-core2_imem_addr\[3\]
-core2_imem_addr\[2\]
-core2_imem_addr\[1\]
-core2_imem_addr\[0\]
-core2_imem_bl\[2\]
-core2_imem_bl\[1\]
-core2_imem_bl\[0\]
-core2_imem_rdata\[31\]
-core2_imem_rdata\[30\]
-core2_imem_rdata\[29\]
-core2_imem_rdata\[28\]
-core2_imem_rdata\[27\]
-core2_imem_rdata\[26\]
-core2_imem_rdata\[25\]
-core2_imem_rdata\[24\]
-core2_imem_rdata\[23\]
-core2_imem_rdata\[22\]
-core2_imem_rdata\[21\]
-core2_imem_rdata\[20\]
-core2_imem_rdata\[19\]
-core2_imem_rdata\[18\]
-core2_imem_rdata\[17\]
-core2_imem_rdata\[16\]
-core2_imem_rdata\[15\]
-core2_imem_rdata\[14\]
-core2_imem_rdata\[13\]
-core2_imem_rdata\[12\]
-core2_imem_rdata\[11\]
-core2_imem_rdata\[10\]
-core2_imem_rdata\[9\]
-core2_imem_rdata\[8\]
-core2_imem_rdata\[7\]
-core2_imem_rdata\[6\]
-core2_imem_rdata\[5\]
-core2_imem_rdata\[4\]
-core2_imem_rdata\[3\]
-core2_imem_rdata\[2\]
-core2_imem_rdata\[1\]
-core2_imem_rdata\[0\]
-core2_imem_resp\[1\]
-core2_imem_resp\[0\]
-
-core2_dmem_req_ack 0400 0 2
-core2_dmem_req
-core2_dmem_cmd
-core2_dmem_width\[1\]
-core2_dmem_width\[0\]
-core2_dmem_addr\[31\]
-core2_dmem_addr\[30\]
-core2_dmem_addr\[29\]
-core2_dmem_addr\[28\]
-core2_dmem_addr\[27\]
-core2_dmem_addr\[26\]
-core2_dmem_addr\[25\]
-core2_dmem_addr\[24\]
-core2_dmem_addr\[23\]
-core2_dmem_addr\[22\]
-core2_dmem_addr\[21\]
-core2_dmem_addr\[20\]
-core2_dmem_addr\[19\]
-core2_dmem_addr\[18\]
-core2_dmem_addr\[17\]
-core2_dmem_addr\[16\]
-core2_dmem_addr\[15\]
-core2_dmem_addr\[14\]
-core2_dmem_addr\[13\]
-core2_dmem_addr\[12\]
-core2_dmem_addr\[11\]
-core2_dmem_addr\[10\]
-core2_dmem_addr\[9\]
-core2_dmem_addr\[8\]
-core2_dmem_addr\[7\]
-core2_dmem_addr\[6\]
-core2_dmem_addr\[5\]
-core2_dmem_addr\[4\]
-core2_dmem_addr\[3\]
-core2_dmem_addr\[2\]
-core2_dmem_addr\[1\]
-core2_dmem_addr\[0\]
-core2_dmem_wdata\[31\]
-core2_dmem_wdata\[30\]
-core2_dmem_wdata\[29\]
-core2_dmem_wdata\[28\]
-core2_dmem_wdata\[27\]
-core2_dmem_wdata\[26\]
-core2_dmem_wdata\[25\]
-core2_dmem_wdata\[24\]
-core2_dmem_wdata\[23\]
-core2_dmem_wdata\[22\]
-core2_dmem_wdata\[21\]
-core2_dmem_wdata\[20\]
-core2_dmem_wdata\[19\]
-core2_dmem_wdata\[18\]
-core2_dmem_wdata\[17\]
-core2_dmem_wdata\[16\]
-core2_dmem_wdata\[15\]
-core2_dmem_wdata\[14\]
-core2_dmem_wdata\[13\]
-core2_dmem_wdata\[12\]
-core2_dmem_wdata\[11\]
-core2_dmem_wdata\[10\]
-core2_dmem_wdata\[9\]
-core2_dmem_wdata\[8\]
-core2_dmem_wdata\[7\]
-core2_dmem_wdata\[6\]
-core2_dmem_wdata\[5\]
-core2_dmem_wdata\[4\]
-core2_dmem_wdata\[3\]
-core2_dmem_wdata\[2\]
-core2_dmem_wdata\[1\]
-core2_dmem_wdata\[0\]
-core2_dmem_rdata\[31\]
-core2_dmem_rdata\[30\]
-core2_dmem_rdata\[29\]
-core2_dmem_rdata\[28\]
-core2_dmem_rdata\[27\]
-core2_dmem_rdata\[26\]
-core2_dmem_rdata\[25\]
-core2_dmem_rdata\[24\]
-core2_dmem_rdata\[23\]
-core2_dmem_rdata\[22\]
-core2_dmem_rdata\[21\]
-core2_dmem_rdata\[20\]
-core2_dmem_rdata\[19\]
-core2_dmem_rdata\[18\]
-core2_dmem_rdata\[17\]
-core2_dmem_rdata\[16\]
-core2_dmem_rdata\[15\]
-core2_dmem_rdata\[14\]
-core2_dmem_rdata\[13\]
-core2_dmem_rdata\[12\]
-core2_dmem_rdata\[11\]
-core2_dmem_rdata\[10\]
-core2_dmem_rdata\[9\]
-core2_dmem_rdata\[8\]
-core2_dmem_rdata\[7\]
-core2_dmem_rdata\[6\]
-core2_dmem_rdata\[5\]
-core2_dmem_rdata\[4\]
-core2_dmem_rdata\[3\]
-core2_dmem_rdata\[2\]
-core2_dmem_rdata\[1\]
-core2_dmem_rdata\[0\]
-core2_dmem_resp\[1\]
-core2_dmem_resp\[0\]
-
-core2_debug\[48\] 0600 0 2
-core2_debug\[47\]
-core2_debug\[46\]
-core2_debug\[45\]
-core2_debug\[44\]
-core2_debug\[43\]
-core2_debug\[42\]
-core2_debug\[41\]
-core2_debug\[40\]
-core2_debug\[39\]
-core2_debug\[38\]
-core2_debug\[37\]
-core2_debug\[36\]
-core2_debug\[35\]
-core2_debug\[34\]
-core2_debug\[33\]
-core2_debug\[32\]
-core2_debug\[31\]
-core2_debug\[30\]
-core2_debug\[29\]
-core2_debug\[28\]
-core2_debug\[27\]
-core2_debug\[26\]
-core2_debug\[25\]
-core2_debug\[24\]
-core2_debug\[23\]
-core2_debug\[22\]
-core2_debug\[21\]
-core2_debug\[20\]
-core2_debug\[19\]
-core2_debug\[18\]
-core2_debug\[17\]
-core2_debug\[16\]
-core2_debug\[15\]
-core2_debug\[14\]
-core2_debug\[13\]
-core2_debug\[12\]
-core2_debug\[11\]
-core2_debug\[10\]
-core2_debug\[9\]
-core2_debug\[8\]
-core2_debug\[7\]
-core2_debug\[6\]
-core2_debug\[5\]
-core2_debug\[4\]
-core2_debug\[3\]
-core2_debug\[2\]
-core2_debug\[1\]
-core2_debug\[0\]
-
-core2_timer_irq
-core2_timer_val\[63\]
-core2_timer_val\[62\]
-core2_timer_val\[61\]
-core2_timer_val\[60\]
-core2_timer_val\[59\]
-core2_timer_val\[58\]
-core2_timer_val\[57\]
-core2_timer_val\[56\]
-core2_timer_val\[55\]
-core2_timer_val\[54\]
-core2_timer_val\[53\]
-core2_timer_val\[52\]
-core2_timer_val\[51\]
-core2_timer_val\[50\]
-core2_timer_val\[49\]
-core2_timer_val\[48\]
-core2_timer_val\[47\]
-core2_timer_val\[46\]
-core2_timer_val\[45\]
-core2_timer_val\[44\]
-core2_timer_val\[43\]
-core2_timer_val\[42\]
-core2_timer_val\[41\]
-core2_timer_val\[40\]
-core2_timer_val\[39\]
-core2_timer_val\[38\]
-core2_timer_val\[37\]
-core2_timer_val\[36\]
-core2_timer_val\[35\]
-core2_timer_val\[34\]
-core2_timer_val\[33\]
-core2_timer_val\[32\]
-core2_timer_val\[31\]
-core2_timer_val\[30\]
-core2_timer_val\[29\]
-core2_timer_val\[28\]
-core2_timer_val\[27\]
-core2_timer_val\[26\]
-core2_timer_val\[25\]
-core2_timer_val\[24\]
-core2_timer_val\[23\]
-core2_timer_val\[22\]
-core2_timer_val\[21\]
-core2_timer_val\[20\]
-core2_timer_val\[19\]
-core2_timer_val\[18\]
-core2_timer_val\[17\]
-core2_timer_val\[16\]
-core2_timer_val\[15\]
-core2_timer_val\[14\]
-core2_timer_val\[13\]
-core2_timer_val\[12\]
-core2_timer_val\[11\]
-core2_timer_val\[10\]
-core2_timer_val\[9\]
-core2_timer_val\[8\]
-core2_timer_val\[7\]
-core2_timer_val\[6\]
-core2_timer_val\[5\]
-core2_timer_val\[4\]
-core2_timer_val\[3\]
-core2_timer_val\[2\]
-core2_timer_val\[1\]
-core2_timer_val\[0\]
-
-core3_uid\[1\] 1200 00 2
-core3_uid\[0\]
-core3_imem_req_ack
-core3_imem_req
-core3_imem_cmd
-core3_imem_addr\[31\]
-core3_imem_addr\[30\]
-core3_imem_addr\[29\]
-core3_imem_addr\[28\]
-core3_imem_addr\[27\]
-core3_imem_addr\[26\]
-core3_imem_addr\[25\]
-core3_imem_addr\[24\]
-core3_imem_addr\[23\]
-core3_imem_addr\[22\]
-core3_imem_addr\[21\]
-core3_imem_addr\[20\]
-core3_imem_addr\[19\]
-core3_imem_addr\[18\]
-core3_imem_addr\[17\]
-core3_imem_addr\[16\]
-core3_imem_addr\[15\]
-core3_imem_addr\[14\]
-core3_imem_addr\[13\]
-core3_imem_addr\[12\]
-core3_imem_addr\[11\]
-core3_imem_addr\[10\]
-core3_imem_addr\[9\]
-core3_imem_addr\[8\]
-core3_imem_addr\[7\]
-core3_imem_addr\[6\]
-core3_imem_addr\[5\]
-core3_imem_addr\[4\]
-core3_imem_addr\[3\]
-core3_imem_addr\[2\]
-core3_imem_addr\[1\]
-core3_imem_addr\[0\]
-core3_imem_bl\[2\]
-core3_imem_bl\[1\]
-core3_imem_bl\[0\]
-core3_imem_rdata\[31\]
-core3_imem_rdata\[30\]
-core3_imem_rdata\[29\]
-core3_imem_rdata\[28\]
-core3_imem_rdata\[27\]
-core3_imem_rdata\[26\]
-core3_imem_rdata\[25\]
-core3_imem_rdata\[24\]
-core3_imem_rdata\[23\]
-core3_imem_rdata\[22\]
-core3_imem_rdata\[21\]
-core3_imem_rdata\[20\]
-core3_imem_rdata\[19\]
-core3_imem_rdata\[18\]
-core3_imem_rdata\[17\]
-core3_imem_rdata\[16\]
-core3_imem_rdata\[15\]
-core3_imem_rdata\[14\]
-core3_imem_rdata\[13\]
-core3_imem_rdata\[12\]
-core3_imem_rdata\[11\]
-core3_imem_rdata\[10\]
-core3_imem_rdata\[9\]
-core3_imem_rdata\[8\]
-core3_imem_rdata\[7\]
-core3_imem_rdata\[6\]
-core3_imem_rdata\[5\]
-core3_imem_rdata\[4\]
-core3_imem_rdata\[3\]
-core3_imem_rdata\[2\]
-core3_imem_rdata\[1\]
-core3_imem_rdata\[0\]
-core3_imem_resp\[1\]
-core3_imem_resp\[0\]
-
-core3_dmem_req_ack 1400 0 2
-core3_dmem_req
-core3_dmem_cmd
-core3_dmem_width\[1\]
-core3_dmem_width\[0\]
-core3_dmem_addr\[31\]
-core3_dmem_addr\[30\]
-core3_dmem_addr\[29\]
-core3_dmem_addr\[28\]
-core3_dmem_addr\[27\]
-core3_dmem_addr\[26\]
-core3_dmem_addr\[25\]
-core3_dmem_addr\[24\]
-core3_dmem_addr\[23\]
-core3_dmem_addr\[22\]
-core3_dmem_addr\[21\]
-core3_dmem_addr\[20\]
-core3_dmem_addr\[19\]
-core3_dmem_addr\[18\]
-core3_dmem_addr\[17\]
-core3_dmem_addr\[16\]
-core3_dmem_addr\[15\]
-core3_dmem_addr\[14\]
-core3_dmem_addr\[13\]
-core3_dmem_addr\[12\]
-core3_dmem_addr\[11\]
-core3_dmem_addr\[10\]
-core3_dmem_addr\[9\]
-core3_dmem_addr\[8\]
-core3_dmem_addr\[7\]
-core3_dmem_addr\[6\]
-core3_dmem_addr\[5\]
-core3_dmem_addr\[4\]
-core3_dmem_addr\[3\]
-core3_dmem_addr\[2\]
-core3_dmem_addr\[1\]
-core3_dmem_addr\[0\]
-core3_dmem_wdata\[31\]
-core3_dmem_wdata\[30\]
-core3_dmem_wdata\[29\]
-core3_dmem_wdata\[28\]
-core3_dmem_wdata\[27\]
-core3_dmem_wdata\[26\]
-core3_dmem_wdata\[25\]
-core3_dmem_wdata\[24\]
-core3_dmem_wdata\[23\]
-core3_dmem_wdata\[22\]
-core3_dmem_wdata\[21\]
-core3_dmem_wdata\[20\]
-core3_dmem_wdata\[19\]
-core3_dmem_wdata\[18\]
-core3_dmem_wdata\[17\]
-core3_dmem_wdata\[16\]
-core3_dmem_wdata\[15\]
-core3_dmem_wdata\[14\]
-core3_dmem_wdata\[13\]
-core3_dmem_wdata\[12\]
-core3_dmem_wdata\[11\]
-core3_dmem_wdata\[10\]
-core3_dmem_wdata\[9\]
-core3_dmem_wdata\[8\]
-core3_dmem_wdata\[7\]
-core3_dmem_wdata\[6\]
-core3_dmem_wdata\[5\]
-core3_dmem_wdata\[4\]
-core3_dmem_wdata\[3\]
-core3_dmem_wdata\[2\]
-core3_dmem_wdata\[1\]
-core3_dmem_wdata\[0\]
-core3_dmem_rdata\[31\]
-core3_dmem_rdata\[30\]
-core3_dmem_rdata\[29\]
-core3_dmem_rdata\[28\]
-core3_dmem_rdata\[27\]
-core3_dmem_rdata\[26\]
-core3_dmem_rdata\[25\]
-core3_dmem_rdata\[24\]
-core3_dmem_rdata\[23\]
-core3_dmem_rdata\[22\]
-core3_dmem_rdata\[21\]
-core3_dmem_rdata\[20\]
-core3_dmem_rdata\[19\]
-core3_dmem_rdata\[18\]
-core3_dmem_rdata\[17\]
-core3_dmem_rdata\[16\]
-core3_dmem_rdata\[15\]
-core3_dmem_rdata\[14\]
-core3_dmem_rdata\[13\]
-core3_dmem_rdata\[12\]
-core3_dmem_rdata\[11\]
-core3_dmem_rdata\[10\]
-core3_dmem_rdata\[9\]
-core3_dmem_rdata\[8\]
-core3_dmem_rdata\[7\]
-core3_dmem_rdata\[6\]
-core3_dmem_rdata\[5\]
-core3_dmem_rdata\[4\]
-core3_dmem_rdata\[3\]
-core3_dmem_rdata\[2\]
-core3_dmem_rdata\[1\]
-core3_dmem_rdata\[0\]
-core3_dmem_resp\[1\]
-core3_dmem_resp\[0\]
-
-core3_debug\[48\] 1600 0 2
-core3_debug\[47\]
-core3_debug\[46\]
-core3_debug\[45\]
-core3_debug\[44\]
-core3_debug\[43\]
-core3_debug\[42\]
-core3_debug\[41\]
-core3_debug\[40\]
-core3_debug\[39\]
-core3_debug\[38\]
-core3_debug\[37\]
-core3_debug\[36\]
-core3_debug\[35\]
-core3_debug\[34\]
-core3_debug\[33\]
-core3_debug\[32\]
-core3_debug\[31\]
-core3_debug\[30\]
-core3_debug\[29\]
-core3_debug\[28\]
-core3_debug\[27\]
-core3_debug\[26\]
-core3_debug\[25\]
-core3_debug\[24\]
-core3_debug\[23\]
-core3_debug\[22\]
-core3_debug\[21\]
-core3_debug\[20\]
-core3_debug\[19\]
-core3_debug\[18\]
-core3_debug\[17\]
-core3_debug\[16\]
-core3_debug\[15\]
-core3_debug\[14\]
-core3_debug\[13\]
-core3_debug\[12\]
-core3_debug\[11\]
-core3_debug\[10\]
-core3_debug\[9\]
-core3_debug\[8\]
-core3_debug\[7\]
-core3_debug\[6\]
-core3_debug\[5\]
-core3_debug\[4\]
-core3_debug\[3\]
-core3_debug\[2\]
-core3_debug\[1\]
-core3_debug\[0\]
-
-core3_timer_irq
-core3_timer_val\[63\]
-core3_timer_val\[62\]
-core3_timer_val\[61\]
-core3_timer_val\[60\]
-core3_timer_val\[59\]
-core3_timer_val\[58\]
-core3_timer_val\[57\]
-core3_timer_val\[56\]
-core3_timer_val\[55\]
-core3_timer_val\[54\]
-core3_timer_val\[53\]
-core3_timer_val\[52\]
-core3_timer_val\[51\]
-core3_timer_val\[50\]
-core3_timer_val\[49\]
-core3_timer_val\[48\]
-core3_timer_val\[47\]
-core3_timer_val\[46\]
-core3_timer_val\[45\]
-core3_timer_val\[44\]
-core3_timer_val\[43\]
-core3_timer_val\[42\]
-core3_timer_val\[41\]
-core3_timer_val\[40\]
-core3_timer_val\[39\]
-core3_timer_val\[38\]
-core3_timer_val\[37\]
-core3_timer_val\[36\]
-core3_timer_val\[35\]
-core3_timer_val\[34\]
-core3_timer_val\[33\]
-core3_timer_val\[32\]
-core3_timer_val\[31\]
-core3_timer_val\[30\]
-core3_timer_val\[29\]
-core3_timer_val\[28\]
-core3_timer_val\[27\]
-core3_timer_val\[26\]
-core3_timer_val\[25\]
-core3_timer_val\[24\]
-core3_timer_val\[23\]
-core3_timer_val\[22\]
-core3_timer_val\[21\]
-core3_timer_val\[20\]
-core3_timer_val\[19\]
-core3_timer_val\[18\]
-core3_timer_val\[17\]
-core3_timer_val\[16\]
-core3_timer_val\[15\]
-core3_timer_val\[14\]
-core3_timer_val\[13\]
-core3_timer_val\[12\]
-core3_timer_val\[11\]
-core3_timer_val\[10\]
-core3_timer_val\[9\]
-core3_timer_val\[8\]
-core3_timer_val\[7\]
-core3_timer_val\[6\]
-core3_timer_val\[5\]
-core3_timer_val\[4\]
-core3_timer_val\[3\]
-core3_timer_val\[2\]
-core3_timer_val\[1\]
-core3_timer_val\[0\]
-
diff --git a/openlane/ycr_core/base.sdc b/openlane/ycr_core_top/base.sdc
similarity index 100%
rename from openlane/ycr_core/base.sdc
rename to openlane/ycr_core_top/base.sdc
diff --git a/openlane/ycr_core/config.tcl b/openlane/ycr_core_top/config.tcl
similarity index 96%
rename from openlane/ycr_core/config.tcl
rename to openlane/ycr_core_top/config.tcl
index c34a09b..65347ff 100644
--- a/openlane/ycr_core/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -71,15 +71,16 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 600 950 "
+set ::env(DIE_AREA) "0 0 590 930 "
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.36
+set ::env(PL_TARGET_DENSITY) 0.38
+set ::env(CELL_PAD) "6"
set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(DIODE_INSERTION_STRATEGY) 3
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/ycr_core/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg
similarity index 100%
rename from openlane/ycr_core/macro_placement.cfg
rename to openlane/ycr_core_top/macro_placement.cfg
diff --git a/openlane/ycr_core/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
similarity index 97%
rename from openlane/ycr_core/pin_order.cfg
rename to openlane/ycr_core_top/pin_order.cfg
index 924f0e6..79b2c6f 100644
--- a/openlane/ycr_core/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,9 +1,8 @@
#BUS_SORT
#MANUAL_PLACE
-#S
-core_uid\[1\] 0000 00 2
+#E
+core_uid\[1\] 0200 00 2
core_uid\[0\]
-cpu_rst_n
imem2core_req_ack_i
core2imem_req_o
core2imem_cmd_o
@@ -77,7 +76,7 @@
imem2core_resp_i\[1\]
imem2core_resp_i\[0\]
-dmem2core_req_ack_i 0100 0 2
+dmem2core_req_ack_i 0350 0 2
core2dmem_req_o
core2dmem_cmd_o
core2dmem_width_o\[1\]
@@ -181,7 +180,7 @@
dmem2core_resp_i\[1\]
dmem2core_resp_i\[0\]
-core_debug\[48\] 0200 0 2
+core_debug\[48\] 0500 0 2
core_debug\[47\]
core_debug\[46\]
core_debug\[45\]
@@ -231,7 +230,7 @@
core_debug\[1\]
core_debug\[0\]
-core_irq_mtimer_i 0300 0 2
+core_irq_mtimer_i 0600 0 2
core_mtimer_val_i\[63\]
core_mtimer_val_i\[62\]
core_mtimer_val_i\[61\]
@@ -297,10 +296,6 @@
core_mtimer_val_i\[1\]
core_mtimer_val_i\[0\]
-pwrup_rst_n
-rst_n
-
-
core_irq_lines_i\[15\]
core_irq_lines_i\[14\]
core_irq_lines_i\[13\]
@@ -318,6 +313,13 @@
core_irq_lines_i\[1\]
core_irq_lines_i\[0\]
core_irq_soft_i
+cpu_rst_n
+
+#S
+pwrup_rst_n
+rst_n
+
+
clk
clk_o
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index aebf0d7..2d497b5 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -63,7 +63,7 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 650 "
+set ::env(DIE_AREA) "0 0 800 640 "
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.38
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg
index 9fdc875..9da42d8 100644
--- a/openlane/ycr_intf/pin_order.cfg
+++ b/openlane/ycr_intf/pin_order.cfg
@@ -287,7 +287,7 @@
core_dmem_resp\[1\]
core_dmem_resp\[0\]
-cfg_icache_pfet_dis 0300 0 2
+cfg_icache_pfet_dis
cfg_icache_ntag_pfet_dis
cfg_dcache_pfet_dis
cfg_dcache_force_flush
@@ -534,7 +534,7 @@
wbd_clk_riscv
wb_clk
-wbd_dmem_stb_o 0050 0 2
+wbd_dmem_stb_o 0100 0 2
wbd_dmem_we_o
wbd_dmem_adr_o\[31\]
wbd_dmem_adr_o\[30\]
@@ -639,7 +639,7 @@
wbd_dmem_ack_i
wbd_dmem_err_i
-wb_dcache_stb_o 0200 0 2
+wb_dcache_stb_o 0300 0 2
wb_dcache_we_o
wb_dcache_adr_o\[31\]
wb_dcache_adr_o\[30\]
@@ -757,7 +757,7 @@
wb_dcache_err_i
wb_dcache_cyc_o
-wb_icache_stb_o 400 0 2
+wb_icache_stb_o 500 0 2
wb_icache_we_o
wb_icache_adr_o\[31\]
wb_icache_adr_o\[30\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index eaac07f..1b4f769 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m45s0ms,0h6m26s0ms,49349.494949494954,0.2475,24674.747474747477,29.39,954.58,6107,0,0,0,0,0,0,0,-1,0,-1,-1,458162,60438,-9.79,-17.09,-1,0.0,0.0,-11322.82,-19478.71,-1,0.0,0.0,363642601.0,0.0,61.71,47.76,26.72,20.99,-1,4043,9507,808,6272,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,12,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h8m24s0ms,0h5m24s0ms,49406.06060606061,0.2475,24703.030303030304,29.45,928.46,6114,0,0,0,0,0,0,0,-1,0,-1,-1,460374,60467,-9.79,-17.11,-1,0.0,0.0,-11339.96,-19481.21,-1,0.0,0.0,363488649.0,0.0,60.22,48.01,28.48,22.13,-1,4047,9515,812,6280,0,0,0,4592,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim_top/final_summary_report.csv b/signoff/qspim_top/final_summary_report.csv
index 65d79bc..f491344 100644
--- a/signoff/qspim_top/final_summary_report.csv
+++ b/signoff/qspim_top/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h12m26s0ms,0h9m19s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1104.07,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h12m59s0ms,0h9m23s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1062.49,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 9cd6bea..5f34d41 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h48m45s0ms,0h5m14s0ms,-2.0,-1,-1,-1,602.58,11,0,0,0,0,0,0,-1,0,0,-1,-1,2385046,17217,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,8.06,11.83,2.96,3.32,0.0,317,3274,317,3274,0,0,0,11,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h1m53s0ms,0h4m26s0ms,-2.0,-1,-1,-1,597.46,18,0,0,0,0,0,0,-1,0,29,-1,-1,1507480,13275,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.57,8.93,1.79,2.26,0.0,391,4275,391,4275,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,100,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 898c873..11d10c7 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m10s0ms,0h3m26s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,773.21,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h6m26s0ms,0h4m28s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,779.29,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 0106066..4087ef0 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h39m31s0ms,0h29m40s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1333.09,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h31m53s0ms,0h24m20s0ms,40348.14814814815,0.54,20174.074074074077,18.13,1386.93,10894,0,0,0,0,0,0,0,-1,0,-1,-1,949047,90644,-1.53,-2.29,-1,-2.25,-2.33,-106.67,-188.2,-1,-259.9,-259.66,793691221.0,0.0,20.02,51.61,1.99,21.92,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7205,0,8511,81.10300081103001,12.33,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,8,4
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr4_iconnect/final_summary_report.csv b/signoff/ycr4_iconnect/final_summary_report.csv
new file mode 100644
index 0000000..722abe2
--- /dev/null
+++ b/signoff/ycr4_iconnect/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h41m14s0ms,0h34m10s0ms,11387.31443994602,0.741,5693.65721997301,5.16,1613.16,4219,0,0,0,0,0,0,0,191,0,0,-1,1293111,71757,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1105514567.0,0.0,28.93,60.6,13.63,53.45,-1,4301,10616,622,6874,0,0,0,4568,425,85,139,123,430,136,20,1551,1026,730,22,1380,10034,0,11414,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,12,3
diff --git a/signoff/ycr_core/final_summary_report.csv b/signoff/ycr_core/final_summary_report.csv
index bbb41ad..2521873 100644
--- a/signoff/ycr_core/final_summary_report.csv
+++ b/signoff/ycr_core/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h38m41s0ms,0h24m58s0ms,67717.64705882354,0.595,33858.82352941177,33.84,2318.47,20146,0,0,0,0,0,0,0,20,0,0,-1,1259376,186378,-23.43,-45.2,-1,0.0,0.0,-25026.44,-48972.85,-1,0.0,0.0,953528811.0,0.0,58.17,60.96,27.8,39.99,-1,16362,22599,511,6648,0,0,0,19139,686,255,523,601,2871,897,265,4812,2499,2405,43,608,8109,0,8717,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/ycr_core,ycr_core_top,ycr_core,flow completed,0h26m15s0ms,0h13m46s0ms,71291.22807017545,0.57,35645.614035087725,35.55,2265.47,20318,0,0,0,0,0,0,0,50,0,0,-1,1367930,192575,0.0,-6.73,-1,0.0,0.0,0.0,-6500.44,-1,0.0,0.0,1018911064.0,0.0,60.43,70.65,30.63,55.95,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,682,7717,0,8399,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.36,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv
new file mode 100644
index 0000000..426bb7a
--- /dev/null
+++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h49m1s0ms,0h41m19s0ms,74058.68416256607,0.5487,37029.34208128304,37.04,2323.93,20318,0,0,0,0,0,0,0,138,0,0,-1,1252569,182628,0.0,-8.3,-1,0.0,0.0,0.0,-8105.44,-1,0.0,0.0,956691859.0,0.0,51.85,67.46,22.39,49.15,-1,16388,22628,537,6677,0,0,0,19143,686,261,526,603,2869,894,266,4810,2496,2403,42,666,7370,0,8036,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,6,3
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane N/A
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
new file mode 100644
index 0000000..22e7dc1
--- /dev/null
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -0,0 +1,3 @@
+openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
+skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/ycr_intf/final_summary_report.csv b/signoff/ycr_intf/final_summary_report.csv
new file mode 100644
index 0000000..2eb6cfe
--- /dev/null
+++ b/signoff/ycr_intf/final_summary_report.csv
@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h21m46s0ms,0h10m38s0ms,60171.875,0.512,30085.9375,33.89,1969.86,15404,0,0,0,0,0,0,0,80,0,0,-1,1129521,148621,-6.74,-21.03,-1,0.0,0.0,-9567.3,-29197.47,-1,0.0,0.0,810410684.0,0.0,67.78,55.22,40.54,30.01,-1,9027,17783,900,9282,0,0,0,11541,549,128,352,277,1962,916,379,1530,2988,2779,24,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index f78d21e..c2424ad 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -1,7 +1,7 @@
- set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino"
- set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
- set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4"
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5"
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
@@ -43,13 +43,14 @@
read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v
# User project netlist
- read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
- read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
- read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr4_iconnect.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
- read_verilog $::env(USER_ROOT)/verilog/gl/mbist_wrapper.v
read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
@@ -144,15 +145,19 @@
read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
## User Project Spef
- read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_wrapper.spef
- read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef
- read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
- read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
- read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
- read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
- read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
- read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
+ read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr4_iconnect.spef
+ read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_1 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_2 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_riscv_top.i_core_top_3 $::env(USER_ROOT)/spef/ycr_core_top.spef
+ read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
+ read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
+ read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+ read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
+ read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef
+ read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef
read_sdc -echo ./sdc/caravel.sdc
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 711014a..68758ab 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -1,7 +1,7 @@
set ::env(IO_PCT) "0.2"
set ::env(SYNTH_MAX_FANOUT) "5"
set ::env(SYNTH_CAP_LOAD) "1"
-set ::env(SYNTH_TIMING_DERATE) 0.05
+set ::env(SYNTH_TIMING_DERATE) 0.01
set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25
set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25
set ::env(SYNTH_CLOCK_TRANSITION) 0.15
@@ -22,10 +22,6 @@
create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}]
create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}]
-create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X]
-create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X]
-create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X]
-create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X]
## Case analysis
@@ -49,10 +45,10 @@
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
-set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
@@ -64,10 +60,6 @@
set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
-set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[0]}]
-set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[1]}]
-set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[2]}]
-set_case_analysis 1 [get_pins {mprj/u_mbist/cfg_cska_mbist[3]}]
#disable clock gating check at static clock select pins
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 82bd34a..2bb2a1b 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -146,9 +146,15 @@
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
- end else begin
+ end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
end
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index ff9d152..6fe9413 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -184,9 +184,15 @@
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
- end else begin
+ end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index aed3a9d..b7e7c30 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -51,7 +51,7 @@
input logic h_reset_n,
// Global Reset control
- output logic [1:0] cpu_core_rst_n ,
+ output logic [3:0] cpu_core_rst_n ,
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 8764605..265aab8 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -43,7 +43,7 @@
input logic h_reset_n,
// Global Reset control
- output logic [1:0] cpu_core_rst_n ,
+ output logic [3:0] cpu_core_rst_n ,
output logic cpu_intf_rst_n ,
output logic qspim_rst_n ,
output logic sspim_rst_n ,
@@ -287,6 +287,8 @@
ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
+ctech_buf u_buf_cpu2_rst (.A(cfg_glb_ctrl[10]),.X(cpu_core_rst_n[2]));
+ctech_buf u_buf_cpu3_rst (.A(cfg_glb_ctrl[11]),.X(cpu_core_rst_n[3]));
gen_32b_reg #(32'h0) u_reg_1 (
//List of Inputs
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 3ef25c7..bd9e315 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -424,7 +424,7 @@
// CPU Configuration
//----------------------------------------------------
wire cpu_intf_rst_n ;
-wire [1:0] cpu_core_rst_n ;
+wire [3:0] cpu_core_rst_n ;
wire qspim_rst_n ;
wire sspim_rst_n ;
wire uart_rst_n ; // uart reset
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c
index 6a0ca40..5f18b62 160000
--- a/verilog/rtl/yifive/ycr4c
+++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@
-Subproject commit 6a0ca40c8876e96449d7ac889e3080ec3044f8e8
+Subproject commit 5f18b62e9ee613c4cf9664ccfbf069bb5ca8be12
