verilog/includes/includes.gl.caravel_user_project

# Caravel user project includes
+define+UNIT_DELAY=#0.1
+incdir+$(USER_PROJECT_VERILOG)/rtl/
+incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes
+incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm
+incdir+$(USER_PROJECT_VERILOG)/dv/common/model
+incdir+$(USER_PROJECT_VERILOG)/dv/common/agents
$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
$(USER_PROJECT_VERILOG)/gl/ycr_intf.v
$(USER_PROJECT_VERILOG)/gl/qspim_top.v
$(USER_PROJECT_VERILOG)/gl/wb_host.v
$(USER_PROJECT_VERILOG)/gl/ycr4_iconnect.v
$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v
$(USER_PROJECT_VERILOG)/gl/pinmux_top.v
$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v


$(USER_PROJECT_VERILOG)/gl/bus_rep_south.v
$(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
$(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
$(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
$(USER_PROJECT_VERILOG)/gl/peri_top.v

-v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
-v $(USER_PROJECT_VERILOG)/rtl/dac/src/dac_top.v