update
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl index 5139fc9..92ee59d 100644 --- a/openlane/ycr4_iconnect/config.tcl +++ b/openlane/ycr4_iconnect/config.tcl
@@ -28,6 +28,7 @@ set ::env(SYNTH_MAX_FANOUT) 4 ## CTS BUFFER +set ::env(CTS_CLK_MAX_WIRE_LENGTH) {250} set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" set ::env(CTS_SINK_CLUSTERING_SIZE) "16" set ::env(CLOCK_BUFFER_FANOUT) "8"
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg index c509d57..a830089 100644 --- a/openlane/ycr4_iconnect/pin_order.cfg +++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -1860,4 +1860,3 @@ core3_irq_lines\[0\] core3_irq_soft -#N
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index f232816..9c5862b 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -28,6 +28,7 @@ set ::env(SYNTH_BUFFERING) {0} ## CTS BUFFER +set ::env(CTS_CLK_MAX_WIRE_LENGTH) {250} set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" set ::env(CTS_SINK_CLUSTERING_SIZE) "16" set ::env(CLOCK_BUFFER_FANOUT) "8"
diff --git a/sta/scripts/riscdunio.tcl b/sta/scripts/riscdunio.tcl index d4fc118..3778d96 100644 --- a/sta/scripts/riscdunio.tcl +++ b/sta/scripts/riscdunio.tcl
@@ -1,6 +1,6 @@ set ::env(USER_ROOT) ".." - set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel" + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel" set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6" read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib @@ -48,9 +48,12 @@ #set tregs [llength [all_registers]] #puts "ycr_iconnect :: $tcell :: $tregs " lassign [get_statistic ycr4_iconnect] a b c + #Consolidated Count set c_total_cnt [expr {$c_total_cnt + $a }] set c_comb_cnt [expr {$c_comb_cnt + $b }] set c_seq_cnt [expr {$c_seq_cnt + $c }] + + #Riscv Count set r_total_cnt [expr {$r_total_cnt + $a }] set r_comb_cnt [expr {$r_comb_cnt + $b }] set r_seq_cnt [expr {$r_seq_cnt + $c }] @@ -61,23 +64,30 @@ #set tregs [llength [all_registers]] #puts "ycr_intf :: $tcell :: $tregs " lassign [get_statistic ycr_intf] a b c + #Consolidated Count set c_total_cnt [expr {$c_total_cnt + $a }] set c_comb_cnt [expr {$c_comb_cnt + $b }] set c_seq_cnt [expr {$c_seq_cnt + $c }] + #Riscv Count + set r_total_cnt [expr {$r_total_cnt + $a }] + set r_comb_cnt [expr {$r_comb_cnt + $b }] + set r_seq_cnt [expr {$r_seq_cnt + $c }] + read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v link_design ycr_core_top #set tcell [llength [get_cell -hier *]] #set tregs [llength [all_registers]] #puts "ycr_intf :: $tcell :: $tregs " lassign [get_statistic ycr_core_top] a b c - #2 core in riscduino_dcore + #4 core in riscduino_qcore set c_total_cnt [expr {$c_total_cnt + ($a *4) }] set c_comb_cnt [expr {$c_comb_cnt + ($b *4) }] set c_seq_cnt [expr {$c_seq_cnt + ($c *4) }] + set r_total_cnt [expr {$r_total_cnt + ($a *4) }] set r_comb_cnt [expr {$r_comb_cnt + ($b *4) }] - set r_seq_cnt [expr {$r_seq_cnt + ($c *2) }] + set r_seq_cnt [expr {$r_seq_cnt + ($c *4) }] puts "RISC :: $r_total_cnt :: $r_comb_cnt :: $r_seq_cnt" read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v @@ -110,16 +120,66 @@ set c_comb_cnt [expr {$c_comb_cnt + $b }] set c_seq_cnt [expr {$c_seq_cnt + $c }] - read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v - link_design pinmux + read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v + link_design pinmux_top #set tcell [llength [get_cell -hier *]] #set tregs [llength [all_registers]] - #puts "ycr_intf :: $tcell :: $tregs " + #puts "pinmux_top :: $tcell :: $tregs " lassign [get_statistic pinmux] a b c set c_total_cnt [expr {$c_total_cnt + $a }] set c_comb_cnt [expr {$c_comb_cnt + $b }] set c_seq_cnt [expr {$c_seq_cnt + $c }] + read_verilog $::env(USER_ROOT)/verilog/gl/peri_top.v + link_design peri_top + #set tcell [llength [get_cell -hier *]] + #set tregs [llength [all_registers]] + #puts "peri_top :: $tcell :: $tregs " + lassign [get_statistic peri_top] a b c + set c_total_cnt [expr {$c_total_cnt + $a }] + set c_comb_cnt [expr {$c_comb_cnt + $b }] + set c_seq_cnt [expr {$c_seq_cnt + $c }] + + read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_north.v + link_design bus_rep_north + #set tcell [llength [get_cell -hier *]] + #set tregs [llength [all_registers]] + #puts "bus_rep_east :: $tcell :: $tregs " + lassign [get_statistic bus_rep_north] a b c + set c_total_cnt [expr {$c_total_cnt + $a }] + set c_comb_cnt [expr {$c_comb_cnt + $b }] + set c_seq_cnt [expr {$c_seq_cnt + $c }] + + read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_south.v + link_design bus_rep_south + #set tcell [llength [get_cell -hier *]] + #set tregs [llength [all_registers]] + #puts "bus_rep_south :: $tcell :: $tregs " + lassign [get_statistic bus_rep_south] a b c + set c_total_cnt [expr {$c_total_cnt + $a }] + set c_comb_cnt [expr {$c_comb_cnt + $b }] + set c_seq_cnt [expr {$c_seq_cnt + $c }] + + read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_east.v + link_design bus_rep_east + #set tcell [llength [get_cell -hier *]] + #set tregs [llength [all_registers]] + #puts "bus_rep_east :: $tcell :: $tregs " + lassign [get_statistic bus_rep_east] a b c + set c_total_cnt [expr {$c_total_cnt + $a }] + set c_comb_cnt [expr {$c_comb_cnt + $b }] + set c_seq_cnt [expr {$c_seq_cnt + $c }] + + read_verilog $::env(USER_ROOT)/verilog/gl/bus_rep_west.v + link_design bus_rep_west + #set tcell [llength [get_cell -hier *]] + #set tregs [llength [all_registers]] + #puts "bus_rep_west :: $tcell :: $tregs " + lassign [get_statistic bus_rep_west] a b c + set c_total_cnt [expr {$c_total_cnt + $a }] + set c_comb_cnt [expr {$c_comb_cnt + $b }] + set c_seq_cnt [expr {$c_seq_cnt + $c }] + puts "digital_top :: $c_total_cnt :: $c_comb_cnt :: $c_seq_cnt" # read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v # read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v