| [submodule "verilog/rtl/yifive/ycr4c"] | |
| path = verilog/rtl/yifive/ycr4c | |
| url = https://github.com/dineshannayya/ycr4c.git | |
| [submodule "verilog/rtl/qspim1"] | |
| path = verilog/rtl/qspim | |
| url = https://github.com/dineshannayya/qspim.git | |
| [submodule "verilog/dv/common/riscduino_board"] | |
| path = verilog/dv/common/riscduino_board | |
| url = https://github.com/dineshannayya/riscduino_board.git | |
| [submodule "rtc"] | |
| path = verilog/rtl/rtc | |
| url = https://github.com/dineshannayya/rtc |