ycr core timing cleanup
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg
index be6ef95..cc3fbf6 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux/pin_order.cfg
@@ -13,8 +13,22 @@
uart_rst_n
i2cm_rst_n
usb_rst_n
-cfg_riscv_debug_sel\[1\]
-cfg_riscv_debug_sel\[0\]
+cfg_riscv_ctrl\[15\]
+cfg_riscv_ctrl\[14\]
+cfg_riscv_ctrl\[13\]
+cfg_riscv_ctrl\[12\]
+cfg_riscv_ctrl\[11\]
+cfg_riscv_ctrl\[10\]
+cfg_riscv_ctrl\[9\]
+cfg_riscv_ctrl\[8\]
+cfg_riscv_ctrl\[7\]
+cfg_riscv_ctrl\[6\]
+cfg_riscv_ctrl\[5\]
+cfg_riscv_ctrl\[4\]
+cfg_riscv_ctrl\[3\]
+cfg_riscv_ctrl\[2\]
+cfg_riscv_ctrl\[1\]
+cfg_riscv_ctrl\[0\]
user_irq\[0\]
user_irq\[1\]
user_irq\[2\]
diff --git a/openlane/ycr4_iconnect/base.sdc b/openlane/ycr4_iconnect/base.sdc
index 00fe508..38463e4 100644
--- a/openlane/ycr4_iconnect/base.sdc
+++ b/openlane/ycr4_iconnect/base.sdc
@@ -2,8 +2,6 @@
# Timing Constraints
###############################################################################
create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
-create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
-create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
@@ -14,16 +12,155 @@
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
-set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {core_clk}]\
- -group [get_clocks {rtc_clk}]\
- -group [get_clocks {wb_clk}] -comment {Async Clock group}
+#CORE-0 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
+
+#CORE-0 DMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
+
+#CORE-1 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
+
+#CORE-1 DMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
+
+#CORE-2 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_bl[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_rdata[*]}]
+
+#CORE-2 DMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_rdata[*]}]
+
+#CORE-3 IMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_bl[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_bl[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_rdata[*]}]
+
+#CORE-3 DMEM Constraints
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_wdata[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_width[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_wdata[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_width[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req_ack}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_rdata[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_rdata[*]}]
###############################################################################
# Environment
###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index e6a3743..01b9806 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -38,6 +38,7 @@
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv \
diff --git a/openlane/ycr4_iconnect/pin_order.cfg b/openlane/ycr4_iconnect/pin_order.cfg
index 4da31ff..0a74c77 100644
--- a/openlane/ycr4_iconnect/pin_order.cfg
+++ b/openlane/ycr4_iconnect/pin_order.cfg
@@ -1665,13 +1665,13 @@
core_dmem_resp\[1\]
core_dmem_resp\[0\]
-cfg_icache_pfet_dis
-cfg_icache_ntag_pfet_dis
-cfg_dcache_pfet_dis
cfg_dcache_force_flush
+cfg_sram_lphase\[1\]
+cfg_sram_lphase\[0\]
core_debug_sel\[1\] 300 0 2
core_debug_sel\[0\]
+
riscv_debug\[63\]
riscv_debug\[62\]
riscv_debug\[61\]
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 51d4ab8..f0ec289 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -12,12 +12,47 @@
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+#IMEM Constraints
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+
+set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+
+#DMEM Constraints
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+
+set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
###############################################################################
# Environment
###############################################################################
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 2d497b5..528078c 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -44,6 +44,7 @@
$script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_intf.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/async_fifo.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \
"
@@ -63,16 +64,17 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 800 640 "
+set ::env(DIE_AREA) "0 0 810 640 "
+set ::env(CELL_PAD) "6"
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.38
+set ::env(PL_TARGET_DENSITY) 0.37
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAXLAYER) "5"
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-set ::env(DIODE_INSERTION_STRATEGY) 4
+set ::env(DIODE_INSERTION_STRATEGY) 3
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg
index 9da42d8..6b93ea3 100644
--- a/openlane/ycr_intf/pin_order.cfg
+++ b/openlane/ycr_intf/pin_order.cfg
@@ -287,9 +287,6 @@
core_dmem_resp\[1\]
core_dmem_resp\[0\]
-cfg_icache_pfet_dis
-cfg_icache_ntag_pfet_dis
-cfg_dcache_pfet_dis
cfg_dcache_force_flush
#S
@@ -843,3 +840,8 @@
wb_icache_err_i
wb_icache_cyc_o
+cfg_icache_pfet_dis
+cfg_icache_ntag_pfet_dis
+cfg_dcache_pfet_dis
+cfg_sram_lphase\[1\]
+cfg_sram_lphase\[0\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index 1b4f769..8e1159a 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h8m24s0ms,0h5m24s0ms,49406.06060606061,0.2475,24703.030303030304,29.45,928.46,6114,0,0,0,0,0,0,0,-1,0,-1,-1,460374,60467,-9.79,-17.11,-1,0.0,0.0,-11339.96,-19481.21,-1,0.0,0.0,363488649.0,0.0,60.22,48.01,28.48,22.13,-1,4047,9515,812,6280,0,0,0,4592,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h9m20s0ms,0h6m7s0ms,49519.191919191915,0.2475,24759.595959595958,29.48,936.63,6128,0,0,0,0,0,0,0,-1,0,-1,-1,468563,60884,-9.8,-16.77,-1,0.0,0.0,-11351.48,-19355.22,-1,0.0,0.0,372119261.0,0.0,61.76,46.64,32.3,20.74,-1,4047,9543,812,6308,0,0,0,4592,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index db85b1d..93b0b63 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h5m44s0ms,0h4m36s0ms,-2.0,-1,-1,-1,586.6,14,0,0,0,0,0,0,-1,0,0,-1,-1,1525321,14003,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.9,9.34,1.49,2.29,0.0,389,4273,389,4273,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h3m3s0ms,0h4m46s0ms,-2.0,-1,-1,-1,600.39,14,0,0,0,0,0,0,-1,0,0,-1,-1,1533953,14147,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.86,9.47,1.53,2.4,0.0,391,4300,391,4300,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/ycr4_iconnect/final_summary_report.csv b/signoff/ycr4_iconnect/final_summary_report.csv
index 7fce1fa..a0dff5b 100644
--- a/signoff/ycr4_iconnect/final_summary_report.csv
+++ b/signoff/ycr4_iconnect/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h50m5s0ms,0h40m33s0ms,11700.831024930747,0.722,5850.4155124653735,5.28,1442.88,4224,0,0,0,0,0,0,0,171,0,0,-1,1207613,66195,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1018439984.0,0.0,28.82,56.67,8.96,52.15,-1,4217,10502,618,6840,0,0,0,4488,417,87,147,120,427,148,8,1550,1027,731,19,1380,9688,0,11068,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
+0,/project/openlane/ycr4_iconnect,ycr4_iconnect,ycr4_iconnect,flow completed,0h57m21s0ms,0h50m30s0ms,12542.936288088646,0.722,6271.468144044323,5.69,1722.84,4528,0,0,0,0,0,0,0,196,0,0,-1,1250687,71879,0.0,-0.01,-1,0.0,0.0,0.0,-0.14,-1,0.0,0.0,1028983094.0,0.0,29.44,57.03,10.91,54.52,-1,4386,10922,657,7130,0,0,0,4712,428,45,148,120,453,149,7,1597,1076,825,19,1380,9688,0,11068,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.2,0.3,sky130_fd_sc_hd,14,3
diff --git a/signoff/ycr_core_top/final_summary_report.csv b/signoff/ycr_core_top/final_summary_report.csv
index e32df54..da87e61 100644
--- a/signoff/ycr_core_top/final_summary_report.csv
+++ b/signoff/ycr_core_top/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h41m10s0ms,0h32m59s0ms,72853.10734463276,0.5664,36426.55367231638,36.53,2336.21,20632,0,0,0,0,0,0,0,156,0,0,-1,1330305,186613,0.0,-9.27,-1,0.0,0.0,0.0,-8367.8,-1,0.0,0.0,1042199582.0,0.0,49.66,70.89,25.54,53.73,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,36,688,7612,0,8300,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
+0,/project/openlane/ycr_core_top,ycr_core_top,ycr_core_top,flow completed,0h36m53s0ms,0h29m14s0ms,72853.10734463276,0.5664,36426.55367231638,36.53,2362.71,20632,0,0,0,0,0,0,0,180,0,0,-1,1333652,187270,0.0,-9.27,-1,-1.37,-1.36,0.0,-8368.03,-1,-15.74,-15.68,1042199582.0,0.0,49.48,71.1,25.41,53.73,-1,16396,22729,542,6775,0,0,0,19178,557,261,518,596,2917,897,259,4835,2528,2435,36,688,7612,0,8300,88.02816901408451,11.36,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
diff --git a/signoff/ycr_intf/final_summary_report.csv b/signoff/ycr_intf/final_summary_report.csv
index 3b861e4..62f9dba 100644
--- a/signoff/ycr_intf/final_summary_report.csv
+++ b/signoff/ycr_intf/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h30m11s0ms,0h17m28s0ms,60675.78125,0.512,30337.890625,34.18,2036.78,15533,0,0,0,0,0,0,0,96,0,0,-1,1153189,147312,-6.78,-20.93,-1,0.0,0.0,-9651.06,-29117.39,-1,0.0,0.0,829937169.0,0.0,65.33,54.11,46.0,34.52,-1,8844,17559,900,9282,0,0,0,11360,577,129,292,278,1938,890,375,1584,2991,2779,24,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/ycr_intf,ycr_intf,ycr_intf,flow completed,0h59m48s0ms,0h53m33s0ms,59564.04320987655,0.5184,29782.021604938276,34.03,2389.13,15439,0,0,0,0,0,0,0,144,0,0,-1,1046581,141440,-18.81,-33.58,-1,0.0,0.0,-14591.96,-36801.79,-1,0.0,0.0,822903171.0,0.0,52.74,46.86,30.27,28.44,-1,8919,18035,965,9748,0,0,0,11590,577,105,290,274,1941,885,380,1694,3104,2999,23,454,6984,0,7438,100.0,10.0,10,AREA 0,4,50,1,153.6,153.18,0.37,0.3,sky130_fd_sc_hd,6,3
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 68758ab..85ec73f 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -45,7 +45,7 @@
set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
-set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}]
set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}]
set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}]
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 99c4ac6..e7612c8 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -240,8 +240,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2603_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_0000);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0104_2022);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_1000);
end
diff --git a/verilog/dv/user_uart/simx.fst b/verilog/dv/user_uart/simx.fst
deleted file mode 100644
index 766079e..0000000
--- a/verilog/dv/user_uart/simx.fst
+++ /dev/null
Binary files differ
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index f5f265c..14c6038 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -91,6 +91,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_imem_wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_router.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index b7e7c30..b206f1d 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -59,7 +59,7 @@
output logic i2cm_rst_n ,
output logic usb_rst_n ,
- output logic [1:0] cfg_riscv_debug_sel,
+ output logic [15:0] cfg_riscv_ctrl,
// Reg Bus Interface Signal
input logic reg_cs,
@@ -365,7 +365,7 @@
.i2cm_rst_n (i2cm_rst_n ),
.usb_rst_n (usb_rst_n ),
- .cfg_riscv_debug_sel (cfg_riscv_debug_sel ),
+ .cfg_riscv_ctrl (cfg_riscv_ctrl ),
// Reg read/write Interface Inputs
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 265aab8..bb318d4 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -72,7 +72,7 @@
input logic i2cm_intr,
output logic [9:0] cfg_pulse_1us,
- output logic [1:0] cfg_riscv_debug_sel,
+ output logic [15:0] cfg_riscv_ctrl,
//---------------------------------------------------
// 6 PWM Configuration
@@ -319,7 +319,7 @@
);
assign cfg_pulse_1us = reg_2[9:0];
-assign cfg_riscv_debug_sel = reg_2[31:30];
+assign cfg_riscv_ctrl = reg_2[31:16];
//-----------------------------------------------------------------------
// reg-3 : Global Interrupt Mask
@@ -717,7 +717,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h2603_2022) u_reg_23 (
+gen_32b_reg #(32'h0104_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -730,9 +730,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.0 = 0004000
+// Software Reg-3: Poject Revison 4.1 = 0004100
// ----------------------------------------
-gen_32b_reg #(32'h0004_0000) u_reg_24 (
+gen_32b_reg #(32'h0004_1000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index bd9e315..5c02cd7 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -198,6 +198,8 @@
//// 4. caravel wb addressing issue restrict to 0x300FFFFF////
//// 4.0 Mar 26 2022, Dinesh A ////
//// 1. Four core risc v integration ////
+//// 4.1 April 1 2022, Dinesh A ////
+//// 1. sram lanuch phase control added inside risc core ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -583,7 +585,14 @@
wire [3:0] spi_csn ;
-wire [1:0] cfg_riscv_debug_sel ;
+
+//--------------------------------------------------------------------------
+// Pinmux Risc core config
+// -------------------------------------------------------------------------
+wire [15:0] cfg_riscv_ctrl;
+wire [3:0] cfg_riscv_sram_lphase = cfg_riscv_ctrl[3:0];
+wire [2:0] cfg_riscv_cache_ctrl = cfg_riscv_ctrl[6:4];
+wire [1:0] cfg_riscv_debug_sel = cfg_riscv_ctrl[9:8];
/////////////////////////////////////////////////////////
// Clock Skew Ctrl
@@ -679,6 +688,8 @@
.cpu_core_rst_n (cpu_core_rst_n ),
.riscv_debug (riscv_debug ),
.core_debug_sel (cfg_riscv_debug_sel ),
+ .cfg_sram_lphase (cfg_riscv_sram_lphase ),
+ .cfg_cache_ctrl (cfg_riscv_cache_ctrl ),
// Clock
.core_clk (cpu_clk ),
@@ -1153,7 +1164,7 @@
.i2cm_rst_n (i2c_rst_n ),
.usb_rst_n (usb_rst_n ),
- .cfg_riscv_debug_sel (cfg_riscv_debug_sel ),
+ .cfg_riscv_ctrl (cfg_riscv_ctrl ),
// Reg Bus Interface Signal
.reg_cs (wbd_glbl_stb_o ),
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c
index 7841cdc..53ae743 160000
--- a/verilog/rtl/yifive/ycr4c
+++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@
-Subproject commit 7841cdc26eafd7ebd83aadc4e0a9a7da5a13da3f
+Subproject commit 53ae7435180d758ffd1833f224fd4e1f7b4d65a8
