mpw-6 tool update
diff --git a/openlane/Makefile b/openlane/Makefile index e2e91a5..aea51b8 100644 --- a/openlane/Makefile +++ b/openlane/Makefile
@@ -1,5 +1,4 @@ # SPDX-FileCopyrightText: 2020 Efabless Corporation -# # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at @@ -13,16 +12,16 @@ # limitations under the License. # # SPDX-License-Identifier: Apache-2.0 - #SHELL = sh -xv + BLOCKS = $(shell find * -maxdepth 0 -type d) CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl) CLEAN = $(foreach block,$(BLOCKS), clean-$(block)) -OPENLANE_TAG = mpw5 -OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG) -OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite" -OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite" +OPENLANE_TAG ?= mpw6 +OPENLANE_IMAGE_NAME ?= riscduino/openlane:$(OPENLANE_TAG) +OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite" +OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl" all: $(BLOCKS) @@ -30,18 +29,45 @@ @echo "Missing $@. Please create a configuration for that design" @exit 1 -$(BLOCKS) : % : ./%/config.tcl FORCE +.PHONY: $(BLOCKS) +$(BLOCKS) : % : ./%/config.tcl +ifeq ($(OPENLANE_ROOT),) + @echo "Please export OPENLANE_ROOT" + @exit 1 +endif +ifeq ($(PDK_ROOT),) + @echo "Please export PDK_ROOT" + @exit 1 +endif @echo "###############################################" @sleep 1 @if [ -f ./$*/interactive.tcl ]; then\ - docker run -it \ - -v $(PWD)/..:/project \ + docker run --rm -v $(OPENLANE_ROOT):/openlane \ + -v $(PDK_ROOT):$(PDK_ROOT) \ + -v $(PWD)/..:$(PWD)/.. \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -e MCW_ROOT=$(MCW_ROOT) \ + -e PDK_ROOT=$(PDK_ROOT) \ + -e CARAVEL_ROOT=$(CARAVEL_ROOT) \ + -e PDK=$(PDK) \ + -e TEST_MISMATCHES=tools \ + -e MISMATCHES_OK=1 \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\ else\ - docker run -it \ - -v $(PWD)/..:/project \ + docker run --rm -v $(OPENLANE_ROOT):/openlane \ + -v $(PDK_ROOT):$(PDK_ROOT) \ + -v $(PWD)/..:$(PWD)/.. \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -e MCW_ROOT=$(MCW_ROOT) \ + -e PDK=$(PDK) \ + -e PDK_ROOT=$(PDK_ROOT) \ + -e CARAVEL_ROOT=$(CARAVEL_ROOT) \ + -e TEST_MISMATCHES=tools \ + -e MISMATCHES_OK=1 \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \ $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\ fi @@ -50,6 +76,25 @@ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/ +.PHONY: openlane +openlane: check-openlane-env + if [ -d "$(OPENLANE_ROOT)" ]; then\ + echo "Deleting exisiting $(OPENLANE_ROOT)" && \ + rm -rf $(OPENLANE_ROOT) && sleep 2; \ + fi + git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \ + cd $(OPENLANE_ROOT) && \ + export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \ + export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \ + $(MAKE) pull-openlane + +.PHONY: check-openlane-env +check-openlane-env: +ifeq ($(OPENLANE_ROOT),) + @echo "Please export OPENLANE_ROOT" + @exit 1 +endif + FORCE: clean:
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl index 68f6db6..7650732 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux/config.tcl
@@ -97,7 +97,7 @@ set ::env(FP_PDN_VWIDTH) 5 set ::env(FP_PDN_HWIDTH) 5 -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl index e2a3b24..f17f63d 100755 --- a/openlane/qspim_top/config.tcl +++ b/openlane/qspim_top/config.tcl
@@ -93,7 +93,7 @@ set ::env(FP_PDN_VWIDTH) 5 set ::env(FP_PDN_HWIDTH) 5 -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 47fba8d..d42ea05 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -102,7 +102,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.45" +set ::env(PL_TARGET_DENSITY) "0.46" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" @@ -115,7 +115,7 @@ set ::env(FP_PDN_VWIDTH) 5 set ::env(FP_PDN_HWIDTH) 5 -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4 @@ -123,6 +123,8 @@ set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1} set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1} +set ::env(GLB_RT_ADJUSTMENT) {0.25} + set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 1dabc40..4ebb2bb 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -97,7 +97,7 @@ set ::env(FP_PDN_VWIDTH) 5 set ::env(FP_PDN_HWIDTH) 5 -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 2b03cd9..33ac3c6 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -113,7 +113,7 @@ set ::env(GLB_RT_ALLOW_CONGESTION) 0 set ::env(GLB_RT_OVERFLOW_ITERS) 200 -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl index d938d00..5ce3013 100644 --- a/openlane/ycr2_iconnect/config.tcl +++ b/openlane/ycr2_iconnect/config.tcl
@@ -83,7 +83,8 @@ #set ::env(FP_PDN_HWIDTH) "3.1" -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 +set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 3038a4e..ff498c8 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -78,7 +78,7 @@ set ::env(PL_TARGET_DENSITY) 0.40 set ::env(CELL_PAD) "4" -set ::env(GLB_RT_MAXLAYER) 5 +#set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index b6a0f68..602c0fa 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -72,7 +72,7 @@ set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAXLAYER) "5" +#set ::env(GLB_RT_MAXLAYER) "5" set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/verilog/rtl/usb1_host/src/top/usb1_host.sv b/verilog/rtl/usb1_host/src/top/usb1_host.sv index 6ee0ff5..6f92942 100644 --- a/verilog/rtl/usb1_host/src/top/usb1_host.sv +++ b/verilog/rtl/usb1_host/src/top/usb1_host.sv
@@ -112,13 +112,35 @@ logic [31:0] reg_rdata; logic reg_ack; + logic wbm_rst_ssn; + logic usb_rst_ssn; +//################################### +// Wishbone Reset Synchronization +//################################### +reset_sync u_wb_rst ( + .scan_mode (1'b0 ), + .dclk (wbm_clk_i ), // Destination clock domain + .arst_n (wbm_rst_n ), // active low async reset + .srst_n (wbm_rst_ssn ) + ); + +//################################### +// USB Reset Synchronization +//################################### +reset_sync u_usb_rst ( + .scan_mode (1'b0 ), + .dclk (usb_clk_i ), // Destination clock domain + .arst_n (usb_rstn_i ), // active low async reset + .srst_n (usb_rst_ssn ) + ); + async_wb #(.AW (6)) u_async_wb( // Master Port - .wbm_rst_n (wbm_rst_n ), // Regular Reset signal + .wbm_rst_n (wbm_rst_ssn ), // Regular Reset signal .wbm_clk_i (wbm_clk_i ), // System clock .wbm_cyc_i (wbm_stb_i ), // strobe/request .wbm_stb_i (wbm_stb_i ), // strobe/request @@ -131,7 +153,7 @@ .wbm_err_o (wbm_err_o ), // error // Slave Port - .wbs_rst_n (usb_rstn_i ), // Regular Reset signal + .wbs_rst_n (usb_rst_ssn ), // Regular Reset signal .wbs_clk_i (usb_clk_i ), // System clock .wbs_cyc_o ( ), // strobe/request .wbs_stb_o (reg_cs ), // strobe/request @@ -148,7 +170,7 @@ usbh_core u_core ( // Inputs .clk_i (usb_clk_i ), - .rstn_i (usb_rstn_i ), + .rstn_i (usb_rst_ssn ), .reg_cs (reg_cs ), .reg_wr (reg_wr ), @@ -185,7 +207,7 @@ usb_fs_phy u_phy( // Inputs .clk_i (usb_clk_i ), - .rstn_i (usb_rstn_i ), + .rstn_i (usb_rst_ssn ), .utmi_data_out_i (utmi_data_out_o ), .utmi_txvalid_i (utmi_txvalid_o ), .utmi_op_mode_i (utmi_op_mode_o ),