test bench cleanup
diff --git a/verilog/dv/firmware/crt.S b/verilog/dv/firmware/crt.S
index d50cb6b..c1ffa33 100644
--- a/verilog/dv/firmware/crt.S
+++ b/verilog/dv/firmware/crt.S
@@ -60,7 +60,7 @@
// Timer init
li t0, mtime_ctrl
- li t1, (1 << YCR1_MTIME_CTRL_EN) // enable, use internal clock
+ li t1, (1 << YCR_MTIME_CTRL_EN) // enable, use internal clock
sw t1, (t0)
li t0, mtime_div
li t1, (100-1) // divide by 100
diff --git a/verilog/dv/firmware/riscv_csr_encoding.h b/verilog/dv/firmware/riscv_csr_encoding.h
index 09f5abb..bf7736a 100644
--- a/verilog/dv/firmware/riscv_csr_encoding.h
+++ b/verilog/dv/firmware/riscv_csr_encoding.h
@@ -1486,4 +1486,4 @@
DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
#endif
-#include "ycr1_specific.h"
+#include "ycr_specific.h"
diff --git a/verilog/dv/firmware/ycr1_specific.h b/verilog/dv/firmware/ycr_specific.h
similarity index 88%
rename from verilog/dv/firmware/ycr1_specific.h
rename to verilog/dv/firmware/ycr_specific.h
index 4c8c583..04201e5 100644
--- a/verilog/dv/firmware/ycr1_specific.h
+++ b/verilog/dv/firmware/ycr_specific.h
@@ -16,8 +16,8 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> ////
//////////////////////////////////////////////////////////////////////////////
-#ifndef __YCR1__SPECIFIC
-#define __YCR1__SPECIFIC
+#ifndef __YCR__SPECIFIC
+#define __YCR__SPECIFIC
#define mcounten 0x7E0
@@ -29,10 +29,10 @@
#define mtimecmp 0x0C490010
#define mtimecmph 0x0C490014
-#define YCR1_MTIME_CTRL_EN 0
-#define YCR1_MTIME_CTRL_CLKSRC 1
+#define YCR_MTIME_CTRL_EN 0
+#define YCR_MTIME_CTRL_CLKSRC 1
-#define YCR1_MTIME_CTRL_WR_MASK 0x3
-#define YCR1_MTIME_DIV_WR_MASK 0x3FF
+#define YCR_MTIME_CTRL_WR_MASK 0x3
+#define YCR_MTIME_DIV_WR_MASK 0x3FF
#endif // _YCR1__SPECIFIC
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index 99e0204..4a82878 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -34,7 +34,8 @@
while(1) {
// Check UART RX fifo has data, if available loop back the data
- if(reg_mprj_uart_reg8 != 0) {
+ // Also check txfifo is not full
+ if((reg_mprj_uart_reg8 != 0) && ((reg_mprj_uart_reg4 & 0x1) != 0x1)) {
reg_mprj_uart_reg5 = reg_mprj_uart_reg6;
}
}