pinmux register remap as glbl,gpio,timer,pwm,semaphore
diff --git a/Makefile b/Makefile
index ff82bc4..8daccc0 100644
--- a/Makefile
+++ b/Makefile
@@ -143,15 +143,22 @@
# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
.PHONY: precheck
precheck:
- @git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+ @git clone --depth=1 --branch $(MPW_TAG) https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
@docker pull efabless/mpw_precheck:latest
.PHONY: run-precheck
run-precheck: check-pdk check-precheck
$(eval INPUT_DIRECTORY := $(shell pwd))
cd $(PRECHECK_ROOT) && \
- docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
- -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+ docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+ -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+ -e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e PDKPATH=$(PDKPATH) \
+ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"
diff --git a/openlane/Makefile b/openlane/Makefile
index 865f452..c21989a 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -18,7 +18,7 @@
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
-OPENLANE_TAG = mpw5
+OPENLANE_TAG = mpw7
OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl"
@@ -43,15 +43,29 @@
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e PDK=$(PDK) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run --rm \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK=$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
diff --git a/openlane/Read.me b/openlane/Read.me
index c0c9895..e69de29 100644
--- a/openlane/Read.me
+++ b/openlane/Read.me
@@ -1,3 +0,0 @@
-ycr2_mintf harden with riscduino/openlane:mpw4 (mpw5 version not able to root due to conjuestion)
-Rest of the cores & top-level are harden with riscduino/openlane:mpw5 docker
-
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
deleted file mode 100755
index f844215..0000000
--- a/openlane/pinmux/config.tcl
+++ /dev/null
@@ -1,113 +0,0 @@
-# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
-
-# Global
-# ------
-
-set script_dir [file dirname [file normalize [info script]]]
-# Name
-
-set ::env(DESIGN_NAME) pinmux
-
-set ::env(DESIGN_IS_CORE) "0"
-set ::env(FP_PDN_CORE_RING) "0"
-
-# Timing configuration
-set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "mclk"
-
-set ::env(SYNTH_MAX_FANOUT) 4
-
-## CTS BUFFER
-set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
-set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
-set ::env(CLOCK_BUFFER_FANOUT) "8"
-
-# Sources
-# -------
-
-# Local sources + no2usb sources
-set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \
- $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \
- $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \
- $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \
- $script_dir/../../verilog/rtl/pinmux/src/timer.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \
- $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- "
-
-
-set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
-
-set ::env(LEC_ENABLE) 0
-
-set ::env(VDD_PIN) [list {vccd1}]
-set ::env(GND_PIN) [list {vssd1}]
-
-
-# Floorplanning
-# -------------
-
-set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
-
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 550 450"
-
-
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
-
-#set ::env(PDN_CFG) $script_dir/pdn.tcl
-
-
-set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
-set ::env(CELL_PAD) "4"
-
-set ::env(FP_IO_VEXTEND) {6}
-set ::env(FP_IO_HEXTEND) {6}
-
-
-# helps in anteena fix
-set ::env(USE_ARC_ANTENNA_CHECK) "0"
-
-set ::env(FP_IO_VEXTEND) 4
-set ::env(FP_IO_HEXTEND) 4
-
-set ::env(FP_PDN_VPITCH) 100
-set ::env(FP_PDN_HPITCH) 100
-set ::env(FP_PDN_VWIDTH) 5
-set ::env(FP_PDN_HWIDTH) 5
-
-#set ::env(GLB_RT_MAXLAYER) 5
-set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
-set ::env(DIODE_INSERTION_STRATEGY) 4
-
-
-set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "1"
-set ::env(QUIT_ON_LVS_ERROR) "1"
-set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux_top/base.sdc
similarity index 98%
rename from openlane/pinmux/base.sdc
rename to openlane/pinmux_top/base.sdc
index 91f9b40..2aa686d 100644
--- a/openlane/pinmux/base.sdc
+++ b/openlane/pinmux_top/base.sdc
@@ -10,7 +10,7 @@
set_propagated_clock [get_clocks {mclk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
new file mode 100755
index 0000000..57819dc
--- /dev/null
+++ b/openlane/pinmux_top/config.tcl
@@ -0,0 +1,121 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) pinmux_top
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/semaphore_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ "
+
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 500 400"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.40"
+set ::env(CELL_PAD) "4"
+
+set ::env(FP_IO_VEXTEND) {6}
+set ::env(FP_IO_HEXTEND) {6}
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 5
+set ::env(FP_PDN_HWIDTH) 5
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
similarity index 99%
rename from openlane/pinmux/pin_order.cfg
rename to openlane/pinmux_top/pin_order.cfg
index baa31fd..6dc053a 100644
--- a/openlane/pinmux/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -129,6 +129,7 @@
reg_cs 200 0
reg_wr
+reg_addr\[8\]
reg_addr\[7\]
reg_addr\[6\]
reg_addr\[5\]
diff --git a/openlane/qspim_top/base.sdc b/openlane/qspim_top/base.sdc
index 327d1f4..c0e8993 100644
--- a/openlane/qspim_top/base.sdc
+++ b/openlane/qspim_top/base.sdc
@@ -24,7 +24,7 @@
set_propagated_clock [get_clocks {spiclk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index 187e486..0ce98bf 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -41,23 +41,23 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/lib/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_fifo.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \
- $script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_regs.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_clkgen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_ctrl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_rx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_tx.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -95,7 +95,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
index 4a33fc5..35bba97 100644
--- a/openlane/uart_i2cm_usb_spi_top/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -12,7 +12,7 @@
create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
@@ -44,9 +44,9 @@
set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
-set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 5.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}]
-set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 5.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 802f0cf..39350c5 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -41,44 +41,45 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/uart/src/uart_core.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
- $script_dir/../../verilog/rtl/lib/async_wb.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/lib/double_sync_low.v \
- $script_dir/../../verilog/rtl/lib/clk_ctl.v \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \
- $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \
- $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \
- $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
- $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_top.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_if.sv \
- $script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv \
- $script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo_th.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_top.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
+ $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_ctl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_cfg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_clkgen.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
"
set ::env(SYNTH_NO_FLAT) {1}
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/includes $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/includes ]
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -91,7 +92,7 @@
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) "absolute"
-set ::env(DIE_AREA) [list 0.0 0.0 510.0 725.0]
+set ::env(DIE_AREA) [list 0.0 0.0 520.0 725.0]
@@ -117,13 +118,14 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
-set ::env(GLB_RT_ADJUSTMENT) {0.25}
+#set ::env(GLB_RT_ADJUSTMENT) {0.25}
+set ::env(GLB_RT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0}
set ::env(CELL_PAD) {2}
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 1c6fc4f..8bace80 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,36 +16,34 @@
# Base Configurations. Don't Touch
# section begin
-set ::env(PDK) "sky130A"
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
+source $::env(DESIGN_DIR)/fixed_dont_change/fixed_wrapper_cfgs.tcl
# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
-source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
+source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl
set script_dir [file dirname [file normalize [info script]]]
set proj_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) user_project_wrapper
-set verilog_root $proj_dir/../../verilog/
-set lef_root $proj_dir/../../lef/
-set gds_root $proj_dir/../../gds/
+set verilog_root $::env(DESIGN_DIR)/../../verilog/
+set lef_root $::env(DESIGN_DIR)/../../lef/
+set gds_root $::env(DESIGN_DIR)/../../gds/
#section end
# User Configurations
#
set ::env(DESIGN_IS_CORE) 1
-set ::env(FP_PDN_CORE_RING) 1
## Source Verilog Files
set ::env(VERILOG_FILES) "\
- $proj_dir/../../verilog/rtl//yifive/ycr2c/src/top/ycr2_top_wb.sv \
- $proj_dir/../../verilog/rtl/user_project_wrapper.v"
+ $::env(DESIGN_DIR)/../../verilog/rtl//yifive/ycr2c/src/top/ycr2_top_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
## Clock configurations
@@ -56,33 +54,32 @@
## Internal Macros
### Macro Placement
-set ::env(FP_SIZING) "absolute"
-set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
-set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl
+#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl
-set ::env(SDC_FILE) "$proj_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
### Black-box verilog and views
set ::env(VERILOG_FILES_BLACKBOX) "\
- $proj_dir/../../verilog/gl/qspim_top.v \
- $proj_dir/../../verilog/gl/wb_interconnect.v \
- $proj_dir/../../verilog/gl/pinmux.v \
- $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \
- $proj_dir/../../verilog/gl/wb_host.v \
- $proj_dir/../../verilog/gl/ycr_intf.v \
- $proj_dir/../../verilog/gl/ycr_core_top.v \
- $proj_dir/../../verilog/gl/ycr2_iconnect.v \
- $proj_dir/../../verilog/gl/digital_pll.v \
- $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/pinmux_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/ycr2_iconnect.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \
+ $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \
"
set ::env(EXTRA_LEFS) "\
$lef_root/qspim_top.lef \
- $lef_root/pinmux.lef \
+ $lef_root/pinmux_top.lef \
$lef_root/wb_interconnect.lef \
$lef_root/uart_i2c_usb_spi_top.lef \
$lef_root/wb_host.lef \
@@ -90,12 +87,12 @@
$lef_root/ycr_core_top.lef \
$lef_root/ycr2_iconnect.lef \
$lef_root/digital_pll.lef \
- $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
+ $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
"
set ::env(EXTRA_GDS_FILES) "\
$gds_root/qspim_top.gds \
- $gds_root/pinmux.gds \
+ $gds_root/pinmux_top.gds \
$gds_root/wb_interconnect.gds \
$gds_root/uart_i2c_usb_spi_top.gds \
$gds_root/wb_host.gds \
@@ -103,12 +100,12 @@
$gds_root/ycr_core_top.gds \
$gds_root/ycr2_iconnect.gds \
$gds_root/digital_pll.gds \
- $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
+ $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/includes ]
#set ::env(GLB_RT_MAXLAYER) 6
set ::env(RT_MAX_LAYER) {met5}
@@ -119,15 +116,15 @@
## Internal Macros
### Macro PDN Connections
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
-set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
+#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
-set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
-set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
-#
+set ::env(VDD_NET) {vccd1}
set ::env(VDD_PIN) {vccd1}
+set ::env(GND_NET) {vssd1}
set ::env(GND_PIN) {vssd1}
-set ::env(GLB_RT_OBS) " \
+
+set ::env(GRT_OBS) " \
li1 150 130 833.1 546.54,\
met1 150 130 833.1 546.54,\
met2 150 130 833.1 546.54,\
@@ -138,37 +135,30 @@
met2 950 130 1633.1 546.54,\
met3 950 130 1633.1 546.54,\
- li1 150 750 833.1 1166.54,\
- met1 150 750 833.1 1166.54,\
- met2 150 750 833.1 1166.54,\
- met3 150 750 833.1 1166.54,\
- met1 950 650 1760 660 ,\
- met3 950 650 1760 660 ,\
- met1 2250 2150 2800 2600,\
- met2 2250 2150 2800 2600,\
- met3 2250 2150 2800 2600,\
+ li1 150 750 833.1 1166.54,\
+ met1 150 750 833.1 1166.54,\
+ met2 150 750 833.1 1166.54,\
+ met3 150 750 833.1 1166.54,\
met5 0 0 2920 3520"
-set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
+#set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1"
-#set ::env(FP_PDN_MACRO_HOOKS) " \
-# u_intercon vccd1 vssd1,\
-# u_pinmux vccd1 vssd1,\
-# u_qspi_master vccd1 vssd1,\
-# u_riscv_top vccd1 vssd1,\
-# u_tsram0_2kb vccd1 vssd1,\
-# u_icache_2kb vccd1 vssd1,\
-# u_dcache_2kb vccd1 vssd1,\
-# u_sram0_2kb vccd1 vssd1,\
-# u_sram1_2kb vccd1 vssd1,\
-# u_sram2_2kb vccd1 vssd1,\
-# u_sram3_2kb vccd1 vssd1,\
-# u_uart_i2c_usb_spi vccd1 vssd1,\
-# u_wb_host vccd1 vssd1,\
-# u_riscv_top.i_core_top_0 vccd1 vssd1, \
-# u_riscv_top.i_core_top_1 vccd1 vssd1, \
-# u_riscv_top.u_intf vccd1 vssd1 \
-# "
+set ::env(FP_PDN_MACRO_HOOKS) " \
+ u_pll vccd1 vssd1 VPWR VGND, \
+ u_intercon vccd1 vssd1 vccd1 vssd1,\
+ u_pinmux vccd1 vssd1 vccd1 vssd1,\
+ u_qspi_master vccd1 vssd1 vccd1 vssd1,\
+ u_tsram0_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_icache_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_dcache_2kb vccd1 vssd1 vccd1 vssd1,\
+ u_uart_i2c_usb_spi vccd1 vssd1 vccd1 vssd1,\
+ u_wb_host vccd1 vssd1 vccd1 vssd1,\
+ u_riscv_top.i_core_top_0 vccd1 vssd1 vccd1 vssd1, \
+ u_riscv_top.i_core_top_1 vccd1 vssd1 vccd1 vssd1, \
+ u_riscv_top.u_connect vccd1 vssd1 VPWR VGND, \
+ u_riscv_top.u_intf vccd1 vssd1 vccd1 vssd1 \
+ "
+
# The following is because there are no std cells in the example wrapper project.
@@ -188,14 +178,15 @@
set ::env(QUIT_ON_NEGATIVE_WNS) "0"
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(FP_PDN_IRDROP) "0"
+
+set ::env(FP_PDN_IRDROP) "1"
set ::env(FP_PDN_HORIZONTAL_HALO) "10"
set ::env(FP_PDN_VERTICAL_HALO) "10"
+
+#
+
set ::env(FP_PDN_VOFFSET) "5"
-set ::env(FP_PDN_VPITCH) "80"
-set ::env(FP_PDN_VSPACING) "15.5"
-set ::env(FP_PDN_VWIDTH) "3.1"
-set ::env(FP_PDN_HOFFSET) "10"
-set ::env(FP_PDN_HPITCH) "90"
-set ::env(FP_PDN_HSPACING) "10"
-set ::env(FP_PDN_HWIDTH) "3.1"
+set ::env(FP_PDN_VPITCH) "180"
+set ::env(FP_PDN_HOFFSET) "5"
+set ::env(FP_PDN_HPITCH) "180"
+
diff --git a/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
new file mode 100644
index 0000000..4a4f8a2
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl
@@ -0,0 +1,24 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# THE FOLLOWING SECTIONS CAN BE CHANGED IF NEEDED
+
+# PDN Pitch
+set ::env(FP_PDN_VPITCH) 180
+set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
+
+# PDN Offset
+set ::env(FP_PDN_VOFFSET) 5
+set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
\ No newline at end of file
diff --git a/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
new file mode 100644
index 0000000..e602da7
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl
@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# DON'T TOUCH THE FOLLOWING SECTIONS
+set script_dir [file dirname [file normalize [info script]]]
+
+# This makes sure that the core rings are outside the boundaries
+# of your block.
+set ::env(MAGIC_ZEROIZE_ORIGIN) 0
+
+# Area Configurations. DON'T TOUCH.
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2920 3520"
+
+set ::env(RUN_CVC) 0
+
+set ::unit 2.4
+set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
+set ::env(FP_IO_VLENGTH) $::unit
+set ::env(FP_IO_HLENGTH) $::unit
+
+set ::env(FP_IO_VTHICKNESS_MULT) 4
+set ::env(FP_IO_HTHICKNESS_MULT) 4
+
+# Power & Pin Configurations. DON'T TOUCH.
+set ::env(FP_PDN_CORE_RING) 1
+set ::env(FP_PDN_CORE_RING_VWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_HWIDTH) 3.1
+set ::env(FP_PDN_CORE_RING_VOFFSET) 12.45
+set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
+set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
+set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
+
+set ::env(FP_PDN_VWIDTH) 3.1
+set ::env(FP_PDN_HWIDTH) 3.1
+set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
+set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
+
+set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
+set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
+
+# Pin placement template
+set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/fixed_dont_change/user_project_wrapper.def
diff --git a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
new file mode 100644
index 0000000..7bf40c0
--- /dev/null
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
@@ -0,0 +1,14496 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN user_project_wrapper ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 2920000 3520000 ) ;
+ROW ROW_0 unithd 5520 10880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 5520 13600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 5520 16320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 5520 19040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 5520 21760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 5520 24480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 5520 27200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 5520 29920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 5520 32640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 5520 35360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 5520 38080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 5520 40800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_12 unithd 5520 43520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_13 unithd 5520 46240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_14 unithd 5520 48960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_15 unithd 5520 51680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_16 unithd 5520 54400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_17 unithd 5520 57120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_18 unithd 5520 59840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_19 unithd 5520 62560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_20 unithd 5520 65280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_21 unithd 5520 68000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_22 unithd 5520 70720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_23 unithd 5520 73440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_24 unithd 5520 76160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_25 unithd 5520 78880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_26 unithd 5520 81600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_27 unithd 5520 84320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_28 unithd 5520 87040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_29 unithd 5520 89760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_30 unithd 5520 92480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_31 unithd 5520 95200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_32 unithd 5520 97920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_33 unithd 5520 100640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_34 unithd 5520 103360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_35 unithd 5520 106080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_36 unithd 5520 108800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_37 unithd 5520 111520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_38 unithd 5520 114240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_39 unithd 5520 116960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_40 unithd 5520 119680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_41 unithd 5520 122400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_42 unithd 5520 125120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_43 unithd 5520 127840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_44 unithd 5520 130560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_45 unithd 5520 133280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_46 unithd 5520 136000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_47 unithd 5520 138720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_48 unithd 5520 141440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_49 unithd 5520 144160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_50 unithd 5520 146880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_51 unithd 5520 149600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_52 unithd 5520 152320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_53 unithd 5520 155040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_54 unithd 5520 157760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_55 unithd 5520 160480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_56 unithd 5520 163200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_57 unithd 5520 165920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_58 unithd 5520 168640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_59 unithd 5520 171360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_60 unithd 5520 174080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_61 unithd 5520 176800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_62 unithd 5520 179520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_63 unithd 5520 182240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_64 unithd 5520 184960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_65 unithd 5520 187680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_66 unithd 5520 190400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_67 unithd 5520 193120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_68 unithd 5520 195840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_69 unithd 5520 198560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_70 unithd 5520 201280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_71 unithd 5520 204000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_72 unithd 5520 206720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_73 unithd 5520 209440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_74 unithd 5520 212160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_75 unithd 5520 214880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_76 unithd 5520 217600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_77 unithd 5520 220320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_78 unithd 5520 223040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_79 unithd 5520 225760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_80 unithd 5520 228480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_81 unithd 5520 231200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_82 unithd 5520 233920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_83 unithd 5520 236640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_84 unithd 5520 239360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_85 unithd 5520 242080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_86 unithd 5520 244800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_87 unithd 5520 247520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_88 unithd 5520 250240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_89 unithd 5520 252960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_90 unithd 5520 255680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_91 unithd 5520 258400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_92 unithd 5520 261120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_93 unithd 5520 263840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_94 unithd 5520 266560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_95 unithd 5520 269280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_96 unithd 5520 272000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_97 unithd 5520 274720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_98 unithd 5520 277440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_99 unithd 5520 280160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_100 unithd 5520 282880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_101 unithd 5520 285600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_102 unithd 5520 288320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_103 unithd 5520 291040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_104 unithd 5520 293760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_105 unithd 5520 296480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_106 unithd 5520 299200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_107 unithd 5520 301920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_108 unithd 5520 304640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_109 unithd 5520 307360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_110 unithd 5520 310080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_111 unithd 5520 312800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_112 unithd 5520 315520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_113 unithd 5520 318240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_114 unithd 5520 320960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_115 unithd 5520 323680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_116 unithd 5520 326400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_117 unithd 5520 329120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_118 unithd 5520 331840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_119 unithd 5520 334560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_120 unithd 5520 337280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_121 unithd 5520 340000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_122 unithd 5520 342720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_123 unithd 5520 345440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_124 unithd 5520 348160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_125 unithd 5520 350880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_126 unithd 5520 353600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_127 unithd 5520 356320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_128 unithd 5520 359040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_129 unithd 5520 361760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_130 unithd 5520 364480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_131 unithd 5520 367200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_132 unithd 5520 369920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_133 unithd 5520 372640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_134 unithd 5520 375360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_135 unithd 5520 378080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_136 unithd 5520 380800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_137 unithd 5520 383520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_138 unithd 5520 386240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_139 unithd 5520 388960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_140 unithd 5520 391680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_141 unithd 5520 394400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_142 unithd 5520 397120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_143 unithd 5520 399840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_144 unithd 5520 402560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_145 unithd 5520 405280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_146 unithd 5520 408000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_147 unithd 5520 410720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_148 unithd 5520 413440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_149 unithd 5520 416160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_150 unithd 5520 418880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_151 unithd 5520 421600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_152 unithd 5520 424320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_153 unithd 5520 427040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_154 unithd 5520 429760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_155 unithd 5520 432480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_156 unithd 5520 435200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_157 unithd 5520 437920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_158 unithd 5520 440640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_159 unithd 5520 443360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_160 unithd 5520 446080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_161 unithd 5520 448800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_162 unithd 5520 451520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_163 unithd 5520 454240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_164 unithd 5520 456960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_165 unithd 5520 459680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_166 unithd 5520 462400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_167 unithd 5520 465120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_168 unithd 5520 467840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_169 unithd 5520 470560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_170 unithd 5520 473280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_171 unithd 5520 476000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_172 unithd 5520 478720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_173 unithd 5520 481440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_174 unithd 5520 484160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_175 unithd 5520 486880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_176 unithd 5520 489600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_177 unithd 5520 492320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_178 unithd 5520 495040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_179 unithd 5520 497760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_180 unithd 5520 500480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_181 unithd 5520 503200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_182 unithd 5520 505920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_183 unithd 5520 508640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_184 unithd 5520 511360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_185 unithd 5520 514080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_186 unithd 5520 516800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_187 unithd 5520 519520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_188 unithd 5520 522240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_189 unithd 5520 524960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_190 unithd 5520 527680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_191 unithd 5520 530400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_192 unithd 5520 533120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_193 unithd 5520 535840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_194 unithd 5520 538560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_195 unithd 5520 541280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_196 unithd 5520 544000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_197 unithd 5520 546720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_198 unithd 5520 549440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_199 unithd 5520 552160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_200 unithd 5520 554880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_201 unithd 5520 557600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_202 unithd 5520 560320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_203 unithd 5520 563040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_204 unithd 5520 565760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_205 unithd 5520 568480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_206 unithd 5520 571200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_207 unithd 5520 573920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_208 unithd 5520 576640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_209 unithd 5520 579360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_210 unithd 5520 582080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_211 unithd 5520 584800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_212 unithd 5520 587520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_213 unithd 5520 590240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_214 unithd 5520 592960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_215 unithd 5520 595680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_216 unithd 5520 598400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_217 unithd 5520 601120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_218 unithd 5520 603840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_219 unithd 5520 606560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_220 unithd 5520 609280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_221 unithd 5520 612000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_222 unithd 5520 614720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_223 unithd 5520 617440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_224 unithd 5520 620160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_225 unithd 5520 622880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_226 unithd 5520 625600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_227 unithd 5520 628320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_228 unithd 5520 631040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_229 unithd 5520 633760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_230 unithd 5520 636480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_231 unithd 5520 639200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_232 unithd 5520 641920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_233 unithd 5520 644640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_234 unithd 5520 647360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_235 unithd 5520 650080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_236 unithd 5520 652800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_237 unithd 5520 655520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_238 unithd 5520 658240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_239 unithd 5520 660960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_240 unithd 5520 663680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_241 unithd 5520 666400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_242 unithd 5520 669120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_243 unithd 5520 671840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_244 unithd 5520 674560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_245 unithd 5520 677280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_246 unithd 5520 680000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_247 unithd 5520 682720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_248 unithd 5520 685440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_249 unithd 5520 688160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_250 unithd 5520 690880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_251 unithd 5520 693600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_252 unithd 5520 696320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_253 unithd 5520 699040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_254 unithd 5520 701760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_255 unithd 5520 704480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_256 unithd 5520 707200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_257 unithd 5520 709920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_258 unithd 5520 712640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_259 unithd 5520 715360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_260 unithd 5520 718080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_261 unithd 5520 720800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_262 unithd 5520 723520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_263 unithd 5520 726240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_264 unithd 5520 728960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_265 unithd 5520 731680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_266 unithd 5520 734400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_267 unithd 5520 737120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_268 unithd 5520 739840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_269 unithd 5520 742560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_270 unithd 5520 745280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_271 unithd 5520 748000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_272 unithd 5520 750720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_273 unithd 5520 753440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_274 unithd 5520 756160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_275 unithd 5520 758880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_276 unithd 5520 761600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_277 unithd 5520 764320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_278 unithd 5520 767040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_279 unithd 5520 769760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_280 unithd 5520 772480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_281 unithd 5520 775200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_282 unithd 5520 777920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_283 unithd 5520 780640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_284 unithd 5520 783360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_285 unithd 5520 786080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_286 unithd 5520 788800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_287 unithd 5520 791520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_288 unithd 5520 794240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_289 unithd 5520 796960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_290 unithd 5520 799680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_291 unithd 5520 802400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_292 unithd 5520 805120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_293 unithd 5520 807840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_294 unithd 5520 810560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_295 unithd 5520 813280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_296 unithd 5520 816000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_297 unithd 5520 818720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_298 unithd 5520 821440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_299 unithd 5520 824160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_300 unithd 5520 826880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_301 unithd 5520 829600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_302 unithd 5520 832320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_303 unithd 5520 835040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_304 unithd 5520 837760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_305 unithd 5520 840480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_306 unithd 5520 843200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_307 unithd 5520 845920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_308 unithd 5520 848640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_309 unithd 5520 851360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_310 unithd 5520 854080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_311 unithd 5520 856800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_312 unithd 5520 859520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_313 unithd 5520 862240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_314 unithd 5520 864960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_315 unithd 5520 867680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_316 unithd 5520 870400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_317 unithd 5520 873120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_318 unithd 5520 875840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_319 unithd 5520 878560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_320 unithd 5520 881280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_321 unithd 5520 884000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_322 unithd 5520 886720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_323 unithd 5520 889440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_324 unithd 5520 892160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_325 unithd 5520 894880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_326 unithd 5520 897600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_327 unithd 5520 900320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_328 unithd 5520 903040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_329 unithd 5520 905760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_330 unithd 5520 908480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_331 unithd 5520 911200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_332 unithd 5520 913920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_333 unithd 5520 916640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_334 unithd 5520 919360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_335 unithd 5520 922080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_336 unithd 5520 924800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_337 unithd 5520 927520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_338 unithd 5520 930240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_339 unithd 5520 932960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_340 unithd 5520 935680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_341 unithd 5520 938400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_342 unithd 5520 941120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_343 unithd 5520 943840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_344 unithd 5520 946560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_345 unithd 5520 949280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_346 unithd 5520 952000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_347 unithd 5520 954720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_348 unithd 5520 957440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_349 unithd 5520 960160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_350 unithd 5520 962880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_351 unithd 5520 965600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_352 unithd 5520 968320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_353 unithd 5520 971040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_354 unithd 5520 973760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_355 unithd 5520 976480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_356 unithd 5520 979200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_357 unithd 5520 981920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_358 unithd 5520 984640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_359 unithd 5520 987360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_360 unithd 5520 990080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_361 unithd 5520 992800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_362 unithd 5520 995520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_363 unithd 5520 998240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_364 unithd 5520 1000960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_365 unithd 5520 1003680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_366 unithd 5520 1006400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_367 unithd 5520 1009120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_368 unithd 5520 1011840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_369 unithd 5520 1014560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_370 unithd 5520 1017280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_371 unithd 5520 1020000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_372 unithd 5520 1022720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_373 unithd 5520 1025440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_374 unithd 5520 1028160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_375 unithd 5520 1030880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_376 unithd 5520 1033600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_377 unithd 5520 1036320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_378 unithd 5520 1039040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_379 unithd 5520 1041760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_380 unithd 5520 1044480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_381 unithd 5520 1047200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_382 unithd 5520 1049920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_383 unithd 5520 1052640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_384 unithd 5520 1055360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_385 unithd 5520 1058080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_386 unithd 5520 1060800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_387 unithd 5520 1063520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_388 unithd 5520 1066240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_389 unithd 5520 1068960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_390 unithd 5520 1071680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_391 unithd 5520 1074400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_392 unithd 5520 1077120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_393 unithd 5520 1079840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_394 unithd 5520 1082560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_395 unithd 5520 1085280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_396 unithd 5520 1088000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_397 unithd 5520 1090720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_398 unithd 5520 1093440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_399 unithd 5520 1096160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_400 unithd 5520 1098880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_401 unithd 5520 1101600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_402 unithd 5520 1104320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_403 unithd 5520 1107040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_404 unithd 5520 1109760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_405 unithd 5520 1112480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_406 unithd 5520 1115200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_407 unithd 5520 1117920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_408 unithd 5520 1120640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_409 unithd 5520 1123360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_410 unithd 5520 1126080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_411 unithd 5520 1128800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_412 unithd 5520 1131520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_413 unithd 5520 1134240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_414 unithd 5520 1136960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_415 unithd 5520 1139680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_416 unithd 5520 1142400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_417 unithd 5520 1145120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_418 unithd 5520 1147840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_419 unithd 5520 1150560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_420 unithd 5520 1153280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_421 unithd 5520 1156000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_422 unithd 5520 1158720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_423 unithd 5520 1161440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_424 unithd 5520 1164160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_425 unithd 5520 1166880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_426 unithd 5520 1169600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_427 unithd 5520 1172320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_428 unithd 5520 1175040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_429 unithd 5520 1177760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_430 unithd 5520 1180480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_431 unithd 5520 1183200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_432 unithd 5520 1185920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_433 unithd 5520 1188640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_434 unithd 5520 1191360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_435 unithd 5520 1194080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_436 unithd 5520 1196800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_437 unithd 5520 1199520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_438 unithd 5520 1202240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_439 unithd 5520 1204960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_440 unithd 5520 1207680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_441 unithd 5520 1210400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_442 unithd 5520 1213120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_443 unithd 5520 1215840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_444 unithd 5520 1218560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_445 unithd 5520 1221280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_446 unithd 5520 1224000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_447 unithd 5520 1226720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_448 unithd 5520 1229440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_449 unithd 5520 1232160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_450 unithd 5520 1234880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_451 unithd 5520 1237600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_452 unithd 5520 1240320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_453 unithd 5520 1243040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_454 unithd 5520 1245760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_455 unithd 5520 1248480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_456 unithd 5520 1251200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_457 unithd 5520 1253920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_458 unithd 5520 1256640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_459 unithd 5520 1259360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_460 unithd 5520 1262080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_461 unithd 5520 1264800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_462 unithd 5520 1267520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_463 unithd 5520 1270240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_464 unithd 5520 1272960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_465 unithd 5520 1275680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_466 unithd 5520 1278400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_467 unithd 5520 1281120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_468 unithd 5520 1283840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_469 unithd 5520 1286560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_470 unithd 5520 1289280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_471 unithd 5520 1292000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_472 unithd 5520 1294720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_473 unithd 5520 1297440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_474 unithd 5520 1300160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_475 unithd 5520 1302880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_476 unithd 5520 1305600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_477 unithd 5520 1308320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_478 unithd 5520 1311040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_479 unithd 5520 1313760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_480 unithd 5520 1316480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_481 unithd 5520 1319200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_482 unithd 5520 1321920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_483 unithd 5520 1324640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_484 unithd 5520 1327360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_485 unithd 5520 1330080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_486 unithd 5520 1332800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_487 unithd 5520 1335520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_488 unithd 5520 1338240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_489 unithd 5520 1340960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_490 unithd 5520 1343680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_491 unithd 5520 1346400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_492 unithd 5520 1349120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_493 unithd 5520 1351840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_494 unithd 5520 1354560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_495 unithd 5520 1357280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_496 unithd 5520 1360000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_497 unithd 5520 1362720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_498 unithd 5520 1365440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_499 unithd 5520 1368160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_500 unithd 5520 1370880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_501 unithd 5520 1373600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_502 unithd 5520 1376320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_503 unithd 5520 1379040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_504 unithd 5520 1381760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_505 unithd 5520 1384480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_506 unithd 5520 1387200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_507 unithd 5520 1389920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_508 unithd 5520 1392640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_509 unithd 5520 1395360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_510 unithd 5520 1398080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_511 unithd 5520 1400800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_512 unithd 5520 1403520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_513 unithd 5520 1406240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_514 unithd 5520 1408960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_515 unithd 5520 1411680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_516 unithd 5520 1414400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_517 unithd 5520 1417120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_518 unithd 5520 1419840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_519 unithd 5520 1422560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_520 unithd 5520 1425280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_521 unithd 5520 1428000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_522 unithd 5520 1430720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_523 unithd 5520 1433440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_524 unithd 5520 1436160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_525 unithd 5520 1438880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_526 unithd 5520 1441600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_527 unithd 5520 1444320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_528 unithd 5520 1447040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_529 unithd 5520 1449760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_530 unithd 5520 1452480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_531 unithd 5520 1455200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_532 unithd 5520 1457920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_533 unithd 5520 1460640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_534 unithd 5520 1463360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_535 unithd 5520 1466080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_536 unithd 5520 1468800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_537 unithd 5520 1471520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_538 unithd 5520 1474240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_539 unithd 5520 1476960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_540 unithd 5520 1479680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_541 unithd 5520 1482400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_542 unithd 5520 1485120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_543 unithd 5520 1487840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_544 unithd 5520 1490560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_545 unithd 5520 1493280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_546 unithd 5520 1496000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_547 unithd 5520 1498720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_548 unithd 5520 1501440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_549 unithd 5520 1504160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_550 unithd 5520 1506880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_551 unithd 5520 1509600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_552 unithd 5520 1512320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_553 unithd 5520 1515040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_554 unithd 5520 1517760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_555 unithd 5520 1520480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_556 unithd 5520 1523200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_557 unithd 5520 1525920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_558 unithd 5520 1528640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_559 unithd 5520 1531360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_560 unithd 5520 1534080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_561 unithd 5520 1536800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_562 unithd 5520 1539520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_563 unithd 5520 1542240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_564 unithd 5520 1544960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_565 unithd 5520 1547680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_566 unithd 5520 1550400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_567 unithd 5520 1553120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_568 unithd 5520 1555840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_569 unithd 5520 1558560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_570 unithd 5520 1561280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_571 unithd 5520 1564000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_572 unithd 5520 1566720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_573 unithd 5520 1569440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_574 unithd 5520 1572160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_575 unithd 5520 1574880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_576 unithd 5520 1577600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_577 unithd 5520 1580320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_578 unithd 5520 1583040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_579 unithd 5520 1585760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_580 unithd 5520 1588480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_581 unithd 5520 1591200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_582 unithd 5520 1593920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_583 unithd 5520 1596640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_584 unithd 5520 1599360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_585 unithd 5520 1602080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_586 unithd 5520 1604800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_587 unithd 5520 1607520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_588 unithd 5520 1610240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_589 unithd 5520 1612960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_590 unithd 5520 1615680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_591 unithd 5520 1618400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_592 unithd 5520 1621120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_593 unithd 5520 1623840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_594 unithd 5520 1626560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_595 unithd 5520 1629280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_596 unithd 5520 1632000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_597 unithd 5520 1634720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_598 unithd 5520 1637440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_599 unithd 5520 1640160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_600 unithd 5520 1642880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_601 unithd 5520 1645600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_602 unithd 5520 1648320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_603 unithd 5520 1651040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_604 unithd 5520 1653760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_605 unithd 5520 1656480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_606 unithd 5520 1659200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_607 unithd 5520 1661920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_608 unithd 5520 1664640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_609 unithd 5520 1667360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_610 unithd 5520 1670080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_611 unithd 5520 1672800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_612 unithd 5520 1675520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_613 unithd 5520 1678240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_614 unithd 5520 1680960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_615 unithd 5520 1683680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_616 unithd 5520 1686400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_617 unithd 5520 1689120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_618 unithd 5520 1691840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_619 unithd 5520 1694560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_620 unithd 5520 1697280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_621 unithd 5520 1700000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_622 unithd 5520 1702720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_623 unithd 5520 1705440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_624 unithd 5520 1708160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_625 unithd 5520 1710880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_626 unithd 5520 1713600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_627 unithd 5520 1716320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_628 unithd 5520 1719040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_629 unithd 5520 1721760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_630 unithd 5520 1724480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_631 unithd 5520 1727200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_632 unithd 5520 1729920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_633 unithd 5520 1732640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_634 unithd 5520 1735360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_635 unithd 5520 1738080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_636 unithd 5520 1740800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_637 unithd 5520 1743520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_638 unithd 5520 1746240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_639 unithd 5520 1748960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_640 unithd 5520 1751680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_641 unithd 5520 1754400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_642 unithd 5520 1757120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_643 unithd 5520 1759840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_644 unithd 5520 1762560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_645 unithd 5520 1765280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_646 unithd 5520 1768000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_647 unithd 5520 1770720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_648 unithd 5520 1773440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_649 unithd 5520 1776160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_650 unithd 5520 1778880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_651 unithd 5520 1781600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_652 unithd 5520 1784320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_653 unithd 5520 1787040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_654 unithd 5520 1789760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_655 unithd 5520 1792480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_656 unithd 5520 1795200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_657 unithd 5520 1797920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_658 unithd 5520 1800640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_659 unithd 5520 1803360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_660 unithd 5520 1806080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_661 unithd 5520 1808800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_662 unithd 5520 1811520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_663 unithd 5520 1814240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_664 unithd 5520 1816960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_665 unithd 5520 1819680 FS DO 6323 BY 1 STEP 460 0 ;
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+ROW ROW_667 unithd 5520 1825120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_668 unithd 5520 1827840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_669 unithd 5520 1830560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_670 unithd 5520 1833280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_671 unithd 5520 1836000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_672 unithd 5520 1838720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_673 unithd 5520 1841440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_674 unithd 5520 1844160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_675 unithd 5520 1846880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_676 unithd 5520 1849600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_677 unithd 5520 1852320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_678 unithd 5520 1855040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_679 unithd 5520 1857760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_680 unithd 5520 1860480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_681 unithd 5520 1863200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_682 unithd 5520 1865920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_683 unithd 5520 1868640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_684 unithd 5520 1871360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_685 unithd 5520 1874080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_686 unithd 5520 1876800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_687 unithd 5520 1879520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_688 unithd 5520 1882240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_689 unithd 5520 1884960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_690 unithd 5520 1887680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_691 unithd 5520 1890400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_692 unithd 5520 1893120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_693 unithd 5520 1895840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_694 unithd 5520 1898560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_695 unithd 5520 1901280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_696 unithd 5520 1904000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_697 unithd 5520 1906720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_698 unithd 5520 1909440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_699 unithd 5520 1912160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_700 unithd 5520 1914880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_701 unithd 5520 1917600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_702 unithd 5520 1920320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_703 unithd 5520 1923040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_704 unithd 5520 1925760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_705 unithd 5520 1928480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_706 unithd 5520 1931200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_707 unithd 5520 1933920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_708 unithd 5520 1936640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_709 unithd 5520 1939360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_710 unithd 5520 1942080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_711 unithd 5520 1944800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_712 unithd 5520 1947520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_713 unithd 5520 1950240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_714 unithd 5520 1952960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_715 unithd 5520 1955680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_716 unithd 5520 1958400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_717 unithd 5520 1961120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_718 unithd 5520 1963840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_719 unithd 5520 1966560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_720 unithd 5520 1969280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_721 unithd 5520 1972000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_722 unithd 5520 1974720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_723 unithd 5520 1977440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_724 unithd 5520 1980160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_725 unithd 5520 1982880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_726 unithd 5520 1985600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_727 unithd 5520 1988320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_728 unithd 5520 1991040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_729 unithd 5520 1993760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_730 unithd 5520 1996480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_731 unithd 5520 1999200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_732 unithd 5520 2001920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_733 unithd 5520 2004640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_734 unithd 5520 2007360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_735 unithd 5520 2010080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_736 unithd 5520 2012800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_737 unithd 5520 2015520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_738 unithd 5520 2018240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_739 unithd 5520 2020960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_740 unithd 5520 2023680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_741 unithd 5520 2026400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_742 unithd 5520 2029120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_743 unithd 5520 2031840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_744 unithd 5520 2034560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_745 unithd 5520 2037280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_746 unithd 5520 2040000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_747 unithd 5520 2042720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_748 unithd 5520 2045440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_749 unithd 5520 2048160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_750 unithd 5520 2050880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_751 unithd 5520 2053600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_752 unithd 5520 2056320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_753 unithd 5520 2059040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_754 unithd 5520 2061760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_755 unithd 5520 2064480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_756 unithd 5520 2067200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_757 unithd 5520 2069920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_758 unithd 5520 2072640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_759 unithd 5520 2075360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_760 unithd 5520 2078080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_761 unithd 5520 2080800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_762 unithd 5520 2083520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_763 unithd 5520 2086240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_764 unithd 5520 2088960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_765 unithd 5520 2091680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_766 unithd 5520 2094400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_767 unithd 5520 2097120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_768 unithd 5520 2099840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_769 unithd 5520 2102560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_770 unithd 5520 2105280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_771 unithd 5520 2108000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_772 unithd 5520 2110720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_773 unithd 5520 2113440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_774 unithd 5520 2116160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_775 unithd 5520 2118880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_776 unithd 5520 2121600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_777 unithd 5520 2124320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_778 unithd 5520 2127040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_779 unithd 5520 2129760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_780 unithd 5520 2132480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_781 unithd 5520 2135200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_782 unithd 5520 2137920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_783 unithd 5520 2140640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_784 unithd 5520 2143360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_785 unithd 5520 2146080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_786 unithd 5520 2148800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_787 unithd 5520 2151520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_788 unithd 5520 2154240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_789 unithd 5520 2156960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_790 unithd 5520 2159680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_791 unithd 5520 2162400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_792 unithd 5520 2165120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_793 unithd 5520 2167840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_794 unithd 5520 2170560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_795 unithd 5520 2173280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_796 unithd 5520 2176000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_797 unithd 5520 2178720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_798 unithd 5520 2181440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_799 unithd 5520 2184160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_800 unithd 5520 2186880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_801 unithd 5520 2189600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_802 unithd 5520 2192320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_803 unithd 5520 2195040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_804 unithd 5520 2197760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_805 unithd 5520 2200480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_806 unithd 5520 2203200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_807 unithd 5520 2205920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_808 unithd 5520 2208640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_809 unithd 5520 2211360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_810 unithd 5520 2214080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_811 unithd 5520 2216800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_812 unithd 5520 2219520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_813 unithd 5520 2222240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_814 unithd 5520 2224960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_815 unithd 5520 2227680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_816 unithd 5520 2230400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_817 unithd 5520 2233120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_818 unithd 5520 2235840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_819 unithd 5520 2238560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_820 unithd 5520 2241280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_821 unithd 5520 2244000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_822 unithd 5520 2246720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_823 unithd 5520 2249440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_824 unithd 5520 2252160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_825 unithd 5520 2254880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_826 unithd 5520 2257600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_827 unithd 5520 2260320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_828 unithd 5520 2263040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_829 unithd 5520 2265760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_830 unithd 5520 2268480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_831 unithd 5520 2271200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_832 unithd 5520 2273920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_833 unithd 5520 2276640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_834 unithd 5520 2279360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_835 unithd 5520 2282080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_836 unithd 5520 2284800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_837 unithd 5520 2287520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_838 unithd 5520 2290240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_839 unithd 5520 2292960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_840 unithd 5520 2295680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_841 unithd 5520 2298400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_842 unithd 5520 2301120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_843 unithd 5520 2303840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_844 unithd 5520 2306560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_845 unithd 5520 2309280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_846 unithd 5520 2312000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_847 unithd 5520 2314720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_848 unithd 5520 2317440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_849 unithd 5520 2320160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_850 unithd 5520 2322880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_851 unithd 5520 2325600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_852 unithd 5520 2328320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_853 unithd 5520 2331040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_854 unithd 5520 2333760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_855 unithd 5520 2336480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_856 unithd 5520 2339200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_857 unithd 5520 2341920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_858 unithd 5520 2344640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_859 unithd 5520 2347360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_860 unithd 5520 2350080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_861 unithd 5520 2352800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_862 unithd 5520 2355520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_863 unithd 5520 2358240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_864 unithd 5520 2360960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_865 unithd 5520 2363680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_866 unithd 5520 2366400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_867 unithd 5520 2369120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_868 unithd 5520 2371840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_869 unithd 5520 2374560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_870 unithd 5520 2377280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_871 unithd 5520 2380000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_872 unithd 5520 2382720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_873 unithd 5520 2385440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_874 unithd 5520 2388160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_875 unithd 5520 2390880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_876 unithd 5520 2393600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_877 unithd 5520 2396320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_878 unithd 5520 2399040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_879 unithd 5520 2401760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_880 unithd 5520 2404480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_881 unithd 5520 2407200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_882 unithd 5520 2409920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_883 unithd 5520 2412640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_884 unithd 5520 2415360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_885 unithd 5520 2418080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_886 unithd 5520 2420800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_887 unithd 5520 2423520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_888 unithd 5520 2426240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_889 unithd 5520 2428960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_890 unithd 5520 2431680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_891 unithd 5520 2434400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_892 unithd 5520 2437120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_893 unithd 5520 2439840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_894 unithd 5520 2442560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_895 unithd 5520 2445280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_896 unithd 5520 2448000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_897 unithd 5520 2450720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_898 unithd 5520 2453440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_899 unithd 5520 2456160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_900 unithd 5520 2458880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_901 unithd 5520 2461600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_902 unithd 5520 2464320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_903 unithd 5520 2467040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_904 unithd 5520 2469760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_905 unithd 5520 2472480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_906 unithd 5520 2475200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_907 unithd 5520 2477920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_908 unithd 5520 2480640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_909 unithd 5520 2483360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_910 unithd 5520 2486080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_911 unithd 5520 2488800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_912 unithd 5520 2491520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_913 unithd 5520 2494240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_914 unithd 5520 2496960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_915 unithd 5520 2499680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_916 unithd 5520 2502400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_917 unithd 5520 2505120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_918 unithd 5520 2507840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_919 unithd 5520 2510560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_920 unithd 5520 2513280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_921 unithd 5520 2516000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_922 unithd 5520 2518720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_923 unithd 5520 2521440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_924 unithd 5520 2524160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_925 unithd 5520 2526880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_926 unithd 5520 2529600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_927 unithd 5520 2532320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_928 unithd 5520 2535040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_929 unithd 5520 2537760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_930 unithd 5520 2540480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_931 unithd 5520 2543200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_932 unithd 5520 2545920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_933 unithd 5520 2548640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_934 unithd 5520 2551360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_935 unithd 5520 2554080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_936 unithd 5520 2556800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_937 unithd 5520 2559520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_938 unithd 5520 2562240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_939 unithd 5520 2564960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_940 unithd 5520 2567680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_941 unithd 5520 2570400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_942 unithd 5520 2573120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_943 unithd 5520 2575840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_944 unithd 5520 2578560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_945 unithd 5520 2581280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_946 unithd 5520 2584000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_947 unithd 5520 2586720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_948 unithd 5520 2589440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_949 unithd 5520 2592160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_950 unithd 5520 2594880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_951 unithd 5520 2597600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_952 unithd 5520 2600320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_953 unithd 5520 2603040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_954 unithd 5520 2605760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_955 unithd 5520 2608480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_956 unithd 5520 2611200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_957 unithd 5520 2613920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_958 unithd 5520 2616640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_959 unithd 5520 2619360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_960 unithd 5520 2622080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_961 unithd 5520 2624800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_962 unithd 5520 2627520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_963 unithd 5520 2630240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_964 unithd 5520 2632960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_965 unithd 5520 2635680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_966 unithd 5520 2638400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_967 unithd 5520 2641120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_968 unithd 5520 2643840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_969 unithd 5520 2646560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_970 unithd 5520 2649280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_971 unithd 5520 2652000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_972 unithd 5520 2654720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_973 unithd 5520 2657440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_974 unithd 5520 2660160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_975 unithd 5520 2662880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_976 unithd 5520 2665600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_977 unithd 5520 2668320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_978 unithd 5520 2671040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_979 unithd 5520 2673760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_980 unithd 5520 2676480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_981 unithd 5520 2679200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_982 unithd 5520 2681920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_983 unithd 5520 2684640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_984 unithd 5520 2687360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_985 unithd 5520 2690080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_986 unithd 5520 2692800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_987 unithd 5520 2695520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_988 unithd 5520 2698240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_989 unithd 5520 2700960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_990 unithd 5520 2703680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_991 unithd 5520 2706400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_992 unithd 5520 2709120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_993 unithd 5520 2711840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_994 unithd 5520 2714560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_995 unithd 5520 2717280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_996 unithd 5520 2720000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_997 unithd 5520 2722720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_998 unithd 5520 2725440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_999 unithd 5520 2728160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1000 unithd 5520 2730880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1001 unithd 5520 2733600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1002 unithd 5520 2736320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1003 unithd 5520 2739040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1004 unithd 5520 2741760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1005 unithd 5520 2744480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1006 unithd 5520 2747200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1007 unithd 5520 2749920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1008 unithd 5520 2752640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1009 unithd 5520 2755360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1010 unithd 5520 2758080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1011 unithd 5520 2760800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1012 unithd 5520 2763520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1013 unithd 5520 2766240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1014 unithd 5520 2768960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1015 unithd 5520 2771680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1016 unithd 5520 2774400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1017 unithd 5520 2777120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1018 unithd 5520 2779840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1019 unithd 5520 2782560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1020 unithd 5520 2785280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1021 unithd 5520 2788000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1022 unithd 5520 2790720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1023 unithd 5520 2793440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1024 unithd 5520 2796160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1025 unithd 5520 2798880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1026 unithd 5520 2801600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1027 unithd 5520 2804320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1028 unithd 5520 2807040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1029 unithd 5520 2809760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1030 unithd 5520 2812480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1031 unithd 5520 2815200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1032 unithd 5520 2817920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1033 unithd 5520 2820640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1034 unithd 5520 2823360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1035 unithd 5520 2826080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1036 unithd 5520 2828800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1037 unithd 5520 2831520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1038 unithd 5520 2834240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1039 unithd 5520 2836960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1040 unithd 5520 2839680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1041 unithd 5520 2842400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1042 unithd 5520 2845120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1043 unithd 5520 2847840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1044 unithd 5520 2850560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1045 unithd 5520 2853280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1046 unithd 5520 2856000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1047 unithd 5520 2858720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1048 unithd 5520 2861440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1049 unithd 5520 2864160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1050 unithd 5520 2866880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1051 unithd 5520 2869600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1052 unithd 5520 2872320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1053 unithd 5520 2875040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1054 unithd 5520 2877760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1055 unithd 5520 2880480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1056 unithd 5520 2883200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1057 unithd 5520 2885920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1058 unithd 5520 2888640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1059 unithd 5520 2891360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1060 unithd 5520 2894080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1061 unithd 5520 2896800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1062 unithd 5520 2899520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1063 unithd 5520 2902240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1064 unithd 5520 2904960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1065 unithd 5520 2907680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1066 unithd 5520 2910400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1067 unithd 5520 2913120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1068 unithd 5520 2915840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1069 unithd 5520 2918560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1070 unithd 5520 2921280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1071 unithd 5520 2924000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1072 unithd 5520 2926720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1073 unithd 5520 2929440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1074 unithd 5520 2932160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1075 unithd 5520 2934880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1076 unithd 5520 2937600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1077 unithd 5520 2940320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1078 unithd 5520 2943040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1079 unithd 5520 2945760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1080 unithd 5520 2948480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1081 unithd 5520 2951200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1082 unithd 5520 2953920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1083 unithd 5520 2956640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1084 unithd 5520 2959360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1085 unithd 5520 2962080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1086 unithd 5520 2964800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1087 unithd 5520 2967520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1088 unithd 5520 2970240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1089 unithd 5520 2972960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1090 unithd 5520 2975680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1091 unithd 5520 2978400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1092 unithd 5520 2981120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1093 unithd 5520 2983840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1094 unithd 5520 2986560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1095 unithd 5520 2989280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1096 unithd 5520 2992000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1097 unithd 5520 2994720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1098 unithd 5520 2997440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1099 unithd 5520 3000160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1100 unithd 5520 3002880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1101 unithd 5520 3005600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1102 unithd 5520 3008320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1103 unithd 5520 3011040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1104 unithd 5520 3013760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1105 unithd 5520 3016480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1106 unithd 5520 3019200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1107 unithd 5520 3021920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1108 unithd 5520 3024640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1109 unithd 5520 3027360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1110 unithd 5520 3030080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1111 unithd 5520 3032800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1112 unithd 5520 3035520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1113 unithd 5520 3038240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1114 unithd 5520 3040960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1115 unithd 5520 3043680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1116 unithd 5520 3046400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1117 unithd 5520 3049120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1118 unithd 5520 3051840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1119 unithd 5520 3054560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1120 unithd 5520 3057280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1121 unithd 5520 3060000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1122 unithd 5520 3062720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1123 unithd 5520 3065440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1124 unithd 5520 3068160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1125 unithd 5520 3070880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1126 unithd 5520 3073600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1127 unithd 5520 3076320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1128 unithd 5520 3079040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1129 unithd 5520 3081760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1130 unithd 5520 3084480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1131 unithd 5520 3087200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1132 unithd 5520 3089920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1133 unithd 5520 3092640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1134 unithd 5520 3095360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1135 unithd 5520 3098080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1136 unithd 5520 3100800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1137 unithd 5520 3103520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1138 unithd 5520 3106240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1139 unithd 5520 3108960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1140 unithd 5520 3111680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1141 unithd 5520 3114400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1142 unithd 5520 3117120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1143 unithd 5520 3119840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1144 unithd 5520 3122560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1145 unithd 5520 3125280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1146 unithd 5520 3128000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1147 unithd 5520 3130720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1148 unithd 5520 3133440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1149 unithd 5520 3136160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1150 unithd 5520 3138880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1151 unithd 5520 3141600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1152 unithd 5520 3144320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1153 unithd 5520 3147040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1154 unithd 5520 3149760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1155 unithd 5520 3152480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1156 unithd 5520 3155200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1157 unithd 5520 3157920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1158 unithd 5520 3160640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1159 unithd 5520 3163360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1160 unithd 5520 3166080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1161 unithd 5520 3168800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1162 unithd 5520 3171520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1163 unithd 5520 3174240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1164 unithd 5520 3176960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1165 unithd 5520 3179680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1166 unithd 5520 3182400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1167 unithd 5520 3185120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1168 unithd 5520 3187840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1169 unithd 5520 3190560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1170 unithd 5520 3193280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1171 unithd 5520 3196000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1172 unithd 5520 3198720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1173 unithd 5520 3201440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1174 unithd 5520 3204160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1175 unithd 5520 3206880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1176 unithd 5520 3209600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1177 unithd 5520 3212320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1178 unithd 5520 3215040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1179 unithd 5520 3217760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1180 unithd 5520 3220480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1181 unithd 5520 3223200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1182 unithd 5520 3225920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1183 unithd 5520 3228640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1184 unithd 5520 3231360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1185 unithd 5520 3234080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1186 unithd 5520 3236800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1187 unithd 5520 3239520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1188 unithd 5520 3242240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1189 unithd 5520 3244960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1190 unithd 5520 3247680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1191 unithd 5520 3250400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1192 unithd 5520 3253120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1193 unithd 5520 3255840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1194 unithd 5520 3258560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1195 unithd 5520 3261280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1196 unithd 5520 3264000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1197 unithd 5520 3266720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1198 unithd 5520 3269440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1199 unithd 5520 3272160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1200 unithd 5520 3274880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1201 unithd 5520 3277600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1202 unithd 5520 3280320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1203 unithd 5520 3283040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1204 unithd 5520 3285760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1205 unithd 5520 3288480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1206 unithd 5520 3291200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1207 unithd 5520 3293920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1208 unithd 5520 3296640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1209 unithd 5520 3299360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1210 unithd 5520 3302080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1211 unithd 5520 3304800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1212 unithd 5520 3307520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1213 unithd 5520 3310240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1214 unithd 5520 3312960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1215 unithd 5520 3315680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1216 unithd 5520 3318400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1217 unithd 5520 3321120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1218 unithd 5520 3323840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1219 unithd 5520 3326560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1220 unithd 5520 3329280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1221 unithd 5520 3332000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1222 unithd 5520 3334720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1223 unithd 5520 3337440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1224 unithd 5520 3340160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1225 unithd 5520 3342880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1226 unithd 5520 3345600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1227 unithd 5520 3348320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1228 unithd 5520 3351040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1229 unithd 5520 3353760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1230 unithd 5520 3356480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1231 unithd 5520 3359200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1232 unithd 5520 3361920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1233 unithd 5520 3364640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1234 unithd 5520 3367360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1235 unithd 5520 3370080 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1236 unithd 5520 3372800 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1237 unithd 5520 3375520 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1238 unithd 5520 3378240 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1239 unithd 5520 3380960 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1240 unithd 5520 3383680 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1241 unithd 5520 3386400 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1242 unithd 5520 3389120 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1243 unithd 5520 3391840 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1244 unithd 5520 3394560 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1245 unithd 5520 3397280 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1246 unithd 5520 3400000 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1247 unithd 5520 3402720 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1248 unithd 5520 3405440 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1249 unithd 5520 3408160 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1250 unithd 5520 3410880 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1251 unithd 5520 3413600 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1252 unithd 5520 3416320 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1253 unithd 5520 3419040 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1254 unithd 5520 3421760 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1255 unithd 5520 3424480 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1256 unithd 5520 3427200 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1257 unithd 5520 3429920 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1258 unithd 5520 3432640 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1259 unithd 5520 3435360 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1260 unithd 5520 3438080 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1261 unithd 5520 3440800 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1262 unithd 5520 3443520 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1263 unithd 5520 3446240 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1264 unithd 5520 3448960 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1265 unithd 5520 3451680 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1266 unithd 5520 3454400 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1267 unithd 5520 3457120 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1268 unithd 5520 3459840 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1269 unithd 5520 3462560 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1270 unithd 5520 3465280 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1271 unithd 5520 3468000 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1272 unithd 5520 3470720 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1273 unithd 5520 3473440 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1274 unithd 5520 3476160 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1275 unithd 5520 3478880 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1276 unithd 5520 3481600 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1277 unithd 5520 3484320 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1278 unithd 5520 3487040 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1279 unithd 5520 3489760 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1280 unithd 5520 3492480 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1281 unithd 5520 3495200 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1282 unithd 5520 3497920 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1283 unithd 5520 3500640 FS DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1284 unithd 5520 3503360 N DO 6323 BY 1 STEP 460 0 ;
+ROW ROW_1285 unithd 5520 3506080 FS DO 6323 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 8588 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 10353 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 6348 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 7652 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 4294 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 5176 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 3174 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 3826 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ;
+GCELLGRID X 0 DO 423 STEP 6900 ;
+GCELLGRID Y 0 DO 510 STEP 6900 ;
+VIAS 2 ;
+ - via4_3100x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 350 350 350 350 + ROWCOL 2 2 ;
+ - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 350 400 350 + ROWCOL 2 1 ;
+END VIAS
+COMPONENTS 1 ;
+ - mprj user_proj_example + FIXED ( 1175000 1690000 ) N ;
+END COMPONENTS
+PINS 645 ;
+ - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1426980 ) N ;
+ - analog_io[10] + NET analog_io[10] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2230770 3521200 ) N ;
+ - analog_io[11] + NET analog_io[11] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 3521200 ) N ;
+ - analog_io[12] + NET analog_io[12] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581710 3521200 ) N ;
+ - analog_io[13] + NET analog_io[13] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1257410 3521200 ) N ;
+ - analog_io[14] + NET analog_io[14] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 932650 3521200 ) N ;
+ - analog_io[15] + NET analog_io[15] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 608350 3521200 ) N ;
+ - analog_io[16] + NET analog_io[16] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 284050 3521200 ) N ;
+ - analog_io[17] + NET analog_io[17] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3486700 ) N ;
+ - analog_io[18] + NET analog_io[18] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3225580 ) N ;
+ - analog_io[19] + NET analog_io[19] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2965140 ) N ;
+ - analog_io[1] + NET analog_io[1] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1692860 ) N ;
+ - analog_io[20] + NET analog_io[20] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2704020 ) N ;
+ - analog_io[21] + NET analog_io[21] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2443580 ) N ;
+ - analog_io[22] + NET analog_io[22] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2183140 ) N ;
+ - analog_io[23] + NET analog_io[23] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1922020 ) N ;
+ - analog_io[24] + NET analog_io[24] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1661580 ) N ;
+ - analog_io[25] + NET analog_io[25] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1400460 ) N ;
+ - analog_io[26] + NET analog_io[26] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1140020 ) N ;
+ - analog_io[27] + NET analog_io[27] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 879580 ) N ;
+ - analog_io[28] + NET analog_io[28] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 618460 ) N ;
+ - analog_io[2] + NET analog_io[2] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1958740 ) N ;
+ - analog_io[3] + NET analog_io[3] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2223940 ) N ;
+ - analog_io[4] + NET analog_io[4] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2489820 ) N ;
+ - analog_io[5] + NET analog_io[5] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2755700 ) N ;
+ - analog_io[6] + NET analog_io[6] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3020900 ) N ;
+ - analog_io[7] + NET analog_io[7] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3286780 ) N ;
+ - analog_io[8] + NET analog_io[8] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2879370 3521200 ) N ;
+ - analog_io[9] + NET analog_io[9] + DIRECTION INOUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2555070 3521200 ) N ;
+ - io_in[0] + NET io_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 32980 ) N ;
+ - io_in[10] + NET io_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2290580 ) N ;
+ - io_in[11] + NET io_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2556460 ) N ;
+ - io_in[12] + NET io_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2821660 ) N ;
+ - io_in[13] + NET io_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3087540 ) N ;
+ - io_in[14] + NET io_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3353420 ) N ;
+ - io_in[15] + NET io_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798410 3521200 ) N ;
+ - io_in[16] + NET io_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2474110 3521200 ) N ;
+ - io_in[17] + NET io_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2149350 3521200 ) N ;
+ - io_in[18] + NET io_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1825050 3521200 ) N ;
+ - io_in[19] + NET io_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1500750 3521200 ) N ;
+ - io_in[1] + NET io_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 231540 ) N ;
+ - io_in[20] + NET io_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1175990 3521200 ) N ;
+ - io_in[21] + NET io_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 851690 3521200 ) N ;
+ - io_in[22] + NET io_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 527390 3521200 ) N ;
+ - io_in[23] + NET io_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 202630 3521200 ) N ;
+ - io_in[24] + NET io_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3421420 ) N ;
+ - io_in[25] + NET io_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3160300 ) N ;
+ - io_in[26] + NET io_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2899860 ) N ;
+ - io_in[27] + NET io_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2639420 ) N ;
+ - io_in[28] + NET io_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2378300 ) N ;
+ - io_in[29] + NET io_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2117860 ) N ;
+ - io_in[2] + NET io_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 430780 ) N ;
+ - io_in[30] + NET io_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1856740 ) N ;
+ - io_in[31] + NET io_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1596300 ) N ;
+ - io_in[32] + NET io_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1335860 ) N ;
+ - io_in[33] + NET io_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1074740 ) N ;
+ - io_in[34] + NET io_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 814300 ) N ;
+ - io_in[35] + NET io_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 553180 ) N ;
+ - io_in[36] + NET io_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 358020 ) N ;
+ - io_in[37] + NET io_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 162180 ) N ;
+ - io_in[3] + NET io_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 630020 ) N ;
+ - io_in[4] + NET io_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 829260 ) N ;
+ - io_in[5] + NET io_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1028500 ) N ;
+ - io_in[6] + NET io_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1227740 ) N ;
+ - io_in[7] + NET io_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1493620 ) N ;
+ - io_in[8] + NET io_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1759500 ) N ;
+ - io_in[9] + NET io_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2024700 ) N ;
+ - io_oeb[0] + NET io_oeb[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 165580 ) N ;
+ - io_oeb[10] + NET io_oeb[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2423180 ) N ;
+ - io_oeb[11] + NET io_oeb[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2689060 ) N ;
+ - io_oeb[12] + NET io_oeb[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2954940 ) N ;
+ - io_oeb[13] + NET io_oeb[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3220140 ) N ;
+ - io_oeb[14] + NET io_oeb[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3486020 ) N ;
+ - io_oeb[15] + NET io_oeb[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2636030 3521200 ) N ;
+ - io_oeb[16] + NET io_oeb[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2311730 3521200 ) N ;
+ - io_oeb[17] + NET io_oeb[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1987430 3521200 ) N ;
+ - io_oeb[18] + NET io_oeb[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1662670 3521200 ) N ;
+ - io_oeb[19] + NET io_oeb[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338370 3521200 ) N ;
+ - io_oeb[1] + NET io_oeb[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 364820 ) N ;
+ - io_oeb[20] + NET io_oeb[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1014070 3521200 ) N ;
+ - io_oeb[21] + NET io_oeb[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 689310 3521200 ) N ;
+ - io_oeb[22] + NET io_oeb[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 365010 3521200 ) N ;
+ - io_oeb[23] + NET io_oeb[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 40710 3521200 ) N ;
+ - io_oeb[24] + NET io_oeb[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3290860 ) N ;
+ - io_oeb[25] + NET io_oeb[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3030420 ) N ;
+ - io_oeb[26] + NET io_oeb[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2769300 ) N ;
+ - io_oeb[27] + NET io_oeb[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2508860 ) N ;
+ - io_oeb[28] + NET io_oeb[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2247740 ) N ;
+ - io_oeb[29] + NET io_oeb[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1987300 ) N ;
+ - io_oeb[2] + NET io_oeb[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 564060 ) N ;
+ - io_oeb[30] + NET io_oeb[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1726860 ) N ;
+ - io_oeb[31] + NET io_oeb[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1465740 ) N ;
+ - io_oeb[32] + NET io_oeb[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1205300 ) N ;
+ - io_oeb[33] + NET io_oeb[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 944180 ) N ;
+ - io_oeb[34] + NET io_oeb[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 683740 ) N ;
+ - io_oeb[35] + NET io_oeb[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 423300 ) N ;
+ - io_oeb[36] + NET io_oeb[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 227460 ) N ;
+ - io_oeb[37] + NET io_oeb[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 32300 ) N ;
+ - io_oeb[3] + NET io_oeb[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 763300 ) N ;
+ - io_oeb[4] + NET io_oeb[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 962540 ) N ;
+ - io_oeb[5] + NET io_oeb[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1161780 ) N ;
+ - io_oeb[6] + NET io_oeb[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1361020 ) N ;
+ - io_oeb[7] + NET io_oeb[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1626220 ) N ;
+ - io_oeb[8] + NET io_oeb[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1892100 ) N ;
+ - io_oeb[9] + NET io_oeb[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2157980 ) N ;
+ - io_out[0] + NET io_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 98940 ) N ;
+ - io_out[10] + NET io_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2357220 ) N ;
+ - io_out[11] + NET io_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2622420 ) N ;
+ - io_out[12] + NET io_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2888300 ) N ;
+ - io_out[13] + NET io_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3154180 ) N ;
+ - io_out[14] + NET io_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 3419380 ) N ;
+ - io_out[15] + NET io_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2717450 3521200 ) N ;
+ - io_out[16] + NET io_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2392690 3521200 ) N ;
+ - io_out[17] + NET io_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2068390 3521200 ) N ;
+ - io_out[18] + NET io_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1744090 3521200 ) N ;
+ - io_out[19] + NET io_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1419330 3521200 ) N ;
+ - io_out[1] + NET io_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 298180 ) N ;
+ - io_out[20] + NET io_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1095030 3521200 ) N ;
+ - io_out[21] + NET io_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 770730 3521200 ) N ;
+ - io_out[22] + NET io_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 3521200 ) N ;
+ - io_out[23] + NET io_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121670 3521200 ) N ;
+ - io_out[24] + NET io_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3356140 ) N ;
+ - io_out[25] + NET io_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 3095700 ) N ;
+ - io_out[26] + NET io_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2834580 ) N ;
+ - io_out[27] + NET io_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2574140 ) N ;
+ - io_out[28] + NET io_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2313020 ) N ;
+ - io_out[29] + NET io_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 2052580 ) N ;
+ - io_out[2] + NET io_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 497420 ) N ;
+ - io_out[30] + NET io_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1792140 ) N ;
+ - io_out[31] + NET io_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1531020 ) N ;
+ - io_out[32] + NET io_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1270580 ) N ;
+ - io_out[33] + NET io_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 1009460 ) N ;
+ - io_out[34] + NET io_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 749020 ) N ;
+ - io_out[35] + NET io_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 487900 ) N ;
+ - io_out[36] + NET io_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 292740 ) N ;
+ - io_out[37] + NET io_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( -1200 96900 ) N ;
+ - io_out[3] + NET io_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 696660 ) N ;
+ - io_out[4] + NET io_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 895900 ) N ;
+ - io_out[5] + NET io_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1095140 ) N ;
+ - io_out[6] + NET io_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1294380 ) N ;
+ - io_out[7] + NET io_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1560260 ) N ;
+ - io_out[8] + NET io_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 1825460 ) N ;
+ - io_out[9] + NET io_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met3 ( -3600 -600 ) ( 3600 600 )
+ + PLACED ( 2921200 2091340 ) N ;
+ - la_data_in[0] + NET la_data_in[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 629510 -1200 ) N ;
+ - la_data_in[100] + NET la_data_in[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2402810 -1200 ) N ;
+ - la_data_in[101] + NET la_data_in[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2420290 -1200 ) N ;
+ - la_data_in[102] + NET la_data_in[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2438230 -1200 ) N ;
+ - la_data_in[103] + NET la_data_in[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2455710 -1200 ) N ;
+ - la_data_in[104] + NET la_data_in[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2473650 -1200 ) N ;
+ - la_data_in[105] + NET la_data_in[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2491130 -1200 ) N ;
+ - la_data_in[106] + NET la_data_in[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2509070 -1200 ) N ;
+ - la_data_in[107] + NET la_data_in[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2527010 -1200 ) N ;
+ - la_data_in[108] + NET la_data_in[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2544490 -1200 ) N ;
+ - la_data_in[109] + NET la_data_in[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2562430 -1200 ) N ;
+ - la_data_in[10] + NET la_data_in[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 806610 -1200 ) N ;
+ - la_data_in[110] + NET la_data_in[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2579910 -1200 ) N ;
+ - la_data_in[111] + NET la_data_in[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2597850 -1200 ) N ;
+ - la_data_in[112] + NET la_data_in[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2615330 -1200 ) N ;
+ - la_data_in[113] + NET la_data_in[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2633270 -1200 ) N ;
+ - la_data_in[114] + NET la_data_in[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2650750 -1200 ) N ;
+ - la_data_in[115] + NET la_data_in[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2668690 -1200 ) N ;
+ - la_data_in[116] + NET la_data_in[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2686170 -1200 ) N ;
+ - la_data_in[117] + NET la_data_in[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2704110 -1200 ) N ;
+ - la_data_in[118] + NET la_data_in[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2722050 -1200 ) N ;
+ - la_data_in[119] + NET la_data_in[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2739530 -1200 ) N ;
+ - la_data_in[11] + NET la_data_in[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 824550 -1200 ) N ;
+ - la_data_in[120] + NET la_data_in[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2757470 -1200 ) N ;
+ - la_data_in[121] + NET la_data_in[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2774950 -1200 ) N ;
+ - la_data_in[122] + NET la_data_in[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2792890 -1200 ) N ;
+ - la_data_in[123] + NET la_data_in[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2810370 -1200 ) N ;
+ - la_data_in[124] + NET la_data_in[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2828310 -1200 ) N ;
+ - la_data_in[125] + NET la_data_in[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2845790 -1200 ) N ;
+ - la_data_in[126] + NET la_data_in[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2863730 -1200 ) N ;
+ - la_data_in[127] + NET la_data_in[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2881670 -1200 ) N ;
+ - la_data_in[12] + NET la_data_in[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 842030 -1200 ) N ;
+ - la_data_in[13] + NET la_data_in[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 859970 -1200 ) N ;
+ - la_data_in[14] + NET la_data_in[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 877450 -1200 ) N ;
+ - la_data_in[15] + NET la_data_in[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 895390 -1200 ) N ;
+ - la_data_in[16] + NET la_data_in[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 912870 -1200 ) N ;
+ - la_data_in[17] + NET la_data_in[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 930810 -1200 ) N ;
+ - la_data_in[18] + NET la_data_in[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 948750 -1200 ) N ;
+ - la_data_in[19] + NET la_data_in[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 966230 -1200 ) N ;
+ - la_data_in[1] + NET la_data_in[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 646990 -1200 ) N ;
+ - la_data_in[20] + NET la_data_in[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 984170 -1200 ) N ;
+ - la_data_in[21] + NET la_data_in[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1001650 -1200 ) N ;
+ - la_data_in[22] + NET la_data_in[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1019590 -1200 ) N ;
+ - la_data_in[23] + NET la_data_in[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1037070 -1200 ) N ;
+ - la_data_in[24] + NET la_data_in[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1055010 -1200 ) N ;
+ - la_data_in[25] + NET la_data_in[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1072490 -1200 ) N ;
+ - la_data_in[26] + NET la_data_in[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1090430 -1200 ) N ;
+ - la_data_in[27] + NET la_data_in[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1107910 -1200 ) N ;
+ - la_data_in[28] + NET la_data_in[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1125850 -1200 ) N ;
+ - la_data_in[29] + NET la_data_in[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1143790 -1200 ) N ;
+ - la_data_in[2] + NET la_data_in[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 664930 -1200 ) N ;
+ - la_data_in[30] + NET la_data_in[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1161270 -1200 ) N ;
+ - la_data_in[31] + NET la_data_in[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1179210 -1200 ) N ;
+ - la_data_in[32] + NET la_data_in[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1196690 -1200 ) N ;
+ - la_data_in[33] + NET la_data_in[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1214630 -1200 ) N ;
+ - la_data_in[34] + NET la_data_in[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1232110 -1200 ) N ;
+ - la_data_in[35] + NET la_data_in[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1250050 -1200 ) N ;
+ - la_data_in[36] + NET la_data_in[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1267530 -1200 ) N ;
+ - la_data_in[37] + NET la_data_in[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1285470 -1200 ) N ;
+ - la_data_in[38] + NET la_data_in[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1303410 -1200 ) N ;
+ - la_data_in[39] + NET la_data_in[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1320890 -1200 ) N ;
+ - la_data_in[3] + NET la_data_in[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 682410 -1200 ) N ;
+ - la_data_in[40] + NET la_data_in[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1338830 -1200 ) N ;
+ - la_data_in[41] + NET la_data_in[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1356310 -1200 ) N ;
+ - la_data_in[42] + NET la_data_in[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1374250 -1200 ) N ;
+ - la_data_in[43] + NET la_data_in[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1391730 -1200 ) N ;
+ - la_data_in[44] + NET la_data_in[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1409670 -1200 ) N ;
+ - la_data_in[45] + NET la_data_in[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1427150 -1200 ) N ;
+ - la_data_in[46] + NET la_data_in[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1445090 -1200 ) N ;
+ - la_data_in[47] + NET la_data_in[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1463030 -1200 ) N ;
+ - la_data_in[48] + NET la_data_in[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1480510 -1200 ) N ;
+ - la_data_in[49] + NET la_data_in[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1498450 -1200 ) N ;
+ - la_data_in[4] + NET la_data_in[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 700350 -1200 ) N ;
+ - la_data_in[50] + NET la_data_in[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1515930 -1200 ) N ;
+ - la_data_in[51] + NET la_data_in[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1533870 -1200 ) N ;
+ - la_data_in[52] + NET la_data_in[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1551350 -1200 ) N ;
+ - la_data_in[53] + NET la_data_in[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1569290 -1200 ) N ;
+ - la_data_in[54] + NET la_data_in[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1586770 -1200 ) N ;
+ - la_data_in[55] + NET la_data_in[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1604710 -1200 ) N ;
+ - la_data_in[56] + NET la_data_in[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1622190 -1200 ) N ;
+ - la_data_in[57] + NET la_data_in[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1640130 -1200 ) N ;
+ - la_data_in[58] + NET la_data_in[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1658070 -1200 ) N ;
+ - la_data_in[59] + NET la_data_in[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1675550 -1200 ) N ;
+ - la_data_in[5] + NET la_data_in[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 717830 -1200 ) N ;
+ - la_data_in[60] + NET la_data_in[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1693490 -1200 ) N ;
+ - la_data_in[61] + NET la_data_in[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1710970 -1200 ) N ;
+ - la_data_in[62] + NET la_data_in[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1728910 -1200 ) N ;
+ - la_data_in[63] + NET la_data_in[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1746390 -1200 ) N ;
+ - la_data_in[64] + NET la_data_in[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1764330 -1200 ) N ;
+ - la_data_in[65] + NET la_data_in[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1781810 -1200 ) N ;
+ - la_data_in[66] + NET la_data_in[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1799750 -1200 ) N ;
+ - la_data_in[67] + NET la_data_in[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1817690 -1200 ) N ;
+ - la_data_in[68] + NET la_data_in[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1835170 -1200 ) N ;
+ - la_data_in[69] + NET la_data_in[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1853110 -1200 ) N ;
+ - la_data_in[6] + NET la_data_in[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 735770 -1200 ) N ;
+ - la_data_in[70] + NET la_data_in[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1870590 -1200 ) N ;
+ - la_data_in[71] + NET la_data_in[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1888530 -1200 ) N ;
+ - la_data_in[72] + NET la_data_in[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1906010 -1200 ) N ;
+ - la_data_in[73] + NET la_data_in[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1923950 -1200 ) N ;
+ - la_data_in[74] + NET la_data_in[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1941430 -1200 ) N ;
+ - la_data_in[75] + NET la_data_in[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1959370 -1200 ) N ;
+ - la_data_in[76] + NET la_data_in[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1976850 -1200 ) N ;
+ - la_data_in[77] + NET la_data_in[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1994790 -1200 ) N ;
+ - la_data_in[78] + NET la_data_in[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2012730 -1200 ) N ;
+ - la_data_in[79] + NET la_data_in[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2030210 -1200 ) N ;
+ - la_data_in[7] + NET la_data_in[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 753250 -1200 ) N ;
+ - la_data_in[80] + NET la_data_in[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2048150 -1200 ) N ;
+ - la_data_in[81] + NET la_data_in[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2065630 -1200 ) N ;
+ - la_data_in[82] + NET la_data_in[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2083570 -1200 ) N ;
+ - la_data_in[83] + NET la_data_in[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2101050 -1200 ) N ;
+ - la_data_in[84] + NET la_data_in[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2118990 -1200 ) N ;
+ - la_data_in[85] + NET la_data_in[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2136470 -1200 ) N ;
+ - la_data_in[86] + NET la_data_in[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2154410 -1200 ) N ;
+ - la_data_in[87] + NET la_data_in[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2172350 -1200 ) N ;
+ - la_data_in[88] + NET la_data_in[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2189830 -1200 ) N ;
+ - la_data_in[89] + NET la_data_in[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2207770 -1200 ) N ;
+ - la_data_in[8] + NET la_data_in[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 771190 -1200 ) N ;
+ - la_data_in[90] + NET la_data_in[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2225250 -1200 ) N ;
+ - la_data_in[91] + NET la_data_in[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2243190 -1200 ) N ;
+ - la_data_in[92] + NET la_data_in[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2260670 -1200 ) N ;
+ - la_data_in[93] + NET la_data_in[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2278610 -1200 ) N ;
+ - la_data_in[94] + NET la_data_in[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2296090 -1200 ) N ;
+ - la_data_in[95] + NET la_data_in[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2314030 -1200 ) N ;
+ - la_data_in[96] + NET la_data_in[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2331510 -1200 ) N ;
+ - la_data_in[97] + NET la_data_in[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2349450 -1200 ) N ;
+ - la_data_in[98] + NET la_data_in[98] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2367390 -1200 ) N ;
+ - la_data_in[99] + NET la_data_in[99] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2384870 -1200 ) N ;
+ - la_data_in[9] + NET la_data_in[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 789130 -1200 ) N ;
+ - la_data_out[0] + NET la_data_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 635030 -1200 ) N ;
+ - la_data_out[100] + NET la_data_out[100] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2408790 -1200 ) N ;
+ - la_data_out[101] + NET la_data_out[101] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2426270 -1200 ) N ;
+ - la_data_out[102] + NET la_data_out[102] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2444210 -1200 ) N ;
+ - la_data_out[103] + NET la_data_out[103] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2461690 -1200 ) N ;
+ - la_data_out[104] + NET la_data_out[104] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2479630 -1200 ) N ;
+ - la_data_out[105] + NET la_data_out[105] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2497110 -1200 ) N ;
+ - la_data_out[106] + NET la_data_out[106] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2515050 -1200 ) N ;
+ - la_data_out[107] + NET la_data_out[107] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2532530 -1200 ) N ;
+ - la_data_out[108] + NET la_data_out[108] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2550470 -1200 ) N ;
+ - la_data_out[109] + NET la_data_out[109] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2567950 -1200 ) N ;
+ - la_data_out[10] + NET la_data_out[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 812590 -1200 ) N ;
+ - la_data_out[110] + NET la_data_out[110] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2585890 -1200 ) N ;
+ - la_data_out[111] + NET la_data_out[111] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2603830 -1200 ) N ;
+ - la_data_out[112] + NET la_data_out[112] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2621310 -1200 ) N ;
+ - la_data_out[113] + NET la_data_out[113] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2639250 -1200 ) N ;
+ - la_data_out[114] + NET la_data_out[114] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2656730 -1200 ) N ;
+ - la_data_out[115] + NET la_data_out[115] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2674670 -1200 ) N ;
+ - la_data_out[116] + NET la_data_out[116] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2692150 -1200 ) N ;
+ - la_data_out[117] + NET la_data_out[117] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2710090 -1200 ) N ;
+ - la_data_out[118] + NET la_data_out[118] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2727570 -1200 ) N ;
+ - la_data_out[119] + NET la_data_out[119] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2745510 -1200 ) N ;
+ - la_data_out[11] + NET la_data_out[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 830530 -1200 ) N ;
+ - la_data_out[120] + NET la_data_out[120] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2763450 -1200 ) N ;
+ - la_data_out[121] + NET la_data_out[121] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2780930 -1200 ) N ;
+ - la_data_out[122] + NET la_data_out[122] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2798870 -1200 ) N ;
+ - la_data_out[123] + NET la_data_out[123] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2816350 -1200 ) N ;
+ - la_data_out[124] + NET la_data_out[124] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2834290 -1200 ) N ;
+ - la_data_out[125] + NET la_data_out[125] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2851770 -1200 ) N ;
+ - la_data_out[126] + NET la_data_out[126] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2869710 -1200 ) N ;
+ - la_data_out[127] + NET la_data_out[127] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2887190 -1200 ) N ;
+ - la_data_out[12] + NET la_data_out[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 848010 -1200 ) N ;
+ - la_data_out[13] + NET la_data_out[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 865950 -1200 ) N ;
+ - la_data_out[14] + NET la_data_out[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 883430 -1200 ) N ;
+ - la_data_out[15] + NET la_data_out[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 901370 -1200 ) N ;
+ - la_data_out[16] + NET la_data_out[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 918850 -1200 ) N ;
+ - la_data_out[17] + NET la_data_out[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 936790 -1200 ) N ;
+ - la_data_out[18] + NET la_data_out[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 954270 -1200 ) N ;
+ - la_data_out[19] + NET la_data_out[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 972210 -1200 ) N ;
+ - la_data_out[1] + NET la_data_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 652970 -1200 ) N ;
+ - la_data_out[20] + NET la_data_out[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 989690 -1200 ) N ;
+ - la_data_out[21] + NET la_data_out[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1007630 -1200 ) N ;
+ - la_data_out[22] + NET la_data_out[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1025570 -1200 ) N ;
+ - la_data_out[23] + NET la_data_out[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1043050 -1200 ) N ;
+ - la_data_out[24] + NET la_data_out[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1060990 -1200 ) N ;
+ - la_data_out[25] + NET la_data_out[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1078470 -1200 ) N ;
+ - la_data_out[26] + NET la_data_out[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1096410 -1200 ) N ;
+ - la_data_out[27] + NET la_data_out[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1113890 -1200 ) N ;
+ - la_data_out[28] + NET la_data_out[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1131830 -1200 ) N ;
+ - la_data_out[29] + NET la_data_out[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1149310 -1200 ) N ;
+ - la_data_out[2] + NET la_data_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 670910 -1200 ) N ;
+ - la_data_out[30] + NET la_data_out[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1167250 -1200 ) N ;
+ - la_data_out[31] + NET la_data_out[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1185190 -1200 ) N ;
+ - la_data_out[32] + NET la_data_out[32] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1202670 -1200 ) N ;
+ - la_data_out[33] + NET la_data_out[33] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1220610 -1200 ) N ;
+ - la_data_out[34] + NET la_data_out[34] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1238090 -1200 ) N ;
+ - la_data_out[35] + NET la_data_out[35] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1256030 -1200 ) N ;
+ - la_data_out[36] + NET la_data_out[36] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1273510 -1200 ) N ;
+ - la_data_out[37] + NET la_data_out[37] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1291450 -1200 ) N ;
+ - la_data_out[38] + NET la_data_out[38] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1308930 -1200 ) N ;
+ - la_data_out[39] + NET la_data_out[39] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1326870 -1200 ) N ;
+ - la_data_out[3] + NET la_data_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 688390 -1200 ) N ;
+ - la_data_out[40] + NET la_data_out[40] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1344350 -1200 ) N ;
+ - la_data_out[41] + NET la_data_out[41] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1362290 -1200 ) N ;
+ - la_data_out[42] + NET la_data_out[42] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1380230 -1200 ) N ;
+ - la_data_out[43] + NET la_data_out[43] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1397710 -1200 ) N ;
+ - la_data_out[44] + NET la_data_out[44] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1415650 -1200 ) N ;
+ - la_data_out[45] + NET la_data_out[45] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1433130 -1200 ) N ;
+ - la_data_out[46] + NET la_data_out[46] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1451070 -1200 ) N ;
+ - la_data_out[47] + NET la_data_out[47] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1468550 -1200 ) N ;
+ - la_data_out[48] + NET la_data_out[48] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1486490 -1200 ) N ;
+ - la_data_out[49] + NET la_data_out[49] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1503970 -1200 ) N ;
+ - la_data_out[4] + NET la_data_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 706330 -1200 ) N ;
+ - la_data_out[50] + NET la_data_out[50] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1521910 -1200 ) N ;
+ - la_data_out[51] + NET la_data_out[51] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1539850 -1200 ) N ;
+ - la_data_out[52] + NET la_data_out[52] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1557330 -1200 ) N ;
+ - la_data_out[53] + NET la_data_out[53] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1575270 -1200 ) N ;
+ - la_data_out[54] + NET la_data_out[54] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1592750 -1200 ) N ;
+ - la_data_out[55] + NET la_data_out[55] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1610690 -1200 ) N ;
+ - la_data_out[56] + NET la_data_out[56] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1628170 -1200 ) N ;
+ - la_data_out[57] + NET la_data_out[57] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1646110 -1200 ) N ;
+ - la_data_out[58] + NET la_data_out[58] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1663590 -1200 ) N ;
+ - la_data_out[59] + NET la_data_out[59] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1681530 -1200 ) N ;
+ - la_data_out[5] + NET la_data_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 723810 -1200 ) N ;
+ - la_data_out[60] + NET la_data_out[60] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1699470 -1200 ) N ;
+ - la_data_out[61] + NET la_data_out[61] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1716950 -1200 ) N ;
+ - la_data_out[62] + NET la_data_out[62] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1734890 -1200 ) N ;
+ - la_data_out[63] + NET la_data_out[63] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1752370 -1200 ) N ;
+ - la_data_out[64] + NET la_data_out[64] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1770310 -1200 ) N ;
+ - la_data_out[65] + NET la_data_out[65] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1787790 -1200 ) N ;
+ - la_data_out[66] + NET la_data_out[66] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1805730 -1200 ) N ;
+ - la_data_out[67] + NET la_data_out[67] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1823210 -1200 ) N ;
+ - la_data_out[68] + NET la_data_out[68] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1841150 -1200 ) N ;
+ - la_data_out[69] + NET la_data_out[69] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1858630 -1200 ) N ;
+ - la_data_out[6] + NET la_data_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 741750 -1200 ) N ;
+ - la_data_out[70] + NET la_data_out[70] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1876570 -1200 ) N ;
+ - la_data_out[71] + NET la_data_out[71] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1894510 -1200 ) N ;
+ - la_data_out[72] + NET la_data_out[72] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1911990 -1200 ) N ;
+ - la_data_out[73] + NET la_data_out[73] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1929930 -1200 ) N ;
+ - la_data_out[74] + NET la_data_out[74] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1947410 -1200 ) N ;
+ - la_data_out[75] + NET la_data_out[75] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1965350 -1200 ) N ;
+ - la_data_out[76] + NET la_data_out[76] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1982830 -1200 ) N ;
+ - la_data_out[77] + NET la_data_out[77] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2000770 -1200 ) N ;
+ - la_data_out[78] + NET la_data_out[78] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2018250 -1200 ) N ;
+ - la_data_out[79] + NET la_data_out[79] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2036190 -1200 ) N ;
+ - la_data_out[7] + NET la_data_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 759230 -1200 ) N ;
+ - la_data_out[80] + NET la_data_out[80] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2054130 -1200 ) N ;
+ - la_data_out[81] + NET la_data_out[81] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2071610 -1200 ) N ;
+ - la_data_out[82] + NET la_data_out[82] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2089550 -1200 ) N ;
+ - la_data_out[83] + NET la_data_out[83] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2107030 -1200 ) N ;
+ - la_data_out[84] + NET la_data_out[84] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2124970 -1200 ) N ;
+ - la_data_out[85] + NET la_data_out[85] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2142450 -1200 ) N ;
+ - la_data_out[86] + NET la_data_out[86] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2160390 -1200 ) N ;
+ - la_data_out[87] + NET la_data_out[87] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2177870 -1200 ) N ;
+ - la_data_out[88] + NET la_data_out[88] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2195810 -1200 ) N ;
+ - la_data_out[89] + NET la_data_out[89] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2213290 -1200 ) N ;
+ - la_data_out[8] + NET la_data_out[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 777170 -1200 ) N ;
+ - la_data_out[90] + NET la_data_out[90] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2231230 -1200 ) N ;
+ - la_data_out[91] + NET la_data_out[91] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2249170 -1200 ) N ;
+ - la_data_out[92] + NET la_data_out[92] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2266650 -1200 ) N ;
+ - la_data_out[93] + NET la_data_out[93] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2284590 -1200 ) N ;
+ - la_data_out[94] + NET la_data_out[94] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2302070 -1200 ) N ;
+ - la_data_out[95] + NET la_data_out[95] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2320010 -1200 ) N ;
+ - la_data_out[96] + NET la_data_out[96] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2337490 -1200 ) N ;
+ - la_data_out[97] + NET la_data_out[97] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2355430 -1200 ) N ;
+ - la_data_out[98] + NET la_data_out[98] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2372910 -1200 ) N ;
+ - la_data_out[99] + NET la_data_out[99] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2390850 -1200 ) N ;
+ - la_data_out[9] + NET la_data_out[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 794650 -1200 ) N ;
+ - la_oenb[0] + NET la_oenb[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 641010 -1200 ) N ;
+ - la_oenb[100] + NET la_oenb[100] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2414310 -1200 ) N ;
+ - la_oenb[101] + NET la_oenb[101] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2432250 -1200 ) N ;
+ - la_oenb[102] + NET la_oenb[102] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2449730 -1200 ) N ;
+ - la_oenb[103] + NET la_oenb[103] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2467670 -1200 ) N ;
+ - la_oenb[104] + NET la_oenb[104] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2485610 -1200 ) N ;
+ - la_oenb[105] + NET la_oenb[105] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2503090 -1200 ) N ;
+ - la_oenb[106] + NET la_oenb[106] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2521030 -1200 ) N ;
+ - la_oenb[107] + NET la_oenb[107] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2538510 -1200 ) N ;
+ - la_oenb[108] + NET la_oenb[108] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2556450 -1200 ) N ;
+ - la_oenb[109] + NET la_oenb[109] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2573930 -1200 ) N ;
+ - la_oenb[10] + NET la_oenb[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 818570 -1200 ) N ;
+ - la_oenb[110] + NET la_oenb[110] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2591870 -1200 ) N ;
+ - la_oenb[111] + NET la_oenb[111] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2609350 -1200 ) N ;
+ - la_oenb[112] + NET la_oenb[112] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2627290 -1200 ) N ;
+ - la_oenb[113] + NET la_oenb[113] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2645230 -1200 ) N ;
+ - la_oenb[114] + NET la_oenb[114] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2662710 -1200 ) N ;
+ - la_oenb[115] + NET la_oenb[115] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2680650 -1200 ) N ;
+ - la_oenb[116] + NET la_oenb[116] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2698130 -1200 ) N ;
+ - la_oenb[117] + NET la_oenb[117] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2716070 -1200 ) N ;
+ - la_oenb[118] + NET la_oenb[118] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2733550 -1200 ) N ;
+ - la_oenb[119] + NET la_oenb[119] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2751490 -1200 ) N ;
+ - la_oenb[11] + NET la_oenb[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 836050 -1200 ) N ;
+ - la_oenb[120] + NET la_oenb[120] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2768970 -1200 ) N ;
+ - la_oenb[121] + NET la_oenb[121] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2786910 -1200 ) N ;
+ - la_oenb[122] + NET la_oenb[122] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2804390 -1200 ) N ;
+ - la_oenb[123] + NET la_oenb[123] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2822330 -1200 ) N ;
+ - la_oenb[124] + NET la_oenb[124] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2840270 -1200 ) N ;
+ - la_oenb[125] + NET la_oenb[125] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2857750 -1200 ) N ;
+ - la_oenb[126] + NET la_oenb[126] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2875690 -1200 ) N ;
+ - la_oenb[127] + NET la_oenb[127] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2893170 -1200 ) N ;
+ - la_oenb[12] + NET la_oenb[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 853990 -1200 ) N ;
+ - la_oenb[13] + NET la_oenb[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 871470 -1200 ) N ;
+ - la_oenb[14] + NET la_oenb[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 889410 -1200 ) N ;
+ - la_oenb[15] + NET la_oenb[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 907350 -1200 ) N ;
+ - la_oenb[16] + NET la_oenb[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 924830 -1200 ) N ;
+ - la_oenb[17] + NET la_oenb[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 942770 -1200 ) N ;
+ - la_oenb[18] + NET la_oenb[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 960250 -1200 ) N ;
+ - la_oenb[19] + NET la_oenb[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 978190 -1200 ) N ;
+ - la_oenb[1] + NET la_oenb[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 658950 -1200 ) N ;
+ - la_oenb[20] + NET la_oenb[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 995670 -1200 ) N ;
+ - la_oenb[21] + NET la_oenb[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1013610 -1200 ) N ;
+ - la_oenb[22] + NET la_oenb[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1031090 -1200 ) N ;
+ - la_oenb[23] + NET la_oenb[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1049030 -1200 ) N ;
+ - la_oenb[24] + NET la_oenb[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1066970 -1200 ) N ;
+ - la_oenb[25] + NET la_oenb[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1084450 -1200 ) N ;
+ - la_oenb[26] + NET la_oenb[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1102390 -1200 ) N ;
+ - la_oenb[27] + NET la_oenb[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1119870 -1200 ) N ;
+ - la_oenb[28] + NET la_oenb[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1137810 -1200 ) N ;
+ - la_oenb[29] + NET la_oenb[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1155290 -1200 ) N ;
+ - la_oenb[2] + NET la_oenb[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 676430 -1200 ) N ;
+ - la_oenb[30] + NET la_oenb[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1173230 -1200 ) N ;
+ - la_oenb[31] + NET la_oenb[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1190710 -1200 ) N ;
+ - la_oenb[32] + NET la_oenb[32] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1208650 -1200 ) N ;
+ - la_oenb[33] + NET la_oenb[33] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1226130 -1200 ) N ;
+ - la_oenb[34] + NET la_oenb[34] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1244070 -1200 ) N ;
+ - la_oenb[35] + NET la_oenb[35] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1262010 -1200 ) N ;
+ - la_oenb[36] + NET la_oenb[36] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1279490 -1200 ) N ;
+ - la_oenb[37] + NET la_oenb[37] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1297430 -1200 ) N ;
+ - la_oenb[38] + NET la_oenb[38] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1314910 -1200 ) N ;
+ - la_oenb[39] + NET la_oenb[39] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1332850 -1200 ) N ;
+ - la_oenb[3] + NET la_oenb[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 694370 -1200 ) N ;
+ - la_oenb[40] + NET la_oenb[40] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1350330 -1200 ) N ;
+ - la_oenb[41] + NET la_oenb[41] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1368270 -1200 ) N ;
+ - la_oenb[42] + NET la_oenb[42] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1385750 -1200 ) N ;
+ - la_oenb[43] + NET la_oenb[43] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1403690 -1200 ) N ;
+ - la_oenb[44] + NET la_oenb[44] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1421630 -1200 ) N ;
+ - la_oenb[45] + NET la_oenb[45] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1439110 -1200 ) N ;
+ - la_oenb[46] + NET la_oenb[46] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1457050 -1200 ) N ;
+ - la_oenb[47] + NET la_oenb[47] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1474530 -1200 ) N ;
+ - la_oenb[48] + NET la_oenb[48] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1492470 -1200 ) N ;
+ - la_oenb[49] + NET la_oenb[49] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1509950 -1200 ) N ;
+ - la_oenb[4] + NET la_oenb[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 712310 -1200 ) N ;
+ - la_oenb[50] + NET la_oenb[50] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1527890 -1200 ) N ;
+ - la_oenb[51] + NET la_oenb[51] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1545370 -1200 ) N ;
+ - la_oenb[52] + NET la_oenb[52] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1563310 -1200 ) N ;
+ - la_oenb[53] + NET la_oenb[53] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1581250 -1200 ) N ;
+ - la_oenb[54] + NET la_oenb[54] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1598730 -1200 ) N ;
+ - la_oenb[55] + NET la_oenb[55] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1616670 -1200 ) N ;
+ - la_oenb[56] + NET la_oenb[56] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1634150 -1200 ) N ;
+ - la_oenb[57] + NET la_oenb[57] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1652090 -1200 ) N ;
+ - la_oenb[58] + NET la_oenb[58] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1669570 -1200 ) N ;
+ - la_oenb[59] + NET la_oenb[59] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1687510 -1200 ) N ;
+ - la_oenb[5] + NET la_oenb[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 729790 -1200 ) N ;
+ - la_oenb[60] + NET la_oenb[60] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1704990 -1200 ) N ;
+ - la_oenb[61] + NET la_oenb[61] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1722930 -1200 ) N ;
+ - la_oenb[62] + NET la_oenb[62] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1740410 -1200 ) N ;
+ - la_oenb[63] + NET la_oenb[63] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1758350 -1200 ) N ;
+ - la_oenb[64] + NET la_oenb[64] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1776290 -1200 ) N ;
+ - la_oenb[65] + NET la_oenb[65] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1793770 -1200 ) N ;
+ - la_oenb[66] + NET la_oenb[66] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1811710 -1200 ) N ;
+ - la_oenb[67] + NET la_oenb[67] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1829190 -1200 ) N ;
+ - la_oenb[68] + NET la_oenb[68] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1847130 -1200 ) N ;
+ - la_oenb[69] + NET la_oenb[69] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1864610 -1200 ) N ;
+ - la_oenb[6] + NET la_oenb[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 747730 -1200 ) N ;
+ - la_oenb[70] + NET la_oenb[70] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1882550 -1200 ) N ;
+ - la_oenb[71] + NET la_oenb[71] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1900030 -1200 ) N ;
+ - la_oenb[72] + NET la_oenb[72] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1917970 -1200 ) N ;
+ - la_oenb[73] + NET la_oenb[73] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1935910 -1200 ) N ;
+ - la_oenb[74] + NET la_oenb[74] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1953390 -1200 ) N ;
+ - la_oenb[75] + NET la_oenb[75] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1971330 -1200 ) N ;
+ - la_oenb[76] + NET la_oenb[76] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 1988810 -1200 ) N ;
+ - la_oenb[77] + NET la_oenb[77] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2006750 -1200 ) N ;
+ - la_oenb[78] + NET la_oenb[78] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2024230 -1200 ) N ;
+ - la_oenb[79] + NET la_oenb[79] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2042170 -1200 ) N ;
+ - la_oenb[7] + NET la_oenb[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 765210 -1200 ) N ;
+ - la_oenb[80] + NET la_oenb[80] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2059650 -1200 ) N ;
+ - la_oenb[81] + NET la_oenb[81] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2077590 -1200 ) N ;
+ - la_oenb[82] + NET la_oenb[82] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2095070 -1200 ) N ;
+ - la_oenb[83] + NET la_oenb[83] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2113010 -1200 ) N ;
+ - la_oenb[84] + NET la_oenb[84] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2130950 -1200 ) N ;
+ - la_oenb[85] + NET la_oenb[85] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2148430 -1200 ) N ;
+ - la_oenb[86] + NET la_oenb[86] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2166370 -1200 ) N ;
+ - la_oenb[87] + NET la_oenb[87] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2183850 -1200 ) N ;
+ - la_oenb[88] + NET la_oenb[88] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2201790 -1200 ) N ;
+ - la_oenb[89] + NET la_oenb[89] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2219270 -1200 ) N ;
+ - la_oenb[8] + NET la_oenb[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 783150 -1200 ) N ;
+ - la_oenb[90] + NET la_oenb[90] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2237210 -1200 ) N ;
+ - la_oenb[91] + NET la_oenb[91] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2254690 -1200 ) N ;
+ - la_oenb[92] + NET la_oenb[92] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2272630 -1200 ) N ;
+ - la_oenb[93] + NET la_oenb[93] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2290570 -1200 ) N ;
+ - la_oenb[94] + NET la_oenb[94] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2308050 -1200 ) N ;
+ - la_oenb[95] + NET la_oenb[95] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2325990 -1200 ) N ;
+ - la_oenb[96] + NET la_oenb[96] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2343470 -1200 ) N ;
+ - la_oenb[97] + NET la_oenb[97] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2361410 -1200 ) N ;
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+ + LAYER met4 ( -313930 -1769310 ) ( -310830 1769310 )
+ + LAYER met4 ( -493930 -1769310 ) ( -490830 1769310 )
+ + LAYER met4 ( -673930 -1769310 ) ( -670830 1769310 )
+ + LAYER met4 ( -853930 540160 ) ( -850830 1769310 )
+ + LAYER met4 ( -1033930 540160 ) ( -1030830 1769310 )
+ + LAYER met4 ( -1213930 540160 ) ( -1210830 1769310 )
+ + LAYER met4 ( -1393930 540160 ) ( -1390830 1769310 )
+ + LAYER met4 ( -1573930 540160 ) ( -1570830 1769310 )
+ + LAYER met4 ( -1753930 540160 ) ( -1750830 1769310 )
+ + LAYER met4 ( -1933930 -1769310 ) ( -1930830 1769310 )
+ + LAYER met4 ( -2113930 -1769310 ) ( -2110830 1769310 )
+ + LAYER met4 ( -2293930 -1769310 ) ( -2290830 1769310 )
+ + LAYER met4 ( -2473930 -1769310 ) ( -2470830 1769310 )
+ + LAYER met4 ( -2653930 -1769310 ) ( -2650830 1769310 )
+ + LAYER met4 ( -2833930 -1769310 ) ( -2830830 1769310 )
+ + LAYER met4 ( -2947730 -1769310 ) ( -2944630 1769310 )
+ + LAYER met4 ( -853930 -1769310 ) ( -850830 -79840 )
+ + LAYER met4 ( -1033930 -1769310 ) ( -1030830 -79840 )
+ + LAYER met4 ( -1213930 -1769310 ) ( -1210830 -79840 )
+ + LAYER met4 ( -1393930 -1769310 ) ( -1390830 -79840 )
+ + LAYER met4 ( -1573930 -1769310 ) ( -1570830 -79840 )
+ + LAYER met4 ( -1753930 -1769310 ) ( -1750830 -79840 )
+ + LAYER met5 ( -2947730 1766210 ) ( 1550 1769310 )
+ + LAYER met5 ( -2947730 1584490 ) ( 1550 1587590 )
+ + LAYER met5 ( -2947730 1404490 ) ( 1550 1407590 )
+ + LAYER met5 ( -2947730 1224490 ) ( 1550 1227590 )
+ + LAYER met5 ( -2947730 1044490 ) ( 1550 1047590 )
+ + LAYER met5 ( -2947730 864490 ) ( 1550 867590 )
+ + LAYER met5 ( -2947730 684490 ) ( 1550 687590 )
+ + LAYER met5 ( -2947730 504490 ) ( 1550 507590 )
+ + LAYER met5 ( -2947730 324490 ) ( 1550 327590 )
+ + LAYER met5 ( -2947730 144490 ) ( 1550 147590 )
+ + LAYER met5 ( -2947730 -35510 ) ( 1550 -32410 )
+ + LAYER met5 ( -2947730 -215510 ) ( 1550 -212410 )
+ + LAYER met5 ( -2947730 -395510 ) ( 1550 -392410 )
+ + LAYER met5 ( -2947730 -575510 ) ( 1550 -572410 )
+ + LAYER met5 ( -2947730 -755510 ) ( 1550 -752410 )
+ + LAYER met5 ( -2947730 -935510 ) ( 1550 -932410 )
+ + LAYER met5 ( -2947730 -1115510 ) ( 1550 -1112410 )
+ + LAYER met5 ( -2947730 -1295510 ) ( 1550 -1292410 )
+ + LAYER met5 ( -2947730 -1475510 ) ( 1550 -1472410 )
+ + LAYER met5 ( -2947730 -1655510 ) ( 1550 -1652410 )
+ + LAYER met5 ( -2947730 -1769310 ) ( 1550 -1766210 )
+ + FIXED ( 2932900 1759840 ) N ;
+ - vssd2 + NET vssd2 + SPECIAL + DIRECTION INPUT + USE GROUND
+ + PORT
+ + LAYER met4 ( -1550 -1778910 ) ( 1550 1778910 )
+ + LAYER met4 ( -124930 -1778910 ) ( -121830 1778910 )
+ + LAYER met4 ( -304930 -1778910 ) ( -301830 1778910 )
+ + LAYER met4 ( -484930 -1778910 ) ( -481830 1778910 )
+ + LAYER met4 ( -664930 -1778910 ) ( -661830 1778910 )
+ + LAYER met4 ( -844930 -1778910 ) ( -841830 1778910 )
+ + LAYER met4 ( -1024930 540160 ) ( -1021830 1778910 )
+ + LAYER met4 ( -1204930 540160 ) ( -1201830 1778910 )
+ + LAYER met4 ( -1384930 540160 ) ( -1381830 1778910 )
+ + LAYER met4 ( -1564930 540160 ) ( -1561830 1778910 )
+ + LAYER met4 ( -1744930 540160 ) ( -1741830 1778910 )
+ + LAYER met4 ( -1924930 -1778910 ) ( -1921830 1778910 )
+ + LAYER met4 ( -2104930 -1778910 ) ( -2101830 1778910 )
+ + LAYER met4 ( -2284930 -1778910 ) ( -2281830 1778910 )
+ + LAYER met4 ( -2464930 -1778910 ) ( -2461830 1778910 )
+ + LAYER met4 ( -2644930 -1778910 ) ( -2641830 1778910 )
+ + LAYER met4 ( -2824930 -1778910 ) ( -2821830 1778910 )
+ + LAYER met4 ( -2966930 -1778910 ) ( -2963830 1778910 )
+ + LAYER met4 ( -1024930 -1778910 ) ( -1021830 -79840 )
+ + LAYER met4 ( -1204930 -1778910 ) ( -1201830 -79840 )
+ + LAYER met4 ( -1384930 -1778910 ) ( -1381830 -79840 )
+ + LAYER met4 ( -1564930 -1778910 ) ( -1561830 -79840 )
+ + LAYER met4 ( -1744930 -1778910 ) ( -1741830 -79840 )
+ + LAYER met5 ( -2966930 1775810 ) ( 1550 1778910 )
+ + LAYER met5 ( -2966930 1603090 ) ( 1550 1606190 )
+ + LAYER met5 ( -2966930 1423090 ) ( 1550 1426190 )
+ + LAYER met5 ( -2966930 1243090 ) ( 1550 1246190 )
+ + LAYER met5 ( -2966930 1063090 ) ( 1550 1066190 )
+ + LAYER met5 ( -2966930 883090 ) ( 1550 886190 )
+ + LAYER met5 ( -2966930 703090 ) ( 1550 706190 )
+ + LAYER met5 ( -2966930 523090 ) ( 1550 526190 )
+ + LAYER met5 ( -2966930 343090 ) ( 1550 346190 )
+ + LAYER met5 ( -2966930 163090 ) ( 1550 166190 )
+ + LAYER met5 ( -2966930 -16910 ) ( 1550 -13810 )
+ + LAYER met5 ( -2966930 -196910 ) ( 1550 -193810 )
+ + LAYER met5 ( -2966930 -376910 ) ( 1550 -373810 )
+ + LAYER met5 ( -2966930 -556910 ) ( 1550 -553810 )
+ + LAYER met5 ( -2966930 -736910 ) ( 1550 -733810 )
+ + LAYER met5 ( -2966930 -916910 ) ( 1550 -913810 )
+ + LAYER met5 ( -2966930 -1096910 ) ( 1550 -1093810 )
+ + LAYER met5 ( -2966930 -1276910 ) ( 1550 -1273810 )
+ + LAYER met5 ( -2966930 -1456910 ) ( 1550 -1453810 )
+ + LAYER met5 ( -2966930 -1636910 ) ( 1550 -1633810 )
+ + LAYER met5 ( -2966930 -1778910 ) ( 1550 -1775810 )
+ + FIXED ( 2942500 1759840 ) N ;
+ - wb_clk_i + NET wb_clk_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 2990 -1200 ) N ;
+ - wb_rst_i + NET wb_rst_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 8510 -1200 ) N ;
+ - wbs_ack_o + NET wbs_ack_o + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 14490 -1200 ) N ;
+ - wbs_adr_i[0] + NET wbs_adr_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 38410 -1200 ) N ;
+ - wbs_adr_i[10] + NET wbs_adr_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 239430 -1200 ) N ;
+ - wbs_adr_i[11] + NET wbs_adr_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 256910 -1200 ) N ;
+ - wbs_adr_i[12] + NET wbs_adr_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 274850 -1200 ) N ;
+ - wbs_adr_i[13] + NET wbs_adr_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 292330 -1200 ) N ;
+ - wbs_adr_i[14] + NET wbs_adr_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 310270 -1200 ) N ;
+ - wbs_adr_i[15] + NET wbs_adr_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 327750 -1200 ) N ;
+ - wbs_adr_i[16] + NET wbs_adr_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 345690 -1200 ) N ;
+ - wbs_adr_i[17] + NET wbs_adr_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 363170 -1200 ) N ;
+ - wbs_adr_i[18] + NET wbs_adr_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 381110 -1200 ) N ;
+ - wbs_adr_i[19] + NET wbs_adr_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 398590 -1200 ) N ;
+ - wbs_adr_i[1] + NET wbs_adr_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 61870 -1200 ) N ;
+ - wbs_adr_i[20] + NET wbs_adr_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 416530 -1200 ) N ;
+ - wbs_adr_i[21] + NET wbs_adr_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 434470 -1200 ) N ;
+ - wbs_adr_i[22] + NET wbs_adr_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 451950 -1200 ) N ;
+ - wbs_adr_i[23] + NET wbs_adr_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 469890 -1200 ) N ;
+ - wbs_adr_i[24] + NET wbs_adr_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 487370 -1200 ) N ;
+ - wbs_adr_i[25] + NET wbs_adr_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 505310 -1200 ) N ;
+ - wbs_adr_i[26] + NET wbs_adr_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 522790 -1200 ) N ;
+ - wbs_adr_i[27] + NET wbs_adr_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 540730 -1200 ) N ;
+ - wbs_adr_i[28] + NET wbs_adr_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 558210 -1200 ) N ;
+ - wbs_adr_i[29] + NET wbs_adr_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 576150 -1200 ) N ;
+ - wbs_adr_i[2] + NET wbs_adr_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 85330 -1200 ) N ;
+ - wbs_adr_i[30] + NET wbs_adr_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 594090 -1200 ) N ;
+ - wbs_adr_i[31] + NET wbs_adr_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 611570 -1200 ) N ;
+ - wbs_adr_i[3] + NET wbs_adr_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 109250 -1200 ) N ;
+ - wbs_adr_i[4] + NET wbs_adr_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 132710 -1200 ) N ;
+ - wbs_adr_i[5] + NET wbs_adr_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 150650 -1200 ) N ;
+ - wbs_adr_i[6] + NET wbs_adr_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 168130 -1200 ) N ;
+ - wbs_adr_i[7] + NET wbs_adr_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 186070 -1200 ) N ;
+ - wbs_adr_i[8] + NET wbs_adr_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 203550 -1200 ) N ;
+ - wbs_adr_i[9] + NET wbs_adr_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 221490 -1200 ) N ;
+ - wbs_cyc_i + NET wbs_cyc_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 20470 -1200 ) N ;
+ - wbs_dat_i[0] + NET wbs_dat_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 43930 -1200 ) N ;
+ - wbs_dat_i[10] + NET wbs_dat_i[10] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 244950 -1200 ) N ;
+ - wbs_dat_i[11] + NET wbs_dat_i[11] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 262890 -1200 ) N ;
+ - wbs_dat_i[12] + NET wbs_dat_i[12] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 280370 -1200 ) N ;
+ - wbs_dat_i[13] + NET wbs_dat_i[13] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 298310 -1200 ) N ;
+ - wbs_dat_i[14] + NET wbs_dat_i[14] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 316250 -1200 ) N ;
+ - wbs_dat_i[15] + NET wbs_dat_i[15] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 333730 -1200 ) N ;
+ - wbs_dat_i[16] + NET wbs_dat_i[16] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 351670 -1200 ) N ;
+ - wbs_dat_i[17] + NET wbs_dat_i[17] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 369150 -1200 ) N ;
+ - wbs_dat_i[18] + NET wbs_dat_i[18] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 387090 -1200 ) N ;
+ - wbs_dat_i[19] + NET wbs_dat_i[19] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 404570 -1200 ) N ;
+ - wbs_dat_i[1] + NET wbs_dat_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 67850 -1200 ) N ;
+ - wbs_dat_i[20] + NET wbs_dat_i[20] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 422510 -1200 ) N ;
+ - wbs_dat_i[21] + NET wbs_dat_i[21] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 439990 -1200 ) N ;
+ - wbs_dat_i[22] + NET wbs_dat_i[22] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 457930 -1200 ) N ;
+ - wbs_dat_i[23] + NET wbs_dat_i[23] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 475870 -1200 ) N ;
+ - wbs_dat_i[24] + NET wbs_dat_i[24] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 493350 -1200 ) N ;
+ - wbs_dat_i[25] + NET wbs_dat_i[25] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 511290 -1200 ) N ;
+ - wbs_dat_i[26] + NET wbs_dat_i[26] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 528770 -1200 ) N ;
+ - wbs_dat_i[27] + NET wbs_dat_i[27] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 546710 -1200 ) N ;
+ - wbs_dat_i[28] + NET wbs_dat_i[28] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 564190 -1200 ) N ;
+ - wbs_dat_i[29] + NET wbs_dat_i[29] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 582130 -1200 ) N ;
+ - wbs_dat_i[2] + NET wbs_dat_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 91310 -1200 ) N ;
+ - wbs_dat_i[30] + NET wbs_dat_i[30] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 599610 -1200 ) N ;
+ - wbs_dat_i[31] + NET wbs_dat_i[31] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 617550 -1200 ) N ;
+ - wbs_dat_i[3] + NET wbs_dat_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 115230 -1200 ) N ;
+ - wbs_dat_i[4] + NET wbs_dat_i[4] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 138690 -1200 ) N ;
+ - wbs_dat_i[5] + NET wbs_dat_i[5] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 156630 -1200 ) N ;
+ - wbs_dat_i[6] + NET wbs_dat_i[6] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 174110 -1200 ) N ;
+ - wbs_dat_i[7] + NET wbs_dat_i[7] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 192050 -1200 ) N ;
+ - wbs_dat_i[8] + NET wbs_dat_i[8] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 209530 -1200 ) N ;
+ - wbs_dat_i[9] + NET wbs_dat_i[9] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 227470 -1200 ) N ;
+ - wbs_dat_o[0] + NET wbs_dat_o[0] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 49910 -1200 ) N ;
+ - wbs_dat_o[10] + NET wbs_dat_o[10] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 250930 -1200 ) N ;
+ - wbs_dat_o[11] + NET wbs_dat_o[11] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 268870 -1200 ) N ;
+ - wbs_dat_o[12] + NET wbs_dat_o[12] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 286350 -1200 ) N ;
+ - wbs_dat_o[13] + NET wbs_dat_o[13] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 304290 -1200 ) N ;
+ - wbs_dat_o[14] + NET wbs_dat_o[14] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 321770 -1200 ) N ;
+ - wbs_dat_o[15] + NET wbs_dat_o[15] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 339710 -1200 ) N ;
+ - wbs_dat_o[16] + NET wbs_dat_o[16] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 357650 -1200 ) N ;
+ - wbs_dat_o[17] + NET wbs_dat_o[17] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 375130 -1200 ) N ;
+ - wbs_dat_o[18] + NET wbs_dat_o[18] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 393070 -1200 ) N ;
+ - wbs_dat_o[19] + NET wbs_dat_o[19] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 410550 -1200 ) N ;
+ - wbs_dat_o[1] + NET wbs_dat_o[1] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 73830 -1200 ) N ;
+ - wbs_dat_o[20] + NET wbs_dat_o[20] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 428490 -1200 ) N ;
+ - wbs_dat_o[21] + NET wbs_dat_o[21] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 445970 -1200 ) N ;
+ - wbs_dat_o[22] + NET wbs_dat_o[22] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 463910 -1200 ) N ;
+ - wbs_dat_o[23] + NET wbs_dat_o[23] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 481390 -1200 ) N ;
+ - wbs_dat_o[24] + NET wbs_dat_o[24] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 499330 -1200 ) N ;
+ - wbs_dat_o[25] + NET wbs_dat_o[25] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 516810 -1200 ) N ;
+ - wbs_dat_o[26] + NET wbs_dat_o[26] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 534750 -1200 ) N ;
+ - wbs_dat_o[27] + NET wbs_dat_o[27] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 552690 -1200 ) N ;
+ - wbs_dat_o[28] + NET wbs_dat_o[28] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 570170 -1200 ) N ;
+ - wbs_dat_o[29] + NET wbs_dat_o[29] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 588110 -1200 ) N ;
+ - wbs_dat_o[2] + NET wbs_dat_o[2] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 97290 -1200 ) N ;
+ - wbs_dat_o[30] + NET wbs_dat_o[30] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 605590 -1200 ) N ;
+ - wbs_dat_o[31] + NET wbs_dat_o[31] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 623530 -1200 ) N ;
+ - wbs_dat_o[3] + NET wbs_dat_o[3] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 121210 -1200 ) N ;
+ - wbs_dat_o[4] + NET wbs_dat_o[4] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 144670 -1200 ) N ;
+ - wbs_dat_o[5] + NET wbs_dat_o[5] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 162150 -1200 ) N ;
+ - wbs_dat_o[6] + NET wbs_dat_o[6] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 180090 -1200 ) N ;
+ - wbs_dat_o[7] + NET wbs_dat_o[7] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 198030 -1200 ) N ;
+ - wbs_dat_o[8] + NET wbs_dat_o[8] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 215510 -1200 ) N ;
+ - wbs_dat_o[9] + NET wbs_dat_o[9] + DIRECTION OUTPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 233450 -1200 ) N ;
+ - wbs_sel_i[0] + NET wbs_sel_i[0] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 55890 -1200 ) N ;
+ - wbs_sel_i[1] + NET wbs_sel_i[1] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 79810 -1200 ) N ;
+ - wbs_sel_i[2] + NET wbs_sel_i[2] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 103270 -1200 ) N ;
+ - wbs_sel_i[3] + NET wbs_sel_i[3] + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 126730 -1200 ) N ;
+ - wbs_stb_i + NET wbs_stb_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 26450 -1200 ) N ;
+ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL
+ + PORT
+ + LAYER met2 ( -280 -3600 ) ( 280 3600 )
+ + PLACED ( 32430 -1200 ) N ;
+END PINS
+SPECIALNETS 8 ;
+ - vccd1 ( PIN vccd1 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 1964840 2175880 ) via4_1600x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1657640 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 2175880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1995880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1964840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1811240 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1657640 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1504040 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1350440 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 1196840 1815880 ) via4_1600x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3522800 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3435880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3255880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 3075880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2895880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2715880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2535880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2355880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 2175880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1995880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2890520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2710520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 1815880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1635880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2928100 1275880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 1275880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 1095880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1990520 915880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1630520 915880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 915880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 735880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2710520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 735880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1630520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 735880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 735880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2928100 555880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -8480 15880 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2710520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2530520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2350520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2170520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1990520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1810520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1630520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1450520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1270520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1090520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 910520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 730520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 550520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 370520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 190520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 10520 -3120 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -8480 -3120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -10030 3522800 ) ( 2929650 3522800 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3435880 ) ( 2934450 3435880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3255880 ) ( 2934450 3255880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3075880 ) ( 2934450 3075880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2895880 ) ( 2934450 2895880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2715880 ) ( 2934450 2715880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2535880 ) ( 2934450 2535880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2355880 ) ( 2934450 2355880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2175880 ) ( 2934450 2175880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1995880 ) ( 2934450 1995880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1815880 ) ( 2934450 1815880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1635880 ) ( 2934450 1635880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1455880 ) ( 2934450 1455880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1275880 ) ( 2934450 1275880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1095880 ) ( 2934450 1095880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 915880 ) ( 2934450 915880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 735880 ) ( 2934450 735880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 555880 ) ( 2934450 555880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 375880 ) ( 2934450 375880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 195880 ) ( 2934450 195880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 15880 ) ( 2934450 15880 )
+ NEW met5 3100 + SHAPE STRIPE ( -10030 -3120 ) ( 2929650 -3120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2890520 -9470 ) ( 2890520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2710520 -9470 ) ( 2710520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2530520 -9470 ) ( 2530520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2350520 -9470 ) ( 2350520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2170520 -9470 ) ( 2170520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 2300000 ) ( 1990520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 2300000 ) ( 1810520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 2300000 ) ( 1630520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 2300000 ) ( 1450520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 2300000 ) ( 1270520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1090520 -9470 ) ( 1090520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 910520 -9470 ) ( 910520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 730520 -9470 ) ( 730520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 550520 -9470 ) ( 550520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 370520 -9470 ) ( 370520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 190520 -9470 ) ( 190520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 10520 -9470 ) ( 10520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2928100 -4670 ) ( 2928100 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( -8480 -4670 ) ( -8480 3524350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1990520 -9470 ) ( 1990520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1810520 -9470 ) ( 1810520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1630520 -9470 ) ( 1630520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1450520 -9470 ) ( 1450520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1270520 -9470 ) ( 1270520 1680000 ) ;
+ - vccd2 ( PIN vccd2 ) + USE POWER
+ + ROUTED met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2549120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3532400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 3532400 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2937700 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2729120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2009120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1829120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1649120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 749120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 569120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 3454480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 3454480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1649120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1469120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1289120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1109120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 394480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 569120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 389120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 209120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 29120 394480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -18080 394480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2909120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2729120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2549120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2369120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2189120 214480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1109120 214480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 929120 214480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 569120 214480 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -18080 214480 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -24430 3454480 ) ( 2944050 3454480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3274480 ) ( 2944050 3274480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3094480 ) ( 2944050 3094480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2914480 ) ( 2944050 2914480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2734480 ) ( 2944050 2734480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2554480 ) ( 2944050 2554480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2374480 ) ( 2944050 2374480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2194480 ) ( 2944050 2194480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2014480 ) ( 2944050 2014480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1834480 ) ( 2944050 1834480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1654480 ) ( 2944050 1654480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1474480 ) ( 2944050 1474480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1294480 ) ( 2944050 1294480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1114480 ) ( 2944050 1114480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 934480 ) ( 2944050 934480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 754480 ) ( 2944050 754480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 574480 ) ( 2944050 574480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 394480 ) ( 2944050 394480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 214480 ) ( 2944050 214480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 34480 ) ( 2944050 34480 )
+ NEW met5 3100 + SHAPE STRIPE ( -19630 -12720 ) ( 2939250 -12720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2909120 -19070 ) ( 2909120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2729120 -19070 ) ( 2729120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2549120 -19070 ) ( 2549120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2369120 -19070 ) ( 2369120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2189120 -19070 ) ( 2189120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 2300000 ) ( 2009120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 2300000 ) ( 1829120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 2300000 ) ( 1649120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 2300000 ) ( 1469120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 2300000 ) ( 1289120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1109120 -19070 ) ( 1109120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 929120 -19070 ) ( 929120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 749120 -19070 ) ( 749120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 569120 -19070 ) ( 569120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 389120 -19070 ) ( 389120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 209120 -19070 ) ( 209120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 29120 -19070 ) ( 29120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2937700 -14270 ) ( 2937700 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( -18080 -14270 ) ( -18080 3533950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2009120 -19070 ) ( 2009120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1829120 -19070 ) ( 1829120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1649120 -19070 ) ( 1649120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1469120 -19070 ) ( 1469120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1289120 -19070 ) ( 1289120 1680000 ) ;
+ - vdda1 ( PIN vdda1 ) + USE POWER
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+ NEW met4 0 + SHAPE STRIPE ( 2567720 2753080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 227720 2753080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 767720 2573080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2387720 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1667720 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1127720 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 767720 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 227720 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -27680 2393080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2567720 2213080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1127720 2213080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 767720 2213080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 227720 2213080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -27680 2213080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 767720 2033080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 227720 2033080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -27680 2033080 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 3113080 ) ( 2953650 3113080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2933080 ) ( 2953650 2933080 )
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+ NEW met5 3100 + SHAPE STRIPE ( -34030 773080 ) ( 2953650 773080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 593080 ) ( 2953650 593080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 413080 ) ( 2953650 413080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 233080 ) ( 2953650 233080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 53080 ) ( 2953650 53080 )
+ NEW met5 3100 + SHAPE STRIPE ( -29230 -22320 ) ( 2948850 -22320 )
+ NEW met4 3100 + SHAPE STRIPE ( 2747720 -28670 ) ( 2747720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2567720 -28670 ) ( 2567720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2387720 -28670 ) ( 2387720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2207720 -28670 ) ( 2207720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 2300000 ) ( 2027720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1847720 2300000 ) ( 1847720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1667720 2300000 ) ( 1667720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1487720 2300000 ) ( 1487720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 2300000 ) ( 1307720 3548350 )
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+ NEW met4 3100 + SHAPE STRIPE ( 947720 -28670 ) ( 947720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 767720 -28670 ) ( 767720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 587720 -28670 ) ( 587720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 407720 -28670 ) ( 407720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 227720 -28670 ) ( 227720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 47720 -28670 ) ( 47720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2947300 -23870 ) ( 2947300 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( -27680 -23870 ) ( -27680 3543550 )
+ NEW met4 3100 + SHAPE STRIPE ( 2027720 -28670 ) ( 2027720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1847720 -28670 ) ( 1847720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1667720 -28670 ) ( 1667720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1487720 -28670 ) ( 1487720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1307720 -28670 ) ( 1307720 1680000 ) ;
+ - vdda2 ( PIN vdda2 ) + USE POWER
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 1691680 ) ( 2963250 1691680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1511680 ) ( 2963250 1511680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1331680 ) ( 2963250 1331680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1151680 ) ( 2963250 1151680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 971680 ) ( 2963250 971680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 791680 ) ( 2963250 791680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 611680 ) ( 2963250 611680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 431680 ) ( 2963250 431680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 251680 ) ( 2963250 251680 )
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+ NEW met5 3100 + SHAPE STRIPE ( -38830 -31920 ) ( 2958450 -31920 )
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+ NEW met4 3100 + SHAPE STRIPE ( 2586320 -38270 ) ( 2586320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2406320 -38270 ) ( 2406320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2226320 -38270 ) ( 2226320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2046320 2300000 ) ( 2046320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1866320 2300000 ) ( 1866320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1686320 2300000 ) ( 1686320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 2300000 ) ( 1506320 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 786320 -38270 ) ( 786320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 606320 -38270 ) ( 606320 3557950 )
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+ NEW met4 3100 + SHAPE STRIPE ( 66320 -38270 ) ( 66320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2956900 -33470 ) ( 2956900 3553150 )
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+ NEW met4 3100 + SHAPE STRIPE ( 1686320 -38270 ) ( 1686320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1506320 -38270 ) ( 1506320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1326320 -38270 ) ( 1326320 1680000 ) ;
+ - vssa1 ( PIN vssa1 ) + USE GROUND
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+ NEW met4 0 + SHAPE STRIPE ( -32480 1583080 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( -32480 -27120 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3546800 ) ( 2953650 3546800 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3383080 ) ( 2953650 3383080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3203080 ) ( 2953650 3203080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 3023080 ) ( 2953650 3023080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2843080 ) ( 2953650 2843080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2663080 ) ( 2953650 2663080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2483080 ) ( 2953650 2483080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2303080 ) ( 2953650 2303080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 2123080 ) ( 2953650 2123080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1943080 ) ( 2953650 1943080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1763080 ) ( 2953650 1763080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1583080 ) ( 2953650 1583080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1403080 ) ( 2953650 1403080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1223080 ) ( 2953650 1223080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 1043080 ) ( 2953650 1043080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 863080 ) ( 2953650 863080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 683080 ) ( 2953650 683080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 503080 ) ( 2953650 503080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 323080 ) ( 2953650 323080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 143080 ) ( 2953650 143080 )
+ NEW met5 3100 + SHAPE STRIPE ( -34030 -27120 ) ( 2953650 -27120 )
+ NEW met4 3100 + SHAPE STRIPE ( 2952100 -28670 ) ( 2952100 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2837720 -28670 ) ( 2837720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2657720 -28670 ) ( 2657720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2477720 -28670 ) ( 2477720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2297720 -28670 ) ( 2297720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 2117720 -28670 ) ( 2117720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 2300000 ) ( 1937720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 2300000 ) ( 1757720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 2300000 ) ( 1577720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 2300000 ) ( 1397720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 2300000 ) ( 1217720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1037720 -28670 ) ( 1037720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 857720 -28670 ) ( 857720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 677720 -28670 ) ( 677720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 497720 -28670 ) ( 497720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 317720 -28670 ) ( 317720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 137720 -28670 ) ( 137720 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( -32480 -28670 ) ( -32480 3548350 )
+ NEW met4 3100 + SHAPE STRIPE ( 1937720 -28670 ) ( 1937720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1757720 -28670 ) ( 1757720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1577720 -28670 ) ( 1577720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1397720 -28670 ) ( 1397720 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1217720 -28670 ) ( 1217720 1680000 ) ;
+ - vssa2 ( PIN vssa2 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2961700 3556400 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 2316320 3041680 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1776320 3041680 ) via4_3100x3100
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+ NEW met4 0 + SHAPE STRIPE ( 1416320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1236320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1056320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 876320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 696320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 516320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 336320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 156320 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -42080 3041680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2961700 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2856320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2676320 2861680 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2496320 2861680 ) via4_3100x3100
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+ NEW met5 3100 + SHAPE STRIPE ( -43630 2501680 ) ( 2963250 2501680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2321680 ) ( 2963250 2321680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 2141680 ) ( 2963250 2141680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1961680 ) ( 2963250 1961680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1781680 ) ( 2963250 1781680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1601680 ) ( 2963250 1601680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1421680 ) ( 2963250 1421680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1241680 ) ( 2963250 1241680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 1061680 ) ( 2963250 1061680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 881680 ) ( 2963250 881680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 701680 ) ( 2963250 701680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 521680 ) ( 2963250 521680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 341680 ) ( 2963250 341680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 161680 ) ( 2963250 161680 )
+ NEW met5 3100 + SHAPE STRIPE ( -43630 -36720 ) ( 2963250 -36720 )
+ NEW met4 3100 + SHAPE STRIPE ( 2961700 -38270 ) ( 2961700 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2856320 -38270 ) ( 2856320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2676320 -38270 ) ( 2676320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2496320 -38270 ) ( 2496320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2316320 -38270 ) ( 2316320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 2136320 -38270 ) ( 2136320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1956320 2300000 ) ( 1956320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 2300000 ) ( 1776320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 2300000 ) ( 1596320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 2300000 ) ( 1416320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 2300000 ) ( 1236320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1056320 -38270 ) ( 1056320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 876320 -38270 ) ( 876320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 696320 -38270 ) ( 696320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 516320 -38270 ) ( 516320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 336320 -38270 ) ( 336320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 156320 -38270 ) ( 156320 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( -42080 -38270 ) ( -42080 3557950 )
+ NEW met4 3100 + SHAPE STRIPE ( 1956320 -38270 ) ( 1956320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1776320 -38270 ) ( 1776320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1596320 -38270 ) ( 1596320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1416320 -38270 ) ( 1416320 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1236320 -38270 ) ( 1236320 1680000 ) ;
+ - vssd1 ( PIN vssd1 ) + USE GROUND
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+ NEW met4 0 + SHAPE STRIPE ( -13280 1185880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 1005880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 825880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 645880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 465880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 285880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 105880 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2932900 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2800520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2620520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2440520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2260520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2080520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1900520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1720520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1540520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1360520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1180520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1000520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 820520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 640520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 460520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 280520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 100520 -7920 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -13280 -7920 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3527600 ) ( 2934450 3527600 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3345880 ) ( 2934450 3345880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 3165880 ) ( 2934450 3165880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2985880 ) ( 2934450 2985880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2805880 ) ( 2934450 2805880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2625880 ) ( 2934450 2625880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2445880 ) ( 2934450 2445880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2265880 ) ( 2934450 2265880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 2085880 ) ( 2934450 2085880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1905880 ) ( 2934450 1905880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1725880 ) ( 2934450 1725880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1545880 ) ( 2934450 1545880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1365880 ) ( 2934450 1365880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1185880 ) ( 2934450 1185880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 1005880 ) ( 2934450 1005880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 825880 ) ( 2934450 825880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 645880 ) ( 2934450 645880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 465880 ) ( 2934450 465880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 285880 ) ( 2934450 285880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 105880 ) ( 2934450 105880 )
+ NEW met5 3100 + SHAPE STRIPE ( -14830 -7920 ) ( 2934450 -7920 )
+ NEW met4 3100 + SHAPE STRIPE ( 2932900 -9470 ) ( 2932900 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2800520 -9470 ) ( 2800520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2620520 -9470 ) ( 2620520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2440520 -9470 ) ( 2440520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2260520 -9470 ) ( 2260520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 2300000 ) ( 2080520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 2300000 ) ( 1900520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 2300000 ) ( 1720520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 2300000 ) ( 1540520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 2300000 ) ( 1360520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 2300000 ) ( 1180520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 1000520 -9470 ) ( 1000520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 820520 -9470 ) ( 820520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 640520 -9470 ) ( 640520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 460520 -9470 ) ( 460520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 280520 -9470 ) ( 280520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 100520 -9470 ) ( 100520 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( -13280 -9470 ) ( -13280 3529150 )
+ NEW met4 3100 + SHAPE STRIPE ( 2080520 -9470 ) ( 2080520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1900520 -9470 ) ( 1900520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1720520 -9470 ) ( 1720520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1540520 -9470 ) ( 1540520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1360520 -9470 ) ( 1360520 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1180520 -9470 ) ( 1180520 1680000 ) ;
+ - vssd2 ( PIN vssd2 ) + USE GROUND
+ + ROUTED met4 0 + SHAPE STRIPE ( 2942500 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3537200 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3364480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3184480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 3004480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2824480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2644480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2464480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2284480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 2104480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1924480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1744480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1564480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1384480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1204480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 1024480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 844480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 664480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 484480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 304480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 124480 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2942500 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2819120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2639120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2459120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2279120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 2099120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1919120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1739120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1559120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1379120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1199120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 1019120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 839120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 659120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 479120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 299120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( 119120 -17520 ) via4_3100x3100
+ NEW met4 0 + SHAPE STRIPE ( -22880 -17520 ) via4_3100x3100
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3537200 ) ( 2944050 3537200 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3364480 ) ( 2944050 3364480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3184480 ) ( 2944050 3184480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 3004480 ) ( 2944050 3004480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2824480 ) ( 2944050 2824480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2644480 ) ( 2944050 2644480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2464480 ) ( 2944050 2464480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2284480 ) ( 2944050 2284480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 2104480 ) ( 2944050 2104480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1924480 ) ( 2944050 1924480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1744480 ) ( 2944050 1744480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1564480 ) ( 2944050 1564480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1384480 ) ( 2944050 1384480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1204480 ) ( 2944050 1204480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 1024480 ) ( 2944050 1024480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 844480 ) ( 2944050 844480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 664480 ) ( 2944050 664480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 484480 ) ( 2944050 484480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 304480 ) ( 2944050 304480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 124480 ) ( 2944050 124480 )
+ NEW met5 3100 + SHAPE STRIPE ( -24430 -17520 ) ( 2944050 -17520 )
+ NEW met4 3100 + SHAPE STRIPE ( 2942500 -19070 ) ( 2942500 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2819120 -19070 ) ( 2819120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2639120 -19070 ) ( 2639120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2459120 -19070 ) ( 2459120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2279120 -19070 ) ( 2279120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 2099120 -19070 ) ( 2099120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 2300000 ) ( 1919120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 2300000 ) ( 1739120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 2300000 ) ( 1559120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 2300000 ) ( 1379120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 2300000 ) ( 1199120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1019120 -19070 ) ( 1019120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 839120 -19070 ) ( 839120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 659120 -19070 ) ( 659120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 479120 -19070 ) ( 479120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 299120 -19070 ) ( 299120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 119120 -19070 ) ( 119120 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( -22880 -19070 ) ( -22880 3538750 )
+ NEW met4 3100 + SHAPE STRIPE ( 1919120 -19070 ) ( 1919120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1739120 -19070 ) ( 1739120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1559120 -19070 ) ( 1559120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1379120 -19070 ) ( 1379120 1680000 )
+ NEW met4 3100 + SHAPE STRIPE ( 1199120 -19070 ) ( 1199120 1680000 ) ;
+END SPECIALNETS
+NETS 637 ;
+ - analog_io[0] ( PIN analog_io[0] ) + USE SIGNAL ;
+ - analog_io[10] ( PIN analog_io[10] ) + USE SIGNAL ;
+ - analog_io[11] ( PIN analog_io[11] ) + USE SIGNAL ;
+ - analog_io[12] ( PIN analog_io[12] ) + USE SIGNAL ;
+ - analog_io[13] ( PIN analog_io[13] ) + USE SIGNAL ;
+ - analog_io[14] ( PIN analog_io[14] ) + USE SIGNAL ;
+ - analog_io[15] ( PIN analog_io[15] ) + USE SIGNAL ;
+ - analog_io[16] ( PIN analog_io[16] ) + USE SIGNAL ;
+ - analog_io[17] ( PIN analog_io[17] ) + USE SIGNAL ;
+ - analog_io[18] ( PIN analog_io[18] ) + USE SIGNAL ;
+ - analog_io[19] ( PIN analog_io[19] ) + USE SIGNAL ;
+ - analog_io[1] ( PIN analog_io[1] ) + USE SIGNAL ;
+ - analog_io[20] ( PIN analog_io[20] ) + USE SIGNAL ;
+ - analog_io[21] ( PIN analog_io[21] ) + USE SIGNAL ;
+ - analog_io[22] ( PIN analog_io[22] ) + USE SIGNAL ;
+ - analog_io[23] ( PIN analog_io[23] ) + USE SIGNAL ;
+ - analog_io[24] ( PIN analog_io[24] ) + USE SIGNAL ;
+ - analog_io[25] ( PIN analog_io[25] ) + USE SIGNAL ;
+ - analog_io[26] ( PIN analog_io[26] ) + USE SIGNAL ;
+ - analog_io[27] ( PIN analog_io[27] ) + USE SIGNAL ;
+ - analog_io[28] ( PIN analog_io[28] ) + USE SIGNAL ;
+ - analog_io[2] ( PIN analog_io[2] ) + USE SIGNAL ;
+ - analog_io[3] ( PIN analog_io[3] ) + USE SIGNAL ;
+ - analog_io[4] ( PIN analog_io[4] ) + USE SIGNAL ;
+ - analog_io[5] ( PIN analog_io[5] ) + USE SIGNAL ;
+ - analog_io[6] ( PIN analog_io[6] ) + USE SIGNAL ;
+ - analog_io[7] ( PIN analog_io[7] ) + USE SIGNAL ;
+ - analog_io[8] ( PIN analog_io[8] ) + USE SIGNAL ;
+ - analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ;
+ - io_in[0] ( PIN io_in[0] ) ( mprj io_in[0] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 32980 ) ( * 34170 )
+ NEW met3 ( 2900990 32980 ) ( 2917780 * 0 )
+ NEW met2 ( 1178980 2289900 0 ) ( 1179670 * )
+ NEW met2 ( 1179670 2289900 ) ( * 2300100 )
+ NEW met1 ( 2080350 34170 ) ( 2900990 * )
+ NEW met2 ( 2080350 34170 ) ( * 2300100 )
+ NEW met3 ( 1179670 2300100 ) ( 2080350 * )
+ NEW met1 ( 2900990 34170 ) M1M2_PR
+ NEW met2 ( 2900990 32980 ) M2M3_PR
+ NEW met2 ( 1179670 2300100 ) M2M3_PR
+ NEW met1 ( 2080350 34170 ) M1M2_PR
+ NEW met2 ( 2080350 2300100 ) M2M3_PR ;
+ - io_in[10] ( PIN io_in[10] ) ( mprj io_in[10] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 2290580 ) ( * 2293810 )
+ NEW met3 ( 2900990 2290580 ) ( 2917780 * 0 )
+ NEW met2 ( 1415880 2289900 0 ) ( 1417490 * )
+ NEW met2 ( 1417490 2289900 ) ( * 2293810 )
+ NEW met1 ( 1417490 2293810 ) ( 2900990 * )
+ NEW met1 ( 2900990 2293810 ) M1M2_PR
+ NEW met2 ( 2900990 2290580 ) M2M3_PR
+ NEW met1 ( 1417490 2293810 ) M1M2_PR ;
+ - io_in[11] ( PIN io_in[11] ) ( mprj io_in[11] ) + USE SIGNAL
+ + ROUTED met2 ( 1437270 2289900 ) ( 1439340 * 0 )
+ NEW met2 ( 1435430 2401200 ) ( 1437270 * )
+ NEW met2 ( 1437270 2289900 ) ( * 2401200 )
+ NEW met2 ( 1435430 2401200 ) ( * 2553230 )
+ NEW met2 ( 2900990 2553230 ) ( * 2556460 )
+ NEW met3 ( 2900990 2556460 ) ( 2917780 * 0 )
+ NEW met1 ( 1435430 2553230 ) ( 2900990 * )
+ NEW met1 ( 1435430 2553230 ) M1M2_PR
+ NEW met1 ( 2900990 2553230 ) M1M2_PR
+ NEW met2 ( 2900990 2556460 ) M2M3_PR ;
+ - io_in[12] ( PIN io_in[12] ) ( mprj io_in[12] ) + USE SIGNAL
+ + ROUTED met2 ( 2899150 2815370 ) ( * 2821660 )
+ NEW met3 ( 2899150 2821660 ) ( 2917780 * 0 )
+ NEW met2 ( 1463030 2289900 ) ( 1463260 * 0 )
+ NEW met2 ( 1463030 2289900 ) ( * 2815370 )
+ NEW met1 ( 1463030 2815370 ) ( 2899150 * )
+ NEW met1 ( 1463030 2815370 ) M1M2_PR
+ NEW met1 ( 2899150 2815370 ) M1M2_PR
+ NEW met2 ( 2899150 2821660 ) M2M3_PR ;
+ - io_in[13] ( PIN io_in[13] ) ( mprj io_in[13] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3084310 ) ( * 3087540 )
+ NEW met3 ( 2900990 3087540 ) ( 2917780 * 0 )
+ NEW met1 ( 1483730 3084310 ) ( 2900990 * )
+ NEW met2 ( 1484650 2289900 ) ( 1486720 * 0 )
+ NEW met2 ( 1483730 2401200 ) ( 1484650 * )
+ NEW met2 ( 1484650 2289900 ) ( * 2401200 )
+ NEW met2 ( 1483730 2401200 ) ( * 3084310 )
+ NEW met1 ( 2900990 3084310 ) M1M2_PR
+ NEW met2 ( 2900990 3087540 ) M2M3_PR
+ NEW met1 ( 1483730 3084310 ) M1M2_PR ;
+ - io_in[14] ( PIN io_in[14] ) ( mprj io_in[14] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3353420 ) ( * 3353930 )
+ NEW met3 ( 2900990 3353420 ) ( 2917780 * 0 )
+ NEW met2 ( 1508570 2289900 ) ( 1510640 * 0 )
+ NEW met2 ( 1504430 2401200 ) ( 1508570 * )
+ NEW met2 ( 1508570 2289900 ) ( * 2401200 )
+ NEW met2 ( 1504430 2401200 ) ( * 3353930 )
+ NEW met1 ( 1504430 3353930 ) ( 2900990 * )
+ NEW met1 ( 2900990 3353930 ) M1M2_PR
+ NEW met2 ( 2900990 3353420 ) M2M3_PR
+ NEW met1 ( 1504430 3353930 ) M1M2_PR ;
+ - io_in[15] ( PIN io_in[15] ) ( mprj io_in[15] ) + USE SIGNAL
+ + ROUTED met2 ( 1534100 2289900 0 ) ( 1535710 * )
+ NEW met2 ( 1535710 2289900 ) ( * 2308430 )
+ NEW met2 ( 2794730 2308430 ) ( * 3512100 )
+ NEW met2 ( 2794730 3512100 ) ( 2798410 * )
+ NEW met2 ( 2798410 3512100 ) ( * 3517980 0 )
+ NEW met1 ( 1535710 2308430 ) ( 2794730 * )
+ NEW met1 ( 1535710 2308430 ) M1M2_PR
+ NEW met1 ( 2794730 2308430 ) M1M2_PR ;
+ - io_in[16] ( PIN io_in[16] ) ( mprj io_in[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1558020 2289900 0 ) ( 1559170 * )
+ NEW met2 ( 1559170 2289900 ) ( * 2309450 )
+ NEW met2 ( 2470430 3517980 ) ( 2473190 * )
+ NEW met2 ( 2473190 3517300 ) ( * 3517980 )
+ NEW met2 ( 2473190 3517300 ) ( 2474110 * )
+ NEW met2 ( 2474110 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 2470430 2309450 ) ( * 3517980 )
+ NEW met1 ( 1559170 2309450 ) ( 2470430 * )
+ NEW met1 ( 1559170 2309450 ) M1M2_PR
+ NEW met1 ( 2470430 2309450 ) M1M2_PR ;
+ - io_in[17] ( PIN io_in[17] ) ( mprj io_in[17] ) + USE SIGNAL
+ + ROUTED met2 ( 2146130 3517980 ) ( 2148430 * )
+ NEW met2 ( 2148430 3517300 ) ( * 3517980 )
+ NEW met2 ( 2148430 3517300 ) ( 2149350 * )
+ NEW met2 ( 2149350 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 2146130 2310130 ) ( * 3517980 )
+ NEW met2 ( 1581480 2289900 0 ) ( 1583090 * )
+ NEW met2 ( 1583090 2289900 ) ( * 2310130 )
+ NEW met1 ( 1583090 2310130 ) ( 2146130 * )
+ NEW met1 ( 2146130 2310130 ) M1M2_PR
+ NEW met1 ( 1583090 2310130 ) M1M2_PR ;
+ - io_in[18] ( PIN io_in[18] ) ( mprj io_in[18] ) + USE SIGNAL
+ + ROUTED met2 ( 1821830 3512100 ) ( 1825050 * )
+ NEW met2 ( 1825050 3512100 ) ( * 3517980 0 )
+ NEW met2 ( 1605400 2289900 0 ) ( 1607010 * )
+ NEW met2 ( 1607010 2289900 ) ( * 2311150 )
+ NEW met1 ( 1607010 2311150 ) ( 1821830 * )
+ NEW met2 ( 1821830 2311150 ) ( * 3512100 )
+ NEW met1 ( 1607010 2311150 ) M1M2_PR
+ NEW met1 ( 1821830 2311150 ) M1M2_PR ;
+ - io_in[19] ( PIN io_in[19] ) ( mprj io_in[19] ) + USE SIGNAL
+ + ROUTED met2 ( 1628630 2289900 ) ( 1628860 * 0 )
+ NEW met2 ( 1628630 2289900 ) ( * 2311490 )
+ NEW met1 ( 1497530 2311490 ) ( 1628630 * )
+ NEW met2 ( 1497530 3517980 ) ( 1499830 * )
+ NEW met2 ( 1499830 3517300 ) ( * 3517980 )
+ NEW met2 ( 1499830 3517300 ) ( 1500750 * )
+ NEW met2 ( 1500750 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 1497530 2311490 ) ( * 3517980 )
+ NEW met1 ( 1628630 2311490 ) M1M2_PR
+ NEW met1 ( 1497530 2311490 ) M1M2_PR ;
+ - io_in[1] ( PIN io_in[1] ) ( mprj io_in[1] ) + USE SIGNAL
+ + ROUTED met3 ( 2902140 231540 ) ( 2917780 * 0 )
+ NEW met4 ( 2902140 231540 ) ( * 2299420 )
+ NEW met2 ( 1202440 2289900 0 ) ( 1204050 * )
+ NEW met2 ( 1204050 2289900 ) ( * 2299420 )
+ NEW met3 ( 1204050 2299420 ) ( 2902140 * )
+ NEW met3 ( 2902140 231540 ) M3M4_PR
+ NEW met3 ( 2902140 2299420 ) M3M4_PR
+ NEW met2 ( 1204050 2299420 ) M2M3_PR ;
+ - io_in[20] ( PIN io_in[20] ) ( mprj io_in[20] ) + USE SIGNAL
+ + ROUTED met2 ( 1173230 3517980 ) ( 1175070 * )
+ NEW met2 ( 1175070 3517300 ) ( * 3517980 )
+ NEW met2 ( 1175070 3517300 ) ( 1175990 * )
+ NEW met2 ( 1175990 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 1173230 2310470 ) ( * 3517980 )
+ NEW met2 ( 1651170 2289900 ) ( 1652780 * 0 )
+ NEW met2 ( 1651170 2289900 ) ( * 2310470 )
+ NEW met1 ( 1173230 2310470 ) ( 1651170 * )
+ NEW met1 ( 1173230 2310470 ) M1M2_PR
+ NEW met1 ( 1651170 2310470 ) M1M2_PR ;
+ - io_in[21] ( PIN io_in[21] ) ( mprj io_in[21] ) + USE SIGNAL
+ + ROUTED met2 ( 1674630 2289900 ) ( 1676240 * 0 )
+ NEW met2 ( 1674630 2289900 ) ( * 2309790 )
+ NEW met1 ( 848930 2309790 ) ( 1674630 * )
+ NEW met2 ( 848930 2309790 ) ( * 3512100 )
+ NEW met2 ( 848930 3512100 ) ( 851690 * )
+ NEW met2 ( 851690 3512100 ) ( * 3517980 0 )
+ NEW met1 ( 1674630 2309790 ) M1M2_PR
+ NEW met1 ( 848930 2309790 ) M1M2_PR ;
+ - io_in[22] ( PIN io_in[22] ) ( mprj io_in[22] ) + USE SIGNAL
+ + ROUTED met1 ( 524630 2308770 ) ( 1698550 * )
+ NEW met2 ( 524630 3517980 ) ( 526470 * )
+ NEW met2 ( 526470 3517300 ) ( * 3517980 )
+ NEW met2 ( 526470 3517300 ) ( 527390 * )
+ NEW met2 ( 527390 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 524630 2308770 ) ( * 3517980 )
+ NEW met2 ( 1698550 2289900 ) ( 1700160 * 0 )
+ NEW met2 ( 1698550 2289900 ) ( * 2308770 )
+ NEW met1 ( 524630 2308770 ) M1M2_PR
+ NEW met1 ( 1698550 2308770 ) M1M2_PR ;
+ - io_in[23] ( PIN io_in[23] ) ( mprj io_in[23] ) + USE SIGNAL
+ + ROUTED met2 ( 200330 3517980 ) ( 201710 * )
+ NEW met2 ( 201710 3517300 ) ( * 3517980 )
+ NEW met2 ( 201710 3517300 ) ( 202630 * )
+ NEW met2 ( 202630 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 200330 2308090 ) ( * 3517980 )
+ NEW met1 ( 200330 2308090 ) ( 1722010 * )
+ NEW met2 ( 1722010 2289900 ) ( 1723620 * 0 )
+ NEW met2 ( 1722010 2289900 ) ( * 2308090 )
+ NEW met1 ( 200330 2308090 ) M1M2_PR
+ NEW met1 ( 1722010 2308090 ) M1M2_PR ;
+ - io_in[24] ( PIN io_in[24] ) ( mprj io_in[24] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3421420 0 ) ( 17250 * )
+ NEW met2 ( 17250 3415810 ) ( * 3421420 )
+ NEW met1 ( 17250 3415810 ) ( 1745930 * )
+ NEW met2 ( 1745930 2289900 ) ( 1747540 * 0 )
+ NEW met2 ( 1745930 2289900 ) ( * 3415810 )
+ NEW met2 ( 17250 3421420 ) M2M3_PR
+ NEW met1 ( 17250 3415810 ) M1M2_PR
+ NEW met1 ( 1745930 3415810 ) M1M2_PR ;
+ - io_in[25] ( PIN io_in[25] ) ( mprj io_in[25] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3160300 0 ) ( 17250 * )
+ NEW met2 ( 17250 3160300 ) ( * 3160470 )
+ NEW met2 ( 1766630 2401200 ) ( 1768930 * )
+ NEW met2 ( 1766630 2401200 ) ( * 3160470 )
+ NEW met1 ( 17250 3160470 ) ( 1766630 * )
+ NEW met2 ( 1768930 2289900 ) ( 1771000 * 0 )
+ NEW met2 ( 1768930 2289900 ) ( * 2401200 )
+ NEW met2 ( 17250 3160300 ) M2M3_PR
+ NEW met1 ( 17250 3160470 ) M1M2_PR
+ NEW met1 ( 1766630 3160470 ) M1M2_PR ;
+ - io_in[26] ( PIN io_in[26] ) ( mprj io_in[26] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2899860 0 ) ( 16790 * )
+ NEW met2 ( 16790 2898330 ) ( * 2899860 )
+ NEW met1 ( 16790 2898330 ) ( 1794230 * )
+ NEW met2 ( 1794230 2289900 ) ( 1794920 * 0 )
+ NEW met2 ( 1794230 2289900 ) ( * 2898330 )
+ NEW met2 ( 16790 2899860 ) M2M3_PR
+ NEW met1 ( 16790 2898330 ) M1M2_PR
+ NEW met1 ( 1794230 2898330 ) M1M2_PR ;
+ - io_in[27] ( PIN io_in[27] ) ( mprj io_in[27] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2639420 0 ) ( 17250 * )
+ NEW met2 ( 17250 2635850 ) ( * 2639420 )
+ NEW met1 ( 17250 2635850 ) ( 1814930 * )
+ NEW met2 ( 1814930 2401200 ) ( 1816310 * )
+ NEW met2 ( 1814930 2401200 ) ( * 2635850 )
+ NEW met2 ( 1816310 2289900 ) ( 1818380 * 0 )
+ NEW met2 ( 1816310 2289900 ) ( * 2401200 )
+ NEW met2 ( 17250 2639420 ) M2M3_PR
+ NEW met1 ( 17250 2635850 ) M1M2_PR
+ NEW met1 ( 1814930 2635850 ) M1M2_PR ;
+ - io_in[28] ( PIN io_in[28] ) ( mprj io_in[28] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2378300 0 ) ( 17250 * )
+ NEW met2 ( 17250 2373710 ) ( * 2378300 )
+ NEW met1 ( 17250 2373710 ) ( 1840230 * )
+ NEW met2 ( 1840230 2289900 ) ( 1842300 * 0 )
+ NEW met2 ( 1840230 2289900 ) ( * 2373710 )
+ NEW met2 ( 17250 2378300 ) M2M3_PR
+ NEW met1 ( 17250 2373710 ) M1M2_PR
+ NEW met1 ( 1840230 2373710 ) M1M2_PR ;
+ - io_in[29] ( PIN io_in[29] ) ( mprj io_in[29] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2117860 0 ) ( 20010 * )
+ NEW met2 ( 20010 2117860 ) ( * 2291430 )
+ NEW met2 ( 1864150 2289900 ) ( 1865760 * 0 )
+ NEW met2 ( 1864150 2289900 ) ( * 2291430 )
+ NEW met1 ( 20010 2291430 ) ( 1864150 * )
+ NEW met2 ( 20010 2117860 ) M2M3_PR
+ NEW met1 ( 20010 2291430 ) M1M2_PR
+ NEW met1 ( 1864150 2291430 ) M1M2_PR ;
+ - io_in[2] ( PIN io_in[2] ) ( mprj io_in[2] ) + USE SIGNAL
+ + ROUTED met3 ( 2901910 430780 ) ( 2917780 * 0 )
+ NEW met2 ( 2901910 430780 ) ( * 2298910 )
+ NEW met2 ( 1226360 2289900 0 ) ( 1227970 * )
+ NEW met2 ( 1227970 2289900 ) ( * 2298910 )
+ NEW met1 ( 1227970 2298910 ) ( 2901910 * )
+ NEW met2 ( 2901910 430780 ) M2M3_PR
+ NEW met1 ( 2901910 2298910 ) M1M2_PR
+ NEW met1 ( 1227970 2298910 ) M1M2_PR ;
+ - io_in[30] ( PIN io_in[30] ) ( mprj io_in[30] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1856740 0 ) ( 18630 * )
+ NEW met2 ( 18630 1856740 ) ( * 2291090 )
+ NEW met2 ( 1889680 2289900 0 ) ( * 2291090 )
+ NEW met1 ( 18630 2291090 ) ( 1889680 * )
+ NEW met2 ( 18630 1856740 ) M2M3_PR
+ NEW met1 ( 18630 2291090 ) M1M2_PR
+ NEW met1 ( 1889680 2291090 ) M1M2_PR ;
+ - io_in[31] ( PIN io_in[31] ) ( mprj io_in[31] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1596300 0 ) ( 17710 * )
+ NEW met2 ( 17710 1596300 ) ( * 1600550 )
+ NEW met2 ( 1168630 1600550 ) ( * 2301290 )
+ NEW met1 ( 17710 1600550 ) ( 1168630 * )
+ NEW met2 ( 1911530 2289900 ) ( 1913140 * 0 )
+ NEW met2 ( 1911530 2289900 ) ( * 2301290 )
+ NEW met1 ( 1168630 2301290 ) ( 1911530 * )
+ NEW met2 ( 17710 1596300 ) M2M3_PR
+ NEW met1 ( 17710 1600550 ) M1M2_PR
+ NEW met1 ( 1168630 1600550 ) M1M2_PR
+ NEW met1 ( 1168630 2301290 ) M1M2_PR
+ NEW met1 ( 1911530 2301290 ) M1M2_PR ;
+ - io_in[32] ( PIN io_in[32] ) ( mprj io_in[32] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1335860 0 ) ( 17710 * )
+ NEW met2 ( 17710 1335860 ) ( * 1338410 )
+ NEW met2 ( 1172770 1338410 ) ( * 2300610 )
+ NEW met2 ( 1935450 2289900 ) ( 1937060 * 0 )
+ NEW met2 ( 1935450 2289900 ) ( * 2300610 )
+ NEW met1 ( 17710 1338410 ) ( 1172770 * )
+ NEW met1 ( 1172770 2300610 ) ( 1935450 * )
+ NEW met2 ( 17710 1335860 ) M2M3_PR
+ NEW met1 ( 17710 1338410 ) M1M2_PR
+ NEW met1 ( 1172770 1338410 ) M1M2_PR
+ NEW met1 ( 1172770 2300610 ) M1M2_PR
+ NEW met1 ( 1935450 2300610 ) M1M2_PR ;
+ - io_in[33] ( PIN io_in[33] ) ( mprj io_in[33] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1074740 0 ) ( 16790 * )
+ NEW met2 ( 16790 1074740 ) ( * 1076270 )
+ NEW met2 ( 1171850 1076270 ) ( * 2300270 )
+ NEW met2 ( 1959830 2289900 ) ( 1960520 * 0 )
+ NEW met2 ( 1959830 2289900 ) ( * 2300270 )
+ NEW met1 ( 16790 1076270 ) ( 1171850 * )
+ NEW met1 ( 1171850 2300270 ) ( 1959830 * )
+ NEW met2 ( 16790 1074740 ) M2M3_PR
+ NEW met1 ( 16790 1076270 ) M1M2_PR
+ NEW met1 ( 1171850 1076270 ) M1M2_PR
+ NEW met1 ( 1171850 2300270 ) M1M2_PR
+ NEW met1 ( 1959830 2300270 ) M1M2_PR ;
+ - io_in[34] ( PIN io_in[34] ) ( mprj io_in[34] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 814300 0 ) ( 16330 * )
+ NEW met2 ( 16330 814300 ) ( * 820930 )
+ NEW met2 ( 1170930 820930 ) ( * 2299590 )
+ NEW met1 ( 16330 820930 ) ( 1170930 * )
+ NEW met2 ( 1982830 2289900 ) ( 1984440 * 0 )
+ NEW met2 ( 1982830 2289900 ) ( * 2299590 )
+ NEW met1 ( 1170930 2299590 ) ( 1982830 * )
+ NEW met2 ( 16330 814300 ) M2M3_PR
+ NEW met1 ( 16330 820930 ) M1M2_PR
+ NEW met1 ( 1170930 820930 ) M1M2_PR
+ NEW met1 ( 1170930 2299590 ) M1M2_PR
+ NEW met1 ( 1982830 2299590 ) M1M2_PR ;
+ - io_in[35] ( PIN io_in[35] ) ( mprj io_in[35] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 553180 0 ) ( 15870 * )
+ NEW met2 ( 15870 553180 ) ( * 558790 )
+ NEW met2 ( 1170010 558790 ) ( * 2299250 )
+ NEW met1 ( 15870 558790 ) ( 1170010 * )
+ NEW met2 ( 2006290 2289900 ) ( 2007900 * 0 )
+ NEW met2 ( 2006290 2289900 ) ( * 2299250 )
+ NEW met1 ( 1170010 2299250 ) ( 2006290 * )
+ NEW met2 ( 15870 553180 ) M2M3_PR
+ NEW met1 ( 15870 558790 ) M1M2_PR
+ NEW met1 ( 1170010 558790 ) M1M2_PR
+ NEW met1 ( 1170010 2299250 ) M1M2_PR
+ NEW met1 ( 2006290 2299250 ) M1M2_PR ;
+ - io_in[36] ( PIN io_in[36] ) ( mprj io_in[36] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 358020 0 ) ( 3220 * )
+ NEW met3 ( 3220 357340 ) ( * 358020 )
+ NEW met3 ( 1380 357340 ) ( 3220 * )
+ NEW met3 ( 1380 354620 ) ( * 357340 )
+ NEW met4 ( 1169780 351900 ) ( * 2300780 )
+ NEW met2 ( 2030210 2289900 ) ( 2031820 * 0 )
+ NEW met2 ( 2030210 2289900 ) ( * 2300780 )
+ NEW met3 ( 1380 354620 ) ( 34500 * )
+ NEW met3 ( 34500 351900 ) ( * 354620 )
+ NEW met3 ( 34500 351900 ) ( 1169780 * )
+ NEW met3 ( 1169780 2300780 ) ( 2030210 * )
+ NEW met3 ( 1169780 351900 ) M3M4_PR
+ NEW met3 ( 1169780 2300780 ) M3M4_PR
+ NEW met2 ( 2030210 2300780 ) M2M3_PR ;
+ - io_in[37] ( PIN io_in[37] ) ( mprj io_in[37] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 162180 0 ) ( 3220 * )
+ NEW met3 ( 3220 161500 ) ( * 162180 )
+ NEW met3 ( 1380 161500 ) ( 3220 * )
+ NEW met3 ( 1380 158780 ) ( * 161500 )
+ NEW met3 ( 2049300 2287180 ) ( 2053670 * )
+ NEW met2 ( 2053670 2287180 ) ( 2055280 * 0 )
+ NEW met4 ( 2049300 158780 ) ( * 2287180 )
+ NEW met3 ( 1380 158780 ) ( 2049300 * )
+ NEW met3 ( 2049300 158780 ) M3M4_PR
+ NEW met3 ( 2049300 2287180 ) M3M4_PR
+ NEW met2 ( 2053670 2287180 ) M2M3_PR ;
+ - io_in[3] ( PIN io_in[3] ) ( mprj io_in[3] ) + USE SIGNAL
+ + ROUTED met3 ( 1270060 2285820 ) ( * 2287180 )
+ NEW met3 ( 1251430 2287180 ) ( 1270060 * )
+ NEW met2 ( 1249820 2287180 0 ) ( 1251430 * )
+ NEW met3 ( 2902370 630020 ) ( 2917780 * 0 )
+ NEW met2 ( 2902370 630020 ) ( * 2285820 )
+ NEW met3 ( 1270060 2285820 ) ( 2902370 * )
+ NEW met2 ( 1251430 2287180 ) M2M3_PR
+ NEW met2 ( 2902370 630020 ) M2M3_PR
+ NEW met2 ( 2902370 2285820 ) M2M3_PR ;
+ - io_in[4] ( PIN io_in[4] ) ( mprj io_in[4] ) + USE SIGNAL
+ + ROUTED met2 ( 1273740 2287180 0 ) ( 1275350 * )
+ NEW met3 ( 2903290 829260 ) ( 2917780 * 0 )
+ NEW met2 ( 2903290 829260 ) ( * 2286500 )
+ NEW met3 ( 1275350 2287180 ) ( 1290300 * )
+ NEW met3 ( 1290300 2286500 ) ( * 2287180 )
+ NEW met3 ( 1290300 2286500 ) ( 2903290 * )
+ NEW met2 ( 1275350 2287180 ) M2M3_PR
+ NEW met2 ( 2903290 829260 ) M2M3_PR
+ NEW met2 ( 2903290 2286500 ) M2M3_PR ;
+ - io_in[5] ( PIN io_in[5] ) ( mprj io_in[5] ) + USE SIGNAL
+ + ROUTED met3 ( 2904210 1028500 ) ( 2917780 * 0 )
+ NEW met2 ( 2904210 1028500 ) ( * 2287180 )
+ NEW met2 ( 1297200 2287180 0 ) ( 1297890 * )
+ NEW met3 ( 1966500 2287180 ) ( * 2287860 )
+ NEW met3 ( 1966500 2287860 ) ( 2063100 * )
+ NEW met3 ( 2063100 2287180 ) ( * 2287860 )
+ NEW met3 ( 2063100 2287180 ) ( 2904210 * )
+ NEW met3 ( 1297890 2287180 ) ( 1966500 * )
+ NEW met2 ( 2904210 1028500 ) M2M3_PR
+ NEW met2 ( 2904210 2287180 ) M2M3_PR
+ NEW met2 ( 1297890 2287180 ) M2M3_PR ;
+ - io_in[6] ( PIN io_in[6] ) ( mprj io_in[6] ) + USE SIGNAL
+ + ROUTED met3 ( 2902830 1227740 ) ( 2917780 * 0 )
+ NEW met2 ( 2902830 1227740 ) ( * 2284630 )
+ NEW met1 ( 1338600 2284630 ) ( * 2287350 )
+ NEW met1 ( 1322730 2287350 ) ( 1338600 * )
+ NEW met2 ( 1322730 2287180 ) ( * 2287350 )
+ NEW met2 ( 1321120 2287180 0 ) ( 1322730 * )
+ NEW met1 ( 1897500 2284630 ) ( 2902830 * )
+ NEW met1 ( 1897500 2283950 ) ( * 2284630 )
+ NEW met1 ( 1890600 2283950 ) ( 1897500 * )
+ NEW met1 ( 1890600 2282930 ) ( * 2283950 )
+ NEW met1 ( 1883700 2282930 ) ( 1890600 * )
+ NEW met1 ( 1883700 2282930 ) ( * 2283270 )
+ NEW met1 ( 1835400 2283270 ) ( 1883700 * )
+ NEW met1 ( 1835400 2282250 ) ( * 2283270 )
+ NEW met1 ( 1828500 2282250 ) ( 1835400 * )
+ NEW met1 ( 1828500 2281910 ) ( * 2282250 )
+ NEW met1 ( 1821600 2281910 ) ( 1828500 * )
+ NEW met1 ( 1821600 2281910 ) ( * 2282250 )
+ NEW met1 ( 1807800 2282250 ) ( 1821600 * )
+ NEW met1 ( 1807800 2281910 ) ( * 2282250 )
+ NEW met1 ( 1800900 2281910 ) ( 1807800 * )
+ NEW met1 ( 1800900 2280890 ) ( * 2281910 )
+ NEW met1 ( 1794000 2280890 ) ( 1800900 * )
+ NEW met1 ( 1794000 2280890 ) ( * 2283270 )
+ NEW met1 ( 1787100 2283270 ) ( 1794000 * )
+ NEW met1 ( 1787100 2282590 ) ( * 2283270 )
+ NEW met1 ( 1780200 2282590 ) ( 1787100 * )
+ NEW met1 ( 1780200 2281910 ) ( * 2282590 )
+ NEW met1 ( 1773300 2281910 ) ( 1780200 * )
+ NEW met1 ( 1773300 2281910 ) ( * 2282250 )
+ NEW met1 ( 1766400 2282250 ) ( 1773300 * )
+ NEW met1 ( 1764330 2281230 ) ( * 2281910 )
+ NEW met1 ( 1764330 2281230 ) ( 1766400 * )
+ NEW met1 ( 1766400 2281230 ) ( * 2282250 )
+ NEW met1 ( 1731900 2281910 ) ( 1764330 * )
+ NEW met1 ( 1731900 2280210 ) ( * 2281910 )
+ NEW met1 ( 1725000 2280210 ) ( 1731900 * )
+ NEW met1 ( 1725000 2280210 ) ( * 2280890 )
+ NEW met1 ( 1718100 2280890 ) ( 1725000 * )
+ NEW met1 ( 1718100 2280550 ) ( * 2280890 )
+ NEW met1 ( 1704300 2280550 ) ( 1718100 * )
+ NEW met1 ( 1704300 2280550 ) ( * 2281570 )
+ NEW met1 ( 1690500 2281570 ) ( 1704300 * )
+ NEW met1 ( 1690500 2279530 ) ( * 2281570 )
+ NEW met1 ( 1683600 2279530 ) ( 1690500 * )
+ NEW met1 ( 1683600 2279190 ) ( * 2279530 )
+ NEW met1 ( 1676700 2279190 ) ( 1683600 * )
+ NEW met1 ( 1676700 2279190 ) ( * 2280550 )
+ NEW met1 ( 1669800 2280550 ) ( 1676700 * )
+ NEW met1 ( 1669800 2280550 ) ( * 2281230 )
+ NEW met1 ( 1662900 2281230 ) ( 1669800 * )
+ NEW met1 ( 1662900 2278170 ) ( * 2281230 )
+ NEW met1 ( 1649100 2278170 ) ( 1662900 * )
+ NEW met1 ( 1610690 2284630 ) ( * 2287350 )
+ NEW met2 ( 1610690 2287350 ) ( * 2288710 )
+ NEW met1 ( 1610690 2288710 ) ( 1617590 * )
+ NEW met2 ( 1617590 2287350 ) ( * 2288710 )
+ NEW met1 ( 1617590 2281570 ) ( * 2287350 )
+ NEW met1 ( 1617590 2281570 ) ( 1618050 * )
+ NEW met1 ( 1618050 2281230 ) ( * 2281570 )
+ NEW met1 ( 1618050 2281230 ) ( 1649100 * )
+ NEW met1 ( 1649100 2278170 ) ( * 2281230 )
+ NEW met1 ( 1338600 2284630 ) ( 1610690 * )
+ NEW met2 ( 2902830 1227740 ) M2M3_PR
+ NEW met1 ( 2902830 2284630 ) M1M2_PR
+ NEW met1 ( 1322730 2287350 ) M1M2_PR
+ NEW met1 ( 1610690 2287350 ) M1M2_PR
+ NEW met1 ( 1610690 2288710 ) M1M2_PR
+ NEW met1 ( 1617590 2288710 ) M1M2_PR
+ NEW met1 ( 1617590 2287350 ) M1M2_PR ;
+ - io_in[7] ( PIN io_in[7] ) ( mprj io_in[7] ) + USE SIGNAL
+ + ROUTED met1 ( 1345270 2284970 ) ( * 2287350 )
+ NEW met2 ( 1345270 2287180 ) ( * 2287350 )
+ NEW met2 ( 1344580 2287180 0 ) ( 1345270 * )
+ NEW met3 ( 2903750 1493620 ) ( 2917780 * 0 )
+ NEW met2 ( 2903750 1493620 ) ( * 2284970 )
+ NEW met1 ( 1890600 2284970 ) ( 2903750 * )
+ NEW met1 ( 1890600 2284630 ) ( * 2284970 )
+ NEW met1 ( 1883700 2284630 ) ( 1890600 * )
+ NEW met1 ( 1883700 2284630 ) ( * 2284970 )
+ NEW met1 ( 1863000 2284970 ) ( 1883700 * )
+ NEW met2 ( 1838390 2287350 ) ( * 2288710 )
+ NEW met1 ( 1838390 2287350 ) ( 1838850 * )
+ NEW met1 ( 1838850 2286330 ) ( * 2287350 )
+ NEW met1 ( 1838850 2286330 ) ( 1863000 * )
+ NEW met1 ( 1863000 2284970 ) ( * 2286330 )
+ NEW met2 ( 1790550 2287350 ) ( * 2288710 )
+ NEW met1 ( 1790550 2288710 ) ( 1838390 * )
+ NEW met1 ( 1780200 2287350 ) ( 1790550 * )
+ NEW met1 ( 1780200 2284970 ) ( * 2287350 )
+ NEW met2 ( 1748230 2287350 ) ( * 2288370 )
+ NEW met1 ( 1748230 2287010 ) ( * 2287350 )
+ NEW met1 ( 1748230 2287010 ) ( 1748690 * )
+ NEW met1 ( 1748690 2284970 ) ( * 2287010 )
+ NEW met1 ( 1748690 2284970 ) ( 1780200 * )
+ NEW met1 ( 1708670 2284970 ) ( * 2287350 )
+ NEW met2 ( 1708670 2287350 ) ( * 2288370 )
+ NEW met1 ( 1708670 2288370 ) ( 1748230 * )
+ NEW met1 ( 1609310 2284970 ) ( * 2285310 )
+ NEW met1 ( 1609310 2285310 ) ( 1610230 * )
+ NEW met1 ( 1610230 2285310 ) ( * 2287350 )
+ NEW met2 ( 1610230 2287350 ) ( * 2288370 )
+ NEW met1 ( 1610230 2288370 ) ( 1620350 * )
+ NEW met2 ( 1620350 2287350 ) ( * 2288370 )
+ NEW met1 ( 1620350 2284970 ) ( * 2287350 )
+ NEW met1 ( 1345270 2284970 ) ( 1609310 * )
+ NEW met1 ( 1620350 2284970 ) ( 1708670 * )
+ NEW met1 ( 1345270 2287350 ) M1M2_PR
+ NEW met2 ( 2903750 1493620 ) M2M3_PR
+ NEW met1 ( 2903750 2284970 ) M1M2_PR
+ NEW met1 ( 1838390 2288710 ) M1M2_PR
+ NEW met1 ( 1838390 2287350 ) M1M2_PR
+ NEW met1 ( 1790550 2287350 ) M1M2_PR
+ NEW met1 ( 1790550 2288710 ) M1M2_PR
+ NEW met1 ( 1748230 2288370 ) M1M2_PR
+ NEW met1 ( 1748230 2287350 ) M1M2_PR
+ NEW met1 ( 1708670 2287350 ) M1M2_PR
+ NEW met1 ( 1708670 2288370 ) M1M2_PR
+ NEW met1 ( 1610230 2287350 ) M1M2_PR
+ NEW met1 ( 1610230 2288370 ) M1M2_PR
+ NEW met1 ( 1620350 2288370 ) M1M2_PR
+ NEW met1 ( 1620350 2287350 ) M1M2_PR ;
+ - io_in[8] ( PIN io_in[8] ) ( mprj io_in[8] ) + USE SIGNAL
+ + ROUTED met3 ( 2904670 1759500 ) ( 2917780 * 0 )
+ NEW met1 ( 1370110 2285310 ) ( * 2287350 )
+ NEW met2 ( 1370110 2287180 ) ( * 2287350 )
+ NEW met2 ( 1368500 2287180 0 ) ( 1370110 * )
+ NEW met2 ( 2904670 1759500 ) ( * 2285310 )
+ NEW met1 ( 1883700 2285310 ) ( 2904670 * )
+ NEW met1 ( 1883700 2285310 ) ( * 2287010 )
+ NEW met2 ( 1837470 2287690 ) ( * 2287860 )
+ NEW met3 ( 1837470 2287860 ) ( 1839310 * )
+ NEW met2 ( 1839310 2287350 ) ( * 2287860 )
+ NEW met1 ( 1839310 2287010 ) ( * 2287350 )
+ NEW met1 ( 1839310 2287010 ) ( 1883700 * )
+ NEW met1 ( 1763870 2285310 ) ( * 2287690 )
+ NEW met1 ( 1763870 2287690 ) ( 1837470 * )
+ NEW met1 ( 1752600 2285310 ) ( 1763870 * )
+ NEW met2 ( 1748690 2287350 ) ( * 2287860 )
+ NEW met1 ( 1748690 2287350 ) ( 1752600 * )
+ NEW met1 ( 1752600 2285310 ) ( * 2287350 )
+ NEW met1 ( 1707290 2285310 ) ( * 2287350 )
+ NEW met2 ( 1707290 2287350 ) ( * 2287860 )
+ NEW met3 ( 1707290 2287860 ) ( 1748690 * )
+ NEW met1 ( 1608850 2285310 ) ( * 2287690 )
+ NEW met1 ( 1608850 2287690 ) ( 1620810 * )
+ NEW met1 ( 1620810 2285310 ) ( * 2287690 )
+ NEW met1 ( 1370110 2285310 ) ( 1608850 * )
+ NEW met1 ( 1620810 2285310 ) ( 1707290 * )
+ NEW met2 ( 2904670 1759500 ) M2M3_PR
+ NEW met1 ( 1370110 2287350 ) M1M2_PR
+ NEW met1 ( 2904670 2285310 ) M1M2_PR
+ NEW met1 ( 1837470 2287690 ) M1M2_PR
+ NEW met2 ( 1837470 2287860 ) M2M3_PR
+ NEW met2 ( 1839310 2287860 ) M2M3_PR
+ NEW met1 ( 1839310 2287350 ) M1M2_PR
+ NEW met2 ( 1748690 2287860 ) M2M3_PR
+ NEW met1 ( 1748690 2287350 ) M1M2_PR
+ NEW met1 ( 1707290 2287350 ) M1M2_PR
+ NEW met2 ( 1707290 2287860 ) M2M3_PR ;
+ - io_in[9] ( PIN io_in[9] ) ( mprj io_in[9] ) + USE SIGNAL
+ + ROUTED met3 ( 2900530 2024700 ) ( 2917780 * 0 )
+ NEW met2 ( 2900530 2024700 ) ( * 2285990 )
+ NEW met1 ( 1435200 2285990 ) ( * 2287350 )
+ NEW met1 ( 1393570 2287350 ) ( 1435200 * )
+ NEW met2 ( 1393570 2287180 ) ( * 2287350 )
+ NEW met2 ( 1391960 2287180 0 ) ( 1393570 * )
+ NEW met1 ( 1897500 2285990 ) ( 2900530 * )
+ NEW met1 ( 1897500 2285990 ) ( * 2287690 )
+ NEW met1 ( 1890600 2287690 ) ( 1897500 * )
+ NEW met1 ( 1890600 2287690 ) ( * 2288030 )
+ NEW met1 ( 1704300 2285990 ) ( * 2288030 )
+ NEW met1 ( 1704300 2288030 ) ( 1890600 * )
+ NEW met1 ( 1649100 2285990 ) ( 1704300 * )
+ NEW met1 ( 1435200 2285990 ) ( 1600800 * )
+ NEW met1 ( 1600800 2285990 ) ( * 2289050 )
+ NEW met1 ( 1600800 2289050 ) ( 1649100 * )
+ NEW met1 ( 1649100 2285990 ) ( * 2289050 )
+ NEW met2 ( 2900530 2024700 ) M2M3_PR
+ NEW met1 ( 2900530 2285990 ) M1M2_PR
+ NEW met1 ( 1393570 2287350 ) M1M2_PR ;
+ - io_oeb[0] ( PIN io_oeb[0] ) ( mprj io_oeb[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1186570 2289900 ) ( 1186800 * 0 )
+ NEW met2 ( 1186570 2289900 ) ( * 2298740 )
+ NEW met3 ( 2901220 165580 ) ( 2917780 * 0 )
+ NEW met4 ( 2901220 165580 ) ( * 2298740 )
+ NEW met3 ( 1186570 2298740 ) ( 2901220 * )
+ NEW met2 ( 1186570 2298740 ) M2M3_PR
+ NEW met3 ( 2901220 165580 ) M3M4_PR
+ NEW met3 ( 2901220 2298740 ) M3M4_PR ;
+ - io_oeb[10] ( PIN io_oeb[10] ) ( mprj io_oeb[10] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 2421990 ) ( * 2423180 )
+ NEW met3 ( 2900990 2423180 ) ( 2917780 * 0 )
+ NEW met1 ( 1421630 2421990 ) ( 2900990 * )
+ NEW met2 ( 1421630 2289900 ) ( 1423700 * 0 )
+ NEW met2 ( 1421630 2289900 ) ( * 2421990 )
+ NEW met1 ( 2900990 2421990 ) M1M2_PR
+ NEW met2 ( 2900990 2423180 ) M2M3_PR
+ NEW met1 ( 1421630 2421990 ) M1M2_PR ;
+ - io_oeb[11] ( PIN io_oeb[11] ) ( mprj io_oeb[11] ) + USE SIGNAL
+ + ROUTED met2 ( 1445090 2289900 ) ( 1447160 * 0 )
+ NEW met2 ( 1442330 2401200 ) ( 1445090 * )
+ NEW met2 ( 1445090 2289900 ) ( * 2401200 )
+ NEW met2 ( 1442330 2401200 ) ( * 2684130 )
+ NEW met2 ( 2900990 2684130 ) ( * 2689060 )
+ NEW met3 ( 2900990 2689060 ) ( 2917780 * 0 )
+ NEW met1 ( 1442330 2684130 ) ( 2900990 * )
+ NEW met1 ( 1442330 2684130 ) M1M2_PR
+ NEW met1 ( 2900990 2684130 ) M1M2_PR
+ NEW met2 ( 2900990 2689060 ) M2M3_PR ;
+ - io_oeb[12] ( PIN io_oeb[12] ) ( mprj io_oeb[12] ) + USE SIGNAL
+ + ROUTED met2 ( 1469930 2289900 ) ( 1471080 * 0 )
+ NEW met2 ( 1469930 2289900 ) ( * 2953410 )
+ NEW met2 ( 2899150 2953410 ) ( * 2954940 )
+ NEW met3 ( 2899150 2954940 ) ( 2917780 * 0 )
+ NEW met1 ( 1469930 2953410 ) ( 2899150 * )
+ NEW met1 ( 1469930 2953410 ) M1M2_PR
+ NEW met1 ( 2899150 2953410 ) M1M2_PR
+ NEW met2 ( 2899150 2954940 ) M2M3_PR ;
+ - io_oeb[13] ( PIN io_oeb[13] ) ( mprj io_oeb[13] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3215550 ) ( * 3220140 )
+ NEW met3 ( 2900990 3220140 ) ( 2917780 * 0 )
+ NEW met1 ( 1490630 3215550 ) ( 2900990 * )
+ NEW met2 ( 1492470 2289900 ) ( 1494540 * 0 )
+ NEW met2 ( 1490630 2401200 ) ( 1492470 * )
+ NEW met2 ( 1492470 2289900 ) ( * 2401200 )
+ NEW met2 ( 1490630 2401200 ) ( * 3215550 )
+ NEW met1 ( 2900990 3215550 ) M1M2_PR
+ NEW met2 ( 2900990 3220140 ) M2M3_PR
+ NEW met1 ( 1490630 3215550 ) M1M2_PR ;
+ - io_oeb[14] ( PIN io_oeb[14] ) ( mprj io_oeb[14] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3484830 ) ( * 3486020 )
+ NEW met3 ( 2900990 3486020 ) ( 2917780 * 0 )
+ NEW met1 ( 1518230 3484830 ) ( 2900990 * )
+ NEW met2 ( 1518230 2289900 ) ( 1518460 * 0 )
+ NEW met2 ( 1518230 2289900 ) ( * 3484830 )
+ NEW met1 ( 2900990 3484830 ) M1M2_PR
+ NEW met2 ( 2900990 3486020 ) M2M3_PR
+ NEW met1 ( 1518230 3484830 ) M1M2_PR ;
+ - io_oeb[15] ( PIN io_oeb[15] ) ( mprj io_oeb[15] ) + USE SIGNAL
+ + ROUTED met2 ( 1541920 2289900 0 ) ( 1543530 * )
+ NEW met2 ( 1543530 2289900 ) ( * 2309110 )
+ NEW met2 ( 2636030 2309110 ) ( * 3517980 0 )
+ NEW met1 ( 1543530 2309110 ) ( 2636030 * )
+ NEW met1 ( 1543530 2309110 ) M1M2_PR
+ NEW met1 ( 2636030 2309110 ) M1M2_PR ;
+ - io_oeb[16] ( PIN io_oeb[16] ) ( mprj io_oeb[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1563770 2289900 ) ( 1565840 * 0 )
+ NEW met2 ( 1559630 2401200 ) ( 1563770 * )
+ NEW met2 ( 1563770 2289900 ) ( * 2401200 )
+ NEW met2 ( 1559630 2401200 ) ( * 3504210 )
+ NEW met2 ( 2311730 3504210 ) ( * 3517980 0 )
+ NEW met1 ( 1559630 3504210 ) ( 2311730 * )
+ NEW met1 ( 1559630 3504210 ) M1M2_PR
+ NEW met1 ( 2311730 3504210 ) M1M2_PR ;
+ - io_oeb[17] ( PIN io_oeb[17] ) ( mprj io_oeb[17] ) + USE SIGNAL
+ + ROUTED met2 ( 1589300 2289900 0 ) ( 1590910 * )
+ NEW met2 ( 1590910 2289900 ) ( * 2310810 )
+ NEW met2 ( 1987430 2310810 ) ( * 3517980 0 )
+ NEW met1 ( 1590910 2310810 ) ( 1987430 * )
+ NEW met1 ( 1590910 2310810 ) M1M2_PR
+ NEW met1 ( 1987430 2310810 ) M1M2_PR ;
+ - io_oeb[18] ( PIN io_oeb[18] ) ( mprj io_oeb[18] ) + USE SIGNAL
+ + ROUTED met2 ( 1656690 3517980 ) ( 1661750 * )
+ NEW met2 ( 1661750 3517300 ) ( * 3517980 )
+ NEW met2 ( 1661750 3517300 ) ( 1662670 * )
+ NEW met2 ( 1662670 3517300 ) ( * 3517980 0 )
+ NEW met2 ( 1656690 2307750 ) ( * 3517980 )
+ NEW met1 ( 1614370 2307750 ) ( 1656690 * )
+ NEW met2 ( 1613220 2289900 0 ) ( 1614370 * )
+ NEW met2 ( 1614370 2289900 ) ( * 2307750 )
+ NEW met1 ( 1656690 2307750 ) M1M2_PR
+ NEW met1 ( 1614370 2307750 ) M1M2_PR ;
+ - io_oeb[19] ( PIN io_oeb[19] ) ( mprj io_oeb[19] ) + USE SIGNAL
+ + ROUTED met2 ( 1635530 2289900 ) ( 1636680 * 0 )
+ NEW met2 ( 1635530 2289900 ) ( * 3500810 )
+ NEW met1 ( 1338370 3500810 ) ( 1635530 * )
+ NEW met2 ( 1338370 3500810 ) ( * 3517980 0 )
+ NEW met1 ( 1635530 3500810 ) M1M2_PR
+ NEW met1 ( 1338370 3500810 ) M1M2_PR ;
+ - io_oeb[1] ( PIN io_oeb[1] ) ( mprj io_oeb[1] ) + USE SIGNAL
+ + ROUTED met3 ( 2901450 364820 ) ( 2917780 * 0 )
+ NEW met2 ( 2901450 364820 ) ( * 2284460 )
+ NEW met3 ( 1225900 2284460 ) ( * 2287180 )
+ NEW met3 ( 1211870 2287180 ) ( 1225900 * )
+ NEW met2 ( 1210260 2287180 0 ) ( 1211870 * )
+ NEW met3 ( 1225900 2284460 ) ( 2901450 * )
+ NEW met2 ( 2901450 364820 ) M2M3_PR
+ NEW met2 ( 2901450 2284460 ) M2M3_PR
+ NEW met2 ( 1211870 2287180 ) M2M3_PR ;
+ - io_oeb[20] ( PIN io_oeb[20] ) ( mprj io_oeb[20] ) + USE SIGNAL
+ + ROUTED met2 ( 1658530 2289900 ) ( 1660600 * 0 )
+ NEW met2 ( 1658530 2289900 ) ( * 2304600 )
+ NEW met2 ( 1656230 2304600 ) ( 1658530 * )
+ NEW met2 ( 1656230 2304600 ) ( * 3504550 )
+ NEW met1 ( 1014070 3504550 ) ( 1656230 * )
+ NEW met2 ( 1014070 3504550 ) ( * 3517980 0 )
+ NEW met1 ( 1656230 3504550 ) M1M2_PR
+ NEW met1 ( 1014070 3504550 ) M1M2_PR ;
+ - io_oeb[21] ( PIN io_oeb[21] ) ( mprj io_oeb[21] ) + USE SIGNAL
+ + ROUTED met2 ( 689310 3503190 ) ( * 3517980 0 )
+ NEW met1 ( 689310 3503190 ) ( 1683830 * )
+ NEW met2 ( 1683830 2289900 ) ( 1684060 * 0 )
+ NEW met2 ( 1683830 2289900 ) ( * 3503190 )
+ NEW met1 ( 689310 3503190 ) M1M2_PR
+ NEW met1 ( 1683830 3503190 ) M1M2_PR ;
+ - io_oeb[22] ( PIN io_oeb[22] ) ( mprj io_oeb[22] ) + USE SIGNAL
+ + ROUTED met1 ( 365010 3502170 ) ( 1704530 * )
+ NEW met2 ( 365010 3502170 ) ( * 3517980 0 )
+ NEW met2 ( 1705910 2289900 ) ( 1707980 * 0 )
+ NEW met2 ( 1704530 2401200 ) ( 1705910 * )
+ NEW met2 ( 1705910 2289900 ) ( * 2401200 )
+ NEW met2 ( 1704530 2401200 ) ( * 3502170 )
+ NEW met1 ( 365010 3502170 ) M1M2_PR
+ NEW met1 ( 1704530 3502170 ) M1M2_PR ;
+ - io_oeb[23] ( PIN io_oeb[23] ) ( mprj io_oeb[23] ) + USE SIGNAL
+ + ROUTED met2 ( 1725230 2401200 ) ( 1729370 * )
+ NEW met2 ( 1725230 2401200 ) ( * 3501490 )
+ NEW met1 ( 40710 3501490 ) ( 1725230 * )
+ NEW met2 ( 40710 3501490 ) ( * 3517980 0 )
+ NEW met2 ( 1729370 2289900 ) ( 1731440 * 0 )
+ NEW met2 ( 1729370 2289900 ) ( * 2401200 )
+ NEW met1 ( 1725230 3501490 ) M1M2_PR
+ NEW met1 ( 40710 3501490 ) M1M2_PR ;
+ - io_oeb[24] ( PIN io_oeb[24] ) ( mprj io_oeb[24] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3290860 0 ) ( 17250 * )
+ NEW met2 ( 17250 3284570 ) ( * 3290860 )
+ NEW met2 ( 1752830 2401200 ) ( 1753290 * )
+ NEW met2 ( 1752830 2401200 ) ( * 3284570 )
+ NEW met1 ( 17250 3284570 ) ( 1752830 * )
+ NEW met2 ( 1753290 2289900 ) ( 1755360 * 0 )
+ NEW met2 ( 1753290 2289900 ) ( * 2401200 )
+ NEW met2 ( 17250 3290860 ) M2M3_PR
+ NEW met1 ( 17250 3284570 ) M1M2_PR
+ NEW met1 ( 1752830 3284570 ) M1M2_PR ;
+ - io_oeb[25] ( PIN io_oeb[25] ) ( mprj io_oeb[25] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3030420 0 ) ( 16330 * )
+ NEW met2 ( 16330 3029230 ) ( * 3030420 )
+ NEW met2 ( 1773530 2401200 ) ( 1776750 * )
+ NEW met1 ( 16330 3029230 ) ( 1773530 * )
+ NEW met2 ( 1773530 2401200 ) ( * 3029230 )
+ NEW met2 ( 1776750 2289900 ) ( 1778820 * 0 )
+ NEW met2 ( 1776750 2289900 ) ( * 2401200 )
+ NEW met2 ( 16330 3030420 ) M2M3_PR
+ NEW met1 ( 16330 3029230 ) M1M2_PR
+ NEW met1 ( 1773530 3029230 ) M1M2_PR ;
+ - io_oeb[26] ( PIN io_oeb[26] ) ( mprj io_oeb[26] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2769300 0 ) ( 17250 * )
+ NEW met2 ( 17250 2767090 ) ( * 2769300 )
+ NEW met1 ( 17250 2767090 ) ( 1801130 * )
+ NEW met2 ( 1801130 2289900 ) ( 1802740 * 0 )
+ NEW met2 ( 1801130 2289900 ) ( * 2767090 )
+ NEW met2 ( 17250 2769300 ) M2M3_PR
+ NEW met1 ( 17250 2767090 ) M1M2_PR
+ NEW met1 ( 1801130 2767090 ) M1M2_PR ;
+ - io_oeb[27] ( PIN io_oeb[27] ) ( mprj io_oeb[27] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2508860 0 ) ( 15410 * )
+ NEW met2 ( 15410 2504950 ) ( * 2508860 )
+ NEW met2 ( 1822290 2401200 ) ( 1824130 * )
+ NEW met2 ( 1822290 2401200 ) ( * 2504950 )
+ NEW met1 ( 15410 2504950 ) ( 1822290 * )
+ NEW met2 ( 1824130 2289900 ) ( 1826200 * 0 )
+ NEW met2 ( 1824130 2289900 ) ( * 2401200 )
+ NEW met2 ( 15410 2508860 ) M2M3_PR
+ NEW met1 ( 15410 2504950 ) M1M2_PR
+ NEW met1 ( 1822290 2504950 ) M1M2_PR ;
+ - io_oeb[28] ( PIN io_oeb[28] ) ( mprj io_oeb[28] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2247740 0 ) ( 20470 * )
+ NEW met2 ( 20470 2247740 ) ( * 2284290 )
+ NEW met2 ( 1848510 2289050 ) ( * 2289220 )
+ NEW met2 ( 1848510 2289220 ) ( 1850120 * 0 )
+ NEW met1 ( 1791010 2284630 ) ( * 2287350 )
+ NEW met2 ( 1791010 2287350 ) ( * 2289050 )
+ NEW met1 ( 1791010 2289050 ) ( 1848510 * )
+ NEW met1 ( 1787100 2284630 ) ( 1791010 * )
+ NEW met1 ( 1787100 2283950 ) ( * 2284630 )
+ NEW met1 ( 1780200 2283950 ) ( 1787100 * )
+ NEW met1 ( 1780200 2283950 ) ( * 2284290 )
+ NEW met1 ( 1773300 2284290 ) ( 1780200 * )
+ NEW met1 ( 1773300 2283270 ) ( * 2284290 )
+ NEW met1 ( 1766400 2283270 ) ( 1773300 * )
+ NEW met1 ( 1766400 2283270 ) ( * 2284630 )
+ NEW met1 ( 1746850 2284630 ) ( * 2287690 )
+ NEW met1 ( 1746850 2284630 ) ( 1766400 * )
+ NEW met1 ( 1738800 2287690 ) ( 1746850 * )
+ NEW met1 ( 1738800 2284970 ) ( * 2287690 )
+ NEW met1 ( 1731900 2284970 ) ( 1738800 * )
+ NEW met1 ( 1731900 2283610 ) ( * 2284970 )
+ NEW met1 ( 1725000 2283610 ) ( 1731900 * )
+ NEW met1 ( 1725000 2283610 ) ( * 2284630 )
+ NEW met1 ( 1690500 2284630 ) ( 1725000 * )
+ NEW met1 ( 1690500 2283610 ) ( * 2284630 )
+ NEW met1 ( 1676700 2283610 ) ( 1690500 * )
+ NEW met1 ( 1676700 2283610 ) ( * 2284630 )
+ NEW met1 ( 1612070 2284290 ) ( * 2286670 )
+ NEW met1 ( 1612070 2286670 ) ( 1612530 * )
+ NEW met1 ( 1612530 2286670 ) ( * 2287350 )
+ NEW met2 ( 1612530 2287350 ) ( * 2287860 )
+ NEW met3 ( 1612530 2287860 ) ( 1618510 * )
+ NEW met2 ( 1618510 2287350 ) ( * 2287860 )
+ NEW met1 ( 1618510 2284630 ) ( * 2287350 )
+ NEW met1 ( 20470 2284290 ) ( 1612070 * )
+ NEW met1 ( 1618510 2284630 ) ( 1676700 * )
+ NEW met2 ( 20470 2247740 ) M2M3_PR
+ NEW met1 ( 20470 2284290 ) M1M2_PR
+ NEW met1 ( 1848510 2289050 ) M1M2_PR
+ NEW met1 ( 1791010 2287350 ) M1M2_PR
+ NEW met1 ( 1791010 2289050 ) M1M2_PR
+ NEW met1 ( 1612530 2287350 ) M1M2_PR
+ NEW met2 ( 1612530 2287860 ) M2M3_PR
+ NEW met2 ( 1618510 2287860 ) M2M3_PR
+ NEW met1 ( 1618510 2287350 ) M1M2_PR ;
+ - io_oeb[29] ( PIN io_oeb[29] ) ( mprj io_oeb[29] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1987300 0 ) ( 19090 * )
+ NEW met2 ( 19090 1987300 ) ( * 2283950 )
+ NEW met2 ( 1871970 2288540 ) ( * 2288710 )
+ NEW met2 ( 1871970 2288540 ) ( 1873580 * 0 )
+ NEW met1 ( 1837470 2283950 ) ( * 2287350 )
+ NEW met1 ( 1837470 2287350 ) ( 1837930 * )
+ NEW met1 ( 1837930 2287350 ) ( * 2287690 )
+ NEW met1 ( 1837930 2287690 ) ( 1838850 * )
+ NEW met2 ( 1838850 2287690 ) ( * 2288710 )
+ NEW met1 ( 1838850 2288710 ) ( 1871970 * )
+ NEW met1 ( 1835400 2283950 ) ( 1837470 * )
+ NEW met1 ( 1835400 2283950 ) ( * 2284290 )
+ NEW met1 ( 1828500 2284290 ) ( 1835400 * )
+ NEW met1 ( 1828500 2284290 ) ( * 2284630 )
+ NEW met1 ( 1821600 2284630 ) ( 1828500 * )
+ NEW met1 ( 1821600 2282590 ) ( * 2284630 )
+ NEW met1 ( 1814700 2282590 ) ( 1821600 * )
+ NEW met1 ( 1814700 2282590 ) ( * 2282930 )
+ NEW met1 ( 1807800 2282930 ) ( 1814700 * )
+ NEW met1 ( 1807800 2282930 ) ( * 2283610 )
+ NEW met1 ( 1780200 2283610 ) ( 1807800 * )
+ NEW met1 ( 1780200 2282930 ) ( * 2283610 )
+ NEW met1 ( 1773300 2282930 ) ( 1780200 * )
+ NEW met1 ( 1773300 2282590 ) ( * 2282930 )
+ NEW met1 ( 1766400 2282590 ) ( 1773300 * )
+ NEW met1 ( 1763410 2282590 ) ( * 2282930 )
+ NEW met1 ( 1763410 2282590 ) ( 1764330 * )
+ NEW met1 ( 1764330 2282590 ) ( * 2282930 )
+ NEW met1 ( 1764330 2282930 ) ( 1764790 * )
+ NEW met1 ( 1764790 2282930 ) ( * 2283270 )
+ NEW met1 ( 1764790 2283270 ) ( 1765710 * )
+ NEW met1 ( 1765710 2282930 ) ( * 2283270 )
+ NEW met1 ( 1765710 2282930 ) ( 1766400 * )
+ NEW met1 ( 1766400 2282590 ) ( * 2282930 )
+ NEW met1 ( 1759500 2282930 ) ( 1763410 * )
+ NEW met1 ( 1759500 2282590 ) ( * 2282930 )
+ NEW met1 ( 1752600 2282590 ) ( 1759500 * )
+ NEW met1 ( 1752600 2282590 ) ( * 2282930 )
+ NEW met1 ( 1745700 2282930 ) ( 1752600 * )
+ NEW met1 ( 1745700 2282590 ) ( * 2282930 )
+ NEW met1 ( 1738800 2282590 ) ( 1745700 * )
+ NEW met1 ( 1738800 2282590 ) ( * 2282930 )
+ NEW met1 ( 1731900 2282930 ) ( 1738800 * )
+ NEW met1 ( 1731900 2282250 ) ( * 2282930 )
+ NEW met1 ( 1725000 2282250 ) ( 1731900 * )
+ NEW met1 ( 1725000 2281230 ) ( * 2282250 )
+ NEW met1 ( 1711200 2281230 ) ( 1725000 * )
+ NEW met1 ( 1711200 2281230 ) ( * 2283270 )
+ NEW met1 ( 1704300 2283270 ) ( 1711200 * )
+ NEW met1 ( 1704300 2283270 ) ( * 2283610 )
+ NEW met1 ( 1697400 2283610 ) ( 1704300 * )
+ NEW met1 ( 1697400 2283270 ) ( * 2283610 )
+ NEW met1 ( 1683600 2283270 ) ( 1697400 * )
+ NEW met1 ( 1683600 2282590 ) ( * 2283270 )
+ NEW met1 ( 1676700 2282590 ) ( 1683600 * )
+ NEW met1 ( 1676700 2282590 ) ( * 2282930 )
+ NEW met1 ( 1669800 2282930 ) ( 1676700 * )
+ NEW met1 ( 1669800 2282590 ) ( * 2282930 )
+ NEW met1 ( 1662900 2282590 ) ( 1669800 * )
+ NEW met1 ( 1662900 2282590 ) ( * 2283270 )
+ NEW met1 ( 1656000 2283270 ) ( 1662900 * )
+ NEW met1 ( 1656000 2282250 ) ( * 2283270 )
+ NEW met1 ( 1617130 2283950 ) ( * 2287350 )
+ NEW met2 ( 1617130 2287350 ) ( * 2289220 )
+ NEW met2 ( 1617130 2289220 ) ( 1618050 * )
+ NEW met2 ( 1618050 2287350 ) ( * 2289220 )
+ NEW met1 ( 1618050 2282250 ) ( * 2287350 )
+ NEW met1 ( 19090 2283950 ) ( 1617130 * )
+ NEW met1 ( 1618050 2282250 ) ( 1656000 * )
+ NEW met2 ( 19090 1987300 ) M2M3_PR
+ NEW met1 ( 19090 2283950 ) M1M2_PR
+ NEW met1 ( 1871970 2288710 ) M1M2_PR
+ NEW met1 ( 1838850 2287690 ) M1M2_PR
+ NEW met1 ( 1838850 2288710 ) M1M2_PR
+ NEW met1 ( 1617130 2287350 ) M1M2_PR
+ NEW met1 ( 1618050 2287350 ) M1M2_PR ;
+ - io_oeb[2] ( PIN io_oeb[2] ) ( mprj io_oeb[2] ) + USE SIGNAL
+ + ROUTED met1 ( 2888570 564910 ) ( 2902370 * )
+ NEW met2 ( 2902370 564060 ) ( * 564910 )
+ NEW met3 ( 2902370 564060 ) ( 2917780 * 0 )
+ NEW met2 ( 2888570 564910 ) ( * 2285140 )
+ NEW met3 ( 1242000 2285140 ) ( * 2287180 )
+ NEW met3 ( 1234870 2287180 ) ( 1242000 * )
+ NEW met2 ( 1234180 2287180 0 ) ( 1234870 * )
+ NEW met3 ( 1242000 2285140 ) ( 2888570 * )
+ NEW met1 ( 2888570 564910 ) M1M2_PR
+ NEW met1 ( 2902370 564910 ) M1M2_PR
+ NEW met2 ( 2902370 564060 ) M2M3_PR
+ NEW met2 ( 2888570 2285140 ) M2M3_PR
+ NEW met2 ( 1234870 2287180 ) M2M3_PR ;
+ - io_oeb[30] ( PIN io_oeb[30] ) ( mprj io_oeb[30] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1726860 0 ) ( 17710 * )
+ NEW met2 ( 17710 1726860 ) ( * 2298230 )
+ NEW met2 ( 1895890 2289900 ) ( 1897500 * 0 )
+ NEW met2 ( 1895890 2289900 ) ( * 2298230 )
+ NEW met1 ( 17710 2298230 ) ( 1895890 * )
+ NEW met2 ( 17710 1726860 ) M2M3_PR
+ NEW met1 ( 17710 2298230 ) M1M2_PR
+ NEW met1 ( 1895890 2298230 ) M1M2_PR ;
+ - io_oeb[31] ( PIN io_oeb[31] ) ( mprj io_oeb[31] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1465740 0 ) ( 15410 * )
+ NEW met2 ( 15410 1465740 ) ( * 1469650 )
+ NEW met2 ( 1169090 1469650 ) ( * 2281740 )
+ NEW met4 ( 1919580 2281740 ) ( * 2287860 )
+ NEW met3 ( 1919580 2287860 ) ( 1919810 * )
+ NEW met2 ( 1919810 2287860 ) ( 1920960 * 0 )
+ NEW met1 ( 15410 1469650 ) ( 1169090 * )
+ NEW met3 ( 1169090 2281740 ) ( 1919580 * )
+ NEW met2 ( 15410 1465740 ) M2M3_PR
+ NEW met1 ( 15410 1469650 ) M1M2_PR
+ NEW met1 ( 1169090 1469650 ) M1M2_PR
+ NEW met2 ( 1169090 2281740 ) M2M3_PR
+ NEW met3 ( 1919580 2281740 ) M3M4_PR
+ NEW met3 ( 1919580 2287860 ) M3M4_PR
+ NEW met2 ( 1919810 2287860 ) M2M3_PR
+ NEW met3 ( 1919580 2287860 ) RECT ( -390 -150 0 150 ) ;
+ - io_oeb[32] ( PIN io_oeb[32] ) ( mprj io_oeb[32] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1205300 0 ) ( 17710 * )
+ NEW met2 ( 17710 1205300 ) ( * 1207170 )
+ NEW met2 ( 1172310 1207170 ) ( * 2281060 )
+ NEW met4 ( 1943500 2281060 ) ( * 2287860 )
+ NEW met3 ( 1943500 2287860 ) ( 1943730 * )
+ NEW met2 ( 1943730 2287860 ) ( 1944880 * 0 )
+ NEW met1 ( 17710 1207170 ) ( 1172310 * )
+ NEW met3 ( 1172310 2281060 ) ( 1943500 * )
+ NEW met2 ( 17710 1205300 ) M2M3_PR
+ NEW met1 ( 17710 1207170 ) M1M2_PR
+ NEW met1 ( 1172310 1207170 ) M1M2_PR
+ NEW met2 ( 1172310 2281060 ) M2M3_PR
+ NEW met3 ( 1943500 2281060 ) M3M4_PR
+ NEW met3 ( 1943500 2287860 ) M3M4_PR
+ NEW met2 ( 1943730 2287860 ) M2M3_PR
+ NEW met3 ( 1943500 2287860 ) RECT ( -390 -150 0 150 ) ;
+ - io_oeb[33] ( PIN io_oeb[33] ) ( mprj io_oeb[33] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 944180 0 ) ( 17710 * )
+ NEW met2 ( 17710 944180 ) ( * 945030 )
+ NEW met2 ( 1171390 945030 ) ( * 2280380 )
+ NEW met4 ( 1965580 2280380 ) ( * 2286500 )
+ NEW met1 ( 17710 945030 ) ( 1171390 * )
+ NEW met4 ( 1967420 2286500 ) ( * 2287180 )
+ NEW met3 ( 1967420 2287180 ) ( 1967650 * )
+ NEW met2 ( 1967650 2287180 ) ( 1968340 * 0 )
+ NEW met4 ( 1965580 2286500 ) ( 1967420 * )
+ NEW met3 ( 1171390 2280380 ) ( 1965580 * )
+ NEW met2 ( 17710 944180 ) M2M3_PR
+ NEW met1 ( 17710 945030 ) M1M2_PR
+ NEW met1 ( 1171390 945030 ) M1M2_PR
+ NEW met2 ( 1171390 2280380 ) M2M3_PR
+ NEW met3 ( 1965580 2280380 ) M3M4_PR
+ NEW met3 ( 1967420 2287180 ) M3M4_PR
+ NEW met2 ( 1967650 2287180 ) M2M3_PR
+ NEW met3 ( 1967650 2287180 ) RECT ( 0 -150 390 150 ) ;
+ - io_oeb[34] ( PIN io_oeb[34] ) ( mprj io_oeb[34] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 683740 0 ) ( 17710 * )
+ NEW met2 ( 17710 683740 ) ( * 689690 )
+ NEW met2 ( 1170470 689690 ) ( * 2294830 )
+ NEW met1 ( 17710 689690 ) ( 1170470 * )
+ NEW met2 ( 1990650 2289900 ) ( 1992260 * 0 )
+ NEW met2 ( 1990650 2289900 ) ( * 2294830 )
+ NEW met1 ( 1170470 2294830 ) ( 1990650 * )
+ NEW met2 ( 17710 683740 ) M2M3_PR
+ NEW met1 ( 17710 689690 ) M1M2_PR
+ NEW met1 ( 1170470 689690 ) M1M2_PR
+ NEW met1 ( 1170470 2294830 ) M1M2_PR
+ NEW met1 ( 1990650 2294830 ) M1M2_PR ;
+ - io_oeb[35] ( PIN io_oeb[35] ) ( mprj io_oeb[35] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 423300 0 ) ( 17710 * )
+ NEW met2 ( 17710 423300 ) ( * 427550 )
+ NEW met2 ( 1169550 427550 ) ( * 2293980 )
+ NEW met2 ( 2015490 2289900 ) ( 2015720 * 0 )
+ NEW met2 ( 2015490 2289900 ) ( * 2293980 )
+ NEW met1 ( 17710 427550 ) ( 1169550 * )
+ NEW met3 ( 1169550 2293980 ) ( 2015490 * )
+ NEW met2 ( 17710 423300 ) M2M3_PR
+ NEW met1 ( 17710 427550 ) M1M2_PR
+ NEW met1 ( 1169550 427550 ) M1M2_PR
+ NEW met2 ( 1169550 2293980 ) M2M3_PR
+ NEW met2 ( 2015490 2293980 ) M2M3_PR ;
+ - io_oeb[36] ( PIN io_oeb[36] ) ( mprj io_oeb[36] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 227460 0 ) ( 3220 * )
+ NEW met3 ( 3220 226780 ) ( * 227460 )
+ NEW met3 ( 1380 226780 ) ( 3220 * )
+ NEW met3 ( 1380 224060 ) ( * 226780 )
+ NEW met4 ( 1168860 221340 ) ( * 2292620 )
+ NEW met2 ( 2038030 2289900 ) ( 2039640 * 0 )
+ NEW met2 ( 2038030 2289900 ) ( * 2292620 )
+ NEW met3 ( 1380 224060 ) ( 34500 * )
+ NEW met3 ( 34500 221340 ) ( * 224060 )
+ NEW met3 ( 34500 221340 ) ( 1168860 * )
+ NEW met3 ( 1168860 2292620 ) ( 2038030 * )
+ NEW met3 ( 1168860 221340 ) M3M4_PR
+ NEW met3 ( 1168860 2292620 ) M3M4_PR
+ NEW met2 ( 2038030 2292620 ) M2M3_PR ;
+ - io_oeb[37] ( PIN io_oeb[37] ) ( mprj io_oeb[37] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 32300 0 ) ( 17250 * )
+ NEW met2 ( 17250 32300 ) ( * 2302140 )
+ NEW met2 ( 2061490 2289900 ) ( * 2302140 )
+ NEW met2 ( 2061490 2289900 ) ( 2063100 * 0 )
+ NEW met3 ( 17250 2302140 ) ( 2061490 * )
+ NEW met2 ( 17250 32300 ) M2M3_PR
+ NEW met2 ( 17250 2302140 ) M2M3_PR
+ NEW met2 ( 2061490 2302140 ) M2M3_PR ;
+ - io_oeb[3] ( PIN io_oeb[3] ) ( mprj io_oeb[3] ) + USE SIGNAL
+ + ROUTED met1 ( 2889490 765850 ) ( 2903750 * )
+ NEW met2 ( 2903750 763300 ) ( * 765850 )
+ NEW met3 ( 2903750 763300 ) ( 2917780 * 0 )
+ NEW met2 ( 1257640 2289900 0 ) ( 1259250 * )
+ NEW met2 ( 1259250 2289900 ) ( * 2292110 )
+ NEW met2 ( 2889490 765850 ) ( * 2292110 )
+ NEW met1 ( 1259250 2292110 ) ( 2889490 * )
+ NEW met1 ( 2889490 765850 ) M1M2_PR
+ NEW met1 ( 2903750 765850 ) M1M2_PR
+ NEW met2 ( 2903750 763300 ) M2M3_PR
+ NEW met1 ( 1259250 2292110 ) M1M2_PR
+ NEW met1 ( 2889490 2292110 ) M1M2_PR ;
+ - io_oeb[4] ( PIN io_oeb[4] ) ( mprj io_oeb[4] ) + USE SIGNAL
+ + ROUTED met1 ( 2890410 965770 ) ( 2898230 * )
+ NEW met2 ( 2898230 962540 ) ( * 965770 )
+ NEW met3 ( 2898230 962540 ) ( 2917780 * 0 )
+ NEW met2 ( 1281560 2289900 0 ) ( 1283170 * )
+ NEW met2 ( 1283170 2289900 ) ( * 2292450 )
+ NEW met2 ( 2890410 965770 ) ( * 2292450 )
+ NEW met1 ( 1283170 2292450 ) ( 2890410 * )
+ NEW met1 ( 2890410 965770 ) M1M2_PR
+ NEW met1 ( 2898230 965770 ) M1M2_PR
+ NEW met2 ( 2898230 962540 ) M2M3_PR
+ NEW met1 ( 1283170 2292450 ) M1M2_PR
+ NEW met1 ( 2890410 2292450 ) M1M2_PR ;
+ - io_oeb[5] ( PIN io_oeb[5] ) ( mprj io_oeb[5] ) + USE SIGNAL
+ + ROUTED met1 ( 2890870 1166030 ) ( 2898230 * )
+ NEW met2 ( 2898230 1161780 ) ( * 1166030 )
+ NEW met3 ( 2898230 1161780 ) ( 2917780 * 0 )
+ NEW met2 ( 2890870 1166030 ) ( * 2292790 )
+ NEW met2 ( 1305020 2289900 0 ) ( 1306630 * )
+ NEW met2 ( 1306630 2289900 ) ( * 2292790 )
+ NEW met1 ( 1306630 2292790 ) ( 2890870 * )
+ NEW met1 ( 2890870 1166030 ) M1M2_PR
+ NEW met1 ( 2898230 1166030 ) M1M2_PR
+ NEW met2 ( 2898230 1161780 ) M2M3_PR
+ NEW met1 ( 2890870 2292790 ) M1M2_PR
+ NEW met1 ( 1306630 2292790 ) M1M2_PR ;
+ - io_oeb[6] ( PIN io_oeb[6] ) ( mprj io_oeb[6] ) + USE SIGNAL
+ + ROUTED met1 ( 2887190 1365950 ) ( 2898230 * )
+ NEW met2 ( 2898230 1361020 ) ( * 1365950 )
+ NEW met3 ( 2898230 1361020 ) ( 2917780 * 0 )
+ NEW met2 ( 2887190 1365950 ) ( * 2293130 )
+ NEW met2 ( 1328940 2289900 0 ) ( 1330550 * )
+ NEW met2 ( 1330550 2289900 ) ( * 2293130 )
+ NEW met1 ( 1330550 2293130 ) ( 2887190 * )
+ NEW met1 ( 2887190 1365950 ) M1M2_PR
+ NEW met1 ( 2898230 1365950 ) M1M2_PR
+ NEW met2 ( 2898230 1361020 ) M2M3_PR
+ NEW met1 ( 2887190 2293130 ) M1M2_PR
+ NEW met1 ( 1330550 2293130 ) M1M2_PR ;
+ - io_oeb[7] ( PIN io_oeb[7] ) ( mprj io_oeb[7] ) + USE SIGNAL
+ + ROUTED met2 ( 1352170 2289900 ) ( 1352400 * 0 )
+ NEW met2 ( 1352170 2289900 ) ( * 2293470 )
+ NEW met1 ( 2886730 1627410 ) ( 2900530 * )
+ NEW met2 ( 2900530 1626220 ) ( * 1627410 )
+ NEW met3 ( 2900530 1626220 ) ( 2917780 * 0 )
+ NEW met2 ( 2886730 1627410 ) ( * 2293470 )
+ NEW met1 ( 1352170 2293470 ) ( 2886730 * )
+ NEW met1 ( 1352170 2293470 ) M1M2_PR
+ NEW met1 ( 2886730 1627410 ) M1M2_PR
+ NEW met1 ( 2900530 1627410 ) M1M2_PR
+ NEW met2 ( 2900530 1626220 ) M2M3_PR
+ NEW met1 ( 2886730 2293470 ) M1M2_PR ;
+ - io_oeb[8] ( PIN io_oeb[8] ) ( mprj io_oeb[8] ) + USE SIGNAL
+ + ROUTED met2 ( 1377930 2287180 ) ( * 2287350 )
+ NEW met2 ( 1376320 2287180 0 ) ( 1377930 * )
+ NEW met3 ( 2900990 1892100 ) ( 2917780 * 0 )
+ NEW met2 ( 2900990 1892100 ) ( * 2285650 )
+ NEW met1 ( 1377930 2287350 ) ( 1386900 * )
+ NEW met1 ( 1386900 2285650 ) ( * 2287350 )
+ NEW met1 ( 1890600 2285650 ) ( 2900990 * )
+ NEW met2 ( 1866450 2287350 ) ( * 2288370 )
+ NEW met1 ( 1866450 2287350 ) ( 1890600 * )
+ NEW met1 ( 1890600 2285650 ) ( * 2287350 )
+ NEW met1 ( 1780200 2288370 ) ( 1866450 * )
+ NEW met1 ( 1780200 2288370 ) ( * 2288710 )
+ NEW met1 ( 1704990 2285650 ) ( * 2287350 )
+ NEW met2 ( 1704990 2287350 ) ( * 2288710 )
+ NEW met1 ( 1704990 2288710 ) ( 1780200 * )
+ NEW met1 ( 1601490 2285650 ) ( * 2288030 )
+ NEW met1 ( 1601490 2288030 ) ( 1621270 * )
+ NEW met1 ( 1621270 2285650 ) ( * 2288030 )
+ NEW met1 ( 1386900 2285650 ) ( 1601490 * )
+ NEW met1 ( 1621270 2285650 ) ( 1704990 * )
+ NEW met1 ( 1377930 2287350 ) M1M2_PR
+ NEW met2 ( 2900990 1892100 ) M2M3_PR
+ NEW met1 ( 2900990 2285650 ) M1M2_PR
+ NEW met1 ( 1866450 2288370 ) M1M2_PR
+ NEW met1 ( 1866450 2287350 ) M1M2_PR
+ NEW met1 ( 1704990 2287350 ) M1M2_PR
+ NEW met1 ( 1704990 2288710 ) M1M2_PR ;
+ - io_oeb[9] ( PIN io_oeb[9] ) ( mprj io_oeb[9] ) + USE SIGNAL
+ + ROUTED met3 ( 2917780 2153220 ) ( * 2157300 )
+ NEW met3 ( 2916860 2157300 ) ( 2917780 * )
+ NEW met3 ( 2916860 2157300 ) ( * 2157980 )
+ NEW met3 ( 2916860 2157980 ) ( 2917780 * 0 )
+ NEW met4 ( 2049300 2296700 ) ( * 2301460 )
+ NEW met4 ( 2048380 2296700 ) ( 2049300 * )
+ NEW met4 ( 2048380 2153220 ) ( * 2296700 )
+ NEW met3 ( 2048380 2153220 ) ( 2917780 * )
+ NEW met2 ( 1399780 2289900 0 ) ( 1400470 * )
+ NEW met2 ( 1400470 2289900 ) ( * 2301460 )
+ NEW met3 ( 1400470 2301460 ) ( 2049300 * )
+ NEW met3 ( 2048380 2153220 ) M3M4_PR
+ NEW met3 ( 2049300 2301460 ) M3M4_PR
+ NEW met2 ( 1400470 2301460 ) M2M3_PR ;
+ - io_out[0] ( PIN io_out[0] ) ( mprj io_out[0] ) + USE SIGNAL
+ + ROUTED met3 ( 2887420 98940 ) ( 2917780 * 0 )
+ NEW met4 ( 2887420 98940 ) ( * 2291260 )
+ NEW met2 ( 1194620 2289900 0 ) ( * 2291260 )
+ NEW met3 ( 1194620 2291260 ) ( 2887420 * )
+ NEW met3 ( 2887420 98940 ) M3M4_PR
+ NEW met3 ( 2887420 2291260 ) M3M4_PR
+ NEW met2 ( 1194620 2291260 ) M2M3_PR ;
+ - io_out[10] ( PIN io_out[10] ) ( mprj io_out[10] ) + USE SIGNAL
+ + ROUTED met2 ( 2900070 2352970 ) ( * 2357220 )
+ NEW met3 ( 2900070 2357220 ) ( 2917780 * 0 )
+ NEW met2 ( 1429450 2289900 ) ( 1431520 * 0 )
+ NEW met2 ( 1429450 2289900 ) ( * 2352970 )
+ NEW met1 ( 1429450 2352970 ) ( 2900070 * )
+ NEW met1 ( 2900070 2352970 ) M1M2_PR
+ NEW met2 ( 2900070 2357220 ) M2M3_PR
+ NEW met1 ( 1429450 2352970 ) M1M2_PR ;
+ - io_out[11] ( PIN io_out[11] ) ( mprj io_out[11] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 2622250 ) ( * 2622420 )
+ NEW met3 ( 2900990 2622420 ) ( 2917780 * 0 )
+ NEW met2 ( 1452910 2289900 ) ( 1454980 * 0 )
+ NEW met2 ( 1449230 2401200 ) ( 1452910 * )
+ NEW met2 ( 1452910 2289900 ) ( * 2401200 )
+ NEW met2 ( 1449230 2401200 ) ( * 2622250 )
+ NEW met1 ( 1449230 2622250 ) ( 2900990 * )
+ NEW met1 ( 1449230 2622250 ) M1M2_PR
+ NEW met1 ( 2900990 2622250 ) M1M2_PR
+ NEW met2 ( 2900990 2622420 ) M2M3_PR ;
+ - io_out[12] ( PIN io_out[12] ) ( mprj io_out[12] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 2884390 ) ( * 2888300 )
+ NEW met3 ( 2900990 2888300 ) ( 2917780 * 0 )
+ NEW met2 ( 1476830 2289900 ) ( 1478900 * 0 )
+ NEW met2 ( 1476830 2289900 ) ( * 2884390 )
+ NEW met1 ( 1476830 2884390 ) ( 2900990 * )
+ NEW met1 ( 1476830 2884390 ) M1M2_PR
+ NEW met1 ( 2900990 2884390 ) M1M2_PR
+ NEW met2 ( 2900990 2888300 ) M2M3_PR ;
+ - io_out[13] ( PIN io_out[13] ) ( mprj io_out[13] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3153330 ) ( * 3154180 )
+ NEW met3 ( 2900990 3154180 ) ( 2917780 * 0 )
+ NEW met2 ( 1500290 2289900 ) ( 1502360 * 0 )
+ NEW met2 ( 1497990 2401200 ) ( 1500290 * )
+ NEW met2 ( 1500290 2289900 ) ( * 2401200 )
+ NEW met2 ( 1497990 2401200 ) ( * 3153330 )
+ NEW met1 ( 1497990 3153330 ) ( 2900990 * )
+ NEW met1 ( 2900990 3153330 ) M1M2_PR
+ NEW met2 ( 2900990 3154180 ) M2M3_PR
+ NEW met1 ( 1497990 3153330 ) M1M2_PR ;
+ - io_out[14] ( PIN io_out[14] ) ( mprj io_out[14] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 3416150 ) ( * 3419380 )
+ NEW met3 ( 2900990 3419380 ) ( 2917780 * 0 )
+ NEW met2 ( 1525130 2289900 ) ( 1526280 * 0 )
+ NEW met2 ( 1525130 2289900 ) ( * 3416150 )
+ NEW met1 ( 1525130 3416150 ) ( 2900990 * )
+ NEW met1 ( 2900990 3416150 ) M1M2_PR
+ NEW met2 ( 2900990 3419380 ) M2M3_PR
+ NEW met1 ( 1525130 3416150 ) M1M2_PR ;
+ - io_out[15] ( PIN io_out[15] ) ( mprj io_out[15] ) + USE SIGNAL
+ + ROUTED met2 ( 1547670 2289900 ) ( 1549740 * 0 )
+ NEW met2 ( 1545830 2401200 ) ( 1547670 * )
+ NEW met2 ( 1547670 2289900 ) ( * 2401200 )
+ NEW met2 ( 1545830 2401200 ) ( * 3502850 )
+ NEW met2 ( 2717450 3502850 ) ( * 3517980 0 )
+ NEW met1 ( 1545830 3502850 ) ( 2717450 * )
+ NEW met1 ( 1545830 3502850 ) M1M2_PR
+ NEW met1 ( 2717450 3502850 ) M1M2_PR ;
+ - io_out[16] ( PIN io_out[16] ) ( mprj io_out[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1573430 2289900 ) ( 1573660 * 0 )
+ NEW met2 ( 1573430 2289900 ) ( * 3503870 )
+ NEW met1 ( 1573430 3503870 ) ( 2392690 * )
+ NEW met2 ( 2392690 3503870 ) ( * 3517980 0 )
+ NEW met1 ( 1573430 3503870 ) M1M2_PR
+ NEW met1 ( 2392690 3503870 ) M1M2_PR ;
+ - io_out[17] ( PIN io_out[17] ) ( mprj io_out[17] ) + USE SIGNAL
+ + ROUTED met1 ( 1594130 3501150 ) ( 2068390 * )
+ NEW met2 ( 1595050 2289900 ) ( 1597120 * 0 )
+ NEW met2 ( 1594130 2401200 ) ( 1595050 * )
+ NEW met2 ( 1595050 2289900 ) ( * 2401200 )
+ NEW met2 ( 1594130 2401200 ) ( * 3501150 )
+ NEW met2 ( 2068390 3501150 ) ( * 3517980 0 )
+ NEW met1 ( 1594130 3501150 ) M1M2_PR
+ NEW met1 ( 2068390 3501150 ) M1M2_PR ;
+ - io_out[18] ( PIN io_out[18] ) ( mprj io_out[18] ) + USE SIGNAL
+ + ROUTED met2 ( 1739030 2302310 ) ( * 3512100 )
+ NEW met2 ( 1739030 3512100 ) ( 1744090 * )
+ NEW met2 ( 1744090 3512100 ) ( * 3517980 0 )
+ NEW met2 ( 1620810 2289220 ) ( 1621040 * 0 )
+ NEW met2 ( 1620810 2289220 ) ( * 2302310 )
+ NEW met1 ( 1620810 2302310 ) ( 1739030 * )
+ NEW met1 ( 1739030 2302310 ) M1M2_PR
+ NEW met1 ( 1620810 2302310 ) M1M2_PR ;
+ - io_out[19] ( PIN io_out[19] ) ( mprj io_out[19] ) + USE SIGNAL
+ + ROUTED met2 ( 1642890 2289900 ) ( 1644500 * 0 )
+ NEW met2 ( 1642890 2289900 ) ( * 2301970 )
+ NEW met2 ( 1414730 2301970 ) ( * 3512100 )
+ NEW met2 ( 1414730 3512100 ) ( 1419330 * )
+ NEW met2 ( 1419330 3512100 ) ( * 3517980 0 )
+ NEW met1 ( 1414730 2301970 ) ( 1642890 * )
+ NEW met1 ( 1642890 2301970 ) M1M2_PR
+ NEW met1 ( 1414730 2301970 ) M1M2_PR ;
+ - io_out[1] ( PIN io_out[1] ) ( mprj io_out[1] ) + USE SIGNAL
+ + ROUTED met1 ( 2888110 303450 ) ( 2899610 * )
+ NEW met2 ( 2899610 298180 ) ( * 303450 )
+ NEW met3 ( 2899610 298180 ) ( 2917780 * 0 )
+ NEW met2 ( 2888110 303450 ) ( * 2291940 )
+ NEW met2 ( 1218080 2289900 0 ) ( 1219690 * )
+ NEW met2 ( 1219690 2289900 ) ( * 2291940 )
+ NEW met3 ( 1219690 2291940 ) ( 2888110 * )
+ NEW met1 ( 2888110 303450 ) M1M2_PR
+ NEW met1 ( 2899610 303450 ) M1M2_PR
+ NEW met2 ( 2899610 298180 ) M2M3_PR
+ NEW met2 ( 2888110 2291940 ) M2M3_PR
+ NEW met2 ( 1219690 2291940 ) M2M3_PR ;
+ - io_out[20] ( PIN io_out[20] ) ( mprj io_out[20] ) + USE SIGNAL
+ + ROUTED met2 ( 1095030 3504890 ) ( * 3517980 0 )
+ NEW met2 ( 1666810 2289900 ) ( 1668420 * 0 )
+ NEW met2 ( 1666810 2289900 ) ( * 2302650 )
+ NEW met1 ( 1645650 2302650 ) ( 1666810 * )
+ NEW met2 ( 1645650 2302650 ) ( * 3504890 )
+ NEW met1 ( 1095030 3504890 ) ( 1645650 * )
+ NEW met1 ( 1095030 3504890 ) M1M2_PR
+ NEW met1 ( 1645650 3504890 ) M1M2_PR
+ NEW met1 ( 1666810 2302650 ) M1M2_PR
+ NEW met1 ( 1645650 2302650 ) M1M2_PR ;
+ - io_out[21] ( PIN io_out[21] ) ( mprj io_out[21] ) + USE SIGNAL
+ + ROUTED met2 ( 770730 3503530 ) ( * 3517980 0 )
+ NEW met2 ( 1666350 2301970 ) ( * 3503530 )
+ NEW met1 ( 770730 3503530 ) ( 1666350 * )
+ NEW met2 ( 1690730 2289900 ) ( 1691880 * 0 )
+ NEW met2 ( 1690730 2289900 ) ( * 2301970 )
+ NEW met1 ( 1666350 2301970 ) ( 1690730 * )
+ NEW met1 ( 770730 3503530 ) M1M2_PR
+ NEW met1 ( 1666350 3503530 ) M1M2_PR
+ NEW met1 ( 1666350 2301970 ) M1M2_PR
+ NEW met1 ( 1690730 2301970 ) M1M2_PR ;
+ - io_out[22] ( PIN io_out[22] ) ( mprj io_out[22] ) + USE SIGNAL
+ + ROUTED met1 ( 445970 3502510 ) ( 1693950 * )
+ NEW met2 ( 445970 3502510 ) ( * 3517980 0 )
+ NEW met1 ( 1693950 2301970 ) ( 1714190 * )
+ NEW met2 ( 1693950 2301970 ) ( * 3502510 )
+ NEW met2 ( 1714190 2289900 ) ( 1715800 * 0 )
+ NEW met2 ( 1714190 2289900 ) ( * 2301970 )
+ NEW met1 ( 445970 3502510 ) M1M2_PR
+ NEW met1 ( 1693950 3502510 ) M1M2_PR
+ NEW met1 ( 1714190 2301970 ) M1M2_PR
+ NEW met1 ( 1693950 2301970 ) M1M2_PR ;
+ - io_out[23] ( PIN io_out[23] ) ( mprj io_out[23] ) + USE SIGNAL
+ + ROUTED met2 ( 121670 3501830 ) ( * 3517980 0 )
+ NEW met2 ( 1739260 2289220 0 ) ( 1739950 * )
+ NEW met2 ( 1739950 2289220 ) ( * 2302990 )
+ NEW met1 ( 121670 3501830 ) ( 1714650 * )
+ NEW met1 ( 1714650 2302990 ) ( 1739950 * )
+ NEW met2 ( 1714650 2302990 ) ( * 3501830 )
+ NEW met1 ( 121670 3501830 ) M1M2_PR
+ NEW met1 ( 1739950 2302990 ) M1M2_PR
+ NEW met1 ( 1714650 3501830 ) M1M2_PR
+ NEW met1 ( 1714650 2302990 ) M1M2_PR ;
+ - io_out[24] ( PIN io_out[24] ) ( mprj io_out[24] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3356140 0 ) ( 17710 * )
+ NEW met2 ( 17710 3353590 ) ( * 3356140 )
+ NEW met2 ( 1759730 2401200 ) ( 1761110 * )
+ NEW met2 ( 1759730 2401200 ) ( * 3353590 )
+ NEW met1 ( 17710 3353590 ) ( 1759730 * )
+ NEW met2 ( 1761110 2289900 ) ( 1763180 * 0 )
+ NEW met2 ( 1761110 2289900 ) ( * 2401200 )
+ NEW met2 ( 17710 3356140 ) M2M3_PR
+ NEW met1 ( 17710 3353590 ) M1M2_PR
+ NEW met1 ( 1759730 3353590 ) M1M2_PR ;
+ - io_out[25] ( PIN io_out[25] ) ( mprj io_out[25] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 3095700 0 ) ( 15870 * )
+ NEW met2 ( 15870 3091450 ) ( * 3095700 )
+ NEW met1 ( 15870 3091450 ) ( 1780430 * )
+ NEW met2 ( 1780430 2401200 ) ( 1784570 * )
+ NEW met2 ( 1780430 2401200 ) ( * 3091450 )
+ NEW met2 ( 1784570 2289900 ) ( 1786640 * 0 )
+ NEW met2 ( 1784570 2289900 ) ( * 2401200 )
+ NEW met2 ( 15870 3095700 ) M2M3_PR
+ NEW met1 ( 15870 3091450 ) M1M2_PR
+ NEW met1 ( 1780430 3091450 ) M1M2_PR ;
+ - io_out[26] ( PIN io_out[26] ) ( mprj io_out[26] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2834580 0 ) ( 17250 * )
+ NEW met2 ( 17250 2829310 ) ( * 2834580 )
+ NEW met1 ( 17250 2829310 ) ( 1808030 * )
+ NEW met2 ( 1808030 2401200 ) ( 1808490 * )
+ NEW met2 ( 1808030 2401200 ) ( * 2829310 )
+ NEW met2 ( 1808490 2289900 ) ( 1810560 * 0 )
+ NEW met2 ( 1808490 2289900 ) ( * 2401200 )
+ NEW met2 ( 17250 2834580 ) M2M3_PR
+ NEW met1 ( 17250 2829310 ) M1M2_PR
+ NEW met1 ( 1808030 2829310 ) M1M2_PR ;
+ - io_out[27] ( PIN io_out[27] ) ( mprj io_out[27] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2574140 0 ) ( 17250 * )
+ NEW met2 ( 17250 2573970 ) ( * 2574140 )
+ NEW met2 ( 1742250 2302310 ) ( * 2573970 )
+ NEW met1 ( 17250 2573970 ) ( 1742250 * )
+ NEW met1 ( 1742250 2302310 ) ( 1832410 * )
+ NEW met2 ( 1832410 2289900 ) ( 1834020 * 0 )
+ NEW met2 ( 1832410 2289900 ) ( * 2302310 )
+ NEW met2 ( 17250 2574140 ) M2M3_PR
+ NEW met1 ( 17250 2573970 ) M1M2_PR
+ NEW met1 ( 1742250 2302310 ) M1M2_PR
+ NEW met1 ( 1742250 2573970 ) M1M2_PR
+ NEW met1 ( 1832410 2302310 ) M1M2_PR ;
+ - io_out[28] ( PIN io_out[28] ) ( mprj io_out[28] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2313020 0 ) ( 16330 * )
+ NEW met2 ( 16330 2311830 ) ( * 2313020 )
+ NEW met2 ( 1745470 2301970 ) ( * 2311830 )
+ NEW met1 ( 16330 2311830 ) ( 1745470 * )
+ NEW met1 ( 1745470 2301970 ) ( 1856330 * )
+ NEW met2 ( 1856330 2289900 ) ( 1857940 * 0 )
+ NEW met2 ( 1856330 2289900 ) ( * 2301970 )
+ NEW met2 ( 16330 2313020 ) M2M3_PR
+ NEW met1 ( 16330 2311830 ) M1M2_PR
+ NEW met1 ( 1745470 2311830 ) M1M2_PR
+ NEW met1 ( 1745470 2301970 ) M1M2_PR
+ NEW met1 ( 1856330 2301970 ) M1M2_PR ;
+ - io_out[29] ( PIN io_out[29] ) ( mprj io_out[29] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 2052580 0 ) ( 19550 * )
+ NEW met2 ( 19550 2052580 ) ( * 2298570 )
+ NEW met2 ( 1879790 2289900 ) ( 1881400 * 0 )
+ NEW met2 ( 1879790 2289900 ) ( * 2298570 )
+ NEW met1 ( 19550 2298570 ) ( 1879790 * )
+ NEW met2 ( 19550 2052580 ) M2M3_PR
+ NEW met1 ( 19550 2298570 ) M1M2_PR
+ NEW met1 ( 1879790 2298570 ) M1M2_PR ;
+ - io_out[2] ( PIN io_out[2] ) ( mprj io_out[2] ) + USE SIGNAL
+ + ROUTED met1 ( 2887650 503370 ) ( 2899150 * )
+ NEW met2 ( 2899150 497420 ) ( * 503370 )
+ NEW met3 ( 2899150 497420 ) ( 2917780 * 0 )
+ NEW met2 ( 2887650 503370 ) ( * 2291770 )
+ NEW met2 ( 1241770 2289900 ) ( 1242000 * 0 )
+ NEW met2 ( 1241770 2289900 ) ( * 2291770 )
+ NEW met1 ( 1241770 2291770 ) ( 2887650 * )
+ NEW met1 ( 2887650 503370 ) M1M2_PR
+ NEW met1 ( 2899150 503370 ) M1M2_PR
+ NEW met2 ( 2899150 497420 ) M2M3_PR
+ NEW met1 ( 2887650 2291770 ) M1M2_PR
+ NEW met1 ( 1241770 2291770 ) M1M2_PR ;
+ - io_out[30] ( PIN io_out[30] ) ( mprj io_out[30] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1792140 0 ) ( 18170 * )
+ NEW met2 ( 18170 1792140 ) ( * 2297890 )
+ NEW met2 ( 1904630 2289900 ) ( 1905320 * 0 )
+ NEW met2 ( 1904630 2289900 ) ( * 2297890 )
+ NEW met1 ( 18170 2297890 ) ( 1904630 * )
+ NEW met2 ( 18170 1792140 ) M2M3_PR
+ NEW met1 ( 18170 2297890 ) M1M2_PR
+ NEW met1 ( 1904630 2297890 ) M1M2_PR ;
+ - io_out[31] ( PIN io_out[31] ) ( mprj io_out[31] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1531020 0 ) ( 17710 * )
+ NEW met2 ( 17710 1531020 ) ( * 1531530 )
+ NEW met2 ( 1157590 1531530 ) ( * 2295510 )
+ NEW met2 ( 1927170 2289900 ) ( 1928780 * 0 )
+ NEW met2 ( 1927170 2289900 ) ( * 2295510 )
+ NEW met1 ( 17710 1531530 ) ( 1157590 * )
+ NEW met1 ( 1157590 2295510 ) ( 1927170 * )
+ NEW met2 ( 17710 1531020 ) M2M3_PR
+ NEW met1 ( 17710 1531530 ) M1M2_PR
+ NEW met1 ( 1157590 1531530 ) M1M2_PR
+ NEW met1 ( 1157590 2295510 ) M1M2_PR
+ NEW met1 ( 1927170 2295510 ) M1M2_PR ;
+ - io_out[32] ( PIN io_out[32] ) ( mprj io_out[32] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1270580 0 ) ( 15870 * )
+ NEW met2 ( 15870 1270580 ) ( * 1276190 )
+ NEW met2 ( 1157130 1276190 ) ( * 2295170 )
+ NEW met2 ( 1951090 2289900 ) ( 1952700 * 0 )
+ NEW met2 ( 1951090 2289900 ) ( * 2295170 )
+ NEW met1 ( 15870 1276190 ) ( 1157130 * )
+ NEW met1 ( 1157130 2295170 ) ( 1951090 * )
+ NEW met2 ( 15870 1270580 ) M2M3_PR
+ NEW met1 ( 15870 1276190 ) M1M2_PR
+ NEW met1 ( 1157130 1276190 ) M1M2_PR
+ NEW met1 ( 1157130 2295170 ) M1M2_PR
+ NEW met1 ( 1951090 2295170 ) M1M2_PR ;
+ - io_out[33] ( PIN io_out[33] ) ( mprj io_out[33] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 1009460 0 ) ( 15410 * )
+ NEW met2 ( 15410 1009460 ) ( * 1014050 )
+ NEW met2 ( 1156670 1014050 ) ( * 2294490 )
+ NEW met1 ( 15410 1014050 ) ( 1156670 * )
+ NEW met2 ( 1974550 2289900 ) ( 1976160 * 0 )
+ NEW met2 ( 1974550 2289900 ) ( * 2294490 )
+ NEW met1 ( 1156670 2294490 ) ( 1974550 * )
+ NEW met2 ( 15410 1009460 ) M2M3_PR
+ NEW met1 ( 15410 1014050 ) M1M2_PR
+ NEW met1 ( 1156670 1014050 ) M1M2_PR
+ NEW met1 ( 1156670 2294490 ) M1M2_PR
+ NEW met1 ( 1974550 2294490 ) M1M2_PR ;
+ - io_out[34] ( PIN io_out[34] ) ( mprj io_out[34] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 749020 0 ) ( 17710 * )
+ NEW met2 ( 17710 749020 ) ( * 751910 )
+ NEW met2 ( 1156210 751910 ) ( * 2294150 )
+ NEW met1 ( 17710 751910 ) ( 1156210 * )
+ NEW met2 ( 1998470 2289900 ) ( 2000080 * 0 )
+ NEW met2 ( 1998470 2289900 ) ( * 2294150 )
+ NEW met1 ( 1156210 2294150 ) ( 1998470 * )
+ NEW met2 ( 17710 749020 ) M2M3_PR
+ NEW met1 ( 17710 751910 ) M1M2_PR
+ NEW met1 ( 1156210 751910 ) M1M2_PR
+ NEW met1 ( 1156210 2294150 ) M1M2_PR
+ NEW met1 ( 1998470 2294150 ) M1M2_PR ;
+ - io_out[35] ( PIN io_out[35] ) ( mprj io_out[35] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 487900 0 ) ( 17710 * )
+ NEW met2 ( 17710 487900 ) ( * 489770 )
+ NEW met2 ( 1155750 489770 ) ( * 2293300 )
+ NEW met2 ( 2021930 2289900 ) ( 2023540 * 0 )
+ NEW met2 ( 2021930 2289900 ) ( * 2293300 )
+ NEW met1 ( 17710 489770 ) ( 1155750 * )
+ NEW met3 ( 1155750 2293300 ) ( 2021930 * )
+ NEW met2 ( 17710 487900 ) M2M3_PR
+ NEW met1 ( 17710 489770 ) M1M2_PR
+ NEW met1 ( 1155750 489770 ) M1M2_PR
+ NEW met2 ( 1155750 2293300 ) M2M3_PR
+ NEW met2 ( 2021930 2293300 ) M2M3_PR ;
+ - io_out[36] ( PIN io_out[36] ) ( mprj io_out[36] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 292740 0 ) ( 3220 * )
+ NEW met3 ( 3220 292060 ) ( * 292740 )
+ NEW met3 ( 1380 292060 ) ( 3220 * )
+ NEW met3 ( 1380 290020 ) ( * 292060 )
+ NEW met3 ( 2043780 2287180 ) ( 2045850 * )
+ NEW met2 ( 2045850 2287180 ) ( 2047460 * 0 )
+ NEW met4 ( 2043780 290020 ) ( * 2287180 )
+ NEW met3 ( 1380 290020 ) ( 2043780 * )
+ NEW met3 ( 2043780 290020 ) M3M4_PR
+ NEW met3 ( 2043780 2287180 ) M3M4_PR
+ NEW met2 ( 2045850 2287180 ) M2M3_PR ;
+ - io_out[37] ( PIN io_out[37] ) ( mprj io_out[37] ) + USE SIGNAL
+ + ROUTED met3 ( 1380 96900 0 ) ( 17710 * )
+ NEW met2 ( 17710 96900 ) ( * 103190 )
+ NEW met1 ( 17710 103190 ) ( 2074830 * )
+ NEW met2 ( 2070920 2287180 0 ) ( 2074830 * )
+ NEW met2 ( 2074830 103190 ) ( * 2287180 )
+ NEW met2 ( 17710 96900 ) M2M3_PR
+ NEW met1 ( 17710 103190 ) M1M2_PR
+ NEW met1 ( 2074830 103190 ) M1M2_PR ;
+ - io_out[3] ( PIN io_out[3] ) ( mprj io_out[3] ) + USE SIGNAL
+ + ROUTED met1 ( 2889030 696830 ) ( 2898230 * )
+ NEW met2 ( 2898230 696660 ) ( * 696830 )
+ NEW met3 ( 2898230 696660 ) ( 2917780 * 0 )
+ NEW met2 ( 1265460 2289900 0 ) ( 1267070 * )
+ NEW met2 ( 1267070 2289900 ) ( * 2304690 )
+ NEW met2 ( 2889030 696830 ) ( * 2304690 )
+ NEW met1 ( 1267070 2304690 ) ( 2889030 * )
+ NEW met1 ( 1267070 2304690 ) M1M2_PR
+ NEW met1 ( 2889030 696830 ) M1M2_PR
+ NEW met1 ( 2898230 696830 ) M1M2_PR
+ NEW met2 ( 2898230 696660 ) M2M3_PR
+ NEW met1 ( 2889030 2304690 ) M1M2_PR ;
+ - io_out[4] ( PIN io_out[4] ) ( mprj io_out[4] ) + USE SIGNAL
+ + ROUTED met1 ( 2889950 896750 ) ( 2898690 * )
+ NEW met2 ( 2898690 895900 ) ( * 896750 )
+ NEW met3 ( 2898690 895900 ) ( 2917780 * 0 )
+ NEW met2 ( 1289380 2289900 0 ) ( 1290070 * )
+ NEW met2 ( 1290070 2289900 ) ( * 2305030 )
+ NEW met2 ( 2889950 896750 ) ( * 2305030 )
+ NEW met1 ( 1290070 2305030 ) ( 2889950 * )
+ NEW met1 ( 1290070 2305030 ) M1M2_PR
+ NEW met1 ( 2889950 896750 ) M1M2_PR
+ NEW met1 ( 2898690 896750 ) M1M2_PR
+ NEW met2 ( 2898690 895900 ) M2M3_PR
+ NEW met1 ( 2889950 2305030 ) M1M2_PR ;
+ - io_out[5] ( PIN io_out[5] ) ( mprj io_out[5] ) + USE SIGNAL
+ + ROUTED met3 ( 2894550 1095140 ) ( 2917780 * 0 )
+ NEW met2 ( 2894550 1095140 ) ( * 2312170 )
+ NEW met2 ( 1312840 2289900 0 ) ( 1314450 * )
+ NEW met2 ( 1314450 2289900 ) ( * 2312170 )
+ NEW met1 ( 1314450 2312170 ) ( 2894550 * )
+ NEW met2 ( 2894550 1095140 ) M2M3_PR
+ NEW met1 ( 2894550 2312170 ) M1M2_PR
+ NEW met1 ( 1314450 2312170 ) M1M2_PR ;
+ - io_out[6] ( PIN io_out[6] ) ( mprj io_out[6] ) + USE SIGNAL
+ + ROUTED met2 ( 2121750 1296930 ) ( * 2299930 )
+ NEW met2 ( 2899150 1294380 ) ( * 1296930 )
+ NEW met3 ( 2899150 1294380 ) ( 2917780 * 0 )
+ NEW met2 ( 1336760 2289900 0 ) ( 1337450 * )
+ NEW met2 ( 1337450 2289900 ) ( * 2299930 )
+ NEW met1 ( 2121750 1296930 ) ( 2899150 * )
+ NEW met1 ( 1337450 2299930 ) ( 2121750 * )
+ NEW met1 ( 2121750 1296930 ) M1M2_PR
+ NEW met1 ( 2121750 2299930 ) M1M2_PR
+ NEW met1 ( 2899150 1296930 ) M1M2_PR
+ NEW met2 ( 2899150 1294380 ) M2M3_PR
+ NEW met1 ( 1337450 2299930 ) M1M2_PR ;
+ - io_out[7] ( PIN io_out[7] ) ( mprj io_out[7] ) + USE SIGNAL
+ + ROUTED met3 ( 2895010 1560260 ) ( 2917780 * 0 )
+ NEW met2 ( 1360220 2289900 0 ) ( 1361830 * )
+ NEW met2 ( 1361830 2289900 ) ( * 2312510 )
+ NEW met2 ( 2895010 1560260 ) ( * 2312510 )
+ NEW met1 ( 1361830 2312510 ) ( 2895010 * )
+ NEW met1 ( 1361830 2312510 ) M1M2_PR
+ NEW met2 ( 2895010 1560260 ) M2M3_PR
+ NEW met1 ( 2895010 2312510 ) M1M2_PR ;
+ - io_out[8] ( PIN io_out[8] ) ( mprj io_out[8] ) + USE SIGNAL
+ + ROUTED met2 ( 2900990 1825460 ) ( * 1828350 )
+ NEW met3 ( 2900990 1825460 ) ( 2917780 * 0 )
+ NEW met2 ( 1384140 2289900 0 ) ( 1385290 * )
+ NEW met2 ( 1385290 2289900 ) ( * 2300950 )
+ NEW met2 ( 2128650 1828350 ) ( * 2300950 )
+ NEW met1 ( 2128650 1828350 ) ( 2900990 * )
+ NEW met1 ( 1385290 2300950 ) ( 2128650 * )
+ NEW met1 ( 2128650 1828350 ) M1M2_PR
+ NEW met1 ( 2900990 1828350 ) M1M2_PR
+ NEW met2 ( 2900990 1825460 ) M2M3_PR
+ NEW met1 ( 1385290 2300950 ) M1M2_PR
+ NEW met1 ( 2128650 2300950 ) M1M2_PR ;
+ - io_out[9] ( PIN io_out[9] ) ( mprj io_out[9] ) + USE SIGNAL
+ + ROUTED met2 ( 2142450 2097290 ) ( * 2301630 )
+ NEW met2 ( 2900070 2091340 ) ( * 2097290 )
+ NEW met3 ( 2900070 2091340 ) ( 2917780 * 0 )
+ NEW met2 ( 1407370 2289900 ) ( 1407600 * 0 )
+ NEW met2 ( 1407370 2289900 ) ( * 2301630 )
+ NEW met1 ( 2142450 2097290 ) ( 2900070 * )
+ NEW met1 ( 1407370 2301630 ) ( 2142450 * )
+ NEW met1 ( 2142450 2097290 ) M1M2_PR
+ NEW met1 ( 2142450 2301630 ) M1M2_PR
+ NEW met1 ( 2900070 2097290 ) M1M2_PR
+ NEW met2 ( 2900070 2091340 ) M2M3_PR
+ NEW met1 ( 1407370 2301630 ) M1M2_PR ;
+ - la_data_in[0] ( PIN la_data_in[0] ) ( mprj la_data_in[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1367810 1688780 ) ( 1368890 * )
+ NEW met2 ( 1368890 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1367810 81090 ) ( * 1688780 )
+ NEW met2 ( 628130 1700 ) ( 629510 * 0 )
+ NEW met2 ( 628130 1700 ) ( * 81090 )
+ NEW met1 ( 628130 81090 ) ( 1367810 * )
+ NEW met1 ( 1367810 81090 ) M1M2_PR
+ NEW met1 ( 628130 81090 ) M1M2_PR ;
+ - la_data_in[100] ( PIN la_data_in[100] ) ( mprj la_data_in[100] ) + USE SIGNAL
+ + ROUTED met2 ( 2402810 1700 0 ) ( * 57630 )
+ NEW met2 ( 1912450 57630 ) ( * 1580100 )
+ NEW met2 ( 1912450 1580100 ) ( 1913370 * )
+ NEW met2 ( 1913370 1688780 ) ( 1916750 * )
+ NEW met2 ( 1916750 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1913370 1580100 ) ( * 1688780 )
+ NEW met1 ( 1912450 57630 ) ( 2402810 * )
+ NEW met1 ( 2402810 57630 ) M1M2_PR
+ NEW met1 ( 1912450 57630 ) M1M2_PR ;
+ - la_data_in[101] ( PIN la_data_in[101] ) ( mprj la_data_in[101] ) + USE SIGNAL
+ + ROUTED met2 ( 1919810 57970 ) ( * 1580100 )
+ NEW met2 ( 1919810 1580100 ) ( 1922110 * )
+ NEW met2 ( 1922110 1688780 ) ( 1922270 * )
+ NEW met2 ( 1922270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1922110 1580100 ) ( * 1688780 )
+ NEW met2 ( 2420290 1700 0 ) ( * 57970 )
+ NEW met1 ( 1919810 57970 ) ( 2420290 * )
+ NEW met1 ( 1919810 57970 ) M1M2_PR
+ NEW met1 ( 2420290 57970 ) M1M2_PR ;
+ - la_data_in[102] ( PIN la_data_in[102] ) ( mprj la_data_in[102] ) + USE SIGNAL
+ + ROUTED met2 ( 2435930 1700 ) ( 2438230 * 0 )
+ NEW met2 ( 1926710 1688780 ) ( 1927790 * )
+ NEW met2 ( 1927790 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1926710 62050 ) ( * 1688780 )
+ NEW met2 ( 2435930 1700 ) ( * 62050 )
+ NEW met1 ( 1926710 62050 ) ( 2435930 * )
+ NEW met1 ( 1926710 62050 ) M1M2_PR
+ NEW met1 ( 2435930 62050 ) M1M2_PR ;
+ - la_data_in[103] ( PIN la_data_in[103] ) ( mprj la_data_in[103] ) + USE SIGNAL
+ + ROUTED met2 ( 1932690 1688780 ) ( 1933310 * )
+ NEW met2 ( 1933310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1932690 61710 ) ( * 1688780 )
+ NEW met2 ( 2453870 1700 ) ( 2455710 * 0 )
+ NEW met2 ( 2453870 1700 ) ( * 16830 )
+ NEW met1 ( 2449730 16830 ) ( 2453870 * )
+ NEW met1 ( 1932690 61710 ) ( 2449730 * )
+ NEW met2 ( 2449730 16830 ) ( * 61710 )
+ NEW met1 ( 1932690 61710 ) M1M2_PR
+ NEW met1 ( 2453870 16830 ) M1M2_PR
+ NEW met1 ( 2449730 16830 ) M1M2_PR
+ NEW met1 ( 2449730 61710 ) M1M2_PR ;
+ - la_data_in[104] ( PIN la_data_in[104] ) ( mprj la_data_in[104] ) + USE SIGNAL
+ + ROUTED met1 ( 1933150 1652570 ) ( 1938670 * )
+ NEW met2 ( 1933150 60690 ) ( * 1652570 )
+ NEW met2 ( 1938670 1688780 ) ( 1938830 * )
+ NEW met2 ( 1938830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1938670 1652570 ) ( * 1688780 )
+ NEW met1 ( 1933150 60690 ) ( 2473650 * )
+ NEW met2 ( 2473650 1700 0 ) ( * 60690 )
+ NEW met1 ( 1933150 1652570 ) M1M2_PR
+ NEW met1 ( 1938670 1652570 ) M1M2_PR
+ NEW met1 ( 1933150 60690 ) M1M2_PR
+ NEW met1 ( 2473650 60690 ) M1M2_PR ;
+ - la_data_in[105] ( PIN la_data_in[105] ) ( mprj la_data_in[105] ) + USE SIGNAL
+ + ROUTED met1 ( 1939130 1683510 ) ( 1944190 * )
+ NEW met2 ( 1944190 1683510 ) ( * 1688780 )
+ NEW met2 ( 1944190 1688780 ) ( 1944350 * )
+ NEW met2 ( 1944350 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1939130 23290 ) ( * 1683510 )
+ NEW met2 ( 2491130 1700 0 ) ( * 23290 )
+ NEW met1 ( 1939130 23290 ) ( 2491130 * )
+ NEW met1 ( 1939130 23290 ) M1M2_PR
+ NEW met1 ( 1939130 1683510 ) M1M2_PR
+ NEW met1 ( 1944190 1683510 ) M1M2_PR
+ NEW met1 ( 2491130 23290 ) M1M2_PR ;
+ - la_data_in[106] ( PIN la_data_in[106] ) ( mprj la_data_in[106] ) + USE SIGNAL
+ + ROUTED met1 ( 1946030 1652570 ) ( 1949710 * )
+ NEW met2 ( 2509070 1700 0 ) ( * 23630 )
+ NEW met2 ( 1946030 23630 ) ( * 1652570 )
+ NEW met2 ( 1949710 1688780 ) ( 1949870 * )
+ NEW met2 ( 1949870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1949710 1652570 ) ( * 1688780 )
+ NEW met1 ( 1946030 23630 ) ( 2509070 * )
+ NEW met1 ( 1946030 23630 ) M1M2_PR
+ NEW met1 ( 1946030 1652570 ) M1M2_PR
+ NEW met1 ( 1949710 1652570 ) M1M2_PR
+ NEW met1 ( 2509070 23630 ) M1M2_PR ;
+ - la_data_in[107] ( PIN la_data_in[107] ) ( mprj la_data_in[107] ) + USE SIGNAL
+ + ROUTED met2 ( 2527010 1700 0 ) ( * 27370 )
+ NEW met1 ( 1952930 1689290 ) ( 1955390 * )
+ NEW met2 ( 1955390 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1952930 27370 ) ( * 1689290 )
+ NEW met1 ( 1952930 27370 ) ( 2527010 * )
+ NEW met1 ( 1952930 27370 ) M1M2_PR
+ NEW met1 ( 2527010 27370 ) M1M2_PR
+ NEW met1 ( 1952930 1689290 ) M1M2_PR
+ NEW met1 ( 1955390 1689290 ) M1M2_PR ;
+ - la_data_in[108] ( PIN la_data_in[108] ) ( mprj la_data_in[108] ) + USE SIGNAL
+ + ROUTED met2 ( 2544490 1700 0 ) ( * 27030 )
+ NEW met2 ( 1960290 1688780 ) ( 1960450 * )
+ NEW met2 ( 1960450 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1960290 27030 ) ( * 1688780 )
+ NEW met1 ( 1960290 27030 ) ( 2544490 * )
+ NEW met1 ( 1960290 27030 ) M1M2_PR
+ NEW met1 ( 2544490 27030 ) M1M2_PR ;
+ - la_data_in[109] ( PIN la_data_in[109] ) ( mprj la_data_in[109] ) + USE SIGNAL
+ + ROUTED met1 ( 1959830 1688950 ) ( 1965970 * )
+ NEW met2 ( 1965970 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1959830 26690 ) ( * 1688950 )
+ NEW met2 ( 2562430 1700 0 ) ( * 26690 )
+ NEW met1 ( 1959830 26690 ) ( 2562430 * )
+ NEW met1 ( 1959830 26690 ) M1M2_PR
+ NEW met1 ( 1959830 1688950 ) M1M2_PR
+ NEW met1 ( 1965970 1688950 ) M1M2_PR
+ NEW met1 ( 2562430 26690 ) M1M2_PR ;
+ - la_data_in[10] ( PIN la_data_in[10] ) ( mprj la_data_in[10] ) + USE SIGNAL
+ + ROUTED met2 ( 806610 1700 0 ) ( * 81770 )
+ NEW met1 ( 806610 81770 ) ( 1423010 * )
+ NEW met2 ( 1423010 1688780 ) ( 1423630 * )
+ NEW met2 ( 1423630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1423010 81770 ) ( * 1688780 )
+ NEW met1 ( 806610 81770 ) M1M2_PR
+ NEW met1 ( 1423010 81770 ) M1M2_PR ;
+ - la_data_in[110] ( PIN la_data_in[110] ) ( mprj la_data_in[110] ) + USE SIGNAL
+ + ROUTED met2 ( 2579910 1700 0 ) ( * 26350 )
+ NEW met1 ( 1966730 26350 ) ( 2579910 * )
+ NEW met1 ( 1966730 1688950 ) ( 1971490 * )
+ NEW met2 ( 1971490 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1966730 26350 ) ( * 1688950 )
+ NEW met1 ( 1966730 26350 ) M1M2_PR
+ NEW met1 ( 2579910 26350 ) M1M2_PR
+ NEW met1 ( 1966730 1688950 ) M1M2_PR
+ NEW met1 ( 1971490 1688950 ) M1M2_PR ;
+ - la_data_in[111] ( PIN la_data_in[111] ) ( mprj la_data_in[111] ) + USE SIGNAL
+ + ROUTED met2 ( 2597850 1700 0 ) ( * 26010 )
+ NEW met1 ( 1973630 26010 ) ( 2597850 * )
+ NEW met1 ( 1973630 1683510 ) ( 1976850 * )
+ NEW met2 ( 1976850 1683510 ) ( * 1688780 )
+ NEW met2 ( 1976850 1688780 ) ( 1977010 * )
+ NEW met2 ( 1977010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1973630 26010 ) ( * 1683510 )
+ NEW met1 ( 2597850 26010 ) M1M2_PR
+ NEW met1 ( 1973630 26010 ) M1M2_PR
+ NEW met1 ( 1973630 1683510 ) M1M2_PR
+ NEW met1 ( 1976850 1683510 ) M1M2_PR ;
+ - la_data_in[112] ( PIN la_data_in[112] ) ( mprj la_data_in[112] ) + USE SIGNAL
+ + ROUTED met2 ( 2615330 1700 0 ) ( * 25670 )
+ NEW met1 ( 1980530 1652910 ) ( 1982370 * )
+ NEW met1 ( 1980530 25670 ) ( 2615330 * )
+ NEW met2 ( 1980530 25670 ) ( * 1652910 )
+ NEW met2 ( 1982370 1688780 ) ( 1982530 * )
+ NEW met2 ( 1982530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1982370 1652910 ) ( * 1688780 )
+ NEW met1 ( 2615330 25670 ) M1M2_PR
+ NEW met1 ( 1980530 25670 ) M1M2_PR
+ NEW met1 ( 1980530 1652910 ) M1M2_PR
+ NEW met1 ( 1982370 1652910 ) M1M2_PR ;
+ - la_data_in[113] ( PIN la_data_in[113] ) ( mprj la_data_in[113] ) + USE SIGNAL
+ + ROUTED met2 ( 2633270 1700 0 ) ( * 25330 )
+ NEW met1 ( 1987430 25330 ) ( 2633270 * )
+ NEW met2 ( 1987430 1688780 ) ( 1988050 * )
+ NEW met2 ( 1988050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1987430 25330 ) ( * 1688780 )
+ NEW met1 ( 2633270 25330 ) M1M2_PR
+ NEW met1 ( 1987430 25330 ) M1M2_PR ;
+ - la_data_in[114] ( PIN la_data_in[114] ) ( mprj la_data_in[114] ) + USE SIGNAL
+ + ROUTED met1 ( 1987890 1652570 ) ( 1993410 * )
+ NEW met2 ( 2650750 1700 0 ) ( * 24140 )
+ NEW met3 ( 1987890 24140 ) ( 2650750 * )
+ NEW met2 ( 1987890 24140 ) ( * 1652570 )
+ NEW met2 ( 1993410 1688780 ) ( 1993570 * )
+ NEW met2 ( 1993570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1993410 1652570 ) ( * 1688780 )
+ NEW met2 ( 1987890 24140 ) M2M3_PR
+ NEW met1 ( 1987890 1652570 ) M1M2_PR
+ NEW met1 ( 1993410 1652570 ) M1M2_PR
+ NEW met2 ( 2650750 24140 ) M2M3_PR ;
+ - la_data_in[115] ( PIN la_data_in[115] ) ( mprj la_data_in[115] ) + USE SIGNAL
+ + ROUTED met2 ( 2668690 1700 0 ) ( * 24990 )
+ NEW met1 ( 1994330 24990 ) ( 2668690 * )
+ NEW met1 ( 1994330 1688950 ) ( 1999090 * )
+ NEW met2 ( 1999090 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1994330 24990 ) ( * 1688950 )
+ NEW met1 ( 1994330 24990 ) M1M2_PR
+ NEW met1 ( 2668690 24990 ) M1M2_PR
+ NEW met1 ( 1994330 1688950 ) M1M2_PR
+ NEW met1 ( 1999090 1688950 ) M1M2_PR ;
+ - la_data_in[116] ( PIN la_data_in[116] ) ( mprj la_data_in[116] ) + USE SIGNAL
+ + ROUTED met2 ( 2686170 1700 0 ) ( * 24650 )
+ NEW met1 ( 2001230 24650 ) ( 2686170 * )
+ NEW met1 ( 2001230 1683510 ) ( 2004450 * )
+ NEW met2 ( 2004450 1683510 ) ( * 1688780 )
+ NEW met2 ( 2004450 1688780 ) ( 2004610 * )
+ NEW met2 ( 2004610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2001230 24650 ) ( * 1683510 )
+ NEW met1 ( 2001230 24650 ) M1M2_PR
+ NEW met1 ( 2686170 24650 ) M1M2_PR
+ NEW met1 ( 2001230 1683510 ) M1M2_PR
+ NEW met1 ( 2004450 1683510 ) M1M2_PR ;
+ - la_data_in[117] ( PIN la_data_in[117] ) ( mprj la_data_in[117] ) + USE SIGNAL
+ + ROUTED met2 ( 2704110 1700 0 ) ( * 24310 )
+ NEW met1 ( 2008130 24310 ) ( 2704110 * )
+ NEW met1 ( 2008130 1688270 ) ( * 1688610 )
+ NEW met1 ( 2008130 1688610 ) ( 2010130 * )
+ NEW met1 ( 2010130 1688610 ) ( * 1689290 )
+ NEW met2 ( 2010130 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 2008130 24310 ) ( * 1688270 )
+ NEW met1 ( 2704110 24310 ) M1M2_PR
+ NEW met1 ( 2008130 24310 ) M1M2_PR
+ NEW met1 ( 2008130 1688270 ) M1M2_PR
+ NEW met1 ( 2010130 1689290 ) M1M2_PR ;
+ - la_data_in[118] ( PIN la_data_in[118] ) ( mprj la_data_in[118] ) + USE SIGNAL
+ + ROUTED met2 ( 2722050 1700 0 ) ( * 23970 )
+ NEW met2 ( 2015030 1688780 ) ( 2015650 * )
+ NEW met2 ( 2015650 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2015030 23970 ) ( * 1688780 )
+ NEW met1 ( 2015030 23970 ) ( 2722050 * )
+ NEW met1 ( 2015030 23970 ) M1M2_PR
+ NEW met1 ( 2722050 23970 ) M1M2_PR ;
+ - la_data_in[119] ( PIN la_data_in[119] ) ( mprj la_data_in[119] ) + USE SIGNAL
+ + ROUTED met1 ( 2015950 1652570 ) ( 2020550 * )
+ NEW met2 ( 2015950 58990 ) ( * 1652570 )
+ NEW met2 ( 2020550 1688780 ) ( 2020710 * )
+ NEW met2 ( 2020710 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2020550 1652570 ) ( * 1688780 )
+ NEW met1 ( 2015950 58990 ) ( 2739530 * )
+ NEW met2 ( 2739530 1700 0 ) ( * 58990 )
+ NEW met1 ( 2015950 1652570 ) M1M2_PR
+ NEW met1 ( 2020550 1652570 ) M1M2_PR
+ NEW met1 ( 2015950 58990 ) M1M2_PR
+ NEW met1 ( 2739530 58990 ) M1M2_PR ;
+ - la_data_in[11] ( PIN la_data_in[11] ) ( mprj la_data_in[11] ) + USE SIGNAL
+ + ROUTED met2 ( 822250 1700 ) ( 824550 * 0 )
+ NEW met2 ( 822250 1700 ) ( * 82110 )
+ NEW met1 ( 822250 82110 ) ( 1429450 * )
+ NEW met2 ( 1429220 1688780 ) ( 1429450 * )
+ NEW met2 ( 1429220 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1429450 82110 ) ( * 1688780 )
+ NEW met1 ( 822250 82110 ) M1M2_PR
+ NEW met1 ( 1429450 82110 ) M1M2_PR ;
+ - la_data_in[120] ( PIN la_data_in[120] ) ( mprj la_data_in[120] ) + USE SIGNAL
+ + ROUTED met2 ( 2023310 1688780 ) ( 2026230 * )
+ NEW met2 ( 2026230 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2023310 58650 ) ( * 1688780 )
+ NEW met2 ( 2755170 1700 ) ( 2757470 * 0 )
+ NEW met1 ( 2023310 58650 ) ( 2755170 * )
+ NEW met2 ( 2755170 1700 ) ( * 58650 )
+ NEW met1 ( 2023310 58650 ) M1M2_PR
+ NEW met1 ( 2755170 58650 ) M1M2_PR ;
+ - la_data_in[121] ( PIN la_data_in[121] ) ( mprj la_data_in[121] ) + USE SIGNAL
+ + ROUTED met1 ( 2029750 1652570 ) ( 2031590 * )
+ NEW met2 ( 2029750 65450 ) ( * 1652570 )
+ NEW met2 ( 2031590 1688780 ) ( 2031750 * )
+ NEW met2 ( 2031750 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2031590 1652570 ) ( * 1688780 )
+ NEW met2 ( 2774030 1700 ) ( 2774950 * 0 )
+ NEW met1 ( 2029750 65450 ) ( 2774030 * )
+ NEW met2 ( 2774030 1700 ) ( * 65450 )
+ NEW met1 ( 2029750 1652570 ) M1M2_PR
+ NEW met1 ( 2031590 1652570 ) M1M2_PR
+ NEW met1 ( 2029750 65450 ) M1M2_PR
+ NEW met1 ( 2774030 65450 ) M1M2_PR ;
+ - la_data_in[122] ( PIN la_data_in[122] ) ( mprj la_data_in[122] ) + USE SIGNAL
+ + ROUTED met2 ( 2792890 1700 0 ) ( * 32130 )
+ NEW met2 ( 2035730 1688780 ) ( 2037270 * )
+ NEW met2 ( 2037270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2035730 32130 ) ( * 1688780 )
+ NEW met1 ( 2035730 32130 ) ( 2792890 * )
+ NEW met1 ( 2035730 32130 ) M1M2_PR
+ NEW met1 ( 2792890 32130 ) M1M2_PR ;
+ - la_data_in[123] ( PIN la_data_in[123] ) ( mprj la_data_in[123] ) + USE SIGNAL
+ + ROUTED met2 ( 2810370 1700 0 ) ( * 31790 )
+ NEW met2 ( 2042630 1688780 ) ( 2042790 * )
+ NEW met2 ( 2042790 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2042630 31790 ) ( * 1688780 )
+ NEW met1 ( 2042630 31790 ) ( 2810370 * )
+ NEW met1 ( 2042630 31790 ) M1M2_PR
+ NEW met1 ( 2810370 31790 ) M1M2_PR ;
+ - la_data_in[124] ( PIN la_data_in[124] ) ( mprj la_data_in[124] ) + USE SIGNAL
+ + ROUTED met1 ( 2043090 1652570 ) ( 2048150 * )
+ NEW met2 ( 2828310 1700 0 ) ( * 31450 )
+ NEW met2 ( 2043090 31450 ) ( * 1652570 )
+ NEW met2 ( 2048150 1688780 ) ( 2048310 * )
+ NEW met2 ( 2048310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2048150 1652570 ) ( * 1688780 )
+ NEW met1 ( 2043090 31450 ) ( 2828310 * )
+ NEW met1 ( 2043090 31450 ) M1M2_PR
+ NEW met1 ( 2043090 1652570 ) M1M2_PR
+ NEW met1 ( 2048150 1652570 ) M1M2_PR
+ NEW met1 ( 2828310 31450 ) M1M2_PR ;
+ - la_data_in[125] ( PIN la_data_in[125] ) ( mprj la_data_in[125] ) + USE SIGNAL
+ + ROUTED met1 ( 2049530 1689290 ) ( 2053830 * )
+ NEW met2 ( 2053830 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 2049530 31110 ) ( * 1689290 )
+ NEW met2 ( 2845790 1700 0 ) ( * 31110 )
+ NEW met1 ( 2049530 31110 ) ( 2845790 * )
+ NEW met1 ( 2049530 31110 ) M1M2_PR
+ NEW met1 ( 2049530 1689290 ) M1M2_PR
+ NEW met1 ( 2053830 1689290 ) M1M2_PR
+ NEW met1 ( 2845790 31110 ) M1M2_PR ;
+ - la_data_in[126] ( PIN la_data_in[126] ) ( mprj la_data_in[126] ) + USE SIGNAL
+ + ROUTED met2 ( 2056890 30940 ) ( * 1676700 )
+ NEW met2 ( 2056890 1676700 ) ( 2058270 * )
+ NEW met2 ( 2058270 1676700 ) ( * 1688780 )
+ NEW met2 ( 2058270 1688780 ) ( 2059350 * )
+ NEW met2 ( 2059350 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2863730 1700 0 ) ( * 30940 )
+ NEW met3 ( 2056890 30940 ) ( 2863730 * )
+ NEW met2 ( 2056890 30940 ) M2M3_PR
+ NEW met2 ( 2863730 30940 ) M2M3_PR ;
+ - la_data_in[127] ( PIN la_data_in[127] ) ( mprj la_data_in[127] ) + USE SIGNAL
+ + ROUTED met2 ( 2881670 1700 0 ) ( * 30770 )
+ NEW met1 ( 2063330 30770 ) ( 2881670 * )
+ NEW met2 ( 2063330 1688780 ) ( 2064870 * )
+ NEW met2 ( 2064870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2063330 30770 ) ( * 1688780 )
+ NEW met1 ( 2063330 30770 ) M1M2_PR
+ NEW met1 ( 2881670 30770 ) M1M2_PR ;
+ - la_data_in[12] ( PIN la_data_in[12] ) ( mprj la_data_in[12] ) + USE SIGNAL
+ + ROUTED met2 ( 842030 1700 0 ) ( * 82450 )
+ NEW met1 ( 842030 82450 ) ( 1429910 * )
+ NEW met2 ( 1429910 1688780 ) ( 1434670 * )
+ NEW met2 ( 1434670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1429910 82450 ) ( * 1688780 )
+ NEW met1 ( 842030 82450 ) M1M2_PR
+ NEW met1 ( 1429910 82450 ) M1M2_PR ;
+ - la_data_in[13] ( PIN la_data_in[13] ) ( mprj la_data_in[13] ) + USE SIGNAL
+ + ROUTED met2 ( 859970 1700 0 ) ( * 82790 )
+ NEW met2 ( 1436810 1688780 ) ( 1440190 * )
+ NEW met2 ( 1440190 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1436810 82790 ) ( * 1688780 )
+ NEW met1 ( 859970 82790 ) ( 1436810 * )
+ NEW met1 ( 859970 82790 ) M1M2_PR
+ NEW met1 ( 1436810 82790 ) M1M2_PR ;
+ - la_data_in[14] ( PIN la_data_in[14] ) ( mprj la_data_in[14] ) + USE SIGNAL
+ + ROUTED met2 ( 877450 1700 0 ) ( * 23290 )
+ NEW met2 ( 1445550 1677730 ) ( * 1688780 )
+ NEW met2 ( 1445550 1688780 ) ( 1445710 * )
+ NEW met2 ( 1445710 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 877450 23290 ) ( 1294210 * )
+ NEW met2 ( 1294210 23290 ) ( * 1677730 )
+ NEW met1 ( 1294210 1677730 ) ( 1445550 * )
+ NEW met1 ( 877450 23290 ) M1M2_PR
+ NEW met1 ( 1445550 1677730 ) M1M2_PR
+ NEW met1 ( 1294210 23290 ) M1M2_PR
+ NEW met1 ( 1294210 1677730 ) M1M2_PR ;
+ - la_data_in[15] ( PIN la_data_in[15] ) ( mprj la_data_in[15] ) + USE SIGNAL
+ + ROUTED met2 ( 895390 1700 0 ) ( * 22950 )
+ NEW met2 ( 1451070 1678750 ) ( * 1688780 )
+ NEW met2 ( 1451070 1688780 ) ( 1451230 * )
+ NEW met2 ( 1451230 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 895390 22950 ) ( 1293750 * )
+ NEW met2 ( 1293750 22950 ) ( * 1678750 )
+ NEW met1 ( 1293750 1678750 ) ( 1451070 * )
+ NEW met1 ( 895390 22950 ) M1M2_PR
+ NEW met1 ( 1451070 1678750 ) M1M2_PR
+ NEW met1 ( 1293750 22950 ) M1M2_PR
+ NEW met1 ( 1293750 1678750 ) M1M2_PR ;
+ - la_data_in[16] ( PIN la_data_in[16] ) ( mprj la_data_in[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1456590 1688780 ) ( 1456750 * )
+ NEW met2 ( 1456750 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 912870 1700 0 ) ( * 24650 )
+ NEW met1 ( 912870 24650 ) ( 1456590 * )
+ NEW met2 ( 1456590 24650 ) ( * 1688780 )
+ NEW met1 ( 912870 24650 ) M1M2_PR
+ NEW met1 ( 1456590 24650 ) M1M2_PR ;
+ - la_data_in[17] ( PIN la_data_in[17] ) ( mprj la_data_in[17] ) + USE SIGNAL
+ + ROUTED met1 ( 1457050 1649510 ) ( 1462110 * )
+ NEW met2 ( 1462110 1688780 ) ( 1462270 * )
+ NEW met2 ( 1462270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1462110 1649510 ) ( * 1688780 )
+ NEW met2 ( 930810 1700 0 ) ( * 24990 )
+ NEW met1 ( 930810 24990 ) ( 1457050 * )
+ NEW met2 ( 1457050 24990 ) ( * 1649510 )
+ NEW met1 ( 1457050 1649510 ) M1M2_PR
+ NEW met1 ( 1462110 1649510 ) M1M2_PR
+ NEW met1 ( 930810 24990 ) M1M2_PR
+ NEW met1 ( 1457050 24990 ) M1M2_PR ;
+ - la_data_in[18] ( PIN la_data_in[18] ) ( mprj la_data_in[18] ) + USE SIGNAL
+ + ROUTED met1 ( 1463030 1688950 ) ( 1467790 * )
+ NEW met2 ( 1467790 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1463030 25330 ) ( * 1688950 )
+ NEW met2 ( 948750 1700 0 ) ( * 25330 )
+ NEW met1 ( 948750 25330 ) ( 1463030 * )
+ NEW met1 ( 1463030 25330 ) M1M2_PR
+ NEW met1 ( 1463030 1688950 ) M1M2_PR
+ NEW met1 ( 1467790 1688950 ) M1M2_PR
+ NEW met1 ( 948750 25330 ) M1M2_PR ;
+ - la_data_in[19] ( PIN la_data_in[19] ) ( mprj la_data_in[19] ) + USE SIGNAL
+ + ROUTED met2 ( 966230 1700 0 ) ( * 25670 )
+ NEW met1 ( 1469930 1683510 ) ( 1473150 * )
+ NEW met2 ( 1473150 1683510 ) ( * 1688780 )
+ NEW met2 ( 1473150 1688780 ) ( 1473310 * )
+ NEW met2 ( 1473310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1469930 25670 ) ( * 1683510 )
+ NEW met1 ( 966230 25670 ) ( 1469930 * )
+ NEW met1 ( 966230 25670 ) M1M2_PR
+ NEW met1 ( 1469930 25670 ) M1M2_PR
+ NEW met1 ( 1469930 1683510 ) M1M2_PR
+ NEW met1 ( 1473150 1683510 ) M1M2_PR ;
+ - la_data_in[1] ( PIN la_data_in[1] ) ( mprj la_data_in[1] ) + USE SIGNAL
+ + ROUTED met2 ( 1373330 1688780 ) ( 1374410 * )
+ NEW met2 ( 1374410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1373330 23970 ) ( * 1688780 )
+ NEW met2 ( 646990 1700 0 ) ( * 23970 )
+ NEW met1 ( 646990 23970 ) ( 1373330 * )
+ NEW met1 ( 1373330 23970 ) M1M2_PR
+ NEW met1 ( 646990 23970 ) M1M2_PR ;
+ - la_data_in[20] ( PIN la_data_in[20] ) ( mprj la_data_in[20] ) + USE SIGNAL
+ + ROUTED met2 ( 984170 1700 0 ) ( * 26010 )
+ NEW met2 ( 1476830 1688780 ) ( 1478370 * )
+ NEW met2 ( 1478370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1476830 26010 ) ( * 1688780 )
+ NEW met1 ( 984170 26010 ) ( 1476830 * )
+ NEW met1 ( 984170 26010 ) M1M2_PR
+ NEW met1 ( 1476830 26010 ) M1M2_PR ;
+ - la_data_in[21] ( PIN la_data_in[21] ) ( mprj la_data_in[21] ) + USE SIGNAL
+ + ROUTED met2 ( 1001650 1700 0 ) ( * 26350 )
+ NEW met2 ( 1484190 82800 ) ( 1484650 * )
+ NEW met2 ( 1484650 26350 ) ( * 82800 )
+ NEW met2 ( 1483960 1688780 ) ( 1484190 * )
+ NEW met2 ( 1483960 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1484190 82800 ) ( * 1688780 )
+ NEW met1 ( 1001650 26350 ) ( 1484650 * )
+ NEW met1 ( 1001650 26350 ) M1M2_PR
+ NEW met1 ( 1484650 26350 ) M1M2_PR ;
+ - la_data_in[22] ( PIN la_data_in[22] ) ( mprj la_data_in[22] ) + USE SIGNAL
+ + ROUTED met2 ( 1483270 26690 ) ( * 27540 )
+ NEW met2 ( 1019590 1700 0 ) ( * 26690 )
+ NEW met2 ( 1483270 27540 ) ( 1483730 * )
+ NEW met1 ( 1483730 1645770 ) ( 1489250 * )
+ NEW met2 ( 1483730 27540 ) ( * 1645770 )
+ NEW met2 ( 1489250 1688780 ) ( 1489410 * )
+ NEW met2 ( 1489410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1489250 1645770 ) ( * 1688780 )
+ NEW met1 ( 1019590 26690 ) ( 1483270 * )
+ NEW met1 ( 1483270 26690 ) M1M2_PR
+ NEW met1 ( 1019590 26690 ) M1M2_PR
+ NEW met1 ( 1483730 1645770 ) M1M2_PR
+ NEW met1 ( 1489250 1645770 ) M1M2_PR ;
+ - la_data_in[23] ( PIN la_data_in[23] ) ( mprj la_data_in[23] ) + USE SIGNAL
+ + ROUTED met2 ( 1037070 1700 0 ) ( * 24140 )
+ NEW met3 ( 1037070 24140 ) ( 1386900 * )
+ NEW met3 ( 1386900 24140 ) ( * 24820 )
+ NEW met2 ( 1490170 1652060 ) ( 1490630 * )
+ NEW met2 ( 1490170 1652060 ) ( * 1652740 )
+ NEW met2 ( 1490170 1652740 ) ( 1491090 * )
+ NEW met2 ( 1490630 24820 ) ( * 1652060 )
+ NEW met1 ( 1491090 1688270 ) ( 1494930 * )
+ NEW met1 ( 1494930 1688270 ) ( * 1689290 )
+ NEW met2 ( 1494930 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1491090 1652740 ) ( * 1688270 )
+ NEW met3 ( 1386900 24820 ) ( 1490630 * )
+ NEW met2 ( 1037070 24140 ) M2M3_PR
+ NEW met2 ( 1490630 24820 ) M2M3_PR
+ NEW met1 ( 1491090 1688270 ) M1M2_PR
+ NEW met1 ( 1494930 1689290 ) M1M2_PR ;
+ - la_data_in[24] ( PIN la_data_in[24] ) ( mprj la_data_in[24] ) + USE SIGNAL
+ + ROUTED met2 ( 1055010 1700 0 ) ( * 27030 )
+ NEW met1 ( 1497530 1689290 ) ( 1500450 * )
+ NEW met2 ( 1500450 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1497530 27030 ) ( * 1689290 )
+ NEW met1 ( 1055010 27030 ) ( 1497530 * )
+ NEW met1 ( 1055010 27030 ) M1M2_PR
+ NEW met1 ( 1497530 27030 ) M1M2_PR
+ NEW met1 ( 1497530 1689290 ) M1M2_PR
+ NEW met1 ( 1500450 1689290 ) M1M2_PR ;
+ - la_data_in[25] ( PIN la_data_in[25] ) ( mprj la_data_in[25] ) + USE SIGNAL
+ + ROUTED met2 ( 1072490 1700 0 ) ( * 27370 )
+ NEW met2 ( 1504430 1689460 ) ( 1505970 * )
+ NEW met2 ( 1505970 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 1504430 27370 ) ( * 1689460 )
+ NEW met1 ( 1072490 27370 ) ( 1504430 * )
+ NEW met1 ( 1072490 27370 ) M1M2_PR
+ NEW met1 ( 1504430 27370 ) M1M2_PR ;
+ - la_data_in[26] ( PIN la_data_in[26] ) ( mprj la_data_in[26] ) + USE SIGNAL
+ + ROUTED met2 ( 1090430 1700 0 ) ( * 23630 )
+ NEW met2 ( 1511330 1688780 ) ( 1511490 * )
+ NEW met2 ( 1511490 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1511330 23630 ) ( * 1688780 )
+ NEW met1 ( 1090430 23630 ) ( 1511330 * )
+ NEW met1 ( 1090430 23630 ) M1M2_PR
+ NEW met1 ( 1511330 23630 ) M1M2_PR ;
+ - la_data_in[27] ( PIN la_data_in[27] ) ( mprj la_data_in[27] ) + USE SIGNAL
+ + ROUTED met2 ( 1105610 1700 ) ( 1107910 * 0 )
+ NEW met2 ( 1105610 1700 ) ( * 79050 )
+ NEW met1 ( 1105610 79050 ) ( 1512710 * )
+ NEW met2 ( 1512710 79050 ) ( * 1580100 )
+ NEW met2 ( 1512710 1580100 ) ( 1516850 * )
+ NEW met2 ( 1516850 1688780 ) ( 1517010 * )
+ NEW met2 ( 1517010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1516850 1580100 ) ( * 1688780 )
+ NEW met1 ( 1105610 79050 ) M1M2_PR
+ NEW met1 ( 1512710 79050 ) M1M2_PR ;
+ - la_data_in[28] ( PIN la_data_in[28] ) ( mprj la_data_in[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1125850 1700 0 ) ( * 78710 )
+ NEW met1 ( 1125850 78710 ) ( 1519610 * )
+ NEW met2 ( 1519610 78710 ) ( * 1580100 )
+ NEW met2 ( 1519610 1580100 ) ( 1522370 * )
+ NEW met2 ( 1522370 1688780 ) ( 1522530 * )
+ NEW met2 ( 1522530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1522370 1580100 ) ( * 1688780 )
+ NEW met1 ( 1125850 78710 ) M1M2_PR
+ NEW met1 ( 1519610 78710 ) M1M2_PR ;
+ - la_data_in[29] ( PIN la_data_in[29] ) ( mprj la_data_in[29] ) + USE SIGNAL
+ + ROUTED met2 ( 1141490 1700 ) ( 1143790 * 0 )
+ NEW met2 ( 1141490 1700 ) ( * 78370 )
+ NEW met1 ( 1141490 78370 ) ( 1526510 * )
+ NEW met2 ( 1526510 1688780 ) ( 1528050 * )
+ NEW met2 ( 1528050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1526510 78370 ) ( * 1688780 )
+ NEW met1 ( 1141490 78370 ) M1M2_PR
+ NEW met1 ( 1526510 78370 ) M1M2_PR ;
+ - la_data_in[2] ( PIN la_data_in[2] ) ( mprj la_data_in[2] ) + USE SIGNAL
+ + ROUTED met2 ( 664930 1700 0 ) ( * 24310 )
+ NEW met1 ( 1373790 1652570 ) ( 1379770 * )
+ NEW met2 ( 1373790 24310 ) ( * 1652570 )
+ NEW met2 ( 1379770 1688780 ) ( 1379930 * )
+ NEW met2 ( 1379930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1379770 1652570 ) ( * 1688780 )
+ NEW met1 ( 664930 24310 ) ( 1373790 * )
+ NEW met1 ( 664930 24310 ) M1M2_PR
+ NEW met1 ( 1373790 24310 ) M1M2_PR
+ NEW met1 ( 1373790 1652570 ) M1M2_PR
+ NEW met1 ( 1379770 1652570 ) M1M2_PR ;
+ - la_data_in[30] ( PIN la_data_in[30] ) ( mprj la_data_in[30] ) + USE SIGNAL
+ + ROUTED met2 ( 1161270 1700 0 ) ( * 29750 )
+ NEW met2 ( 1532490 1688780 ) ( 1533570 * )
+ NEW met2 ( 1533570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1532490 29750 ) ( * 1688780 )
+ NEW met1 ( 1161270 29750 ) ( 1290300 * )
+ NEW met1 ( 1290300 29070 ) ( * 29750 )
+ NEW met1 ( 1290300 29070 ) ( 1414500 * )
+ NEW met1 ( 1414500 29070 ) ( * 29750 )
+ NEW met1 ( 1414500 29750 ) ( 1532490 * )
+ NEW met1 ( 1161270 29750 ) M1M2_PR
+ NEW met1 ( 1532490 29750 ) M1M2_PR ;
+ - la_data_in[31] ( PIN la_data_in[31] ) ( mprj la_data_in[31] ) + USE SIGNAL
+ + ROUTED met2 ( 1179210 1700 0 ) ( * 31110 )
+ NEW met1 ( 1532030 1652230 ) ( 1538470 * )
+ NEW met2 ( 1532030 31110 ) ( * 1652230 )
+ NEW met2 ( 1538470 1688780 ) ( 1538630 * )
+ NEW met2 ( 1538630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1538470 1652230 ) ( * 1688780 )
+ NEW met1 ( 1179210 31110 ) ( 1532030 * )
+ NEW met1 ( 1179210 31110 ) M1M2_PR
+ NEW met1 ( 1532030 31110 ) M1M2_PR
+ NEW met1 ( 1532030 1652230 ) M1M2_PR
+ NEW met1 ( 1538470 1652230 ) M1M2_PR ;
+ - la_data_in[32] ( PIN la_data_in[32] ) ( mprj la_data_in[32] ) + USE SIGNAL
+ + ROUTED met1 ( 1538930 1683850 ) ( 1543990 * )
+ NEW met2 ( 1543990 1683850 ) ( * 1688780 )
+ NEW met2 ( 1543990 1688780 ) ( 1544150 * )
+ NEW met2 ( 1544150 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1538930 31790 ) ( * 1683850 )
+ NEW met2 ( 1196690 1700 0 ) ( * 31790 )
+ NEW met1 ( 1196690 31790 ) ( 1538930 * )
+ NEW met1 ( 1538930 31790 ) M1M2_PR
+ NEW met1 ( 1538930 1683850 ) M1M2_PR
+ NEW met1 ( 1543990 1683850 ) M1M2_PR
+ NEW met1 ( 1196690 31790 ) M1M2_PR ;
+ - la_data_in[33] ( PIN la_data_in[33] ) ( mprj la_data_in[33] ) + USE SIGNAL
+ + ROUTED met1 ( 1546290 1652570 ) ( 1549510 * )
+ NEW met2 ( 1546290 17510 ) ( * 1652570 )
+ NEW met2 ( 1549510 1688780 ) ( 1549670 * )
+ NEW met2 ( 1549670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1549510 1652570 ) ( * 1688780 )
+ NEW met2 ( 1214630 1700 0 ) ( * 17510 )
+ NEW met1 ( 1214630 17510 ) ( 1546290 * )
+ NEW met1 ( 1546290 17510 ) M1M2_PR
+ NEW met1 ( 1546290 1652570 ) M1M2_PR
+ NEW met1 ( 1549510 1652570 ) M1M2_PR
+ NEW met1 ( 1214630 17510 ) M1M2_PR ;
+ - la_data_in[34] ( PIN la_data_in[34] ) ( mprj la_data_in[34] ) + USE SIGNAL
+ + ROUTED met1 ( 1552730 1688950 ) ( 1555190 * )
+ NEW met2 ( 1555190 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1552730 17850 ) ( * 1688950 )
+ NEW met2 ( 1232110 1700 0 ) ( * 17850 )
+ NEW met1 ( 1232110 17850 ) ( 1552730 * )
+ NEW met1 ( 1552730 17850 ) M1M2_PR
+ NEW met1 ( 1552730 1688950 ) M1M2_PR
+ NEW met1 ( 1555190 1688950 ) M1M2_PR
+ NEW met1 ( 1232110 17850 ) M1M2_PR ;
+ - la_data_in[35] ( PIN la_data_in[35] ) ( mprj la_data_in[35] ) + USE SIGNAL
+ + ROUTED met2 ( 1250050 1700 0 ) ( * 20230 )
+ NEW met2 ( 1559630 1680110 ) ( * 1689460 )
+ NEW met2 ( 1559630 1689460 ) ( 1560710 * )
+ NEW met2 ( 1560710 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1250050 20230 ) ( 1300650 * )
+ NEW met2 ( 1300650 20230 ) ( * 1680110 )
+ NEW met1 ( 1300650 1680110 ) ( 1559630 * )
+ NEW met1 ( 1250050 20230 ) M1M2_PR
+ NEW met1 ( 1559630 1680110 ) M1M2_PR
+ NEW met1 ( 1300650 20230 ) M1M2_PR
+ NEW met1 ( 1300650 1680110 ) M1M2_PR ;
+ - la_data_in[36] ( PIN la_data_in[36] ) ( mprj la_data_in[36] ) + USE SIGNAL
+ + ROUTED met2 ( 1267530 1700 0 ) ( * 16490 )
+ NEW met2 ( 1555030 1680620 ) ( * 1680790 )
+ NEW met2 ( 1555030 1680620 ) ( 1555950 * )
+ NEW met2 ( 1555950 1680450 ) ( * 1680620 )
+ NEW met1 ( 1555950 1680450 ) ( 1566070 * )
+ NEW met2 ( 1566070 1680450 ) ( * 1688780 )
+ NEW met2 ( 1566070 1688780 ) ( 1566230 * )
+ NEW met2 ( 1566230 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1267530 16490 ) ( 1307550 * )
+ NEW met2 ( 1307550 16490 ) ( * 1680790 )
+ NEW met1 ( 1307550 1680790 ) ( 1555030 * )
+ NEW met1 ( 1267530 16490 ) M1M2_PR
+ NEW met1 ( 1555030 1680790 ) M1M2_PR
+ NEW met1 ( 1555950 1680450 ) M1M2_PR
+ NEW met1 ( 1566070 1680450 ) M1M2_PR
+ NEW met1 ( 1307550 16490 ) M1M2_PR
+ NEW met1 ( 1307550 1680790 ) M1M2_PR ;
+ - la_data_in[37] ( PIN la_data_in[37] ) ( mprj la_data_in[37] ) + USE SIGNAL
+ + ROUTED met2 ( 1285470 1700 0 ) ( * 15810 )
+ NEW met1 ( 1552270 1681130 ) ( * 1681470 )
+ NEW met1 ( 1552270 1681470 ) ( 1571590 * )
+ NEW met2 ( 1571590 1681470 ) ( * 1688780 )
+ NEW met2 ( 1571590 1688780 ) ( 1571750 * )
+ NEW met2 ( 1571750 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1285470 15810 ) ( 1321350 * )
+ NEW met2 ( 1321350 15810 ) ( * 1681130 )
+ NEW met1 ( 1321350 1681130 ) ( 1552270 * )
+ NEW met1 ( 1285470 15810 ) M1M2_PR
+ NEW met1 ( 1571590 1681470 ) M1M2_PR
+ NEW met1 ( 1321350 15810 ) M1M2_PR
+ NEW met1 ( 1321350 1681130 ) M1M2_PR ;
+ - la_data_in[38] ( PIN la_data_in[38] ) ( mprj la_data_in[38] ) + USE SIGNAL
+ + ROUTED met2 ( 1574810 21930 ) ( * 1580100 )
+ NEW met2 ( 1574810 1580100 ) ( 1576190 * )
+ NEW met2 ( 1576190 1688780 ) ( 1577270 * )
+ NEW met2 ( 1577270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1576190 1580100 ) ( * 1688780 )
+ NEW met2 ( 1303410 1700 0 ) ( * 19890 )
+ NEW met2 ( 1456590 19890 ) ( * 21930 )
+ NEW met1 ( 1303410 19890 ) ( 1456590 * )
+ NEW met1 ( 1456590 21930 ) ( 1574810 * )
+ NEW met1 ( 1574810 21930 ) M1M2_PR
+ NEW met1 ( 1303410 19890 ) M1M2_PR
+ NEW met1 ( 1456590 19890 ) M1M2_PR
+ NEW met1 ( 1456590 21930 ) M1M2_PR ;
+ - la_data_in[39] ( PIN la_data_in[39] ) ( mprj la_data_in[39] ) + USE SIGNAL
+ + ROUTED met2 ( 1320890 1700 0 ) ( * 20230 )
+ NEW met1 ( 1580790 1688950 ) ( * 1689290 )
+ NEW met1 ( 1580790 1689290 ) ( 1582790 * )
+ NEW met2 ( 1582790 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1580790 22610 ) ( * 1688950 )
+ NEW met2 ( 1457050 20230 ) ( * 22610 )
+ NEW met1 ( 1320890 20230 ) ( 1457050 * )
+ NEW met1 ( 1457050 22610 ) ( 1580790 * )
+ NEW met1 ( 1320890 20230 ) M1M2_PR
+ NEW met1 ( 1580790 22610 ) M1M2_PR
+ NEW met1 ( 1580790 1688950 ) M1M2_PR
+ NEW met1 ( 1582790 1689290 ) M1M2_PR
+ NEW met1 ( 1457050 20230 ) M1M2_PR
+ NEW met1 ( 1457050 22610 ) M1M2_PR ;
+ - la_data_in[3] ( PIN la_data_in[3] ) ( mprj la_data_in[3] ) + USE SIGNAL
+ + ROUTED met2 ( 682410 1700 0 ) ( * 30430 )
+ NEW met1 ( 1380690 1688950 ) ( 1385450 * )
+ NEW met2 ( 1385450 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1380690 30430 ) ( * 1688950 )
+ NEW met1 ( 682410 30430 ) ( 1380690 * )
+ NEW met1 ( 682410 30430 ) M1M2_PR
+ NEW met1 ( 1380690 30430 ) M1M2_PR
+ NEW met1 ( 1380690 1688950 ) M1M2_PR
+ NEW met1 ( 1385450 1688950 ) M1M2_PR ;
+ - la_data_in[40] ( PIN la_data_in[40] ) ( mprj la_data_in[40] ) + USE SIGNAL
+ + ROUTED met2 ( 1338830 1700 0 ) ( * 16830 )
+ NEW met2 ( 1469930 16830 ) ( * 22270 )
+ NEW met1 ( 1469930 22270 ) ( 1588150 * )
+ NEW met2 ( 1588150 1688780 ) ( 1588310 * )
+ NEW met2 ( 1588310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1588150 22270 ) ( * 1688780 )
+ NEW met1 ( 1338830 16830 ) ( 1469930 * )
+ NEW met1 ( 1338830 16830 ) M1M2_PR
+ NEW met1 ( 1469930 16830 ) M1M2_PR
+ NEW met1 ( 1469930 22270 ) M1M2_PR
+ NEW met1 ( 1588150 22270 ) M1M2_PR ;
+ - la_data_in[41] ( PIN la_data_in[41] ) ( mprj la_data_in[41] ) + USE SIGNAL
+ + ROUTED met2 ( 1356310 1700 0 ) ( * 20570 )
+ NEW met2 ( 1490170 20570 ) ( * 26690 )
+ NEW met1 ( 1490170 26690 ) ( 1587690 * )
+ NEW met1 ( 1587690 1688950 ) ( 1593830 * )
+ NEW met2 ( 1593830 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1587690 26690 ) ( * 1688950 )
+ NEW met1 ( 1356310 20570 ) ( 1490170 * )
+ NEW met1 ( 1356310 20570 ) M1M2_PR
+ NEW met1 ( 1490170 20570 ) M1M2_PR
+ NEW met1 ( 1490170 26690 ) M1M2_PR
+ NEW met1 ( 1587690 26690 ) M1M2_PR
+ NEW met1 ( 1587690 1688950 ) M1M2_PR
+ NEW met1 ( 1593830 1688950 ) M1M2_PR ;
+ - la_data_in[42] ( PIN la_data_in[42] ) ( mprj la_data_in[42] ) + USE SIGNAL
+ + ROUTED met2 ( 1374250 1700 0 ) ( * 23970 )
+ NEW met1 ( 1594590 1688950 ) ( 1598890 * )
+ NEW met2 ( 1598890 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1594590 23970 ) ( * 1688950 )
+ NEW met1 ( 1374250 23970 ) ( 1594590 * )
+ NEW met1 ( 1374250 23970 ) M1M2_PR
+ NEW met1 ( 1594590 23970 ) M1M2_PR
+ NEW met1 ( 1594590 1688950 ) M1M2_PR
+ NEW met1 ( 1598890 1688950 ) M1M2_PR ;
+ - la_data_in[43] ( PIN la_data_in[43] ) ( mprj la_data_in[43] ) + USE SIGNAL
+ + ROUTED met2 ( 1391730 1700 0 ) ( * 24310 )
+ NEW met2 ( 1601950 1688780 ) ( 1604410 * )
+ NEW met2 ( 1604410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1601950 24310 ) ( * 1688780 )
+ NEW met1 ( 1391730 24310 ) ( 1601950 * )
+ NEW met1 ( 1391730 24310 ) M1M2_PR
+ NEW met1 ( 1601950 24310 ) M1M2_PR ;
+ - la_data_in[44] ( PIN la_data_in[44] ) ( mprj la_data_in[44] ) + USE SIGNAL
+ + ROUTED met2 ( 1409670 1700 0 ) ( * 15810 )
+ NEW met2 ( 1489710 15810 ) ( * 26010 )
+ NEW met1 ( 1489710 26010 ) ( 1608850 * )
+ NEW met2 ( 1608850 1688780 ) ( 1609930 * )
+ NEW met2 ( 1609930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1608850 26010 ) ( * 1688780 )
+ NEW met1 ( 1409670 15810 ) ( 1489710 * )
+ NEW met1 ( 1409670 15810 ) M1M2_PR
+ NEW met1 ( 1489710 15810 ) M1M2_PR
+ NEW met1 ( 1489710 26010 ) M1M2_PR
+ NEW met1 ( 1608850 26010 ) M1M2_PR ;
+ - la_data_in[45] ( PIN la_data_in[45] ) ( mprj la_data_in[45] ) + USE SIGNAL
+ + ROUTED met2 ( 1615290 1688780 ) ( 1615450 * )
+ NEW met2 ( 1615450 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1615290 23290 ) ( * 1688780 )
+ NEW met2 ( 1427150 1700 0 ) ( * 23290 )
+ NEW met1 ( 1427150 23290 ) ( 1615290 * )
+ NEW met1 ( 1615290 23290 ) M1M2_PR
+ NEW met1 ( 1427150 23290 ) M1M2_PR ;
+ - la_data_in[46] ( PIN la_data_in[46] ) ( mprj la_data_in[46] ) + USE SIGNAL
+ + ROUTED met1 ( 1615750 1652570 ) ( 1620810 * )
+ NEW met2 ( 1615750 22950 ) ( * 1652570 )
+ NEW met2 ( 1620810 1688780 ) ( 1620970 * )
+ NEW met2 ( 1620970 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1620810 1652570 ) ( * 1688780 )
+ NEW met2 ( 1445090 1700 0 ) ( * 22950 )
+ NEW met1 ( 1445090 22950 ) ( 1615750 * )
+ NEW met1 ( 1615750 22950 ) M1M2_PR
+ NEW met1 ( 1615750 1652570 ) M1M2_PR
+ NEW met1 ( 1620810 1652570 ) M1M2_PR
+ NEW met1 ( 1445090 22950 ) M1M2_PR ;
+ - la_data_in[47] ( PIN la_data_in[47] ) ( mprj la_data_in[47] ) + USE SIGNAL
+ + ROUTED met2 ( 1463030 1700 0 ) ( * 24650 )
+ NEW met1 ( 1463030 24650 ) ( 1622190 * )
+ NEW met1 ( 1622190 1688950 ) ( 1626490 * )
+ NEW met2 ( 1626490 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1622190 24650 ) ( * 1688950 )
+ NEW met1 ( 1463030 24650 ) M1M2_PR
+ NEW met1 ( 1622190 24650 ) M1M2_PR
+ NEW met1 ( 1622190 1688950 ) M1M2_PR
+ NEW met1 ( 1626490 1688950 ) M1M2_PR ;
+ - la_data_in[48] ( PIN la_data_in[48] ) ( mprj la_data_in[48] ) + USE SIGNAL
+ + ROUTED met2 ( 1480510 1700 0 ) ( * 24990 )
+ NEW met2 ( 1629090 1688780 ) ( 1632010 * )
+ NEW met2 ( 1632010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1629090 24990 ) ( * 1688780 )
+ NEW met1 ( 1480510 24990 ) ( 1629090 * )
+ NEW met1 ( 1480510 24990 ) M1M2_PR
+ NEW met1 ( 1629090 24990 ) M1M2_PR ;
+ - la_data_in[49] ( PIN la_data_in[49] ) ( mprj la_data_in[49] ) + USE SIGNAL
+ + ROUTED met2 ( 1636450 1688780 ) ( 1637530 * )
+ NEW met2 ( 1637530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1636450 25330 ) ( * 1688780 )
+ NEW met2 ( 1498450 1700 0 ) ( * 25330 )
+ NEW met1 ( 1498450 25330 ) ( 1636450 * )
+ NEW met1 ( 1636450 25330 ) M1M2_PR
+ NEW met1 ( 1498450 25330 ) M1M2_PR ;
+ - la_data_in[4] ( PIN la_data_in[4] ) ( mprj la_data_in[4] ) + USE SIGNAL
+ + ROUTED met2 ( 700350 1700 0 ) ( * 30090 )
+ NEW met1 ( 1362290 29410 ) ( * 30090 )
+ NEW met1 ( 700350 30090 ) ( 1362290 * )
+ NEW met1 ( 1362290 29410 ) ( 1387130 * )
+ NEW met1 ( 1387130 1652570 ) ( 1390810 * )
+ NEW met2 ( 1387130 29410 ) ( * 1652570 )
+ NEW met2 ( 1390810 1688780 ) ( 1390970 * )
+ NEW met2 ( 1390970 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1390810 1652570 ) ( * 1688780 )
+ NEW met1 ( 700350 30090 ) M1M2_PR
+ NEW met1 ( 1387130 29410 ) M1M2_PR
+ NEW met1 ( 1387130 1652570 ) M1M2_PR
+ NEW met1 ( 1390810 1652570 ) M1M2_PR ;
+ - la_data_in[50] ( PIN la_data_in[50] ) ( mprj la_data_in[50] ) + USE SIGNAL
+ + ROUTED met2 ( 1643120 1688780 ) ( 1643350 * )
+ NEW met2 ( 1643120 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1643350 25670 ) ( * 1688780 )
+ NEW met2 ( 1515930 1700 0 ) ( * 25670 )
+ NEW met1 ( 1515930 25670 ) ( 1643350 * )
+ NEW met1 ( 1643350 25670 ) M1M2_PR
+ NEW met1 ( 1515930 25670 ) M1M2_PR ;
+ - la_data_in[51] ( PIN la_data_in[51] ) ( mprj la_data_in[51] ) + USE SIGNAL
+ + ROUTED met2 ( 1533870 1700 0 ) ( * 26350 )
+ NEW met2 ( 1643810 1688780 ) ( 1648570 * )
+ NEW met2 ( 1648570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1643810 26350 ) ( * 1688780 )
+ NEW met1 ( 1533870 26350 ) ( 1643810 * )
+ NEW met1 ( 1533870 26350 ) M1M2_PR
+ NEW met1 ( 1643810 26350 ) M1M2_PR ;
+ - la_data_in[52] ( PIN la_data_in[52] ) ( mprj la_data_in[52] ) + USE SIGNAL
+ + ROUTED met2 ( 1549050 1700 ) ( 1551350 * 0 )
+ NEW met2 ( 1549050 1700 ) ( * 3060 )
+ NEW met2 ( 1545830 3060 ) ( 1549050 * )
+ NEW met2 ( 1545830 3060 ) ( * 1679770 )
+ NEW met2 ( 1653930 1679770 ) ( * 1688780 )
+ NEW met2 ( 1653930 1688780 ) ( 1654090 * )
+ NEW met2 ( 1654090 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1545830 1679770 ) ( 1653930 * )
+ NEW met1 ( 1545830 1679770 ) M1M2_PR
+ NEW met1 ( 1653930 1679770 ) M1M2_PR ;
+ - la_data_in[53] ( PIN la_data_in[53] ) ( mprj la_data_in[53] ) + USE SIGNAL
+ + ROUTED met2 ( 1569290 1700 0 ) ( * 17340 )
+ NEW met2 ( 1566530 17340 ) ( 1569290 * )
+ NEW met2 ( 1566530 17340 ) ( * 1680110 )
+ NEW met2 ( 1658990 1680110 ) ( * 1688780 )
+ NEW met2 ( 1658990 1688780 ) ( 1659150 * )
+ NEW met2 ( 1659150 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1566530 1680110 ) ( 1658990 * )
+ NEW met1 ( 1566530 1680110 ) M1M2_PR
+ NEW met1 ( 1658990 1680110 ) M1M2_PR ;
+ - la_data_in[54] ( PIN la_data_in[54] ) ( mprj la_data_in[54] ) + USE SIGNAL
+ + ROUTED met2 ( 1664510 1681130 ) ( * 1688780 )
+ NEW met2 ( 1664510 1688780 ) ( 1664670 * )
+ NEW met2 ( 1664670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1582170 82800 ) ( 1586770 * )
+ NEW met2 ( 1586770 1700 0 ) ( * 82800 )
+ NEW met1 ( 1628400 1681130 ) ( 1664510 * )
+ NEW met1 ( 1582170 1681470 ) ( 1628400 * )
+ NEW met1 ( 1628400 1681130 ) ( * 1681470 )
+ NEW met2 ( 1582170 82800 ) ( * 1681470 )
+ NEW met1 ( 1664510 1681130 ) M1M2_PR
+ NEW met1 ( 1582170 1681470 ) M1M2_PR ;
+ - la_data_in[55] ( PIN la_data_in[55] ) ( mprj la_data_in[55] ) + USE SIGNAL
+ + ROUTED met2 ( 1670260 1688780 ) ( 1671410 * )
+ NEW met2 ( 1670260 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1671410 16490 ) ( * 1688780 )
+ NEW met2 ( 1604710 1700 0 ) ( * 16490 )
+ NEW met1 ( 1604710 16490 ) ( 1671410 * )
+ NEW met1 ( 1671410 16490 ) M1M2_PR
+ NEW met1 ( 1604710 16490 ) M1M2_PR ;
+ - la_data_in[56] ( PIN la_data_in[56] ) ( mprj la_data_in[56] ) + USE SIGNAL
+ + ROUTED met1 ( 1645190 15470 ) ( * 16150 )
+ NEW met1 ( 1645190 15470 ) ( 1670950 * )
+ NEW met1 ( 1670950 1652230 ) ( 1675550 * )
+ NEW met2 ( 1670950 15470 ) ( * 1652230 )
+ NEW met2 ( 1675550 1688780 ) ( 1675710 * )
+ NEW met2 ( 1675710 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1675550 1652230 ) ( * 1688780 )
+ NEW met2 ( 1622190 1700 0 ) ( * 16150 )
+ NEW met1 ( 1622190 16150 ) ( 1645190 * )
+ NEW met1 ( 1670950 15470 ) M1M2_PR
+ NEW met1 ( 1670950 1652230 ) M1M2_PR
+ NEW met1 ( 1675550 1652230 ) M1M2_PR
+ NEW met1 ( 1622190 16150 ) M1M2_PR ;
+ - la_data_in[57] ( PIN la_data_in[57] ) ( mprj la_data_in[57] ) + USE SIGNAL
+ + ROUTED met2 ( 1640130 1700 0 ) ( * 17340 )
+ NEW met2 ( 1635530 17340 ) ( 1640130 * )
+ NEW met2 ( 1635530 17340 ) ( * 1680790 )
+ NEW met2 ( 1679690 1680790 ) ( * 1689290 )
+ NEW met2 ( 1679690 1689290 ) ( 1681230 * )
+ NEW met2 ( 1681230 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 1635530 1680790 ) ( 1679690 * )
+ NEW met1 ( 1635530 1680790 ) M1M2_PR
+ NEW met1 ( 1679690 1680790 ) M1M2_PR ;
+ - la_data_in[58] ( PIN la_data_in[58] ) ( mprj la_data_in[58] ) + USE SIGNAL
+ + ROUTED met2 ( 1658070 1700 0 ) ( * 19550 )
+ NEW met1 ( 1658070 19550 ) ( 1684290 * )
+ NEW met1 ( 1684290 1688950 ) ( 1686750 * )
+ NEW met2 ( 1686750 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1684290 19550 ) ( * 1688950 )
+ NEW met1 ( 1658070 19550 ) M1M2_PR
+ NEW met1 ( 1684290 19550 ) M1M2_PR
+ NEW met1 ( 1684290 1688950 ) M1M2_PR
+ NEW met1 ( 1686750 1688950 ) M1M2_PR ;
+ - la_data_in[59] ( PIN la_data_in[59] ) ( mprj la_data_in[59] ) + USE SIGNAL
+ + ROUTED met2 ( 1675550 1700 0 ) ( * 18530 )
+ NEW met1 ( 1675550 18530 ) ( 1691190 * )
+ NEW met2 ( 1691190 1688780 ) ( 1692270 * )
+ NEW met2 ( 1692270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1691190 18530 ) ( * 1688780 )
+ NEW met1 ( 1675550 18530 ) M1M2_PR
+ NEW met1 ( 1691190 18530 ) M1M2_PR ;
+ - la_data_in[5] ( PIN la_data_in[5] ) ( mprj la_data_in[5] ) + USE SIGNAL
+ + ROUTED met2 ( 717830 1700 0 ) ( * 34500 )
+ NEW met2 ( 717830 34500 ) ( 718290 * )
+ NEW met2 ( 718290 34500 ) ( * 81430 )
+ NEW met1 ( 718290 81430 ) ( 1394030 * )
+ NEW met1 ( 1394030 1689290 ) ( 1396490 * )
+ NEW met2 ( 1396490 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1394030 81430 ) ( * 1689290 )
+ NEW met1 ( 718290 81430 ) M1M2_PR
+ NEW met1 ( 1394030 81430 ) M1M2_PR
+ NEW met1 ( 1394030 1689290 ) M1M2_PR
+ NEW met1 ( 1396490 1689290 ) M1M2_PR ;
+ - la_data_in[60] ( PIN la_data_in[60] ) ( mprj la_data_in[60] ) + USE SIGNAL
+ + ROUTED met2 ( 1693490 1700 0 ) ( * 17510 )
+ NEW met1 ( 1693490 17510 ) ( 1698090 * )
+ NEW met2 ( 1697860 1688780 ) ( 1698090 * )
+ NEW met2 ( 1697860 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1698090 17510 ) ( * 1688780 )
+ NEW met1 ( 1693490 17510 ) M1M2_PR
+ NEW met1 ( 1698090 17510 ) M1M2_PR ;
+ - la_data_in[61] ( PIN la_data_in[61] ) ( mprj la_data_in[61] ) + USE SIGNAL
+ + ROUTED met2 ( 1706830 82800 ) ( 1710970 * )
+ NEW met2 ( 1710970 1700 0 ) ( * 82800 )
+ NEW met1 ( 1703610 1679770 ) ( 1706830 * )
+ NEW met2 ( 1703610 1679770 ) ( * 1688780 )
+ NEW met2 ( 1703380 1688780 ) ( 1703610 * )
+ NEW met2 ( 1703380 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1706830 82800 ) ( * 1679770 )
+ NEW met1 ( 1706830 1679770 ) M1M2_PR
+ NEW met1 ( 1703610 1679770 ) M1M2_PR ;
+ - la_data_in[62] ( PIN la_data_in[62] ) ( mprj la_data_in[62] ) + USE SIGNAL
+ + ROUTED met2 ( 1728910 1700 0 ) ( * 19550 )
+ NEW met1 ( 1706370 19550 ) ( 1728910 * )
+ NEW met2 ( 1706370 1688780 ) ( 1708830 * )
+ NEW met2 ( 1708830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1706370 19550 ) ( * 1688780 )
+ NEW met1 ( 1728910 19550 ) M1M2_PR
+ NEW met1 ( 1706370 19550 ) M1M2_PR ;
+ - la_data_in[63] ( PIN la_data_in[63] ) ( mprj la_data_in[63] ) + USE SIGNAL
+ + ROUTED met2 ( 1746390 1700 0 ) ( * 14790 )
+ NEW met1 ( 1711890 14790 ) ( 1746390 * )
+ NEW met1 ( 1711890 1689290 ) ( 1714350 * )
+ NEW met2 ( 1714350 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1711890 14790 ) ( * 1689290 )
+ NEW met1 ( 1746390 14790 ) M1M2_PR
+ NEW met1 ( 1711890 14790 ) M1M2_PR
+ NEW met1 ( 1711890 1689290 ) M1M2_PR
+ NEW met1 ( 1714350 1689290 ) M1M2_PR ;
+ - la_data_in[64] ( PIN la_data_in[64] ) ( mprj la_data_in[64] ) + USE SIGNAL
+ + ROUTED met2 ( 1764330 1700 0 ) ( * 16830 )
+ NEW met1 ( 1728450 16830 ) ( 1764330 * )
+ NEW met2 ( 1728450 16830 ) ( * 1676710 )
+ NEW met1 ( 1725000 1676710 ) ( 1728450 * )
+ NEW met1 ( 1725000 1676710 ) ( * 1677390 )
+ NEW met1 ( 1719710 1677390 ) ( 1725000 * )
+ NEW met2 ( 1719710 1677390 ) ( * 1689290 )
+ NEW met2 ( 1719480 1689290 ) ( 1719710 * )
+ NEW met2 ( 1719480 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 1764330 16830 ) M1M2_PR
+ NEW met1 ( 1728450 16830 ) M1M2_PR
+ NEW met1 ( 1728450 1676710 ) M1M2_PR
+ NEW met1 ( 1719710 1677390 ) M1M2_PR ;
+ - la_data_in[65] ( PIN la_data_in[65] ) ( mprj la_data_in[65] ) + USE SIGNAL
+ + ROUTED met1 ( 1718790 1651890 ) ( 1724770 * )
+ NEW met2 ( 1781810 1700 0 ) ( * 19890 )
+ NEW met1 ( 1718790 19890 ) ( 1781810 * )
+ NEW met2 ( 1718790 19890 ) ( * 1651890 )
+ NEW met2 ( 1724770 1688780 ) ( 1724930 * )
+ NEW met2 ( 1724930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1724770 1651890 ) ( * 1688780 )
+ NEW met1 ( 1718790 19890 ) M1M2_PR
+ NEW met1 ( 1718790 1651890 ) M1M2_PR
+ NEW met1 ( 1724770 1651890 ) M1M2_PR
+ NEW met1 ( 1781810 19890 ) M1M2_PR ;
+ - la_data_in[66] ( PIN la_data_in[66] ) ( mprj la_data_in[66] ) + USE SIGNAL
+ + ROUTED met2 ( 1725690 1683340 ) ( 1728910 * )
+ NEW met2 ( 1728910 1683340 ) ( * 1688780 )
+ NEW met2 ( 1728910 1688780 ) ( 1730450 * )
+ NEW met2 ( 1730450 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1725690 14450 ) ( * 1683340 )
+ NEW met2 ( 1799750 1700 0 ) ( * 14450 )
+ NEW met1 ( 1725690 14450 ) ( 1799750 * )
+ NEW met1 ( 1725690 14450 ) M1M2_PR
+ NEW met1 ( 1799750 14450 ) M1M2_PR ;
+ - la_data_in[67] ( PIN la_data_in[67] ) ( mprj la_data_in[67] ) + USE SIGNAL
+ + ROUTED met1 ( 1732590 1652570 ) ( 1735810 * )
+ NEW met2 ( 1732590 19550 ) ( * 1652570 )
+ NEW met2 ( 1735810 1688780 ) ( 1735970 * )
+ NEW met2 ( 1735970 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1735810 1652570 ) ( * 1688780 )
+ NEW met2 ( 1817690 1700 0 ) ( * 19550 )
+ NEW met1 ( 1732590 19550 ) ( 1817690 * )
+ NEW met1 ( 1732590 19550 ) M1M2_PR
+ NEW met1 ( 1732590 1652570 ) M1M2_PR
+ NEW met1 ( 1735810 1652570 ) M1M2_PR
+ NEW met1 ( 1817690 19550 ) M1M2_PR ;
+ - la_data_in[68] ( PIN la_data_in[68] ) ( mprj la_data_in[68] ) + USE SIGNAL
+ + ROUTED met2 ( 1835170 1700 0 ) ( * 19210 )
+ NEW met2 ( 1739030 19210 ) ( * 1676700 )
+ NEW met2 ( 1739030 1676700 ) ( 1740870 * )
+ NEW met2 ( 1740870 1676700 ) ( * 1688780 )
+ NEW met2 ( 1740870 1688780 ) ( 1741490 * )
+ NEW met2 ( 1741490 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1739030 19210 ) ( 1835170 * )
+ NEW met1 ( 1739030 19210 ) M1M2_PR
+ NEW met1 ( 1835170 19210 ) M1M2_PR ;
+ - la_data_in[69] ( PIN la_data_in[69] ) ( mprj la_data_in[69] ) + USE SIGNAL
+ + ROUTED met2 ( 1853110 1700 0 ) ( * 18190 )
+ NEW met2 ( 1745930 1688780 ) ( 1747010 * )
+ NEW met2 ( 1747010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1745930 18190 ) ( * 1688780 )
+ NEW met1 ( 1745930 18190 ) ( 1853110 * )
+ NEW met1 ( 1745930 18190 ) M1M2_PR
+ NEW met1 ( 1853110 18190 ) M1M2_PR ;
+ - la_data_in[6] ( PIN la_data_in[6] ) ( mprj la_data_in[6] ) + USE SIGNAL
+ + ROUTED met1 ( 731630 86870 ) ( 1401850 * )
+ NEW met2 ( 731630 82800 ) ( * 86870 )
+ NEW met2 ( 731630 82800 ) ( 735770 * )
+ NEW met2 ( 735770 1700 0 ) ( * 82800 )
+ NEW met2 ( 1401850 1688780 ) ( 1402010 * )
+ NEW met2 ( 1402010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1401850 86870 ) ( * 1688780 )
+ NEW met1 ( 731630 86870 ) M1M2_PR
+ NEW met1 ( 1401850 86870 ) M1M2_PR ;
+ - la_data_in[70] ( PIN la_data_in[70] ) ( mprj la_data_in[70] ) + USE SIGNAL
+ + ROUTED met2 ( 1752370 1676710 ) ( * 1688780 )
+ NEW met2 ( 1752370 1688780 ) ( 1752530 * )
+ NEW met2 ( 1752530 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1776750 16150 ) ( 1812630 * )
+ NEW met2 ( 1812630 16150 ) ( * 20230 )
+ NEW met2 ( 1870590 1700 0 ) ( * 20230 )
+ NEW met1 ( 1812630 20230 ) ( 1870590 * )
+ NEW met1 ( 1752370 1676710 ) ( 1776750 * )
+ NEW met2 ( 1776750 16150 ) ( * 1676710 )
+ NEW met1 ( 1752370 1676710 ) M1M2_PR
+ NEW met1 ( 1776750 16150 ) M1M2_PR
+ NEW met1 ( 1812630 16150 ) M1M2_PR
+ NEW met1 ( 1812630 20230 ) M1M2_PR
+ NEW met1 ( 1870590 20230 ) M1M2_PR
+ NEW met1 ( 1776750 1676710 ) M1M2_PR ;
+ - la_data_in[71] ( PIN la_data_in[71] ) ( mprj la_data_in[71] ) + USE SIGNAL
+ + ROUTED met2 ( 1758350 1677050 ) ( * 1688780 )
+ NEW met2 ( 1758120 1688780 ) ( 1758350 * )
+ NEW met2 ( 1758120 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1783650 20230 ) ( 1802050 * )
+ NEW met1 ( 1802050 19890 ) ( * 20230 )
+ NEW met2 ( 1888530 1700 0 ) ( * 19890 )
+ NEW met1 ( 1802050 19890 ) ( 1888530 * )
+ NEW met1 ( 1758350 1677050 ) ( 1783650 * )
+ NEW met2 ( 1783650 20230 ) ( * 1677050 )
+ NEW met1 ( 1758350 1677050 ) M1M2_PR
+ NEW met1 ( 1783650 20230 ) M1M2_PR
+ NEW met1 ( 1888530 19890 ) M1M2_PR
+ NEW met1 ( 1783650 1677050 ) M1M2_PR ;
+ - la_data_in[72] ( PIN la_data_in[72] ) ( mprj la_data_in[72] ) + USE SIGNAL
+ + ROUTED met2 ( 1763870 1678750 ) ( * 1688780 )
+ NEW met2 ( 1763640 1688780 ) ( 1763870 * )
+ NEW met2 ( 1763640 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1790550 19890 ) ( 1794230 * )
+ NEW met2 ( 1794230 18530 ) ( * 19890 )
+ NEW met2 ( 1906010 1700 0 ) ( * 18530 )
+ NEW met1 ( 1794230 18530 ) ( 1906010 * )
+ NEW met1 ( 1763870 1678750 ) ( 1790550 * )
+ NEW met2 ( 1790550 19890 ) ( * 1678750 )
+ NEW met1 ( 1763870 1678750 ) M1M2_PR
+ NEW met1 ( 1790550 19890 ) M1M2_PR
+ NEW met1 ( 1794230 19890 ) M1M2_PR
+ NEW met1 ( 1794230 18530 ) M1M2_PR
+ NEW met1 ( 1906010 18530 ) M1M2_PR
+ NEW met1 ( 1790550 1678750 ) M1M2_PR ;
+ - la_data_in[73] ( PIN la_data_in[73] ) ( mprj la_data_in[73] ) + USE SIGNAL
+ + ROUTED met2 ( 1923950 1700 0 ) ( * 20570 )
+ NEW met2 ( 1769390 1679430 ) ( * 1688780 )
+ NEW met2 ( 1769160 1688780 ) ( 1769390 * )
+ NEW met2 ( 1769160 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1811250 20230 ) ( 1812170 * )
+ NEW met1 ( 1812170 20230 ) ( * 20570 )
+ NEW met1 ( 1812170 20570 ) ( 1923950 * )
+ NEW met2 ( 1811250 20230 ) ( * 1676700 )
+ NEW met2 ( 1810790 1676700 ) ( * 1679430 )
+ NEW met2 ( 1810790 1676700 ) ( 1811250 * )
+ NEW met1 ( 1769390 1679430 ) ( 1810790 * )
+ NEW met1 ( 1923950 20570 ) M1M2_PR
+ NEW met1 ( 1769390 1679430 ) M1M2_PR
+ NEW met1 ( 1811250 20230 ) M1M2_PR
+ NEW met1 ( 1810790 1679430 ) M1M2_PR ;
+ - la_data_in[74] ( PIN la_data_in[74] ) ( mprj la_data_in[74] ) + USE SIGNAL
+ + ROUTED met2 ( 1941430 1700 0 ) ( * 16490 )
+ NEW met2 ( 1832410 16490 ) ( * 1683170 )
+ NEW met1 ( 1832410 16490 ) ( 1941430 * )
+ NEW met2 ( 1774910 1683170 ) ( * 1688780 )
+ NEW met2 ( 1774680 1688780 ) ( 1774910 * )
+ NEW met2 ( 1774680 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1774910 1683170 ) ( 1832410 * )
+ NEW met1 ( 1832410 16490 ) M1M2_PR
+ NEW met1 ( 1941430 16490 ) M1M2_PR
+ NEW met1 ( 1832410 1683170 ) M1M2_PR
+ NEW met1 ( 1774910 1683170 ) M1M2_PR ;
+ - la_data_in[75] ( PIN la_data_in[75] ) ( mprj la_data_in[75] ) + USE SIGNAL
+ + ROUTED met2 ( 1959370 1700 0 ) ( * 19550 )
+ NEW met2 ( 1832870 19550 ) ( * 1682830 )
+ NEW met1 ( 1832870 19550 ) ( 1959370 * )
+ NEW met2 ( 1779970 1682830 ) ( * 1688780 )
+ NEW met2 ( 1779740 1688780 ) ( 1779970 * )
+ NEW met2 ( 1779740 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1779970 1682830 ) ( 1832870 * )
+ NEW met1 ( 1832870 19550 ) M1M2_PR
+ NEW met1 ( 1959370 19550 ) M1M2_PR
+ NEW met1 ( 1832870 1682830 ) M1M2_PR
+ NEW met1 ( 1779970 1682830 ) M1M2_PR ;
+ - la_data_in[76] ( PIN la_data_in[76] ) ( mprj la_data_in[76] ) + USE SIGNAL
+ + ROUTED met2 ( 1845750 16830 ) ( * 1678410 )
+ NEW met2 ( 1976850 1700 0 ) ( * 16830 )
+ NEW met1 ( 1845750 16830 ) ( 1976850 * )
+ NEW met2 ( 1785490 1678410 ) ( * 1688780 )
+ NEW met2 ( 1785260 1688780 ) ( 1785490 * )
+ NEW met2 ( 1785260 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1785490 1678410 ) ( 1845750 * )
+ NEW met1 ( 1845750 16830 ) M1M2_PR
+ NEW met1 ( 1845750 1678410 ) M1M2_PR
+ NEW met1 ( 1976850 16830 ) M1M2_PR
+ NEW met1 ( 1785490 1678410 ) M1M2_PR ;
+ - la_data_in[77] ( PIN la_data_in[77] ) ( mprj la_data_in[77] ) + USE SIGNAL
+ + ROUTED met1 ( 1787790 1652230 ) ( * 1653250 )
+ NEW met2 ( 1994790 1700 0 ) ( * 23970 )
+ NEW met1 ( 1787790 23970 ) ( 1994790 * )
+ NEW met2 ( 1787790 23970 ) ( * 1652230 )
+ NEW met1 ( 1787790 1689290 ) ( 1790710 * )
+ NEW met2 ( 1790710 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1787790 1653250 ) ( * 1689290 )
+ NEW met1 ( 1787790 23970 ) M1M2_PR
+ NEW met1 ( 1787790 1652230 ) M1M2_PR
+ NEW met1 ( 1787790 1653250 ) M1M2_PR
+ NEW met1 ( 1994790 23970 ) M1M2_PR
+ NEW met1 ( 1787790 1689290 ) M1M2_PR
+ NEW met1 ( 1790710 1689290 ) M1M2_PR ;
+ - la_data_in[78] ( PIN la_data_in[78] ) ( mprj la_data_in[78] ) + USE SIGNAL
+ + ROUTED met2 ( 2012730 1700 0 ) ( * 22270 )
+ NEW met1 ( 1795150 22270 ) ( 2012730 * )
+ NEW met2 ( 1795150 22270 ) ( * 1580100 )
+ NEW met2 ( 1795150 1580100 ) ( 1796070 * )
+ NEW met2 ( 1796070 1688780 ) ( 1796230 * )
+ NEW met2 ( 1796230 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1796070 1580100 ) ( * 1688780 )
+ NEW met1 ( 1795150 22270 ) M1M2_PR
+ NEW met1 ( 2012730 22270 ) M1M2_PR ;
+ - la_data_in[79] ( PIN la_data_in[79] ) ( mprj la_data_in[79] ) + USE SIGNAL
+ + ROUTED met2 ( 2030210 1700 0 ) ( * 22950 )
+ NEW met1 ( 1801130 22950 ) ( 2030210 * )
+ NEW met2 ( 1801130 1688780 ) ( 1801750 * )
+ NEW met2 ( 1801750 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1801130 22950 ) ( * 1688780 )
+ NEW met1 ( 2030210 22950 ) M1M2_PR
+ NEW met1 ( 1801130 22950 ) M1M2_PR ;
+ - la_data_in[7] ( PIN la_data_in[7] ) ( mprj la_data_in[7] ) + USE SIGNAL
+ + ROUTED met1 ( 752330 87550 ) ( 1402310 * )
+ NEW met1 ( 1402310 1642370 ) ( 1407370 * )
+ NEW met2 ( 752330 82800 ) ( * 87550 )
+ NEW met2 ( 752330 82800 ) ( 753250 * )
+ NEW met2 ( 753250 1700 0 ) ( * 82800 )
+ NEW met2 ( 1402310 87550 ) ( * 1642370 )
+ NEW met2 ( 1407370 1688780 ) ( 1407530 * )
+ NEW met2 ( 1407530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1407370 1642370 ) ( * 1688780 )
+ NEW met1 ( 752330 87550 ) M1M2_PR
+ NEW met1 ( 1402310 87550 ) M1M2_PR
+ NEW met1 ( 1402310 1642370 ) M1M2_PR
+ NEW met1 ( 1407370 1642370 ) M1M2_PR ;
+ - la_data_in[80] ( PIN la_data_in[80] ) ( mprj la_data_in[80] ) + USE SIGNAL
+ + ROUTED met2 ( 2048150 1700 0 ) ( * 30770 )
+ NEW met1 ( 1801590 1652570 ) ( 1807110 * )
+ NEW met1 ( 1801590 30770 ) ( 2048150 * )
+ NEW met2 ( 1801590 30770 ) ( * 1652570 )
+ NEW met2 ( 1807110 1688780 ) ( 1807270 * )
+ NEW met2 ( 1807270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1807110 1652570 ) ( * 1688780 )
+ NEW met1 ( 2048150 30770 ) M1M2_PR
+ NEW met1 ( 1801590 30770 ) M1M2_PR
+ NEW met1 ( 1801590 1652570 ) M1M2_PR
+ NEW met1 ( 1807110 1652570 ) M1M2_PR ;
+ - la_data_in[81] ( PIN la_data_in[81] ) ( mprj la_data_in[81] ) + USE SIGNAL
+ + ROUTED met2 ( 2065630 1700 0 ) ( * 29410 )
+ NEW met1 ( 1808030 29410 ) ( 2065630 * )
+ NEW met1 ( 1808030 1688950 ) ( 1812790 * )
+ NEW met2 ( 1812790 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1808030 29410 ) ( * 1688950 )
+ NEW met1 ( 1808030 29410 ) M1M2_PR
+ NEW met1 ( 2065630 29410 ) M1M2_PR
+ NEW met1 ( 1808030 1688950 ) M1M2_PR
+ NEW met1 ( 1812790 1688950 ) M1M2_PR ;
+ - la_data_in[82] ( PIN la_data_in[82] ) ( mprj la_data_in[82] ) + USE SIGNAL
+ + ROUTED met2 ( 2083570 1700 0 ) ( * 27710 )
+ NEW met1 ( 2077590 27710 ) ( 2083570 * )
+ NEW met2 ( 2077590 27710 ) ( * 34170 )
+ NEW met1 ( 1815390 34170 ) ( 2077590 * )
+ NEW met2 ( 1815390 34170 ) ( * 1676700 )
+ NEW met2 ( 1815390 1676700 ) ( 1817230 * )
+ NEW met2 ( 1817230 1676700 ) ( * 1688780 )
+ NEW met2 ( 1817230 1688780 ) ( 1818310 * )
+ NEW met2 ( 1818310 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1815390 34170 ) M1M2_PR
+ NEW met1 ( 2083570 27710 ) M1M2_PR
+ NEW met1 ( 2077590 27710 ) M1M2_PR
+ NEW met1 ( 2077590 34170 ) M1M2_PR ;
+ - la_data_in[83] ( PIN la_data_in[83] ) ( mprj la_data_in[83] ) + USE SIGNAL
+ + ROUTED met2 ( 1821830 29750 ) ( * 1676700 )
+ NEW met2 ( 1821830 1676700 ) ( 1823670 * )
+ NEW met2 ( 1823670 1676700 ) ( * 1688780 )
+ NEW met2 ( 1823670 1688780 ) ( 1823830 * )
+ NEW met2 ( 1823830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2101050 1700 0 ) ( * 29750 )
+ NEW met1 ( 1821830 29750 ) ( 2101050 * )
+ NEW met1 ( 1821830 29750 ) M1M2_PR
+ NEW met1 ( 2101050 29750 ) M1M2_PR ;
+ - la_data_in[84] ( PIN la_data_in[84] ) ( mprj la_data_in[84] ) + USE SIGNAL
+ + ROUTED met2 ( 2118990 1700 0 ) ( * 30090 )
+ NEW met2 ( 1829420 1688780 ) ( 1829650 * )
+ NEW met2 ( 1829420 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1829650 30090 ) ( * 1688780 )
+ NEW met1 ( 1829650 30090 ) ( 2118990 * )
+ NEW met1 ( 1829650 30090 ) M1M2_PR
+ NEW met1 ( 2118990 30090 ) M1M2_PR ;
+ - la_data_in[85] ( PIN la_data_in[85] ) ( mprj la_data_in[85] ) + USE SIGNAL
+ + ROUTED met1 ( 1829190 1652570 ) ( 1834710 * )
+ NEW met2 ( 2136470 1700 0 ) ( * 30430 )
+ NEW met2 ( 1829190 30430 ) ( * 1652570 )
+ NEW met2 ( 1834710 1688780 ) ( 1834870 * )
+ NEW met2 ( 1834870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1834710 1652570 ) ( * 1688780 )
+ NEW met1 ( 1829190 30430 ) ( 2136470 * )
+ NEW met1 ( 1829190 30430 ) M1M2_PR
+ NEW met1 ( 1829190 1652570 ) M1M2_PR
+ NEW met1 ( 1834710 1652570 ) M1M2_PR
+ NEW met1 ( 2136470 30430 ) M1M2_PR ;
+ - la_data_in[86] ( PIN la_data_in[86] ) ( mprj la_data_in[86] ) + USE SIGNAL
+ + ROUTED met2 ( 1836090 1652740 ) ( 1837010 * )
+ NEW met2 ( 2154410 1700 0 ) ( * 33830 )
+ NEW met2 ( 1836090 33830 ) ( * 1652740 )
+ NEW met1 ( 1837010 1689290 ) ( 1839930 * )
+ NEW met2 ( 1839930 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1837010 1652740 ) ( * 1689290 )
+ NEW met1 ( 1836090 33830 ) ( 2154410 * )
+ NEW met1 ( 1836090 33830 ) M1M2_PR
+ NEW met1 ( 2154410 33830 ) M1M2_PR
+ NEW met1 ( 1837010 1689290 ) M1M2_PR
+ NEW met1 ( 1839930 1689290 ) M1M2_PR ;
+ - la_data_in[87] ( PIN la_data_in[87] ) ( mprj la_data_in[87] ) + USE SIGNAL
+ + ROUTED met1 ( 1842530 1689290 ) ( 1845450 * )
+ NEW met2 ( 1845450 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1842530 33490 ) ( * 1689290 )
+ NEW met2 ( 2172350 1700 0 ) ( * 33490 )
+ NEW met1 ( 1842530 33490 ) ( 2172350 * )
+ NEW met1 ( 1842530 33490 ) M1M2_PR
+ NEW met1 ( 1842530 1689290 ) M1M2_PR
+ NEW met1 ( 1845450 1689290 ) M1M2_PR
+ NEW met1 ( 2172350 33490 ) M1M2_PR ;
+ - la_data_in[88] ( PIN la_data_in[88] ) ( mprj la_data_in[88] ) + USE SIGNAL
+ + ROUTED met2 ( 2189830 1700 0 ) ( * 33150 )
+ NEW met1 ( 1849430 33150 ) ( 2189830 * )
+ NEW met2 ( 1849430 1688780 ) ( 1850970 * )
+ NEW met2 ( 1850970 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1849430 33150 ) ( * 1688780 )
+ NEW met1 ( 1849430 33150 ) M1M2_PR
+ NEW met1 ( 2189830 33150 ) M1M2_PR ;
+ - la_data_in[89] ( PIN la_data_in[89] ) ( mprj la_data_in[89] ) + USE SIGNAL
+ + ROUTED met2 ( 2207770 1700 0 ) ( * 32810 )
+ NEW met1 ( 1856790 32810 ) ( 2207770 * )
+ NEW met2 ( 1856560 1688780 ) ( 1856790 * )
+ NEW met2 ( 1856560 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1856790 32810 ) ( * 1688780 )
+ NEW met1 ( 1856790 32810 ) M1M2_PR
+ NEW met1 ( 2207770 32810 ) M1M2_PR ;
+ - la_data_in[8] ( PIN la_data_in[8] ) ( mprj la_data_in[8] ) + USE SIGNAL
+ + ROUTED met2 ( 768890 1700 ) ( 771190 * 0 )
+ NEW met2 ( 766130 82800 ) ( * 88230 )
+ NEW met2 ( 766130 82800 ) ( 768890 * )
+ NEW met2 ( 768890 1700 ) ( * 82800 )
+ NEW met1 ( 766130 88230 ) ( 1407830 * )
+ NEW met1 ( 1407830 1652570 ) ( 1412890 * )
+ NEW met2 ( 1407830 88230 ) ( * 1652570 )
+ NEW met2 ( 1412890 1688780 ) ( 1413050 * )
+ NEW met2 ( 1413050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1412890 1652570 ) ( * 1688780 )
+ NEW met1 ( 766130 88230 ) M1M2_PR
+ NEW met1 ( 1407830 88230 ) M1M2_PR
+ NEW met1 ( 1407830 1652570 ) M1M2_PR
+ NEW met1 ( 1412890 1652570 ) M1M2_PR ;
+ - la_data_in[90] ( PIN la_data_in[90] ) ( mprj la_data_in[90] ) + USE SIGNAL
+ + ROUTED met1 ( 1856330 1652570 ) ( 1861850 * )
+ NEW met2 ( 2225250 1700 0 ) ( * 32470 )
+ NEW met2 ( 1856330 32470 ) ( * 1652570 )
+ NEW met1 ( 1856330 32470 ) ( 2225250 * )
+ NEW met2 ( 1861850 1688780 ) ( 1862010 * )
+ NEW met2 ( 1862010 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1861850 1652570 ) ( * 1688780 )
+ NEW met1 ( 1856330 32470 ) M1M2_PR
+ NEW met1 ( 1856330 1652570 ) M1M2_PR
+ NEW met1 ( 1861850 1652570 ) M1M2_PR
+ NEW met1 ( 2225250 32470 ) M1M2_PR ;
+ - la_data_in[91] ( PIN la_data_in[91] ) ( mprj la_data_in[91] ) + USE SIGNAL
+ + ROUTED met2 ( 2243190 1700 0 ) ( * 15300 )
+ NEW met2 ( 2242730 15300 ) ( 2243190 * )
+ NEW met2 ( 2242730 15300 ) ( * 68510 )
+ NEW met1 ( 1864150 68510 ) ( 2242730 * )
+ NEW met2 ( 1864150 1681300 ) ( 1866450 * )
+ NEW met2 ( 1866450 1681300 ) ( * 1688780 )
+ NEW met2 ( 1866450 1688780 ) ( 1867530 * )
+ NEW met2 ( 1867530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1864150 68510 ) ( * 1681300 )
+ NEW met1 ( 1864150 68510 ) M1M2_PR
+ NEW met1 ( 2242730 68510 ) M1M2_PR ;
+ - la_data_in[92] ( PIN la_data_in[92] ) ( mprj la_data_in[92] ) + USE SIGNAL
+ + ROUTED met2 ( 2258370 1700 ) ( 2260670 * 0 )
+ NEW met1 ( 1871050 68170 ) ( 2258370 * )
+ NEW met2 ( 2258370 1700 ) ( * 68170 )
+ NEW met2 ( 1871050 1688780 ) ( 1873050 * )
+ NEW met2 ( 1873050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1871050 68170 ) ( * 1688780 )
+ NEW met1 ( 1871050 68170 ) M1M2_PR
+ NEW met1 ( 2258370 68170 ) M1M2_PR ;
+ - la_data_in[93] ( PIN la_data_in[93] ) ( mprj la_data_in[93] ) + USE SIGNAL
+ + ROUTED met1 ( 1877490 67830 ) ( 2278610 * )
+ NEW met2 ( 2278610 1700 0 ) ( * 67830 )
+ NEW met2 ( 1877490 1688780 ) ( 1878570 * )
+ NEW met2 ( 1878570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1877490 67830 ) ( * 1688780 )
+ NEW met1 ( 1877490 67830 ) M1M2_PR
+ NEW met1 ( 2278610 67830 ) M1M2_PR ;
+ - la_data_in[94] ( PIN la_data_in[94] ) ( mprj la_data_in[94] ) + USE SIGNAL
+ + ROUTED met1 ( 1884850 67490 ) ( 2296090 * )
+ NEW met2 ( 2296090 1700 0 ) ( * 67490 )
+ NEW met2 ( 1884160 1688780 ) ( 1884850 * )
+ NEW met2 ( 1884160 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1884850 67490 ) ( * 1688780 )
+ NEW met1 ( 1884850 67490 ) M1M2_PR
+ NEW met1 ( 2296090 67490 ) M1M2_PR ;
+ - la_data_in[95] ( PIN la_data_in[95] ) ( mprj la_data_in[95] ) + USE SIGNAL
+ + ROUTED met2 ( 2311730 1700 ) ( 2314030 * 0 )
+ NEW met2 ( 2311730 1700 ) ( * 67150 )
+ NEW met1 ( 1884390 1652230 ) ( 1889450 * )
+ NEW met2 ( 1884390 67150 ) ( * 1652230 )
+ NEW met1 ( 1884390 67150 ) ( 2311730 * )
+ NEW met2 ( 1889450 1688780 ) ( 1889610 * )
+ NEW met2 ( 1889610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1889450 1652230 ) ( * 1688780 )
+ NEW met1 ( 2311730 67150 ) M1M2_PR
+ NEW met1 ( 1884390 1652230 ) M1M2_PR
+ NEW met1 ( 1889450 1652230 ) M1M2_PR
+ NEW met1 ( 1884390 67150 ) M1M2_PR ;
+ - la_data_in[96] ( PIN la_data_in[96] ) ( mprj la_data_in[96] ) + USE SIGNAL
+ + ROUTED met2 ( 2331510 1700 0 ) ( * 36890 )
+ NEW met1 ( 1890830 36890 ) ( 2331510 * )
+ NEW met1 ( 1890830 1688950 ) ( 1895130 * )
+ NEW met2 ( 1895130 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1890830 36890 ) ( * 1688950 )
+ NEW met1 ( 2331510 36890 ) M1M2_PR
+ NEW met1 ( 1890830 36890 ) M1M2_PR
+ NEW met1 ( 1890830 1688950 ) M1M2_PR
+ NEW met1 ( 1895130 1688950 ) M1M2_PR ;
+ - la_data_in[97] ( PIN la_data_in[97] ) ( mprj la_data_in[97] ) + USE SIGNAL
+ + ROUTED met2 ( 2349450 1700 0 ) ( * 37230 )
+ NEW met2 ( 1898190 37230 ) ( * 1676700 )
+ NEW met2 ( 1898190 1676700 ) ( 1899110 * )
+ NEW met2 ( 1899110 1676700 ) ( * 1688780 )
+ NEW met2 ( 1899110 1688780 ) ( 1900190 * )
+ NEW met2 ( 1900190 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1898190 37230 ) ( 2349450 * )
+ NEW met1 ( 2349450 37230 ) M1M2_PR
+ NEW met1 ( 1898190 37230 ) M1M2_PR ;
+ - la_data_in[98] ( PIN la_data_in[98] ) ( mprj la_data_in[98] ) + USE SIGNAL
+ + ROUTED met2 ( 1905090 1688780 ) ( 1905710 * )
+ NEW met2 ( 1905710 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1905090 37570 ) ( * 1688780 )
+ NEW met1 ( 1905090 37570 ) ( 2367390 * )
+ NEW met2 ( 2367390 1700 0 ) ( * 37570 )
+ NEW met1 ( 1905090 37570 ) M1M2_PR
+ NEW met1 ( 2367390 37570 ) M1M2_PR ;
+ - la_data_in[99] ( PIN la_data_in[99] ) ( mprj la_data_in[99] ) + USE SIGNAL
+ + ROUTED met1 ( 1904630 1652570 ) ( 1911070 * )
+ NEW met2 ( 1904630 41310 ) ( * 1652570 )
+ NEW met2 ( 1911070 1688780 ) ( 1911230 * )
+ NEW met2 ( 1911230 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1911070 1652570 ) ( * 1688780 )
+ NEW met1 ( 1904630 41310 ) ( 2384870 * )
+ NEW met2 ( 2384870 1700 0 ) ( * 41310 )
+ NEW met1 ( 1904630 1652570 ) M1M2_PR
+ NEW met1 ( 1911070 1652570 ) M1M2_PR
+ NEW met1 ( 1904630 41310 ) M1M2_PR
+ NEW met1 ( 2384870 41310 ) M1M2_PR ;
+ - la_data_in[9] ( PIN la_data_in[9] ) ( mprj la_data_in[9] ) + USE SIGNAL
+ + ROUTED met2 ( 789130 1700 0 ) ( * 38930 )
+ NEW met1 ( 1414730 1652570 ) ( 1417950 * )
+ NEW met2 ( 1417950 1688780 ) ( 1418110 * )
+ NEW met2 ( 1418110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1417950 1652570 ) ( * 1688780 )
+ NEW met1 ( 789130 38930 ) ( 1414730 * )
+ NEW met2 ( 1414730 38930 ) ( * 1652570 )
+ NEW met1 ( 789130 38930 ) M1M2_PR
+ NEW met1 ( 1414730 1652570 ) M1M2_PR
+ NEW met1 ( 1417950 1652570 ) M1M2_PR
+ NEW met1 ( 1414730 38930 ) M1M2_PR ;
+ - la_data_out[0] ( PIN la_data_out[0] ) ( mprj la_data_out[0] ) + USE SIGNAL
+ + ROUTED met1 ( 1366890 1652570 ) ( 1370570 * )
+ NEW met2 ( 1366890 37910 ) ( * 1652570 )
+ NEW met2 ( 1370570 1688780 ) ( 1370730 * )
+ NEW met2 ( 1370730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1370570 1652570 ) ( * 1688780 )
+ NEW met2 ( 635030 1700 0 ) ( * 17340 )
+ NEW met2 ( 635030 17340 ) ( 635490 * )
+ NEW met2 ( 635490 17340 ) ( * 37910 )
+ NEW met1 ( 635490 37910 ) ( 1366890 * )
+ NEW met1 ( 1366890 1652570 ) M1M2_PR
+ NEW met1 ( 1370570 1652570 ) M1M2_PR
+ NEW met1 ( 1366890 37910 ) M1M2_PR
+ NEW met1 ( 635490 37910 ) M1M2_PR ;
+ - la_data_out[100] ( PIN la_data_out[100] ) ( mprj la_data_out[100] ) + USE SIGNAL
+ + ROUTED met2 ( 1918660 1688780 ) ( 1918890 * )
+ NEW met2 ( 1918660 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1918890 40970 ) ( * 1688780 )
+ NEW met2 ( 2408790 1700 0 ) ( * 40970 )
+ NEW met1 ( 1918890 40970 ) ( 2408790 * )
+ NEW met1 ( 1918890 40970 ) M1M2_PR
+ NEW met1 ( 2408790 40970 ) M1M2_PR ;
+ - la_data_out[101] ( PIN la_data_out[101] ) ( mprj la_data_out[101] ) + USE SIGNAL
+ + ROUTED met1 ( 1918430 1652570 ) ( 1923950 * )
+ NEW met2 ( 1918430 40630 ) ( * 1652570 )
+ NEW met2 ( 1923950 1688780 ) ( 1924110 * )
+ NEW met2 ( 1924110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1923950 1652570 ) ( * 1688780 )
+ NEW met2 ( 2426270 1700 0 ) ( * 40630 )
+ NEW met1 ( 1918430 40630 ) ( 2426270 * )
+ NEW met1 ( 1918430 1652570 ) M1M2_PR
+ NEW met1 ( 1923950 1652570 ) M1M2_PR
+ NEW met1 ( 1918430 40630 ) M1M2_PR
+ NEW met1 ( 2426270 40630 ) M1M2_PR ;
+ - la_data_out[102] ( PIN la_data_out[102] ) ( mprj la_data_out[102] ) + USE SIGNAL
+ + ROUTED met1 ( 1925330 1688950 ) ( 1929630 * )
+ NEW met2 ( 1929630 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1925330 40290 ) ( * 1688950 )
+ NEW met2 ( 2444210 1700 0 ) ( * 40290 )
+ NEW met1 ( 1925330 40290 ) ( 2444210 * )
+ NEW met1 ( 1925330 40290 ) M1M2_PR
+ NEW met1 ( 1925330 1688950 ) M1M2_PR
+ NEW met1 ( 1929630 1688950 ) M1M2_PR
+ NEW met1 ( 2444210 40290 ) M1M2_PR ;
+ - la_data_out[103] ( PIN la_data_out[103] ) ( mprj la_data_out[103] ) + USE SIGNAL
+ + ROUTED met1 ( 1932230 1689290 ) ( 1935150 * )
+ NEW met2 ( 1935150 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1932230 39950 ) ( * 1689290 )
+ NEW met1 ( 1932230 39950 ) ( 2461690 * )
+ NEW met2 ( 2461690 1700 0 ) ( * 39950 )
+ NEW met1 ( 1932230 39950 ) M1M2_PR
+ NEW met1 ( 1932230 1689290 ) M1M2_PR
+ NEW met1 ( 1935150 1689290 ) M1M2_PR
+ NEW met1 ( 2461690 39950 ) M1M2_PR ;
+ - la_data_out[104] ( PIN la_data_out[104] ) ( mprj la_data_out[104] ) + USE SIGNAL
+ + ROUTED met2 ( 1939590 1688780 ) ( 1940670 * )
+ NEW met2 ( 1940670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1939590 39610 ) ( * 1688780 )
+ NEW met1 ( 1939590 39610 ) ( 2479630 * )
+ NEW met2 ( 2479630 1700 0 ) ( * 39610 )
+ NEW met1 ( 1939590 39610 ) M1M2_PR
+ NEW met1 ( 2479630 39610 ) M1M2_PR ;
+ - la_data_out[105] ( PIN la_data_out[105] ) ( mprj la_data_out[105] ) + USE SIGNAL
+ + ROUTED met2 ( 1946260 1688780 ) ( 1946490 * )
+ NEW met2 ( 1946260 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1946490 39270 ) ( * 1688780 )
+ NEW met1 ( 1946490 39270 ) ( 2497110 * )
+ NEW met2 ( 2497110 1700 0 ) ( * 39270 )
+ NEW met1 ( 1946490 39270 ) M1M2_PR
+ NEW met1 ( 2497110 39270 ) M1M2_PR ;
+ - la_data_out[106] ( PIN la_data_out[106] ) ( mprj la_data_out[106] ) + USE SIGNAL
+ + ROUTED met1 ( 1946950 1688950 ) ( 1951710 * )
+ NEW met2 ( 1951710 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1946950 38930 ) ( * 1688950 )
+ NEW met2 ( 2515050 1700 0 ) ( * 38930 )
+ NEW met1 ( 1946950 38930 ) ( 2515050 * )
+ NEW met1 ( 1946950 38930 ) M1M2_PR
+ NEW met1 ( 1946950 1688950 ) M1M2_PR
+ NEW met1 ( 1951710 1688950 ) M1M2_PR
+ NEW met1 ( 2515050 38930 ) M1M2_PR ;
+ - la_data_out[107] ( PIN la_data_out[107] ) ( mprj la_data_out[107] ) + USE SIGNAL
+ + ROUTED met1 ( 1953390 1688270 ) ( 1956770 * )
+ NEW met1 ( 1956770 1688270 ) ( * 1689290 )
+ NEW met2 ( 1956770 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1953390 38590 ) ( * 1688270 )
+ NEW met2 ( 2532530 1700 0 ) ( * 38590 )
+ NEW met1 ( 1953390 38590 ) ( 2532530 * )
+ NEW met1 ( 1953390 38590 ) M1M2_PR
+ NEW met1 ( 1953390 1688270 ) M1M2_PR
+ NEW met1 ( 1956770 1689290 ) M1M2_PR
+ NEW met1 ( 2532530 38590 ) M1M2_PR ;
+ - la_data_out[108] ( PIN la_data_out[108] ) ( mprj la_data_out[108] ) + USE SIGNAL
+ + ROUTED met2 ( 1960750 1688780 ) ( 1962290 * )
+ NEW met2 ( 1962290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1960750 38250 ) ( * 1688780 )
+ NEW met1 ( 1960750 38250 ) ( 2550470 * )
+ NEW met2 ( 2550470 1700 0 ) ( * 38250 )
+ NEW met1 ( 1960750 38250 ) M1M2_PR
+ NEW met1 ( 2550470 38250 ) M1M2_PR ;
+ - la_data_out[109] ( PIN la_data_out[109] ) ( mprj la_data_out[109] ) + USE SIGNAL
+ + ROUTED met2 ( 1967190 1688780 ) ( 1967810 * )
+ NEW met2 ( 1967810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1967190 37910 ) ( * 1688780 )
+ NEW met1 ( 1967190 37910 ) ( 2567950 * )
+ NEW met2 ( 2567950 1700 0 ) ( * 37910 )
+ NEW met1 ( 1967190 37910 ) M1M2_PR
+ NEW met1 ( 2567950 37910 ) M1M2_PR ;
+ - la_data_out[10] ( PIN la_data_out[10] ) ( mprj la_data_out[10] ) + USE SIGNAL
+ + ROUTED met1 ( 1421630 1637610 ) ( 1425310 * )
+ NEW met2 ( 812590 1700 0 ) ( * 37740 )
+ NEW met2 ( 1425310 1688780 ) ( 1425470 * )
+ NEW met2 ( 1425470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1425310 1637610 ) ( * 1688780 )
+ NEW met3 ( 812590 37740 ) ( 1421630 * )
+ NEW met2 ( 1421630 37740 ) ( * 1637610 )
+ NEW met1 ( 1421630 1637610 ) M1M2_PR
+ NEW met1 ( 1425310 1637610 ) M1M2_PR
+ NEW met2 ( 812590 37740 ) M2M3_PR
+ NEW met2 ( 1421630 37740 ) M2M3_PR ;
+ - la_data_out[110] ( PIN la_data_out[110] ) ( mprj la_data_out[110] ) + USE SIGNAL
+ + ROUTED met1 ( 1967650 1652570 ) ( 1973170 * )
+ NEW met2 ( 1967650 66810 ) ( * 1652570 )
+ NEW met2 ( 1973170 1688780 ) ( 1973330 * )
+ NEW met2 ( 1973330 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1973170 1652570 ) ( * 1688780 )
+ NEW met1 ( 1967650 66810 ) ( 2585890 * )
+ NEW met2 ( 2585890 1700 0 ) ( * 66810 )
+ NEW met1 ( 1967650 1652570 ) M1M2_PR
+ NEW met1 ( 1973170 1652570 ) M1M2_PR
+ NEW met1 ( 1967650 66810 ) M1M2_PR
+ NEW met1 ( 2585890 66810 ) M1M2_PR ;
+ - la_data_out[111] ( PIN la_data_out[111] ) ( mprj la_data_out[111] ) + USE SIGNAL
+ + ROUTED met2 ( 2601530 1700 ) ( 2603830 * 0 )
+ NEW met2 ( 2601530 1700 ) ( * 66470 )
+ NEW met1 ( 1974090 1688950 ) ( 1978850 * )
+ NEW met2 ( 1978850 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1974090 66470 ) ( * 1688950 )
+ NEW met1 ( 1974090 66470 ) ( 2601530 * )
+ NEW met1 ( 2601530 66470 ) M1M2_PR
+ NEW met1 ( 1974090 66470 ) M1M2_PR
+ NEW met1 ( 1974090 1688950 ) M1M2_PR
+ NEW met1 ( 1978850 1688950 ) M1M2_PR ;
+ - la_data_out[112] ( PIN la_data_out[112] ) ( mprj la_data_out[112] ) + USE SIGNAL
+ + ROUTED met2 ( 2619010 1700 ) ( 2621310 * 0 )
+ NEW met2 ( 2619010 1700 ) ( * 66130 )
+ NEW met1 ( 1980990 1652570 ) ( 1984210 * )
+ NEW met2 ( 1980990 66130 ) ( * 1652570 )
+ NEW met2 ( 1984210 1688780 ) ( 1984370 * )
+ NEW met2 ( 1984370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1984210 1652570 ) ( * 1688780 )
+ NEW met1 ( 1980990 66130 ) ( 2619010 * )
+ NEW met1 ( 2619010 66130 ) M1M2_PR
+ NEW met1 ( 1980990 1652570 ) M1M2_PR
+ NEW met1 ( 1984210 1652570 ) M1M2_PR
+ NEW met1 ( 1980990 66130 ) M1M2_PR ;
+ - la_data_out[113] ( PIN la_data_out[113] ) ( mprj la_data_out[113] ) + USE SIGNAL
+ + ROUTED met2 ( 2639250 1700 0 ) ( * 65790 )
+ NEW met2 ( 1988350 1688780 ) ( 1989890 * )
+ NEW met2 ( 1989890 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1988350 65790 ) ( * 1688780 )
+ NEW met1 ( 1988350 65790 ) ( 2639250 * )
+ NEW met1 ( 2639250 65790 ) M1M2_PR
+ NEW met1 ( 1988350 65790 ) M1M2_PR ;
+ - la_data_out[114] ( PIN la_data_out[114] ) ( mprj la_data_out[114] ) + USE SIGNAL
+ + ROUTED met2 ( 1994790 1688780 ) ( 1995410 * )
+ NEW met2 ( 1995410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1994790 44030 ) ( * 1688780 )
+ NEW met1 ( 1994790 44030 ) ( 2656730 * )
+ NEW met2 ( 2656730 1700 0 ) ( * 44030 )
+ NEW met1 ( 1994790 44030 ) M1M2_PR
+ NEW met1 ( 2656730 44030 ) M1M2_PR ;
+ - la_data_out[115] ( PIN la_data_out[115] ) ( mprj la_data_out[115] ) + USE SIGNAL
+ + ROUTED met1 ( 1995250 1652570 ) ( 2000770 * )
+ NEW met2 ( 1995250 44370 ) ( * 1652570 )
+ NEW met2 ( 2000770 1688780 ) ( 2000930 * )
+ NEW met2 ( 2000930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2000770 1652570 ) ( * 1688780 )
+ NEW met1 ( 1995250 44370 ) ( 2674670 * )
+ NEW met2 ( 2674670 1700 0 ) ( * 44370 )
+ NEW met1 ( 1995250 1652570 ) M1M2_PR
+ NEW met1 ( 2000770 1652570 ) M1M2_PR
+ NEW met1 ( 1995250 44370 ) M1M2_PR
+ NEW met1 ( 2674670 44370 ) M1M2_PR ;
+ - la_data_out[116] ( PIN la_data_out[116] ) ( mprj la_data_out[116] ) + USE SIGNAL
+ + ROUTED met2 ( 2692150 1700 0 ) ( * 48110 )
+ NEW met1 ( 2001690 1688950 ) ( 2006450 * )
+ NEW met2 ( 2006450 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 2001690 48110 ) ( * 1688950 )
+ NEW met1 ( 2001690 48110 ) ( 2692150 * )
+ NEW met1 ( 2692150 48110 ) M1M2_PR
+ NEW met1 ( 2001690 48110 ) M1M2_PR
+ NEW met1 ( 2001690 1688950 ) M1M2_PR
+ NEW met1 ( 2006450 1688950 ) M1M2_PR ;
+ - la_data_out[117] ( PIN la_data_out[117] ) ( mprj la_data_out[117] ) + USE SIGNAL
+ + ROUTED met2 ( 2710090 1700 0 ) ( * 47770 )
+ NEW met1 ( 2008590 1688270 ) ( 2011970 * )
+ NEW met1 ( 2011970 1688270 ) ( * 1689290 )
+ NEW met2 ( 2011970 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 2008590 47770 ) ( * 1688270 )
+ NEW met1 ( 2008590 47770 ) ( 2710090 * )
+ NEW met1 ( 2710090 47770 ) M1M2_PR
+ NEW met1 ( 2008590 47770 ) M1M2_PR
+ NEW met1 ( 2008590 1688270 ) M1M2_PR
+ NEW met1 ( 2011970 1689290 ) M1M2_PR ;
+ - la_data_out[118] ( PIN la_data_out[118] ) ( mprj la_data_out[118] ) + USE SIGNAL
+ + ROUTED met2 ( 2015490 47430 ) ( * 1676700 )
+ NEW met2 ( 2015490 1676700 ) ( 2015950 * )
+ NEW met2 ( 2015950 1676700 ) ( * 1689460 )
+ NEW met2 ( 2015950 1689460 ) ( 2017030 * )
+ NEW met2 ( 2017030 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 2727570 1700 0 ) ( * 47430 )
+ NEW met1 ( 2015490 47430 ) ( 2727570 * )
+ NEW met1 ( 2015490 47430 ) M1M2_PR
+ NEW met1 ( 2727570 47430 ) M1M2_PR ;
+ - la_data_out[119] ( PIN la_data_out[119] ) ( mprj la_data_out[119] ) + USE SIGNAL
+ + ROUTED met2 ( 2022390 1688780 ) ( 2022550 * )
+ NEW met2 ( 2022550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2022390 47090 ) ( * 1688780 )
+ NEW met1 ( 2022390 47090 ) ( 2745510 * )
+ NEW met2 ( 2745510 1700 0 ) ( * 47090 )
+ NEW met1 ( 2022390 47090 ) M1M2_PR
+ NEW met1 ( 2745510 47090 ) M1M2_PR ;
+ - la_data_out[11] ( PIN la_data_out[11] ) ( mprj la_data_out[11] ) + USE SIGNAL
+ + ROUTED met2 ( 830530 1700 0 ) ( * 39270 )
+ NEW met1 ( 1428530 1689290 ) ( 1430990 * )
+ NEW met2 ( 1430990 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 830530 39270 ) ( 1428530 * )
+ NEW met2 ( 1428530 39270 ) ( * 1689290 )
+ NEW met1 ( 830530 39270 ) M1M2_PR
+ NEW met1 ( 1428530 1689290 ) M1M2_PR
+ NEW met1 ( 1430990 1689290 ) M1M2_PR
+ NEW met1 ( 1428530 39270 ) M1M2_PR ;
+ - la_data_out[120] ( PIN la_data_out[120] ) ( mprj la_data_out[120] ) + USE SIGNAL
+ + ROUTED met1 ( 2022850 1652570 ) ( 2027910 * )
+ NEW met2 ( 2022850 46750 ) ( * 1652570 )
+ NEW met2 ( 2027910 1688780 ) ( 2028070 * )
+ NEW met2 ( 2028070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2027910 1652570 ) ( * 1688780 )
+ NEW met1 ( 2022850 46750 ) ( 2763450 * )
+ NEW met2 ( 2763450 1700 0 ) ( * 46750 )
+ NEW met1 ( 2022850 1652570 ) M1M2_PR
+ NEW met1 ( 2027910 1652570 ) M1M2_PR
+ NEW met1 ( 2022850 46750 ) M1M2_PR
+ NEW met1 ( 2763450 46750 ) M1M2_PR ;
+ - la_data_out[121] ( PIN la_data_out[121] ) ( mprj la_data_out[121] ) + USE SIGNAL
+ + ROUTED met1 ( 2029290 1688950 ) ( 2033590 * )
+ NEW met2 ( 2033590 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 2029290 46410 ) ( * 1688950 )
+ NEW met1 ( 2029290 46410 ) ( 2780930 * )
+ NEW met2 ( 2780930 1700 0 ) ( * 46410 )
+ NEW met1 ( 2029290 46410 ) M1M2_PR
+ NEW met1 ( 2029290 1688950 ) M1M2_PR
+ NEW met1 ( 2033590 1688950 ) M1M2_PR
+ NEW met1 ( 2780930 46410 ) M1M2_PR ;
+ - la_data_out[122] ( PIN la_data_out[122] ) ( mprj la_data_out[122] ) + USE SIGNAL
+ + ROUTED met2 ( 2036190 46070 ) ( * 1580100 )
+ NEW met2 ( 2036190 1580100 ) ( 2038490 * )
+ NEW met2 ( 2038490 1688780 ) ( 2039110 * )
+ NEW met2 ( 2039110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2038490 1580100 ) ( * 1688780 )
+ NEW met2 ( 2798870 1700 0 ) ( * 46070 )
+ NEW met1 ( 2036190 46070 ) ( 2798870 * )
+ NEW met1 ( 2036190 46070 ) M1M2_PR
+ NEW met1 ( 2798870 46070 ) M1M2_PR ;
+ - la_data_out[123] ( PIN la_data_out[123] ) ( mprj la_data_out[123] ) + USE SIGNAL
+ + ROUTED met2 ( 2043550 1689460 ) ( 2044630 * )
+ NEW met2 ( 2044630 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 2043550 45730 ) ( * 1689460 )
+ NEW met2 ( 2816350 1700 0 ) ( * 45730 )
+ NEW met1 ( 2043550 45730 ) ( 2816350 * )
+ NEW met1 ( 2043550 45730 ) M1M2_PR
+ NEW met1 ( 2816350 45730 ) M1M2_PR ;
+ - la_data_out[124] ( PIN la_data_out[124] ) ( mprj la_data_out[124] ) + USE SIGNAL
+ + ROUTED met2 ( 2049990 1688780 ) ( 2050150 * )
+ NEW met2 ( 2050150 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2049990 45390 ) ( * 1688780 )
+ NEW met2 ( 2834290 1700 0 ) ( * 45390 )
+ NEW met1 ( 2049990 45390 ) ( 2834290 * )
+ NEW met1 ( 2049990 45390 ) M1M2_PR
+ NEW met1 ( 2834290 45390 ) M1M2_PR ;
+ - la_data_out[125] ( PIN la_data_out[125] ) ( mprj la_data_out[125] ) + USE SIGNAL
+ + ROUTED met2 ( 2050450 45050 ) ( * 1580100 )
+ NEW met2 ( 2050450 1580100 ) ( 2052750 * )
+ NEW met2 ( 2052750 1688780 ) ( 2055670 * )
+ NEW met2 ( 2055670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2052750 1580100 ) ( * 1688780 )
+ NEW met1 ( 2050450 45050 ) ( 2851770 * )
+ NEW met2 ( 2851770 1700 0 ) ( * 45050 )
+ NEW met1 ( 2050450 45050 ) M1M2_PR
+ NEW met1 ( 2851770 45050 ) M1M2_PR ;
+ - la_data_out[126] ( PIN la_data_out[126] ) ( mprj la_data_out[126] ) + USE SIGNAL
+ + ROUTED met2 ( 2057350 44710 ) ( * 1580100 )
+ NEW met2 ( 2057350 1580100 ) ( 2061030 * )
+ NEW met2 ( 2061030 1688780 ) ( 2061190 * )
+ NEW met2 ( 2061190 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2061030 1580100 ) ( * 1688780 )
+ NEW met1 ( 2057350 44710 ) ( 2869710 * )
+ NEW met2 ( 2869710 1700 0 ) ( * 44710 )
+ NEW met1 ( 2057350 44710 ) M1M2_PR
+ NEW met1 ( 2869710 44710 ) M1M2_PR ;
+ - la_data_out[127] ( PIN la_data_out[127] ) ( mprj la_data_out[127] ) + USE SIGNAL
+ + ROUTED met2 ( 2887190 1700 0 ) ( * 44540 )
+ NEW met2 ( 2063790 44540 ) ( * 1676700 )
+ NEW met2 ( 2063790 1676700 ) ( 2065630 * )
+ NEW met2 ( 2065630 1676700 ) ( * 1688780 )
+ NEW met2 ( 2065630 1688780 ) ( 2066710 * )
+ NEW met2 ( 2066710 1688780 ) ( * 1690140 0 )
+ NEW met3 ( 2063790 44540 ) ( 2887190 * )
+ NEW met2 ( 2887190 44540 ) M2M3_PR
+ NEW met2 ( 2063790 44540 ) M2M3_PR ;
+ - la_data_out[12] ( PIN la_data_out[12] ) ( mprj la_data_out[12] ) + USE SIGNAL
+ + ROUTED met2 ( 1435430 1688780 ) ( 1436510 * )
+ NEW met2 ( 1436510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 848010 1700 0 ) ( * 39610 )
+ NEW met1 ( 848010 39610 ) ( 1435430 * )
+ NEW met2 ( 1435430 39610 ) ( * 1688780 )
+ NEW met1 ( 848010 39610 ) M1M2_PR
+ NEW met1 ( 1435430 39610 ) M1M2_PR ;
+ - la_data_out[13] ( PIN la_data_out[13] ) ( mprj la_data_out[13] ) + USE SIGNAL
+ + ROUTED met1 ( 1435890 1652570 ) ( 1441870 * )
+ NEW met2 ( 865950 1700 0 ) ( * 39950 )
+ NEW met2 ( 1441870 1688780 ) ( 1442030 * )
+ NEW met2 ( 1442030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1441870 1652570 ) ( * 1688780 )
+ NEW met1 ( 865950 39950 ) ( 1435890 * )
+ NEW met2 ( 1435890 39950 ) ( * 1652570 )
+ NEW met1 ( 1435890 1652570 ) M1M2_PR
+ NEW met1 ( 1441870 1652570 ) M1M2_PR
+ NEW met1 ( 865950 39950 ) M1M2_PR
+ NEW met1 ( 1435890 39950 ) M1M2_PR ;
+ - la_data_out[14] ( PIN la_data_out[14] ) ( mprj la_data_out[14] ) + USE SIGNAL
+ + ROUTED met2 ( 883430 1700 0 ) ( * 17340 )
+ NEW met2 ( 883430 17340 ) ( 883890 * )
+ NEW met2 ( 883890 17340 ) ( * 40290 )
+ NEW met2 ( 1443250 1580100 ) ( 1446930 * )
+ NEW met2 ( 1446930 1688780 ) ( 1447550 * )
+ NEW met2 ( 1447550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1446930 1580100 ) ( * 1688780 )
+ NEW met1 ( 883890 40290 ) ( 1443250 * )
+ NEW met2 ( 1443250 40290 ) ( * 1580100 )
+ NEW met1 ( 883890 40290 ) M1M2_PR
+ NEW met1 ( 1443250 40290 ) M1M2_PR ;
+ - la_data_out[15] ( PIN la_data_out[15] ) ( mprj la_data_out[15] ) + USE SIGNAL
+ + ROUTED met2 ( 901370 1700 0 ) ( * 40630 )
+ NEW met2 ( 1450610 1580100 ) ( 1452450 * )
+ NEW met2 ( 1452450 1688780 ) ( 1453070 * )
+ NEW met2 ( 1453070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1452450 1580100 ) ( * 1688780 )
+ NEW met1 ( 901370 40630 ) ( 1450610 * )
+ NEW met2 ( 1450610 40630 ) ( * 1580100 )
+ NEW met1 ( 901370 40630 ) M1M2_PR
+ NEW met1 ( 1450610 40630 ) M1M2_PR ;
+ - la_data_out[16] ( PIN la_data_out[16] ) ( mprj la_data_out[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1457510 1688780 ) ( 1458590 * )
+ NEW met2 ( 1458590 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 918850 1700 0 ) ( * 40970 )
+ NEW met1 ( 918850 40970 ) ( 1457510 * )
+ NEW met2 ( 1457510 40970 ) ( * 1688780 )
+ NEW met1 ( 918850 40970 ) M1M2_PR
+ NEW met1 ( 1457510 40970 ) M1M2_PR ;
+ - la_data_out[17] ( PIN la_data_out[17] ) ( mprj la_data_out[17] ) + USE SIGNAL
+ + ROUTED met2 ( 1463490 1688780 ) ( 1464110 * )
+ NEW met2 ( 1464110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1463490 41310 ) ( * 1688780 )
+ NEW met2 ( 936790 1700 0 ) ( * 41310 )
+ NEW met1 ( 936790 41310 ) ( 1463490 * )
+ NEW met1 ( 1463490 41310 ) M1M2_PR
+ NEW met1 ( 936790 41310 ) M1M2_PR ;
+ - la_data_out[18] ( PIN la_data_out[18] ) ( mprj la_data_out[18] ) + USE SIGNAL
+ + ROUTED met1 ( 1463950 1643730 ) ( 1469470 * )
+ NEW met2 ( 954270 1700 0 ) ( * 37570 )
+ NEW met2 ( 1463950 37570 ) ( * 1643730 )
+ NEW met2 ( 1469470 1688780 ) ( 1469630 * )
+ NEW met2 ( 1469630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1469470 1643730 ) ( * 1688780 )
+ NEW met1 ( 954270 37570 ) ( 1463950 * )
+ NEW met1 ( 1463950 1643730 ) M1M2_PR
+ NEW met1 ( 1469470 1643730 ) M1M2_PR
+ NEW met1 ( 954270 37570 ) M1M2_PR
+ NEW met1 ( 1463950 37570 ) M1M2_PR ;
+ - la_data_out[19] ( PIN la_data_out[19] ) ( mprj la_data_out[19] ) + USE SIGNAL
+ + ROUTED met2 ( 972210 1700 0 ) ( * 37230 )
+ NEW met1 ( 1470390 1688950 ) ( 1475150 * )
+ NEW met2 ( 1475150 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1470390 37230 ) ( * 1688950 )
+ NEW met1 ( 972210 37230 ) ( 1470390 * )
+ NEW met1 ( 972210 37230 ) M1M2_PR
+ NEW met1 ( 1470390 37230 ) M1M2_PR
+ NEW met1 ( 1470390 1688950 ) M1M2_PR
+ NEW met1 ( 1475150 1688950 ) M1M2_PR ;
+ - la_data_out[1] ( PIN la_data_out[1] ) ( mprj la_data_out[1] ) + USE SIGNAL
+ + ROUTED met1 ( 1374250 1688270 ) ( 1376250 * )
+ NEW met1 ( 1376250 1688270 ) ( * 1689290 )
+ NEW met2 ( 1376250 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1374250 38250 ) ( * 1688270 )
+ NEW met2 ( 652970 1700 0 ) ( * 38250 )
+ NEW met1 ( 652970 38250 ) ( 1374250 * )
+ NEW met1 ( 1374250 38250 ) M1M2_PR
+ NEW met1 ( 1374250 1688270 ) M1M2_PR
+ NEW met1 ( 1376250 1689290 ) M1M2_PR
+ NEW met1 ( 652970 38250 ) M1M2_PR ;
+ - la_data_out[20] ( PIN la_data_out[20] ) ( mprj la_data_out[20] ) + USE SIGNAL
+ + ROUTED met2 ( 989690 1700 0 ) ( * 36890 )
+ NEW met2 ( 1477290 36890 ) ( * 1676700 )
+ NEW met2 ( 1477290 1676700 ) ( 1480050 * )
+ NEW met2 ( 1480050 1676700 ) ( * 1688780 )
+ NEW met2 ( 1480050 1688780 ) ( 1480210 * )
+ NEW met2 ( 1480210 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 989690 36890 ) ( 1477290 * )
+ NEW met1 ( 989690 36890 ) M1M2_PR
+ NEW met1 ( 1477290 36890 ) M1M2_PR ;
+ - la_data_out[21] ( PIN la_data_out[21] ) ( mprj la_data_out[21] ) + USE SIGNAL
+ + ROUTED met1 ( 1008090 89250 ) ( 1484650 * )
+ NEW met2 ( 1007630 1700 0 ) ( * 34500 )
+ NEW met2 ( 1007630 34500 ) ( 1008090 * )
+ NEW met2 ( 1008090 34500 ) ( * 89250 )
+ NEW met2 ( 1484650 1688780 ) ( 1485730 * )
+ NEW met2 ( 1485730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1484650 89250 ) ( * 1688780 )
+ NEW met1 ( 1008090 89250 ) M1M2_PR
+ NEW met1 ( 1484650 89250 ) M1M2_PR ;
+ - la_data_out[22] ( PIN la_data_out[22] ) ( mprj la_data_out[22] ) + USE SIGNAL
+ + ROUTED met1 ( 1021430 89590 ) ( 1491550 * )
+ NEW met2 ( 1021430 82800 ) ( * 89590 )
+ NEW met2 ( 1021430 82800 ) ( 1025570 * )
+ NEW met2 ( 1025570 1700 0 ) ( * 82800 )
+ NEW met2 ( 1491320 1688780 ) ( 1491550 * )
+ NEW met2 ( 1491320 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1491550 89590 ) ( * 1688780 )
+ NEW met1 ( 1021430 89590 ) M1M2_PR
+ NEW met1 ( 1491550 89590 ) M1M2_PR ;
+ - la_data_out[23] ( PIN la_data_out[23] ) ( mprj la_data_out[23] ) + USE SIGNAL
+ + ROUTED met1 ( 1042130 85850 ) ( 1492010 * )
+ NEW met2 ( 1042130 82800 ) ( * 85850 )
+ NEW met2 ( 1042130 82800 ) ( 1043050 * )
+ NEW met2 ( 1043050 1700 0 ) ( * 82800 )
+ NEW met2 ( 1492010 1688780 ) ( 1496770 * )
+ NEW met2 ( 1496770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1492010 85850 ) ( * 1688780 )
+ NEW met1 ( 1042130 85850 ) M1M2_PR
+ NEW met1 ( 1492010 85850 ) M1M2_PR ;
+ - la_data_out[24] ( PIN la_data_out[24] ) ( mprj la_data_out[24] ) + USE SIGNAL
+ + ROUTED met2 ( 1058690 1700 ) ( 1060990 * 0 )
+ NEW met2 ( 1055930 82800 ) ( * 85510 )
+ NEW met2 ( 1055930 82800 ) ( 1058690 * )
+ NEW met2 ( 1058690 1700 ) ( * 82800 )
+ NEW met1 ( 1055930 85510 ) ( 1498910 * )
+ NEW met2 ( 1498910 1688780 ) ( 1502290 * )
+ NEW met2 ( 1502290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1498910 85510 ) ( * 1688780 )
+ NEW met1 ( 1055930 85510 ) M1M2_PR
+ NEW met1 ( 1498910 85510 ) M1M2_PR ;
+ - la_data_out[25] ( PIN la_data_out[25] ) ( mprj la_data_out[25] ) + USE SIGNAL
+ + ROUTED met2 ( 1076630 1700 ) ( 1078470 * 0 )
+ NEW met2 ( 1076630 1700 ) ( * 85170 )
+ NEW met1 ( 1076630 85170 ) ( 1505350 * )
+ NEW met2 ( 1505350 1688780 ) ( 1507810 * )
+ NEW met2 ( 1507810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1505350 85170 ) ( * 1688780 )
+ NEW met1 ( 1076630 85170 ) M1M2_PR
+ NEW met1 ( 1505350 85170 ) M1M2_PR ;
+ - la_data_out[26] ( PIN la_data_out[26] ) ( mprj la_data_out[26] ) + USE SIGNAL
+ + ROUTED met2 ( 1096410 1700 0 ) ( * 47770 )
+ NEW met2 ( 1511790 1688780 ) ( 1513330 * )
+ NEW met2 ( 1513330 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1511790 47770 ) ( * 1688780 )
+ NEW met1 ( 1096410 47770 ) ( 1511790 * )
+ NEW met1 ( 1096410 47770 ) M1M2_PR
+ NEW met1 ( 1511790 47770 ) M1M2_PR ;
+ - la_data_out[27] ( PIN la_data_out[27] ) ( mprj la_data_out[27] ) + USE SIGNAL
+ + ROUTED met2 ( 1113890 1700 0 ) ( * 48110 )
+ NEW met2 ( 1518690 1688780 ) ( 1518850 * )
+ NEW met2 ( 1518850 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1518690 48110 ) ( * 1688780 )
+ NEW met1 ( 1113890 48110 ) ( 1518690 * )
+ NEW met1 ( 1113890 48110 ) M1M2_PR
+ NEW met1 ( 1518690 48110 ) M1M2_PR ;
+ - la_data_out[28] ( PIN la_data_out[28] ) ( mprj la_data_out[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1131830 1700 0 ) ( * 17340 )
+ NEW met2 ( 1131830 17340 ) ( 1132290 * )
+ NEW met2 ( 1132290 17340 ) ( * 44370 )
+ NEW met1 ( 1518230 1688950 ) ( 1524370 * )
+ NEW met2 ( 1524370 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1518230 44370 ) ( * 1688950 )
+ NEW met1 ( 1132290 44370 ) ( 1518230 * )
+ NEW met1 ( 1132290 44370 ) M1M2_PR
+ NEW met1 ( 1518230 44370 ) M1M2_PR
+ NEW met1 ( 1518230 1688950 ) M1M2_PR
+ NEW met1 ( 1524370 1688950 ) M1M2_PR ;
+ - la_data_out[29] ( PIN la_data_out[29] ) ( mprj la_data_out[29] ) + USE SIGNAL
+ + ROUTED met2 ( 1149310 1700 0 ) ( * 44030 )
+ NEW met1 ( 1525130 1688950 ) ( 1529890 * )
+ NEW met2 ( 1529890 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1525130 44030 ) ( * 1688950 )
+ NEW met1 ( 1149310 44030 ) ( 1525130 * )
+ NEW met1 ( 1149310 44030 ) M1M2_PR
+ NEW met1 ( 1525130 44030 ) M1M2_PR
+ NEW met1 ( 1525130 1688950 ) M1M2_PR
+ NEW met1 ( 1529890 1688950 ) M1M2_PR ;
+ - la_data_out[2] ( PIN la_data_out[2] ) ( mprj la_data_out[2] ) + USE SIGNAL
+ + ROUTED met2 ( 670910 1700 0 ) ( * 38590 )
+ NEW met2 ( 1381150 1688780 ) ( 1381770 * )
+ NEW met2 ( 1381770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1381150 38590 ) ( * 1688780 )
+ NEW met1 ( 670910 38590 ) ( 1381150 * )
+ NEW met1 ( 670910 38590 ) M1M2_PR
+ NEW met1 ( 1381150 38590 ) M1M2_PR ;
+ - la_data_out[30] ( PIN la_data_out[30] ) ( mprj la_data_out[30] ) + USE SIGNAL
+ + ROUTED met2 ( 1167250 1700 0 ) ( * 43690 )
+ NEW met2 ( 1532950 43690 ) ( * 1676700 )
+ NEW met2 ( 1532950 1676700 ) ( 1534790 * )
+ NEW met2 ( 1534790 1676700 ) ( * 1688780 )
+ NEW met2 ( 1534790 1688780 ) ( 1535410 * )
+ NEW met2 ( 1535410 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1167250 43690 ) ( 1532950 * )
+ NEW met1 ( 1167250 43690 ) M1M2_PR
+ NEW met1 ( 1532950 43690 ) M1M2_PR ;
+ - la_data_out[31] ( PIN la_data_out[31] ) ( mprj la_data_out[31] ) + USE SIGNAL
+ + ROUTED met2 ( 1185190 1700 0 ) ( * 30770 )
+ NEW met2 ( 1539390 1688780 ) ( 1540470 * )
+ NEW met2 ( 1540470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1539390 30770 ) ( * 1688780 )
+ NEW met1 ( 1185190 30770 ) ( 1539390 * )
+ NEW met1 ( 1185190 30770 ) M1M2_PR
+ NEW met1 ( 1539390 30770 ) M1M2_PR ;
+ - la_data_out[32] ( PIN la_data_out[32] ) ( mprj la_data_out[32] ) + USE SIGNAL
+ + ROUTED met2 ( 1546290 1653420 ) ( 1547210 * )
+ NEW met2 ( 1547210 31450 ) ( * 1653420 )
+ NEW met2 ( 1546060 1688780 ) ( 1546290 * )
+ NEW met2 ( 1546060 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1546290 1653420 ) ( * 1688780 )
+ NEW met2 ( 1202670 1700 0 ) ( * 31450 )
+ NEW met1 ( 1202670 31450 ) ( 1547210 * )
+ NEW met1 ( 1547210 31450 ) M1M2_PR
+ NEW met1 ( 1202670 31450 ) M1M2_PR ;
+ - la_data_out[33] ( PIN la_data_out[33] ) ( mprj la_data_out[33] ) + USE SIGNAL
+ + ROUTED met2 ( 1551350 1682830 ) ( * 1688780 )
+ NEW met2 ( 1551350 1688780 ) ( 1551510 * )
+ NEW met2 ( 1551510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1220610 1700 0 ) ( * 16830 )
+ NEW met1 ( 1220610 16830 ) ( 1328250 * )
+ NEW met2 ( 1328250 16830 ) ( * 1682830 )
+ NEW met1 ( 1328250 1682830 ) ( 1551350 * )
+ NEW met1 ( 1551350 1682830 ) M1M2_PR
+ NEW met1 ( 1220610 16830 ) M1M2_PR
+ NEW met1 ( 1328250 16830 ) M1M2_PR
+ NEW met1 ( 1328250 1682830 ) M1M2_PR ;
+ - la_data_out[34] ( PIN la_data_out[34] ) ( mprj la_data_out[34] ) + USE SIGNAL
+ + ROUTED met1 ( 1553190 1639650 ) ( 1556870 * )
+ NEW met2 ( 1553190 24140 ) ( * 1639650 )
+ NEW met2 ( 1556870 1688780 ) ( 1557030 * )
+ NEW met2 ( 1557030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1556870 1639650 ) ( * 1688780 )
+ NEW met2 ( 1238090 1700 0 ) ( * 18190 )
+ NEW met2 ( 1495230 18190 ) ( * 24140 )
+ NEW met3 ( 1495230 24140 ) ( 1553190 * )
+ NEW met1 ( 1238090 18190 ) ( 1495230 * )
+ NEW met2 ( 1553190 24140 ) M2M3_PR
+ NEW met1 ( 1553190 1639650 ) M1M2_PR
+ NEW met1 ( 1556870 1639650 ) M1M2_PR
+ NEW met1 ( 1238090 18190 ) M1M2_PR
+ NEW met1 ( 1495230 18190 ) M1M2_PR
+ NEW met2 ( 1495230 24140 ) M2M3_PR ;
+ - la_data_out[35] ( PIN la_data_out[35] ) ( mprj la_data_out[35] ) + USE SIGNAL
+ + ROUTED met2 ( 1256030 1700 0 ) ( * 32130 )
+ NEW met2 ( 1560550 1688780 ) ( 1562550 * )
+ NEW met2 ( 1562550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1560550 32130 ) ( * 1688780 )
+ NEW met1 ( 1256030 32130 ) ( 1560550 * )
+ NEW met1 ( 1256030 32130 ) M1M2_PR
+ NEW met1 ( 1560550 32130 ) M1M2_PR ;
+ - la_data_out[36] ( PIN la_data_out[36] ) ( mprj la_data_out[36] ) + USE SIGNAL
+ + ROUTED met2 ( 1273510 1700 0 ) ( * 32470 )
+ NEW met2 ( 1566990 1688780 ) ( 1568070 * )
+ NEW met2 ( 1568070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1566990 32470 ) ( * 1688780 )
+ NEW met1 ( 1273510 32470 ) ( 1566990 * )
+ NEW met1 ( 1273510 32470 ) M1M2_PR
+ NEW met1 ( 1566990 32470 ) M1M2_PR ;
+ - la_data_out[37] ( PIN la_data_out[37] ) ( mprj la_data_out[37] ) + USE SIGNAL
+ + ROUTED met2 ( 1573660 1688780 ) ( 1573890 * )
+ NEW met2 ( 1573660 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1573890 32810 ) ( * 1688780 )
+ NEW met2 ( 1291450 1700 0 ) ( * 32810 )
+ NEW met1 ( 1291450 32810 ) ( 1573890 * )
+ NEW met1 ( 1573890 32810 ) M1M2_PR
+ NEW met1 ( 1291450 32810 ) M1M2_PR ;
+ - la_data_out[38] ( PIN la_data_out[38] ) ( mprj la_data_out[38] ) + USE SIGNAL
+ + ROUTED met1 ( 1574350 1688950 ) ( 1579110 * )
+ NEW met2 ( 1579110 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1574350 33150 ) ( * 1688950 )
+ NEW met2 ( 1308930 1700 0 ) ( * 33150 )
+ NEW met1 ( 1308930 33150 ) ( 1574350 * )
+ NEW met1 ( 1574350 33150 ) M1M2_PR
+ NEW met1 ( 1574350 1688950 ) M1M2_PR
+ NEW met1 ( 1579110 1688950 ) M1M2_PR
+ NEW met1 ( 1308930 33150 ) M1M2_PR ;
+ - la_data_out[39] ( PIN la_data_out[39] ) ( mprj la_data_out[39] ) + USE SIGNAL
+ + ROUTED met2 ( 1326870 1700 0 ) ( * 33490 )
+ NEW met2 ( 1581250 1688780 ) ( 1584630 * )
+ NEW met2 ( 1584630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1581250 33490 ) ( * 1688780 )
+ NEW met1 ( 1326870 33490 ) ( 1581250 * )
+ NEW met1 ( 1326870 33490 ) M1M2_PR
+ NEW met1 ( 1581250 33490 ) M1M2_PR ;
+ - la_data_out[3] ( PIN la_data_out[3] ) ( mprj la_data_out[3] ) + USE SIGNAL
+ + ROUTED met2 ( 688390 1700 0 ) ( * 47090 )
+ NEW met1 ( 688390 47090 ) ( 1387590 * )
+ NEW met2 ( 1387360 1688780 ) ( 1387590 * )
+ NEW met2 ( 1387360 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1387590 47090 ) ( * 1688780 )
+ NEW met1 ( 688390 47090 ) M1M2_PR
+ NEW met1 ( 1387590 47090 ) M1M2_PR ;
+ - la_data_out[40] ( PIN la_data_out[40] ) ( mprj la_data_out[40] ) + USE SIGNAL
+ + ROUTED met2 ( 1344350 1700 0 ) ( * 33830 )
+ NEW met2 ( 1588610 1688780 ) ( 1590150 * )
+ NEW met2 ( 1590150 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1588610 33830 ) ( * 1688780 )
+ NEW met1 ( 1344350 33830 ) ( 1588610 * )
+ NEW met1 ( 1344350 33830 ) M1M2_PR
+ NEW met1 ( 1588610 33830 ) M1M2_PR ;
+ - la_data_out[41] ( PIN la_data_out[41] ) ( mprj la_data_out[41] ) + USE SIGNAL
+ + ROUTED met2 ( 1362290 1700 0 ) ( * 34170 )
+ NEW met2 ( 1595050 1688780 ) ( 1595670 * )
+ NEW met2 ( 1595670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1595050 34170 ) ( * 1688780 )
+ NEW met1 ( 1362290 34170 ) ( 1595050 * )
+ NEW met1 ( 1362290 34170 ) M1M2_PR
+ NEW met1 ( 1595050 34170 ) M1M2_PR ;
+ - la_data_out[42] ( PIN la_data_out[42] ) ( mprj la_data_out[42] ) + USE SIGNAL
+ + ROUTED met2 ( 1380230 1700 0 ) ( * 30090 )
+ NEW met1 ( 1380230 30090 ) ( 1386900 * )
+ NEW met1 ( 1386900 30090 ) ( * 30430 )
+ NEW met1 ( 1595510 1652570 ) ( 1600570 * )
+ NEW met2 ( 1595510 30430 ) ( * 1652570 )
+ NEW met2 ( 1600570 1688780 ) ( 1600730 * )
+ NEW met2 ( 1600730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1600570 1652570 ) ( * 1688780 )
+ NEW met1 ( 1386900 30430 ) ( 1595510 * )
+ NEW met1 ( 1380230 30090 ) M1M2_PR
+ NEW met1 ( 1595510 30430 ) M1M2_PR
+ NEW met1 ( 1595510 1652570 ) M1M2_PR
+ NEW met1 ( 1600570 1652570 ) M1M2_PR ;
+ - la_data_out[43] ( PIN la_data_out[43] ) ( mprj la_data_out[43] ) + USE SIGNAL
+ + ROUTED met2 ( 1397710 1700 0 ) ( * 30090 )
+ NEW met1 ( 1601490 1688950 ) ( 1606250 * )
+ NEW met2 ( 1606250 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1601490 30090 ) ( * 1688950 )
+ NEW met1 ( 1397710 30090 ) ( 1601490 * )
+ NEW met1 ( 1397710 30090 ) M1M2_PR
+ NEW met1 ( 1601490 30090 ) M1M2_PR
+ NEW met1 ( 1601490 1688950 ) M1M2_PR
+ NEW met1 ( 1606250 1688950 ) M1M2_PR ;
+ - la_data_out[44] ( PIN la_data_out[44] ) ( mprj la_data_out[44] ) + USE SIGNAL
+ + ROUTED met2 ( 1609310 18530 ) ( * 1580100 )
+ NEW met2 ( 1609310 1580100 ) ( 1610230 * )
+ NEW met2 ( 1610230 1688780 ) ( 1611770 * )
+ NEW met2 ( 1611770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1610230 1580100 ) ( * 1688780 )
+ NEW met2 ( 1415650 1700 0 ) ( * 18530 )
+ NEW met1 ( 1415650 18530 ) ( 1609310 * )
+ NEW met1 ( 1609310 18530 ) M1M2_PR
+ NEW met1 ( 1415650 18530 ) M1M2_PR ;
+ - la_data_out[45] ( PIN la_data_out[45] ) ( mprj la_data_out[45] ) + USE SIGNAL
+ + ROUTED met2 ( 1528810 16490 ) ( * 1678750 )
+ NEW met2 ( 1615750 1678750 ) ( * 1689460 )
+ NEW met2 ( 1615750 1689460 ) ( 1617290 * )
+ NEW met2 ( 1617290 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1528810 1678750 ) ( 1615750 * )
+ NEW met2 ( 1433130 1700 0 ) ( * 16490 )
+ NEW met1 ( 1433130 16490 ) ( 1528810 * )
+ NEW met1 ( 1528810 16490 ) M1M2_PR
+ NEW met1 ( 1528810 1678750 ) M1M2_PR
+ NEW met1 ( 1615750 1678750 ) M1M2_PR
+ NEW met1 ( 1433130 16490 ) M1M2_PR ;
+ - la_data_out[46] ( PIN la_data_out[46] ) ( mprj la_data_out[46] ) + USE SIGNAL
+ + ROUTED met2 ( 1622650 1688780 ) ( 1622810 * )
+ NEW met2 ( 1622810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1622650 19550 ) ( * 1688780 )
+ NEW met2 ( 1451070 1700 0 ) ( * 19550 )
+ NEW met1 ( 1451070 19550 ) ( 1622650 * )
+ NEW met1 ( 1622650 19550 ) M1M2_PR
+ NEW met1 ( 1451070 19550 ) M1M2_PR ;
+ - la_data_out[47] ( PIN la_data_out[47] ) ( mprj la_data_out[47] ) + USE SIGNAL
+ + ROUTED met2 ( 1468550 1700 0 ) ( * 20230 )
+ NEW met1 ( 1468550 20230 ) ( 1528350 * )
+ NEW met2 ( 1528350 20230 ) ( * 1679090 )
+ NEW met2 ( 1628170 1679090 ) ( * 1688780 )
+ NEW met2 ( 1628170 1688780 ) ( 1628330 * )
+ NEW met2 ( 1628330 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1528350 1679090 ) ( 1628170 * )
+ NEW met1 ( 1468550 20230 ) M1M2_PR
+ NEW met1 ( 1528350 20230 ) M1M2_PR
+ NEW met1 ( 1528350 1679090 ) M1M2_PR
+ NEW met1 ( 1628170 1679090 ) M1M2_PR ;
+ - la_data_out[48] ( PIN la_data_out[48] ) ( mprj la_data_out[48] ) + USE SIGNAL
+ + ROUTED met2 ( 1562850 15470 ) ( * 1680790 )
+ NEW met2 ( 1633690 1680790 ) ( * 1688780 )
+ NEW met2 ( 1633690 1688780 ) ( 1633850 * )
+ NEW met2 ( 1633850 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1486490 1700 0 ) ( * 15470 )
+ NEW met1 ( 1486490 15470 ) ( 1562850 * )
+ NEW met1 ( 1562850 1680790 ) ( 1633690 * )
+ NEW met1 ( 1562850 15470 ) M1M2_PR
+ NEW met1 ( 1562850 1680790 ) M1M2_PR
+ NEW met1 ( 1633690 1680790 ) M1M2_PR
+ NEW met1 ( 1486490 15470 ) M1M2_PR ;
+ - la_data_out[49] ( PIN la_data_out[49] ) ( mprj la_data_out[49] ) + USE SIGNAL
+ + ROUTED met2 ( 1535250 20570 ) ( * 1580100 )
+ NEW met2 ( 1535250 1580100 ) ( 1535710 * )
+ NEW met2 ( 1535710 1580100 ) ( * 1679430 )
+ NEW met2 ( 1639210 1679430 ) ( * 1688780 )
+ NEW met2 ( 1639210 1688780 ) ( 1639370 * )
+ NEW met2 ( 1639370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1503970 1700 0 ) ( * 20570 )
+ NEW met1 ( 1503970 20570 ) ( 1535250 * )
+ NEW met1 ( 1535710 1679430 ) ( 1639210 * )
+ NEW met1 ( 1535250 20570 ) M1M2_PR
+ NEW met1 ( 1535710 1679430 ) M1M2_PR
+ NEW met1 ( 1639210 1679430 ) M1M2_PR
+ NEW met1 ( 1503970 20570 ) M1M2_PR ;
+ - la_data_out[4] ( PIN la_data_out[4] ) ( mprj la_data_out[4] ) + USE SIGNAL
+ + ROUTED met2 ( 706330 1700 0 ) ( * 47430 )
+ NEW met1 ( 706330 47430 ) ( 1388050 * )
+ NEW met1 ( 1388050 1688950 ) ( 1392810 * )
+ NEW met2 ( 1392810 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1388050 47430 ) ( * 1688950 )
+ NEW met1 ( 706330 47430 ) M1M2_PR
+ NEW met1 ( 1388050 47430 ) M1M2_PR
+ NEW met1 ( 1388050 1688950 ) M1M2_PR
+ NEW met1 ( 1392810 1688950 ) M1M2_PR ;
+ - la_data_out[50] ( PIN la_data_out[50] ) ( mprj la_data_out[50] ) + USE SIGNAL
+ + ROUTED met2 ( 1642430 1652740 ) ( 1642890 * )
+ NEW met2 ( 1642890 18190 ) ( * 1652740 )
+ NEW met1 ( 1642430 1689290 ) ( 1644890 * )
+ NEW met2 ( 1644890 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1642430 1652740 ) ( * 1689290 )
+ NEW met2 ( 1521910 1700 0 ) ( * 18190 )
+ NEW met1 ( 1521910 18190 ) ( 1642890 * )
+ NEW met1 ( 1642890 18190 ) M1M2_PR
+ NEW met1 ( 1642430 1689290 ) M1M2_PR
+ NEW met1 ( 1644890 1689290 ) M1M2_PR
+ NEW met1 ( 1521910 18190 ) M1M2_PR ;
+ - la_data_out[51] ( PIN la_data_out[51] ) ( mprj la_data_out[51] ) + USE SIGNAL
+ + ROUTED met2 ( 1539850 1700 0 ) ( * 20230 )
+ NEW met2 ( 1649790 1688780 ) ( 1650410 * )
+ NEW met2 ( 1650410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1649790 20230 ) ( * 1688780 )
+ NEW met1 ( 1539850 20230 ) ( 1649790 * )
+ NEW met1 ( 1539850 20230 ) M1M2_PR
+ NEW met1 ( 1649790 20230 ) M1M2_PR ;
+ - la_data_out[52] ( PIN la_data_out[52] ) ( mprj la_data_out[52] ) + USE SIGNAL
+ + ROUTED met2 ( 1557330 1700 0 ) ( * 17170 )
+ NEW met1 ( 1650250 1652570 ) ( 1655310 * )
+ NEW met2 ( 1650250 17170 ) ( * 1652570 )
+ NEW met2 ( 1655310 1688780 ) ( 1655470 * )
+ NEW met2 ( 1655470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1655310 1652570 ) ( * 1688780 )
+ NEW met1 ( 1557330 17170 ) ( 1650250 * )
+ NEW met1 ( 1557330 17170 ) M1M2_PR
+ NEW met1 ( 1650250 17170 ) M1M2_PR
+ NEW met1 ( 1650250 1652570 ) M1M2_PR
+ NEW met1 ( 1655310 1652570 ) M1M2_PR ;
+ - la_data_out[53] ( PIN la_data_out[53] ) ( mprj la_data_out[53] ) + USE SIGNAL
+ + ROUTED met2 ( 1575270 1700 0 ) ( * 17850 )
+ NEW met1 ( 1656690 1688950 ) ( 1660990 * )
+ NEW met2 ( 1660990 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1656690 17850 ) ( * 1688950 )
+ NEW met1 ( 1575270 17850 ) ( 1656690 * )
+ NEW met1 ( 1575270 17850 ) M1M2_PR
+ NEW met1 ( 1656690 17850 ) M1M2_PR
+ NEW met1 ( 1656690 1688950 ) M1M2_PR
+ NEW met1 ( 1660990 1688950 ) M1M2_PR ;
+ - la_data_out[54] ( PIN la_data_out[54] ) ( mprj la_data_out[54] ) + USE SIGNAL
+ + ROUTED met2 ( 1666350 1680450 ) ( * 1688780 )
+ NEW met2 ( 1666350 1688780 ) ( 1666510 * )
+ NEW met2 ( 1666510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1590450 1700 ) ( 1592750 * 0 )
+ NEW met2 ( 1590450 1700 ) ( * 5780 )
+ NEW met2 ( 1587230 5780 ) ( 1590450 * )
+ NEW met2 ( 1587230 5780 ) ( * 1680450 )
+ NEW met1 ( 1587230 1680450 ) ( 1666350 * )
+ NEW met1 ( 1666350 1680450 ) M1M2_PR
+ NEW met1 ( 1587230 1680450 ) M1M2_PR ;
+ - la_data_out[55] ( PIN la_data_out[55] ) ( mprj la_data_out[55] ) + USE SIGNAL
+ + ROUTED met1 ( 1670490 1652570 ) ( 1671870 * )
+ NEW met2 ( 1670490 15130 ) ( * 1652570 )
+ NEW met2 ( 1671870 1688780 ) ( 1672030 * )
+ NEW met2 ( 1672030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1671870 1652570 ) ( * 1688780 )
+ NEW met2 ( 1610690 1700 0 ) ( * 15130 )
+ NEW met1 ( 1610690 15130 ) ( 1670490 * )
+ NEW met1 ( 1670490 15130 ) M1M2_PR
+ NEW met1 ( 1670490 1652570 ) M1M2_PR
+ NEW met1 ( 1671870 1652570 ) M1M2_PR
+ NEW met1 ( 1610690 15130 ) M1M2_PR ;
+ - la_data_out[56] ( PIN la_data_out[56] ) ( mprj la_data_out[56] ) + USE SIGNAL
+ + ROUTED met2 ( 1628170 1700 0 ) ( * 18870 )
+ NEW met1 ( 1628170 18870 ) ( 1677390 * )
+ NEW met2 ( 1677390 1688780 ) ( 1677550 * )
+ NEW met2 ( 1677550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1677390 18870 ) ( * 1688780 )
+ NEW met1 ( 1628170 18870 ) M1M2_PR
+ NEW met1 ( 1677390 18870 ) M1M2_PR ;
+ - la_data_out[57] ( PIN la_data_out[57] ) ( mprj la_data_out[57] ) + USE SIGNAL
+ + ROUTED met2 ( 1646110 1700 0 ) ( * 15810 )
+ NEW met1 ( 1646110 15810 ) ( 1678770 * )
+ NEW met2 ( 1678770 15810 ) ( * 1580100 )
+ NEW met2 ( 1678770 1580100 ) ( 1680150 * )
+ NEW met2 ( 1680150 1688780 ) ( 1683070 * )
+ NEW met2 ( 1683070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1680150 1580100 ) ( * 1688780 )
+ NEW met1 ( 1646110 15810 ) M1M2_PR
+ NEW met1 ( 1678770 15810 ) M1M2_PR ;
+ - la_data_out[58] ( PIN la_data_out[58] ) ( mprj la_data_out[58] ) + USE SIGNAL
+ + ROUTED met2 ( 1663130 82800 ) ( 1663590 * )
+ NEW met2 ( 1663590 1700 0 ) ( * 82800 )
+ NEW met2 ( 1663130 82800 ) ( * 1676710 )
+ NEW met2 ( 1688430 1676710 ) ( * 1688780 )
+ NEW met2 ( 1688430 1688780 ) ( 1688590 * )
+ NEW met2 ( 1688590 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1663130 1676710 ) ( 1688430 * )
+ NEW met1 ( 1663130 1676710 ) M1M2_PR
+ NEW met1 ( 1688430 1676710 ) M1M2_PR ;
+ - la_data_out[59] ( PIN la_data_out[59] ) ( mprj la_data_out[59] ) + USE SIGNAL
+ + ROUTED met2 ( 1681530 1700 0 ) ( * 14450 )
+ NEW met1 ( 1681530 14450 ) ( 1690730 * )
+ NEW met2 ( 1690730 1689290 ) ( 1691190 * )
+ NEW met1 ( 1691190 1689290 ) ( 1694110 * )
+ NEW met2 ( 1694110 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1690730 14450 ) ( * 1689290 )
+ NEW met1 ( 1681530 14450 ) M1M2_PR
+ NEW met1 ( 1690730 14450 ) M1M2_PR
+ NEW met1 ( 1691190 1689290 ) M1M2_PR
+ NEW met1 ( 1694110 1689290 ) M1M2_PR ;
+ - la_data_out[5] ( PIN la_data_out[5] ) ( mprj la_data_out[5] ) + USE SIGNAL
+ + ROUTED met1 ( 717830 86530 ) ( 1394950 * )
+ NEW met1 ( 717830 58310 ) ( 723810 * )
+ NEW met2 ( 717830 58310 ) ( * 86530 )
+ NEW met2 ( 723810 1700 0 ) ( * 58310 )
+ NEW met2 ( 1394950 1688780 ) ( 1398330 * )
+ NEW met2 ( 1398330 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1394950 86530 ) ( * 1688780 )
+ NEW met1 ( 717830 86530 ) M1M2_PR
+ NEW met1 ( 1394950 86530 ) M1M2_PR
+ NEW met1 ( 717830 58310 ) M1M2_PR
+ NEW met1 ( 723810 58310 ) M1M2_PR ;
+ - la_data_out[60] ( PIN la_data_out[60] ) ( mprj la_data_out[60] ) + USE SIGNAL
+ + ROUTED met2 ( 1697630 1700 ) ( 1699470 * 0 )
+ NEW met1 ( 1697630 1688270 ) ( * 1689290 )
+ NEW met1 ( 1697630 1689290 ) ( 1699630 * )
+ NEW met2 ( 1699630 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1697630 1700 ) ( * 1688270 )
+ NEW met1 ( 1697630 1688270 ) M1M2_PR
+ NEW met1 ( 1699630 1689290 ) M1M2_PR ;
+ - la_data_out[61] ( PIN la_data_out[61] ) ( mprj la_data_out[61] ) + USE SIGNAL
+ + ROUTED met2 ( 1716950 1700 0 ) ( * 15810 )
+ NEW met1 ( 1705450 15810 ) ( 1716950 * )
+ NEW met2 ( 1705220 1688780 ) ( 1705450 * )
+ NEW met2 ( 1705220 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1705450 15810 ) ( * 1688780 )
+ NEW met1 ( 1716950 15810 ) M1M2_PR
+ NEW met1 ( 1705450 15810 ) M1M2_PR ;
+ - la_data_out[62] ( PIN la_data_out[62] ) ( mprj la_data_out[62] ) + USE SIGNAL
+ + ROUTED met2 ( 1734890 1700 0 ) ( * 15130 )
+ NEW met1 ( 1705910 15130 ) ( 1734890 * )
+ NEW met1 ( 1705910 1688950 ) ( 1710670 * )
+ NEW met2 ( 1710670 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1705910 15130 ) ( * 1688950 )
+ NEW met1 ( 1734890 15130 ) M1M2_PR
+ NEW met1 ( 1705910 15130 ) M1M2_PR
+ NEW met1 ( 1705910 1688950 ) M1M2_PR
+ NEW met1 ( 1710670 1688950 ) M1M2_PR ;
+ - la_data_out[63] ( PIN la_data_out[63] ) ( mprj la_data_out[63] ) + USE SIGNAL
+ + ROUTED met2 ( 1752370 1700 0 ) ( * 15470 )
+ NEW met1 ( 1712810 15470 ) ( 1752370 * )
+ NEW met2 ( 1712810 1688780 ) ( 1715730 * )
+ NEW met2 ( 1715730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1712810 15470 ) ( * 1688780 )
+ NEW met1 ( 1752370 15470 ) M1M2_PR
+ NEW met1 ( 1712810 15470 ) M1M2_PR ;
+ - la_data_out[64] ( PIN la_data_out[64] ) ( mprj la_data_out[64] ) + USE SIGNAL
+ + ROUTED met2 ( 1770310 1700 0 ) ( * 16490 )
+ NEW met1 ( 1718330 16490 ) ( 1770310 * )
+ NEW met1 ( 1718330 1688950 ) ( 1721250 * )
+ NEW met2 ( 1721250 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1718330 16490 ) ( * 1688950 )
+ NEW met1 ( 1770310 16490 ) M1M2_PR
+ NEW met1 ( 1718330 16490 ) M1M2_PR
+ NEW met1 ( 1718330 1688950 ) M1M2_PR
+ NEW met1 ( 1721250 1688950 ) M1M2_PR ;
+ - la_data_out[65] ( PIN la_data_out[65] ) ( mprj la_data_out[65] ) + USE SIGNAL
+ + ROUTED met2 ( 1731210 1681810 ) ( * 1689290 )
+ NEW met1 ( 1726840 1689290 ) ( 1731210 * )
+ NEW met2 ( 1726840 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1787790 1700 0 ) ( * 16830 )
+ NEW met1 ( 1777210 16830 ) ( 1787790 * )
+ NEW met1 ( 1731210 1681810 ) ( 1777210 * )
+ NEW met2 ( 1777210 16830 ) ( * 1681810 )
+ NEW met1 ( 1731210 1681810 ) M1M2_PR
+ NEW met1 ( 1731210 1689290 ) M1M2_PR
+ NEW met1 ( 1726840 1689290 ) M1M2_PR
+ NEW met1 ( 1787790 16830 ) M1M2_PR
+ NEW met1 ( 1777210 16830 ) M1M2_PR
+ NEW met1 ( 1777210 1681810 ) M1M2_PR ;
+ - la_data_out[66] ( PIN la_data_out[66] ) ( mprj la_data_out[66] ) + USE SIGNAL
+ + ROUTED met1 ( 1732130 16150 ) ( 1770770 * )
+ NEW met1 ( 1770770 16150 ) ( * 16830 )
+ NEW met2 ( 1732130 1688780 ) ( 1732290 * )
+ NEW met2 ( 1732290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1732130 16150 ) ( * 1688780 )
+ NEW met1 ( 1770770 16830 ) ( 1773300 * )
+ NEW met2 ( 1805730 1700 0 ) ( * 16490 )
+ NEW met1 ( 1773300 16490 ) ( 1805730 * )
+ NEW met1 ( 1773300 16490 ) ( * 16830 )
+ NEW met1 ( 1732130 16150 ) M1M2_PR
+ NEW met1 ( 1805730 16490 ) M1M2_PR ;
+ - la_data_out[67] ( PIN la_data_out[67] ) ( mprj la_data_out[67] ) + USE SIGNAL
+ + ROUTED met2 ( 1823210 1700 0 ) ( * 16830 )
+ NEW met2 ( 1738110 1682150 ) ( * 1688780 )
+ NEW met2 ( 1737880 1688780 ) ( 1738110 * )
+ NEW met2 ( 1737880 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1812170 16830 ) ( 1823210 * )
+ NEW met2 ( 1811710 82800 ) ( 1812170 * )
+ NEW met2 ( 1812170 16830 ) ( * 82800 )
+ NEW met1 ( 1738110 1682150 ) ( 1811710 * )
+ NEW met2 ( 1811710 82800 ) ( * 1682150 )
+ NEW met1 ( 1823210 16830 ) M1M2_PR
+ NEW met1 ( 1738110 1682150 ) M1M2_PR
+ NEW met1 ( 1812170 16830 ) M1M2_PR
+ NEW met1 ( 1811710 1682150 ) M1M2_PR ;
+ - la_data_out[68] ( PIN la_data_out[68] ) ( mprj la_data_out[68] ) + USE SIGNAL
+ + ROUTED met2 ( 1838850 1700 ) ( 1841150 * 0 )
+ NEW met2 ( 1838850 1700 ) ( * 3060 )
+ NEW met2 ( 1835630 3060 ) ( 1838850 * )
+ NEW met2 ( 1743630 1680110 ) ( * 1688780 )
+ NEW met2 ( 1743400 1688780 ) ( 1743630 * )
+ NEW met2 ( 1743400 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1835630 3060 ) ( * 1680110 )
+ NEW met1 ( 1743630 1680110 ) ( 1835630 * )
+ NEW met1 ( 1743630 1680110 ) M1M2_PR
+ NEW met1 ( 1835630 1680110 ) M1M2_PR ;
+ - la_data_out[69] ( PIN la_data_out[69] ) ( mprj la_data_out[69] ) + USE SIGNAL
+ + ROUTED met2 ( 1858630 1700 0 ) ( * 15810 )
+ NEW met1 ( 1831950 15810 ) ( 1858630 * )
+ NEW met2 ( 1749150 1680790 ) ( * 1688780 )
+ NEW met2 ( 1748920 1688780 ) ( 1749150 * )
+ NEW met2 ( 1748920 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1831950 15810 ) ( * 1680790 )
+ NEW met1 ( 1749150 1680790 ) ( 1831950 * )
+ NEW met1 ( 1858630 15810 ) M1M2_PR
+ NEW met1 ( 1831950 15810 ) M1M2_PR
+ NEW met1 ( 1749150 1680790 ) M1M2_PR
+ NEW met1 ( 1831950 1680790 ) M1M2_PR ;
+ - la_data_out[6] ( PIN la_data_out[6] ) ( mprj la_data_out[6] ) + USE SIGNAL
+ + ROUTED met2 ( 739450 1700 ) ( 741750 * 0 )
+ NEW met1 ( 738530 87210 ) ( 1401390 * )
+ NEW met2 ( 738530 82800 ) ( * 87210 )
+ NEW met2 ( 738530 82800 ) ( 739450 * )
+ NEW met2 ( 739450 1700 ) ( * 82800 )
+ NEW met1 ( 1401390 1689290 ) ( 1403850 * )
+ NEW met2 ( 1403850 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1401390 87210 ) ( * 1689290 )
+ NEW met1 ( 738530 87210 ) M1M2_PR
+ NEW met1 ( 1401390 87210 ) M1M2_PR
+ NEW met1 ( 1401390 1689290 ) M1M2_PR
+ NEW met1 ( 1403850 1689290 ) M1M2_PR ;
+ - la_data_out[70] ( PIN la_data_out[70] ) ( mprj la_data_out[70] ) + USE SIGNAL
+ + ROUTED met2 ( 1754670 1682490 ) ( * 1688780 )
+ NEW met2 ( 1754440 1688780 ) ( 1754670 * )
+ NEW met2 ( 1754440 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1825050 16150 ) ( * 1580100 )
+ NEW met2 ( 1825050 1580100 ) ( 1825510 * )
+ NEW met2 ( 1825510 1580100 ) ( * 1682490 )
+ NEW met2 ( 1876570 1700 0 ) ( * 16150 )
+ NEW met1 ( 1825050 16150 ) ( 1876570 * )
+ NEW met1 ( 1754670 1682490 ) ( 1825510 * )
+ NEW met1 ( 1825050 16150 ) M1M2_PR
+ NEW met1 ( 1754670 1682490 ) M1M2_PR
+ NEW met1 ( 1825510 1682490 ) M1M2_PR
+ NEW met1 ( 1876570 16150 ) M1M2_PR ;
+ - la_data_out[71] ( PIN la_data_out[71] ) ( mprj la_data_out[71] ) + USE SIGNAL
+ + ROUTED met2 ( 1759730 1688780 ) ( 1759890 * )
+ NEW met2 ( 1759890 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1759730 26350 ) ( * 1688780 )
+ NEW met2 ( 1894510 1700 0 ) ( * 26350 )
+ NEW met1 ( 1759730 26350 ) ( 1894510 * )
+ NEW met1 ( 1759730 26350 ) M1M2_PR
+ NEW met1 ( 1894510 26350 ) M1M2_PR ;
+ - la_data_out[72] ( PIN la_data_out[72] ) ( mprj la_data_out[72] ) + USE SIGNAL
+ + ROUTED met2 ( 1760190 26010 ) ( * 1580100 )
+ NEW met2 ( 1760190 1580100 ) ( 1764790 * )
+ NEW met2 ( 1764790 1688780 ) ( 1765410 * )
+ NEW met2 ( 1765410 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1764790 1580100 ) ( * 1688780 )
+ NEW met2 ( 1911990 1700 0 ) ( * 26010 )
+ NEW met1 ( 1760190 26010 ) ( 1911990 * )
+ NEW met1 ( 1760190 26010 ) M1M2_PR
+ NEW met1 ( 1911990 26010 ) M1M2_PR ;
+ - la_data_out[73] ( PIN la_data_out[73] ) ( mprj la_data_out[73] ) + USE SIGNAL
+ + ROUTED met2 ( 1929930 1700 0 ) ( * 25670 )
+ NEW met2 ( 1767090 25670 ) ( * 1580100 )
+ NEW met2 ( 1767090 1580100 ) ( 1770310 * )
+ NEW met2 ( 1770310 1688780 ) ( 1770930 * )
+ NEW met2 ( 1770930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1770310 1580100 ) ( * 1688780 )
+ NEW met1 ( 1767090 25670 ) ( 1929930 * )
+ NEW met1 ( 1767090 25670 ) M1M2_PR
+ NEW met1 ( 1929930 25670 ) M1M2_PR ;
+ - la_data_out[74] ( PIN la_data_out[74] ) ( mprj la_data_out[74] ) + USE SIGNAL
+ + ROUTED met2 ( 1947410 1700 0 ) ( * 25330 )
+ NEW met1 ( 1773530 25330 ) ( 1947410 * )
+ NEW met2 ( 1773530 25330 ) ( * 1580100 )
+ NEW met2 ( 1773530 1580100 ) ( 1775370 * )
+ NEW met2 ( 1775370 1688780 ) ( 1775990 * )
+ NEW met2 ( 1775990 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1775370 1580100 ) ( * 1688780 )
+ NEW met1 ( 1947410 25330 ) M1M2_PR
+ NEW met1 ( 1773530 25330 ) M1M2_PR ;
+ - la_data_out[75] ( PIN la_data_out[75] ) ( mprj la_data_out[75] ) + USE SIGNAL
+ + ROUTED met2 ( 1965350 1700 0 ) ( * 24990 )
+ NEW met1 ( 1780890 24990 ) ( 1965350 * )
+ NEW met2 ( 1780890 1688780 ) ( 1781510 * )
+ NEW met2 ( 1781510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1780890 24990 ) ( * 1688780 )
+ NEW met1 ( 1965350 24990 ) M1M2_PR
+ NEW met1 ( 1780890 24990 ) M1M2_PR ;
+ - la_data_out[76] ( PIN la_data_out[76] ) ( mprj la_data_out[76] ) + USE SIGNAL
+ + ROUTED met2 ( 1982830 1700 0 ) ( * 24650 )
+ NEW met1 ( 1780430 24650 ) ( 1982830 * )
+ NEW met1 ( 1780430 1688950 ) ( 1787030 * )
+ NEW met2 ( 1787030 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1780430 24650 ) ( * 1688950 )
+ NEW met1 ( 1780430 24650 ) M1M2_PR
+ NEW met1 ( 1982830 24650 ) M1M2_PR
+ NEW met1 ( 1780430 1688950 ) M1M2_PR
+ NEW met1 ( 1787030 1688950 ) M1M2_PR ;
+ - la_data_out[77] ( PIN la_data_out[77] ) ( mprj la_data_out[77] ) + USE SIGNAL
+ + ROUTED met2 ( 2000770 1700 0 ) ( * 24310 )
+ NEW met1 ( 1788250 24310 ) ( 2000770 * )
+ NEW met2 ( 1788250 24310 ) ( * 1580100 )
+ NEW met2 ( 1788250 1580100 ) ( 1788710 * )
+ NEW met2 ( 1788710 1580100 ) ( * 1676700 )
+ NEW met2 ( 1788710 1676700 ) ( 1789170 * )
+ NEW met2 ( 1789170 1676700 ) ( * 1688780 )
+ NEW met2 ( 1789170 1688780 ) ( 1792550 * )
+ NEW met2 ( 1792550 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1788250 24310 ) M1M2_PR
+ NEW met1 ( 2000770 24310 ) M1M2_PR ;
+ - la_data_out[78] ( PIN la_data_out[78] ) ( mprj la_data_out[78] ) + USE SIGNAL
+ + ROUTED met2 ( 2018250 1700 0 ) ( * 22610 )
+ NEW met1 ( 1794690 22610 ) ( 2018250 * )
+ NEW met1 ( 1794690 1688950 ) ( 1798070 * )
+ NEW met2 ( 1798070 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1794690 22610 ) ( * 1688950 )
+ NEW met1 ( 2018250 22610 ) M1M2_PR
+ NEW met1 ( 1794690 22610 ) M1M2_PR
+ NEW met1 ( 1794690 1688950 ) M1M2_PR
+ NEW met1 ( 1798070 1688950 ) M1M2_PR ;
+ - la_data_out[79] ( PIN la_data_out[79] ) ( mprj la_data_out[79] ) + USE SIGNAL
+ + ROUTED met2 ( 2036190 1700 0 ) ( * 31110 )
+ NEW met1 ( 1802050 31110 ) ( 2036190 * )
+ NEW met2 ( 1802050 1688780 ) ( 1803590 * )
+ NEW met2 ( 1803590 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1802050 31110 ) ( * 1688780 )
+ NEW met1 ( 2036190 31110 ) M1M2_PR
+ NEW met1 ( 1802050 31110 ) M1M2_PR ;
+ - la_data_out[7] ( PIN la_data_out[7] ) ( mprj la_data_out[7] ) + USE SIGNAL
+ + ROUTED met2 ( 759230 1700 0 ) ( * 34500 )
+ NEW met2 ( 759230 34500 ) ( 759690 * )
+ NEW met2 ( 759690 34500 ) ( * 87890 )
+ NEW met1 ( 759690 87890 ) ( 1408290 * )
+ NEW met2 ( 1408290 1688780 ) ( 1409370 * )
+ NEW met2 ( 1409370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1408290 87890 ) ( * 1688780 )
+ NEW met1 ( 759690 87890 ) M1M2_PR
+ NEW met1 ( 1408290 87890 ) M1M2_PR ;
+ - la_data_out[80] ( PIN la_data_out[80] ) ( mprj la_data_out[80] ) + USE SIGNAL
+ + ROUTED met2 ( 2054130 1700 0 ) ( * 29070 )
+ NEW met1 ( 1808490 29070 ) ( 2054130 * )
+ NEW met2 ( 1808490 1688780 ) ( 1809110 * )
+ NEW met2 ( 1809110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1808490 29070 ) ( * 1688780 )
+ NEW met1 ( 2054130 29070 ) M1M2_PR
+ NEW met1 ( 1808490 29070 ) M1M2_PR ;
+ - la_data_out[81] ( PIN la_data_out[81] ) ( mprj la_data_out[81] ) + USE SIGNAL
+ + ROUTED met1 ( 1808950 1652570 ) ( 1814470 * )
+ NEW met2 ( 1808950 43690 ) ( * 1652570 )
+ NEW met2 ( 1814470 1688780 ) ( 1814630 * )
+ NEW met2 ( 1814630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1814470 1652570 ) ( * 1688780 )
+ NEW met1 ( 1808950 43690 ) ( 2071610 * )
+ NEW met2 ( 2071610 1700 0 ) ( * 43690 )
+ NEW met1 ( 1808950 1652570 ) M1M2_PR
+ NEW met1 ( 1814470 1652570 ) M1M2_PR
+ NEW met1 ( 1808950 43690 ) M1M2_PR
+ NEW met1 ( 2071610 43690 ) M1M2_PR ;
+ - la_data_out[82] ( PIN la_data_out[82] ) ( mprj la_data_out[82] ) + USE SIGNAL
+ + ROUTED met2 ( 2087250 1700 ) ( 2089550 * 0 )
+ NEW met2 ( 1815850 64430 ) ( * 1580100 )
+ NEW met2 ( 1815850 1580100 ) ( 1819990 * )
+ NEW met2 ( 1819990 1688780 ) ( 1820150 * )
+ NEW met2 ( 1820150 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1819990 1580100 ) ( * 1688780 )
+ NEW met1 ( 1815850 64430 ) ( 2087250 * )
+ NEW met2 ( 2087250 1700 ) ( * 64430 )
+ NEW met1 ( 1815850 64430 ) M1M2_PR
+ NEW met1 ( 2087250 64430 ) M1M2_PR ;
+ - la_data_out[83] ( PIN la_data_out[83] ) ( mprj la_data_out[83] ) + USE SIGNAL
+ + ROUTED met2 ( 1822290 64770 ) ( * 1580100 )
+ NEW met2 ( 1822290 1580100 ) ( 1824590 * )
+ NEW met2 ( 1824590 1688780 ) ( 1825670 * )
+ NEW met2 ( 1825670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1824590 1580100 ) ( * 1688780 )
+ NEW met2 ( 2104730 1700 ) ( 2107030 * 0 )
+ NEW met1 ( 1822290 64770 ) ( 2104730 * )
+ NEW met2 ( 2104730 1700 ) ( * 64770 )
+ NEW met1 ( 1822290 64770 ) M1M2_PR
+ NEW met1 ( 2104730 64770 ) M1M2_PR ;
+ - la_data_out[84] ( PIN la_data_out[84] ) ( mprj la_data_out[84] ) + USE SIGNAL
+ + ROUTED met2 ( 2124970 1700 0 ) ( * 16830 )
+ NEW met1 ( 2118530 16830 ) ( 2124970 * )
+ NEW met2 ( 1830110 1688780 ) ( 1831190 * )
+ NEW met2 ( 1831190 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1830110 65110 ) ( * 1688780 )
+ NEW met2 ( 2118530 16830 ) ( * 65110 )
+ NEW met1 ( 1830110 65110 ) ( 2118530 * )
+ NEW met1 ( 2124970 16830 ) M1M2_PR
+ NEW met1 ( 2118530 16830 ) M1M2_PR
+ NEW met1 ( 1830110 65110 ) M1M2_PR
+ NEW met1 ( 2118530 65110 ) M1M2_PR ;
+ - la_data_out[85] ( PIN la_data_out[85] ) ( mprj la_data_out[85] ) + USE SIGNAL
+ + ROUTED met1 ( 1836550 1652230 ) ( * 1653250 )
+ NEW met2 ( 1836550 68850 ) ( * 1652230 )
+ NEW met2 ( 1836320 1688780 ) ( 1836550 * )
+ NEW met2 ( 1836320 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1836550 1653250 ) ( * 1688780 )
+ NEW met2 ( 2142450 1700 0 ) ( * 68850 )
+ NEW met1 ( 1836550 68850 ) ( 2142450 * )
+ NEW met1 ( 1836550 1652230 ) M1M2_PR
+ NEW met1 ( 1836550 1653250 ) M1M2_PR
+ NEW met1 ( 1836550 68850 ) M1M2_PR
+ NEW met1 ( 2142450 68850 ) M1M2_PR ;
+ - la_data_out[86] ( PIN la_data_out[86] ) ( mprj la_data_out[86] ) + USE SIGNAL
+ + ROUTED met2 ( 1837010 71230 ) ( * 1580100 )
+ NEW met2 ( 1837010 1580100 ) ( 1838850 * )
+ NEW met2 ( 1838850 1688780 ) ( 1841770 * )
+ NEW met2 ( 1841770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1838850 1580100 ) ( * 1688780 )
+ NEW met1 ( 1837010 71230 ) ( 2160390 * )
+ NEW met2 ( 2160390 1700 0 ) ( * 71230 )
+ NEW met1 ( 1837010 71230 ) M1M2_PR
+ NEW met1 ( 2160390 71230 ) M1M2_PR ;
+ - la_data_out[87] ( PIN la_data_out[87] ) ( mprj la_data_out[87] ) + USE SIGNAL
+ + ROUTED met2 ( 1842990 50490 ) ( * 1676700 )
+ NEW met2 ( 1842990 1676700 ) ( 1845290 * )
+ NEW met2 ( 1845290 1676700 ) ( * 1688780 )
+ NEW met2 ( 1845290 1688780 ) ( 1847290 * )
+ NEW met2 ( 1847290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2175570 1700 ) ( 2177870 * 0 )
+ NEW met1 ( 1842990 50490 ) ( 2175570 * )
+ NEW met2 ( 2175570 1700 ) ( * 50490 )
+ NEW met1 ( 1842990 50490 ) M1M2_PR
+ NEW met1 ( 2175570 50490 ) M1M2_PR ;
+ - la_data_out[88] ( PIN la_data_out[88] ) ( mprj la_data_out[88] ) + USE SIGNAL
+ + ROUTED met2 ( 1849890 50830 ) ( * 1580100 )
+ NEW met2 ( 1849890 1580100 ) ( 1852190 * )
+ NEW met1 ( 1849890 50830 ) ( 2195810 * )
+ NEW met2 ( 2195810 1700 0 ) ( * 50830 )
+ NEW met2 ( 1852190 1688780 ) ( 1852810 * )
+ NEW met2 ( 1852810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1852190 1580100 ) ( * 1688780 )
+ NEW met1 ( 1849890 50830 ) M1M2_PR
+ NEW met1 ( 2195810 50830 ) M1M2_PR ;
+ - la_data_out[89] ( PIN la_data_out[89] ) ( mprj la_data_out[89] ) + USE SIGNAL
+ + ROUTED met2 ( 2213290 1700 0 ) ( * 17340 )
+ NEW met2 ( 2210990 17340 ) ( 2213290 * )
+ NEW met2 ( 2210990 17340 ) ( * 51170 )
+ NEW met1 ( 1857250 51170 ) ( 2210990 * )
+ NEW met2 ( 1857250 1688780 ) ( 1858330 * )
+ NEW met2 ( 1858330 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1857250 51170 ) ( * 1688780 )
+ NEW met1 ( 1857250 51170 ) M1M2_PR
+ NEW met1 ( 2210990 51170 ) M1M2_PR ;
+ - la_data_out[8] ( PIN la_data_out[8] ) ( mprj la_data_out[8] ) + USE SIGNAL
+ + ROUTED met2 ( 777170 1700 0 ) ( * 52870 )
+ NEW met2 ( 1414960 1688780 ) ( 1415650 * )
+ NEW met2 ( 1414960 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 777170 52870 ) ( 1415650 * )
+ NEW met2 ( 1415650 52870 ) ( * 1688780 )
+ NEW met1 ( 777170 52870 ) M1M2_PR
+ NEW met1 ( 1415650 52870 ) M1M2_PR ;
+ - la_data_out[90] ( PIN la_data_out[90] ) ( mprj la_data_out[90] ) + USE SIGNAL
+ + ROUTED met2 ( 2228930 1700 ) ( 2231230 * 0 )
+ NEW met2 ( 2228930 1700 ) ( * 54910 )
+ NEW met1 ( 1863230 54910 ) ( 2228930 * )
+ NEW met2 ( 1863230 1688780 ) ( 1863850 * )
+ NEW met2 ( 1863850 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1863230 54910 ) ( * 1688780 )
+ NEW met1 ( 1863230 54910 ) M1M2_PR
+ NEW met1 ( 2228930 54910 ) M1M2_PR ;
+ - la_data_out[91] ( PIN la_data_out[91] ) ( mprj la_data_out[91] ) + USE SIGNAL
+ + ROUTED met1 ( 1863690 1652570 ) ( 1869210 * )
+ NEW met2 ( 2249170 1700 0 ) ( * 16150 )
+ NEW met1 ( 2243190 16150 ) ( 2249170 * )
+ NEW met2 ( 1863690 54570 ) ( * 1652570 )
+ NEW met2 ( 2243190 16150 ) ( * 54570 )
+ NEW met1 ( 1863690 54570 ) ( 2243190 * )
+ NEW met2 ( 1869210 1688780 ) ( 1869370 * )
+ NEW met2 ( 1869370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1869210 1652570 ) ( * 1688780 )
+ NEW met1 ( 1863690 1652570 ) M1M2_PR
+ NEW met1 ( 1869210 1652570 ) M1M2_PR
+ NEW met1 ( 2249170 16150 ) M1M2_PR
+ NEW met1 ( 2243190 16150 ) M1M2_PR
+ NEW met1 ( 1863690 54570 ) M1M2_PR
+ NEW met1 ( 2243190 54570 ) M1M2_PR ;
+ - la_data_out[92] ( PIN la_data_out[92] ) ( mprj la_data_out[92] ) + USE SIGNAL
+ + ROUTED met1 ( 1870590 54230 ) ( 2266650 * )
+ NEW met2 ( 2266650 1700 0 ) ( * 54230 )
+ NEW met1 ( 1870590 1688950 ) ( 1874890 * )
+ NEW met2 ( 1874890 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1870590 54230 ) ( * 1688950 )
+ NEW met1 ( 1870590 54230 ) M1M2_PR
+ NEW met1 ( 2266650 54230 ) M1M2_PR
+ NEW met1 ( 1870590 1688950 ) M1M2_PR
+ NEW met1 ( 1874890 1688950 ) M1M2_PR ;
+ - la_data_out[93] ( PIN la_data_out[93] ) ( mprj la_data_out[93] ) + USE SIGNAL
+ + ROUTED met1 ( 1877030 53890 ) ( 2284590 * )
+ NEW met2 ( 2284590 1700 0 ) ( * 53890 )
+ NEW met1 ( 1877030 1688950 ) ( 1880410 * )
+ NEW met2 ( 1880410 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1877030 53890 ) ( * 1688950 )
+ NEW met1 ( 1877030 53890 ) M1M2_PR
+ NEW met1 ( 2284590 53890 ) M1M2_PR
+ NEW met1 ( 1877030 1688950 ) M1M2_PR
+ NEW met1 ( 1880410 1688950 ) M1M2_PR ;
+ - la_data_out[94] ( PIN la_data_out[94] ) ( mprj la_data_out[94] ) + USE SIGNAL
+ + ROUTED met1 ( 1883930 1652570 ) ( 1885770 * )
+ NEW met2 ( 2299770 1700 ) ( 2302070 * 0 )
+ NEW met2 ( 1883930 53550 ) ( * 1652570 )
+ NEW met1 ( 1883930 53550 ) ( 2299770 * )
+ NEW met2 ( 2299770 1700 ) ( * 53550 )
+ NEW met2 ( 1885770 1688780 ) ( 1885930 * )
+ NEW met2 ( 1885930 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1885770 1652570 ) ( * 1688780 )
+ NEW met1 ( 1883930 1652570 ) M1M2_PR
+ NEW met1 ( 1885770 1652570 ) M1M2_PR
+ NEW met1 ( 1883930 53550 ) M1M2_PR
+ NEW met1 ( 2299770 53550 ) M1M2_PR ;
+ - la_data_out[95] ( PIN la_data_out[95] ) ( mprj la_data_out[95] ) + USE SIGNAL
+ + ROUTED met2 ( 2320010 1700 0 ) ( * 53210 )
+ NEW met1 ( 1891290 53210 ) ( 2320010 * )
+ NEW met2 ( 1891290 1688780 ) ( 1891450 * )
+ NEW met2 ( 1891450 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1891290 53210 ) ( * 1688780 )
+ NEW met1 ( 2320010 53210 ) M1M2_PR
+ NEW met1 ( 1891290 53210 ) M1M2_PR ;
+ - la_data_out[96] ( PIN la_data_out[96] ) ( mprj la_data_out[96] ) + USE SIGNAL
+ + ROUTED met2 ( 2337490 1700 0 ) ( * 52870 )
+ NEW met1 ( 1891750 1652570 ) ( 1896350 * )
+ NEW met2 ( 1891750 52870 ) ( * 1652570 )
+ NEW met1 ( 1891750 52870 ) ( 2337490 * )
+ NEW met2 ( 1896350 1688780 ) ( 1896510 * )
+ NEW met2 ( 1896510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1896350 1652570 ) ( * 1688780 )
+ NEW met1 ( 2337490 52870 ) M1M2_PR
+ NEW met1 ( 1891750 1652570 ) M1M2_PR
+ NEW met1 ( 1896350 1652570 ) M1M2_PR
+ NEW met1 ( 1891750 52870 ) M1M2_PR ;
+ - la_data_out[97] ( PIN la_data_out[97] ) ( mprj la_data_out[97] ) + USE SIGNAL
+ + ROUTED met2 ( 2353130 1700 ) ( 2355430 * 0 )
+ NEW met2 ( 1898650 52530 ) ( * 1580100 )
+ NEW met2 ( 1898650 1580100 ) ( 1901870 * )
+ NEW met2 ( 1901870 1688780 ) ( 1902030 * )
+ NEW met2 ( 1902030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1901870 1580100 ) ( * 1688780 )
+ NEW met1 ( 1898650 52530 ) ( 2353130 * )
+ NEW met2 ( 2353130 1700 ) ( * 52530 )
+ NEW met1 ( 1898650 52530 ) M1M2_PR
+ NEW met1 ( 2353130 52530 ) M1M2_PR ;
+ - la_data_out[98] ( PIN la_data_out[98] ) ( mprj la_data_out[98] ) + USE SIGNAL
+ + ROUTED met2 ( 2370610 1700 ) ( 2372910 * 0 )
+ NEW met2 ( 1905550 52190 ) ( * 1580100 )
+ NEW met2 ( 1905550 1580100 ) ( 1907390 * )
+ NEW met2 ( 1907390 1688780 ) ( 1907550 * )
+ NEW met2 ( 1907550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1907390 1580100 ) ( * 1688780 )
+ NEW met1 ( 1905550 52190 ) ( 2370610 * )
+ NEW met2 ( 2370610 1700 ) ( * 52190 )
+ NEW met1 ( 1905550 52190 ) M1M2_PR
+ NEW met1 ( 2370610 52190 ) M1M2_PR ;
+ - la_data_out[99] ( PIN la_data_out[99] ) ( mprj la_data_out[99] ) + USE SIGNAL
+ + ROUTED met2 ( 1911990 1688780 ) ( 1913070 * )
+ NEW met2 ( 1913070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1911990 51850 ) ( * 1688780 )
+ NEW met1 ( 1911990 51850 ) ( 2390850 * )
+ NEW met2 ( 2390850 1700 0 ) ( * 51850 )
+ NEW met1 ( 1911990 51850 ) M1M2_PR
+ NEW met1 ( 2390850 51850 ) M1M2_PR ;
+ - la_data_out[9] ( PIN la_data_out[9] ) ( mprj la_data_out[9] ) + USE SIGNAL
+ + ROUTED met2 ( 794650 1700 0 ) ( * 53210 )
+ NEW met1 ( 1415190 1652230 ) ( 1419790 * )
+ NEW met2 ( 1419790 1688780 ) ( 1419950 * )
+ NEW met2 ( 1419950 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1419790 1652230 ) ( * 1688780 )
+ NEW met1 ( 794650 53210 ) ( 1415190 * )
+ NEW met2 ( 1415190 53210 ) ( * 1652230 )
+ NEW met1 ( 794650 53210 ) M1M2_PR
+ NEW met1 ( 1415190 1652230 ) M1M2_PR
+ NEW met1 ( 1419790 1652230 ) M1M2_PR
+ NEW met1 ( 1415190 53210 ) M1M2_PR ;
+ - la_oenb[0] ( PIN la_oenb[0] ) ( mprj la_oenb[0] ) + USE SIGNAL
+ + ROUTED met1 ( 1367350 1688950 ) ( 1372570 * )
+ NEW met2 ( 1372570 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1367350 52530 ) ( * 1688950 )
+ NEW met2 ( 641010 1700 0 ) ( * 20910 )
+ NEW met1 ( 635030 20910 ) ( 641010 * )
+ NEW met2 ( 635030 20910 ) ( * 52530 )
+ NEW met1 ( 635030 52530 ) ( 1367350 * )
+ NEW met1 ( 1367350 52530 ) M1M2_PR
+ NEW met1 ( 1367350 1688950 ) M1M2_PR
+ NEW met1 ( 1372570 1688950 ) M1M2_PR
+ NEW met1 ( 641010 20910 ) M1M2_PR
+ NEW met1 ( 635030 20910 ) M1M2_PR
+ NEW met1 ( 635030 52530 ) M1M2_PR ;
+ - la_oenb[100] ( PIN la_oenb[100] ) ( mprj la_oenb[100] ) + USE SIGNAL
+ + ROUTED met2 ( 2412010 1700 ) ( 2414310 * 0 )
+ NEW met2 ( 1919350 1688780 ) ( 1920430 * )
+ NEW met2 ( 1920430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1919350 51510 ) ( * 1688780 )
+ NEW met2 ( 2412010 1700 ) ( * 51510 )
+ NEW met1 ( 1919350 51510 ) ( 2412010 * )
+ NEW met1 ( 1919350 51510 ) M1M2_PR
+ NEW met1 ( 2412010 51510 ) M1M2_PR ;
+ - la_oenb[101] ( PIN la_oenb[101] ) ( mprj la_oenb[101] ) + USE SIGNAL
+ + ROUTED met2 ( 1926020 1688780 ) ( 1926250 * )
+ NEW met2 ( 1926020 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1926250 58310 ) ( * 1688780 )
+ NEW met2 ( 2432250 1700 0 ) ( * 58310 )
+ NEW met1 ( 1926250 58310 ) ( 2432250 * )
+ NEW met1 ( 1926250 58310 ) M1M2_PR
+ NEW met1 ( 2432250 58310 ) M1M2_PR ;
+ - la_oenb[102] ( PIN la_oenb[102] ) ( mprj la_oenb[102] ) + USE SIGNAL
+ + ROUTED met1 ( 1925790 1652570 ) ( 1931310 * )
+ NEW met2 ( 1925790 61370 ) ( * 1652570 )
+ NEW met2 ( 1931310 1688780 ) ( 1931470 * )
+ NEW met2 ( 1931470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1931310 1652570 ) ( * 1688780 )
+ NEW met2 ( 2449730 1700 0 ) ( * 15980 )
+ NEW met2 ( 2449730 15980 ) ( 2450190 * )
+ NEW met1 ( 1925790 61370 ) ( 2450190 * )
+ NEW met2 ( 2450190 15980 ) ( * 61370 )
+ NEW met1 ( 1925790 1652570 ) M1M2_PR
+ NEW met1 ( 1931310 1652570 ) M1M2_PR
+ NEW met1 ( 1925790 61370 ) M1M2_PR
+ NEW met1 ( 2450190 61370 ) M1M2_PR ;
+ - la_oenb[103] ( PIN la_oenb[103] ) ( mprj la_oenb[103] ) + USE SIGNAL
+ + ROUTED met2 ( 1933610 1688780 ) ( 1936990 * )
+ NEW met2 ( 1936990 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1933610 61030 ) ( * 1688780 )
+ NEW met2 ( 2465370 1700 ) ( 2467670 * 0 )
+ NEW met1 ( 1933610 61030 ) ( 2465370 * )
+ NEW met2 ( 2465370 1700 ) ( * 61030 )
+ NEW met1 ( 1933610 61030 ) M1M2_PR
+ NEW met1 ( 2465370 61030 ) M1M2_PR ;
+ - la_oenb[104] ( PIN la_oenb[104] ) ( mprj la_oenb[104] ) + USE SIGNAL
+ + ROUTED met2 ( 1940050 60350 ) ( * 1580100 )
+ NEW met2 ( 1940050 1580100 ) ( 1941890 * )
+ NEW met2 ( 1941890 1688780 ) ( 1942510 * )
+ NEW met2 ( 1942510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1941890 1580100 ) ( * 1688780 )
+ NEW met1 ( 1940050 60350 ) ( 2485610 * )
+ NEW met2 ( 2485610 1700 0 ) ( * 60350 )
+ NEW met1 ( 1940050 60350 ) M1M2_PR
+ NEW met1 ( 2485610 60350 ) M1M2_PR ;
+ - la_oenb[105] ( PIN la_oenb[105] ) ( mprj la_oenb[105] ) + USE SIGNAL
+ + ROUTED met2 ( 1947410 1688780 ) ( 1948030 * )
+ NEW met2 ( 1948030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1947410 60010 ) ( * 1688780 )
+ NEW met2 ( 2503090 1700 0 ) ( * 60010 )
+ NEW met1 ( 1947410 60010 ) ( 2503090 * )
+ NEW met1 ( 1947410 60010 ) M1M2_PR
+ NEW met1 ( 2503090 60010 ) M1M2_PR ;
+ - la_oenb[106] ( PIN la_oenb[106] ) ( mprj la_oenb[106] ) + USE SIGNAL
+ + ROUTED met2 ( 2518730 1700 ) ( 2521030 * 0 )
+ NEW met2 ( 1953620 1688780 ) ( 1953850 * )
+ NEW met2 ( 1953620 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1953850 59670 ) ( * 1688780 )
+ NEW met2 ( 2518730 1700 ) ( * 59670 )
+ NEW met1 ( 1953850 59670 ) ( 2518730 * )
+ NEW met1 ( 1953850 59670 ) M1M2_PR
+ NEW met1 ( 2518730 59670 ) M1M2_PR ;
+ - la_oenb[107] ( PIN la_oenb[107] ) ( mprj la_oenb[107] ) + USE SIGNAL
+ + ROUTED met2 ( 2536210 1700 ) ( 2538510 * 0 )
+ NEW met2 ( 1954310 1688780 ) ( 1958610 * )
+ NEW met2 ( 1958610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1954310 71570 ) ( * 1688780 )
+ NEW met2 ( 2536210 1700 ) ( * 71570 )
+ NEW met1 ( 1954310 71570 ) ( 2536210 * )
+ NEW met1 ( 1954310 71570 ) M1M2_PR
+ NEW met1 ( 2536210 71570 ) M1M2_PR ;
+ - la_oenb[108] ( PIN la_oenb[108] ) ( mprj la_oenb[108] ) + USE SIGNAL
+ + ROUTED met2 ( 1961210 59330 ) ( * 1580100 )
+ NEW met2 ( 1961210 1580100 ) ( 1963510 * )
+ NEW met2 ( 1963510 1688780 ) ( 1964130 * )
+ NEW met2 ( 1964130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1963510 1580100 ) ( * 1688780 )
+ NEW met1 ( 1961210 59330 ) ( 2556450 * )
+ NEW met2 ( 2556450 1700 0 ) ( * 59330 )
+ NEW met1 ( 1961210 59330 ) M1M2_PR
+ NEW met1 ( 2556450 59330 ) M1M2_PR ;
+ - la_oenb[109] ( PIN la_oenb[109] ) ( mprj la_oenb[109] ) + USE SIGNAL
+ + ROUTED met2 ( 1968110 1688780 ) ( 1969650 * )
+ NEW met2 ( 1969650 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1968110 71910 ) ( * 1688780 )
+ NEW met1 ( 1968110 71910 ) ( 2573930 * )
+ NEW met2 ( 2573930 1700 0 ) ( * 71910 )
+ NEW met1 ( 1968110 71910 ) M1M2_PR
+ NEW met1 ( 2573930 71910 ) M1M2_PR ;
+ - la_oenb[10] ( PIN la_oenb[10] ) ( mprj la_oenb[10] ) + USE SIGNAL
+ + ROUTED met2 ( 818570 1700 0 ) ( * 17340 )
+ NEW met2 ( 817190 17340 ) ( 818570 * )
+ NEW met1 ( 1422090 1652570 ) ( 1427150 * )
+ NEW met2 ( 817190 17340 ) ( * 53550 )
+ NEW met2 ( 1427150 1688780 ) ( 1427310 * )
+ NEW met2 ( 1427310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1427150 1652570 ) ( * 1688780 )
+ NEW met1 ( 817190 53550 ) ( 1422090 * )
+ NEW met2 ( 1422090 53550 ) ( * 1652570 )
+ NEW met1 ( 1422090 1652570 ) M1M2_PR
+ NEW met1 ( 1427150 1652570 ) M1M2_PR
+ NEW met1 ( 817190 53550 ) M1M2_PR
+ NEW met1 ( 1422090 53550 ) M1M2_PR ;
+ - la_oenb[110] ( PIN la_oenb[110] ) ( mprj la_oenb[110] ) + USE SIGNAL
+ + ROUTED met2 ( 2589570 1700 ) ( 2591870 * 0 )
+ NEW met2 ( 1974550 1688780 ) ( 1975170 * )
+ NEW met2 ( 1975170 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1974550 75650 ) ( * 1688780 )
+ NEW met1 ( 1974550 75650 ) ( 2589570 * )
+ NEW met2 ( 2589570 1700 ) ( * 75650 )
+ NEW met1 ( 1974550 75650 ) M1M2_PR
+ NEW met1 ( 2589570 75650 ) M1M2_PR ;
+ - la_oenb[111] ( PIN la_oenb[111] ) ( mprj la_oenb[111] ) + USE SIGNAL
+ + ROUTED met2 ( 2608430 1700 ) ( 2609350 * 0 )
+ NEW met2 ( 2608430 1700 ) ( * 75310 )
+ NEW met2 ( 1981450 1652740 ) ( 1981910 * )
+ NEW met2 ( 1981910 75310 ) ( * 1652740 )
+ NEW met2 ( 1980760 1688780 ) ( 1981450 * )
+ NEW met2 ( 1980760 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1981450 1652740 ) ( * 1688780 )
+ NEW met1 ( 1981910 75310 ) ( 2608430 * )
+ NEW met1 ( 2608430 75310 ) M1M2_PR
+ NEW met1 ( 1981910 75310 ) M1M2_PR ;
+ - la_oenb[112] ( PIN la_oenb[112] ) ( mprj la_oenb[112] ) + USE SIGNAL
+ + ROUTED met2 ( 2627290 1700 0 ) ( * 74970 )
+ NEW met1 ( 1981450 1652230 ) ( 1986050 * )
+ NEW met2 ( 1981450 74970 ) ( * 1652230 )
+ NEW met2 ( 1986050 1688780 ) ( 1986210 * )
+ NEW met2 ( 1986210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1986050 1652230 ) ( * 1688780 )
+ NEW met1 ( 1981450 74970 ) ( 2627290 * )
+ NEW met1 ( 2627290 74970 ) M1M2_PR
+ NEW met1 ( 1981450 1652230 ) M1M2_PR
+ NEW met1 ( 1986050 1652230 ) M1M2_PR
+ NEW met1 ( 1981450 74970 ) M1M2_PR ;
+ - la_oenb[113] ( PIN la_oenb[113] ) ( mprj la_oenb[113] ) + USE SIGNAL
+ + ROUTED met2 ( 2642930 1700 ) ( 2645230 * 0 )
+ NEW met2 ( 1988810 74630 ) ( * 1580100 )
+ NEW met2 ( 1988810 1580100 ) ( 1990190 * )
+ NEW met2 ( 1990190 1688780 ) ( 1991730 * )
+ NEW met2 ( 1991730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1990190 1580100 ) ( * 1688780 )
+ NEW met1 ( 1988810 74630 ) ( 2642930 * )
+ NEW met2 ( 2642930 1700 ) ( * 74630 )
+ NEW met1 ( 1988810 74630 ) M1M2_PR
+ NEW met1 ( 2642930 74630 ) M1M2_PR ;
+ - la_oenb[114] ( PIN la_oenb[114] ) ( mprj la_oenb[114] ) + USE SIGNAL
+ + ROUTED met2 ( 2660410 1700 ) ( 2662710 * 0 )
+ NEW met2 ( 1995710 1688780 ) ( 1997250 * )
+ NEW met2 ( 1997250 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1995710 74290 ) ( * 1688780 )
+ NEW met1 ( 1995710 74290 ) ( 2660410 * )
+ NEW met2 ( 2660410 1700 ) ( * 74290 )
+ NEW met1 ( 1995710 74290 ) M1M2_PR
+ NEW met1 ( 2660410 74290 ) M1M2_PR ;
+ - la_oenb[115] ( PIN la_oenb[115] ) ( mprj la_oenb[115] ) + USE SIGNAL
+ + ROUTED met2 ( 2002150 1688780 ) ( 2002770 * )
+ NEW met2 ( 2002770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2002150 73950 ) ( * 1688780 )
+ NEW met1 ( 2002150 73950 ) ( 2680650 * )
+ NEW met2 ( 2680650 1700 0 ) ( * 73950 )
+ NEW met1 ( 2002150 73950 ) M1M2_PR
+ NEW met1 ( 2680650 73950 ) M1M2_PR ;
+ - la_oenb[116] ( PIN la_oenb[116] ) ( mprj la_oenb[116] ) + USE SIGNAL
+ + ROUTED met2 ( 2698130 1700 0 ) ( * 73610 )
+ NEW met2 ( 2008360 1688780 ) ( 2009050 * )
+ NEW met2 ( 2008360 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2009050 73610 ) ( * 1688780 )
+ NEW met1 ( 2009050 73610 ) ( 2698130 * )
+ NEW met1 ( 2698130 73610 ) M1M2_PR
+ NEW met1 ( 2009050 73610 ) M1M2_PR ;
+ - la_oenb[117] ( PIN la_oenb[117] ) ( mprj la_oenb[117] ) + USE SIGNAL
+ + ROUTED met2 ( 2713770 1700 ) ( 2716070 * 0 )
+ NEW met2 ( 2713770 1700 ) ( * 73270 )
+ NEW met2 ( 2009510 1688780 ) ( 2013810 * )
+ NEW met2 ( 2013810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2009510 73270 ) ( * 1688780 )
+ NEW met1 ( 2009510 73270 ) ( 2713770 * )
+ NEW met1 ( 2713770 73270 ) M1M2_PR
+ NEW met1 ( 2009510 73270 ) M1M2_PR ;
+ - la_oenb[118] ( PIN la_oenb[118] ) ( mprj la_oenb[118] ) + USE SIGNAL
+ + ROUTED met2 ( 2732630 1700 ) ( 2733550 * 0 )
+ NEW met2 ( 2016410 1688780 ) ( 2018870 * )
+ NEW met2 ( 2018870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2016410 72930 ) ( * 1688780 )
+ NEW met2 ( 2732630 1700 ) ( * 72930 )
+ NEW met1 ( 2016410 72930 ) ( 2732630 * )
+ NEW met1 ( 2016410 72930 ) M1M2_PR
+ NEW met1 ( 2732630 72930 ) M1M2_PR ;
+ - la_oenb[119] ( PIN la_oenb[119] ) ( mprj la_oenb[119] ) + USE SIGNAL
+ + ROUTED met1 ( 2021930 1689290 ) ( 2024390 * )
+ NEW met2 ( 2024390 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 2021930 18190 ) ( * 1689290 )
+ NEW met2 ( 2751490 1700 0 ) ( * 18190 )
+ NEW met1 ( 2021930 18190 ) ( 2751490 * )
+ NEW met1 ( 2021930 18190 ) M1M2_PR
+ NEW met1 ( 2021930 1689290 ) M1M2_PR
+ NEW met1 ( 2024390 1689290 ) M1M2_PR
+ NEW met1 ( 2751490 18190 ) M1M2_PR ;
+ - la_oenb[11] ( PIN la_oenb[11] ) ( mprj la_oenb[11] ) + USE SIGNAL
+ + ROUTED met2 ( 836050 1700 0 ) ( * 53890 )
+ NEW met1 ( 1428990 1688270 ) ( 1432830 * )
+ NEW met1 ( 1432830 1688270 ) ( * 1689290 )
+ NEW met2 ( 1432830 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 836050 53890 ) ( 1428990 * )
+ NEW met2 ( 1428990 53890 ) ( * 1688270 )
+ NEW met1 ( 836050 53890 ) M1M2_PR
+ NEW met1 ( 1428990 1688270 ) M1M2_PR
+ NEW met1 ( 1432830 1689290 ) M1M2_PR
+ NEW met1 ( 1428990 53890 ) M1M2_PR ;
+ - la_oenb[120] ( PIN la_oenb[120] ) ( mprj la_oenb[120] ) + USE SIGNAL
+ + ROUTED met2 ( 2029980 1688780 ) ( 2030210 * )
+ NEW met2 ( 2029980 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2030210 72590 ) ( * 1688780 )
+ NEW met1 ( 2030210 72590 ) ( 2768970 * )
+ NEW met2 ( 2768970 1700 0 ) ( * 72590 )
+ NEW met1 ( 2030210 72590 ) M1M2_PR
+ NEW met1 ( 2768970 72590 ) M1M2_PR ;
+ - la_oenb[121] ( PIN la_oenb[121] ) ( mprj la_oenb[121] ) + USE SIGNAL
+ + ROUTED met1 ( 2028830 1689290 ) ( 2035430 * )
+ NEW met2 ( 2035430 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 2028830 17510 ) ( * 1689290 )
+ NEW met2 ( 2786910 1700 0 ) ( * 17510 )
+ NEW met1 ( 2028830 17510 ) ( 2786910 * )
+ NEW met1 ( 2028830 17510 ) M1M2_PR
+ NEW met1 ( 2028830 1689290 ) M1M2_PR
+ NEW met1 ( 2035430 1689290 ) M1M2_PR
+ NEW met1 ( 2786910 17510 ) M1M2_PR ;
+ - la_oenb[122] ( PIN la_oenb[122] ) ( mprj la_oenb[122] ) + USE SIGNAL
+ + ROUTED met2 ( 2804390 1700 0 ) ( * 18870 )
+ NEW met2 ( 2041250 1679430 ) ( * 1688780 )
+ NEW met2 ( 2041020 1688780 ) ( 2041250 * )
+ NEW met2 ( 2041020 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 2094610 18870 ) ( 2804390 * )
+ NEW met1 ( 2041250 1679430 ) ( 2094610 * )
+ NEW met2 ( 2094610 18870 ) ( * 1679430 )
+ NEW met1 ( 2804390 18870 ) M1M2_PR
+ NEW met1 ( 2041250 1679430 ) M1M2_PR
+ NEW met1 ( 2094610 18870 ) M1M2_PR
+ NEW met1 ( 2094610 1679430 ) M1M2_PR ;
+ - la_oenb[123] ( PIN la_oenb[123] ) ( mprj la_oenb[123] ) + USE SIGNAL
+ + ROUTED met2 ( 2044010 1688780 ) ( 2046470 * )
+ NEW met2 ( 2046470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2044010 72250 ) ( * 1688780 )
+ NEW met2 ( 2822330 1700 0 ) ( * 72250 )
+ NEW met1 ( 2044010 72250 ) ( 2822330 * )
+ NEW met1 ( 2044010 72250 ) M1M2_PR
+ NEW met1 ( 2822330 72250 ) M1M2_PR ;
+ - la_oenb[124] ( PIN la_oenb[124] ) ( mprj la_oenb[124] ) + USE SIGNAL
+ + ROUTED met2 ( 2052290 1679090 ) ( * 1688780 )
+ NEW met2 ( 2052060 1688780 ) ( 2052290 * )
+ NEW met2 ( 2052060 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 2094150 20570 ) ( 2095530 * )
+ NEW met2 ( 2095530 17850 ) ( * 20570 )
+ NEW met2 ( 2840270 1700 0 ) ( * 17850 )
+ NEW met1 ( 2095530 17850 ) ( 2840270 * )
+ NEW met1 ( 2052290 1679090 ) ( 2094150 * )
+ NEW met2 ( 2094150 20570 ) ( * 1679090 )
+ NEW met1 ( 2052290 1679090 ) M1M2_PR
+ NEW met1 ( 2094150 20570 ) M1M2_PR
+ NEW met1 ( 2095530 20570 ) M1M2_PR
+ NEW met1 ( 2095530 17850 ) M1M2_PR
+ NEW met1 ( 2840270 17850 ) M1M2_PR
+ NEW met1 ( 2094150 1679090 ) M1M2_PR ;
+ - la_oenb[125] ( PIN la_oenb[125] ) ( mprj la_oenb[125] ) + USE SIGNAL
+ + ROUTED met2 ( 2056430 1688780 ) ( 2057510 * )
+ NEW met2 ( 2057510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2056430 17170 ) ( * 1688780 )
+ NEW met2 ( 2857750 1700 0 ) ( * 17170 )
+ NEW met1 ( 2056430 17170 ) ( 2857750 * )
+ NEW met1 ( 2056430 17170 ) M1M2_PR
+ NEW met1 ( 2857750 17170 ) M1M2_PR ;
+ - la_oenb[126] ( PIN la_oenb[126] ) ( mprj la_oenb[126] ) + USE SIGNAL
+ + ROUTED met2 ( 2062870 1679770 ) ( * 1688780 )
+ NEW met2 ( 2062870 1688780 ) ( 2063030 * )
+ NEW met2 ( 2063030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2156250 18530 ) ( * 1679770 )
+ NEW met2 ( 2875690 1700 0 ) ( * 18530 )
+ NEW met1 ( 2156250 18530 ) ( 2875690 * )
+ NEW met1 ( 2062870 1679770 ) ( 2156250 * )
+ NEW met1 ( 2156250 18530 ) M1M2_PR
+ NEW met1 ( 2062870 1679770 ) M1M2_PR
+ NEW met1 ( 2156250 1679770 ) M1M2_PR
+ NEW met1 ( 2875690 18530 ) M1M2_PR ;
+ - la_oenb[127] ( PIN la_oenb[127] ) ( mprj la_oenb[127] ) + USE SIGNAL
+ + ROUTED met2 ( 2893170 1700 0 ) ( * 79390 )
+ NEW met2 ( 2064250 79390 ) ( * 1580100 )
+ NEW met2 ( 2064250 1580100 ) ( 2068390 * )
+ NEW met2 ( 2068390 1688780 ) ( 2068550 * )
+ NEW met2 ( 2068550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2068390 1580100 ) ( * 1688780 )
+ NEW met1 ( 2064250 79390 ) ( 2893170 * )
+ NEW met1 ( 2893170 79390 ) M1M2_PR
+ NEW met1 ( 2064250 79390 ) M1M2_PR ;
+ - la_oenb[12] ( PIN la_oenb[12] ) ( mprj la_oenb[12] ) + USE SIGNAL
+ + ROUTED met1 ( 1436350 1688270 ) ( * 1689290 )
+ NEW met1 ( 1436350 1689290 ) ( 1438350 * )
+ NEW met2 ( 1438350 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 851690 1700 ) ( 853990 * 0 )
+ NEW met2 ( 851690 1700 ) ( * 54230 )
+ NEW met1 ( 851690 54230 ) ( 1436350 * )
+ NEW met2 ( 1436350 54230 ) ( * 1688270 )
+ NEW met1 ( 1436350 1688270 ) M1M2_PR
+ NEW met1 ( 1438350 1689290 ) M1M2_PR
+ NEW met1 ( 851690 54230 ) M1M2_PR
+ NEW met1 ( 1436350 54230 ) M1M2_PR ;
+ - la_oenb[13] ( PIN la_oenb[13] ) ( mprj la_oenb[13] ) + USE SIGNAL
+ + ROUTED met2 ( 869630 1700 ) ( 871470 * 0 )
+ NEW met2 ( 869630 1700 ) ( * 54570 )
+ NEW met2 ( 1442790 1688780 ) ( 1443870 * )
+ NEW met2 ( 1443870 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 869630 54570 ) ( 1442790 * )
+ NEW met2 ( 1442790 54570 ) ( * 1688780 )
+ NEW met1 ( 869630 54570 ) M1M2_PR
+ NEW met1 ( 1442790 54570 ) M1M2_PR ;
+ - la_oenb[14] ( PIN la_oenb[14] ) ( mprj la_oenb[14] ) + USE SIGNAL
+ + ROUTED met2 ( 889410 1700 0 ) ( * 20910 )
+ NEW met1 ( 883430 20910 ) ( 889410 * )
+ NEW met2 ( 883430 20910 ) ( * 54910 )
+ NEW met2 ( 1449460 1688780 ) ( 1449690 * )
+ NEW met2 ( 1449460 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 883430 54910 ) ( 1449690 * )
+ NEW met2 ( 1449690 54910 ) ( * 1688780 )
+ NEW met1 ( 889410 20910 ) M1M2_PR
+ NEW met1 ( 883430 20910 ) M1M2_PR
+ NEW met1 ( 883430 54910 ) M1M2_PR
+ NEW met1 ( 1449690 54910 ) M1M2_PR ;
+ - la_oenb[15] ( PIN la_oenb[15] ) ( mprj la_oenb[15] ) + USE SIGNAL
+ + ROUTED met1 ( 1450150 1688950 ) ( 1454910 * )
+ NEW met2 ( 1454910 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 905050 1700 ) ( 907350 * 0 )
+ NEW met2 ( 905050 1700 ) ( * 51170 )
+ NEW met1 ( 905050 51170 ) ( 1450150 * )
+ NEW met2 ( 1450150 51170 ) ( * 1688950 )
+ NEW met1 ( 1450150 1688950 ) M1M2_PR
+ NEW met1 ( 1454910 1688950 ) M1M2_PR
+ NEW met1 ( 905050 51170 ) M1M2_PR
+ NEW met1 ( 1450150 51170 ) M1M2_PR ;
+ - la_oenb[16] ( PIN la_oenb[16] ) ( mprj la_oenb[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1457970 82800 ) ( 1458890 * )
+ NEW met2 ( 1457970 82800 ) ( * 1580100 )
+ NEW met2 ( 1457970 1580100 ) ( 1459810 * )
+ NEW met2 ( 1459810 1688780 ) ( 1460430 * )
+ NEW met2 ( 1460430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1459810 1580100 ) ( * 1688780 )
+ NEW met2 ( 924830 1700 0 ) ( * 50830 )
+ NEW met1 ( 924830 50830 ) ( 1458890 * )
+ NEW met2 ( 1458890 50830 ) ( * 82800 )
+ NEW met1 ( 924830 50830 ) M1M2_PR
+ NEW met1 ( 1458890 50830 ) M1M2_PR ;
+ - la_oenb[17] ( PIN la_oenb[17] ) ( mprj la_oenb[17] ) + USE SIGNAL
+ + ROUTED met2 ( 1464410 1688780 ) ( 1465950 * )
+ NEW met2 ( 1465950 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1464410 50490 ) ( * 1688780 )
+ NEW met2 ( 942770 1700 0 ) ( * 17340 )
+ NEW met2 ( 941390 17340 ) ( 942770 * )
+ NEW met2 ( 941390 17340 ) ( * 50490 )
+ NEW met1 ( 941390 50490 ) ( 1464410 * )
+ NEW met1 ( 1464410 50490 ) M1M2_PR
+ NEW met1 ( 941390 50490 ) M1M2_PR ;
+ - la_oenb[18] ( PIN la_oenb[18] ) ( mprj la_oenb[18] ) + USE SIGNAL
+ + ROUTED met2 ( 959330 82800 ) ( * 88570 )
+ NEW met2 ( 959330 82800 ) ( 960250 * )
+ NEW met2 ( 960250 1700 0 ) ( * 82800 )
+ NEW met2 ( 1471310 1688780 ) ( 1471470 * )
+ NEW met2 ( 1471470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1471310 88570 ) ( * 1688780 )
+ NEW met1 ( 959330 88570 ) ( 1471310 * )
+ NEW met1 ( 959330 88570 ) M1M2_PR
+ NEW met1 ( 1471310 88570 ) M1M2_PR ;
+ - la_oenb[19] ( PIN la_oenb[19] ) ( mprj la_oenb[19] ) + USE SIGNAL
+ + ROUTED met2 ( 975890 1700 ) ( 978190 * 0 )
+ NEW met2 ( 973130 82800 ) ( * 88910 )
+ NEW met2 ( 973130 82800 ) ( 975890 * )
+ NEW met2 ( 975890 1700 ) ( * 82800 )
+ NEW met1 ( 1470850 1689290 ) ( 1476530 * )
+ NEW met2 ( 1476530 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1470850 88910 ) ( * 1689290 )
+ NEW met1 ( 973130 88910 ) ( 1470850 * )
+ NEW met1 ( 973130 88910 ) M1M2_PR
+ NEW met1 ( 1470850 88910 ) M1M2_PR
+ NEW met1 ( 1470850 1689290 ) M1M2_PR
+ NEW met1 ( 1476530 1689290 ) M1M2_PR ;
+ - la_oenb[1] ( PIN la_oenb[1] ) ( mprj la_oenb[1] ) + USE SIGNAL
+ + ROUTED met2 ( 1374710 1688780 ) ( 1378090 * )
+ NEW met2 ( 1378090 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1374710 86020 ) ( * 1688780 )
+ NEW met2 ( 656650 1700 ) ( 658950 * 0 )
+ NEW met3 ( 655730 86020 ) ( 1374710 * )
+ NEW met2 ( 655730 82800 ) ( * 86020 )
+ NEW met2 ( 655730 82800 ) ( 656650 * )
+ NEW met2 ( 656650 1700 ) ( * 82800 )
+ NEW met2 ( 1374710 86020 ) M2M3_PR
+ NEW met2 ( 655730 86020 ) M2M3_PR ;
+ - la_oenb[20] ( PIN la_oenb[20] ) ( mprj la_oenb[20] ) + USE SIGNAL
+ + ROUTED met2 ( 993830 1700 ) ( 995670 * 0 )
+ NEW met2 ( 993830 1700 ) ( * 92310 )
+ NEW met2 ( 1477750 92310 ) ( * 1580100 )
+ NEW met2 ( 1477750 1580100 ) ( 1481890 * )
+ NEW met2 ( 1481890 1688780 ) ( 1482050 * )
+ NEW met2 ( 1482050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1481890 1580100 ) ( * 1688780 )
+ NEW met1 ( 993830 92310 ) ( 1477750 * )
+ NEW met1 ( 993830 92310 ) M1M2_PR
+ NEW met1 ( 1477750 92310 ) M1M2_PR ;
+ - la_oenb[21] ( PIN la_oenb[21] ) ( mprj la_oenb[21] ) + USE SIGNAL
+ + ROUTED met1 ( 1007630 91970 ) ( 1485110 * )
+ NEW met1 ( 1007630 58310 ) ( 1013610 * )
+ NEW met2 ( 1007630 58310 ) ( * 91970 )
+ NEW met2 ( 1013610 1700 0 ) ( * 58310 )
+ NEW met2 ( 1485110 91970 ) ( * 1580100 )
+ NEW met2 ( 1485110 1580100 ) ( 1486950 * )
+ NEW met2 ( 1486950 1688780 ) ( 1487570 * )
+ NEW met2 ( 1487570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1486950 1580100 ) ( * 1688780 )
+ NEW met1 ( 1007630 91970 ) M1M2_PR
+ NEW met1 ( 1485110 91970 ) M1M2_PR
+ NEW met1 ( 1007630 58310 ) M1M2_PR
+ NEW met1 ( 1013610 58310 ) M1M2_PR ;
+ - la_oenb[22] ( PIN la_oenb[22] ) ( mprj la_oenb[22] ) + USE SIGNAL
+ + ROUTED met1 ( 1490630 1651890 ) ( * 1653930 )
+ NEW met1 ( 1490630 1651890 ) ( 1491090 * )
+ NEW met2 ( 1031090 1700 0 ) ( * 60350 )
+ NEW met2 ( 1491090 60350 ) ( * 1651890 )
+ NEW met1 ( 1490630 1689290 ) ( 1493090 * )
+ NEW met2 ( 1493090 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1490630 1653930 ) ( * 1689290 )
+ NEW met1 ( 1031090 60350 ) ( 1491090 * )
+ NEW met1 ( 1490630 1653930 ) M1M2_PR
+ NEW met1 ( 1491090 1651890 ) M1M2_PR
+ NEW met1 ( 1031090 60350 ) M1M2_PR
+ NEW met1 ( 1491090 60350 ) M1M2_PR
+ NEW met1 ( 1490630 1689290 ) M1M2_PR
+ NEW met1 ( 1493090 1689290 ) M1M2_PR ;
+ - la_oenb[23] ( PIN la_oenb[23] ) ( mprj la_oenb[23] ) + USE SIGNAL
+ + ROUTED met2 ( 1049030 1700 0 ) ( * 60690 )
+ NEW met2 ( 1498450 1688780 ) ( 1498610 * )
+ NEW met2 ( 1498610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1498450 60690 ) ( * 1688780 )
+ NEW met1 ( 1049030 60690 ) ( 1498450 * )
+ NEW met1 ( 1049030 60690 ) M1M2_PR
+ NEW met1 ( 1498450 60690 ) M1M2_PR ;
+ - la_oenb[24] ( PIN la_oenb[24] ) ( mprj la_oenb[24] ) + USE SIGNAL
+ + ROUTED met2 ( 1066970 1700 0 ) ( * 61030 )
+ NEW met1 ( 1497990 1652570 ) ( 1503970 * )
+ NEW met2 ( 1497990 61030 ) ( * 1652570 )
+ NEW met2 ( 1503970 1688780 ) ( 1504130 * )
+ NEW met2 ( 1504130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1503970 1652570 ) ( * 1688780 )
+ NEW met1 ( 1066970 61030 ) ( 1497990 * )
+ NEW met1 ( 1066970 61030 ) M1M2_PR
+ NEW met1 ( 1497990 1652570 ) M1M2_PR
+ NEW met1 ( 1503970 1652570 ) M1M2_PR
+ NEW met1 ( 1497990 61030 ) M1M2_PR ;
+ - la_oenb[25] ( PIN la_oenb[25] ) ( mprj la_oenb[25] ) + USE SIGNAL
+ + ROUTED met2 ( 1084450 1700 0 ) ( * 61370 )
+ NEW met1 ( 1504890 1688950 ) ( 1509650 * )
+ NEW met2 ( 1509650 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1504890 61370 ) ( * 1688950 )
+ NEW met1 ( 1084450 61370 ) ( 1504890 * )
+ NEW met1 ( 1084450 61370 ) M1M2_PR
+ NEW met1 ( 1504890 61370 ) M1M2_PR
+ NEW met1 ( 1504890 1688950 ) M1M2_PR
+ NEW met1 ( 1509650 1688950 ) M1M2_PR ;
+ - la_oenb[26] ( PIN la_oenb[26] ) ( mprj la_oenb[26] ) + USE SIGNAL
+ + ROUTED met2 ( 1100090 1700 ) ( 1102390 * 0 )
+ NEW met2 ( 1100090 1700 ) ( * 61710 )
+ NEW met2 ( 1512250 61710 ) ( * 1676700 )
+ NEW met2 ( 1512250 1676700 ) ( 1515010 * )
+ NEW met2 ( 1515010 1676700 ) ( * 1688780 )
+ NEW met2 ( 1515010 1688780 ) ( 1515170 * )
+ NEW met2 ( 1515170 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1100090 61710 ) ( 1512250 * )
+ NEW met1 ( 1100090 61710 ) M1M2_PR
+ NEW met1 ( 1512250 61710 ) M1M2_PR ;
+ - la_oenb[27] ( PIN la_oenb[27] ) ( mprj la_oenb[27] ) + USE SIGNAL
+ + ROUTED met2 ( 1118030 1700 ) ( 1119870 * 0 )
+ NEW met2 ( 1118030 1700 ) ( * 62050 )
+ NEW met2 ( 1519150 1688780 ) ( 1520690 * )
+ NEW met2 ( 1520690 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1519150 62050 ) ( * 1688780 )
+ NEW met1 ( 1118030 62050 ) ( 1519150 * )
+ NEW met1 ( 1118030 62050 ) M1M2_PR
+ NEW met1 ( 1519150 62050 ) M1M2_PR ;
+ - la_oenb[28] ( PIN la_oenb[28] ) ( mprj la_oenb[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1137810 1700 0 ) ( * 20910 )
+ NEW met1 ( 1131830 20910 ) ( 1137810 * )
+ NEW met2 ( 1131830 20910 ) ( * 58310 )
+ NEW met2 ( 1525590 1688780 ) ( 1526210 * )
+ NEW met2 ( 1526210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1525590 58310 ) ( * 1688780 )
+ NEW met1 ( 1131830 58310 ) ( 1525590 * )
+ NEW met1 ( 1137810 20910 ) M1M2_PR
+ NEW met1 ( 1131830 20910 ) M1M2_PR
+ NEW met1 ( 1131830 58310 ) M1M2_PR
+ NEW met1 ( 1525590 58310 ) M1M2_PR ;
+ - la_oenb[29] ( PIN la_oenb[29] ) ( mprj la_oenb[29] ) + USE SIGNAL
+ + ROUTED met2 ( 1155290 1700 0 ) ( * 57970 )
+ NEW met1 ( 1526050 1652570 ) ( 1531570 * )
+ NEW met2 ( 1526050 57970 ) ( * 1652570 )
+ NEW met2 ( 1531570 1688780 ) ( 1531730 * )
+ NEW met2 ( 1531730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1531570 1652570 ) ( * 1688780 )
+ NEW met1 ( 1155290 57970 ) ( 1526050 * )
+ NEW met1 ( 1155290 57970 ) M1M2_PR
+ NEW met1 ( 1526050 1652570 ) M1M2_PR
+ NEW met1 ( 1531570 1652570 ) M1M2_PR
+ NEW met1 ( 1526050 57970 ) M1M2_PR ;
+ - la_oenb[2] ( PIN la_oenb[2] ) ( mprj la_oenb[2] ) + USE SIGNAL
+ + ROUTED met2 ( 676430 1700 0 ) ( * 59670 )
+ NEW met2 ( 1381610 59670 ) ( * 1580100 )
+ NEW met2 ( 1381610 1580100 ) ( 1382990 * )
+ NEW met2 ( 1382990 1688780 ) ( 1383610 * )
+ NEW met2 ( 1383610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1382990 1580100 ) ( * 1688780 )
+ NEW met1 ( 676430 59670 ) ( 1381610 * )
+ NEW met1 ( 676430 59670 ) M1M2_PR
+ NEW met1 ( 1381610 59670 ) M1M2_PR ;
+ - la_oenb[30] ( PIN la_oenb[30] ) ( mprj la_oenb[30] ) + USE SIGNAL
+ + ROUTED met2 ( 1173230 1700 0 ) ( * 17340 )
+ NEW met2 ( 1173230 17340 ) ( 1174610 * )
+ NEW met1 ( 1533410 1652570 ) ( 1536630 * )
+ NEW met2 ( 1174610 17340 ) ( * 57630 )
+ NEW met2 ( 1533410 57630 ) ( * 1652570 )
+ NEW met2 ( 1536630 1688780 ) ( 1536790 * )
+ NEW met2 ( 1536790 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1536630 1652570 ) ( * 1688780 )
+ NEW met1 ( 1174610 57630 ) ( 1533410 * )
+ NEW met1 ( 1533410 1652570 ) M1M2_PR
+ NEW met1 ( 1536630 1652570 ) M1M2_PR
+ NEW met1 ( 1174610 57630 ) M1M2_PR
+ NEW met1 ( 1533410 57630 ) M1M2_PR ;
+ - la_oenb[31] ( PIN la_oenb[31] ) ( mprj la_oenb[31] ) + USE SIGNAL
+ + ROUTED met2 ( 1190710 1700 0 ) ( * 44710 )
+ NEW met2 ( 1539850 44710 ) ( * 1580100 )
+ NEW met2 ( 1539850 1580100 ) ( 1541230 * )
+ NEW met2 ( 1541230 1688780 ) ( 1542310 * )
+ NEW met2 ( 1542310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1541230 1580100 ) ( * 1688780 )
+ NEW met1 ( 1190710 44710 ) ( 1539850 * )
+ NEW met1 ( 1190710 44710 ) M1M2_PR
+ NEW met1 ( 1539850 44710 ) M1M2_PR ;
+ - la_oenb[32] ( PIN la_oenb[32] ) ( mprj la_oenb[32] ) + USE SIGNAL
+ + ROUTED met1 ( 1546750 1652910 ) ( * 1653930 )
+ NEW met2 ( 1546750 17170 ) ( * 1652910 )
+ NEW met2 ( 1546750 1688780 ) ( 1547830 * )
+ NEW met2 ( 1547830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1546750 1653930 ) ( * 1688780 )
+ NEW met2 ( 1208650 1700 0 ) ( * 17170 )
+ NEW met1 ( 1208650 17170 ) ( 1546750 * )
+ NEW met1 ( 1546750 17170 ) M1M2_PR
+ NEW met1 ( 1546750 1652910 ) M1M2_PR
+ NEW met1 ( 1546750 1653930 ) M1M2_PR
+ NEW met1 ( 1208650 17170 ) M1M2_PR ;
+ - la_oenb[33] ( PIN la_oenb[33] ) ( mprj la_oenb[33] ) + USE SIGNAL
+ + ROUTED met2 ( 1372870 18530 ) ( * 37910 )
+ NEW met2 ( 1553420 1688780 ) ( 1554110 * )
+ NEW met2 ( 1553420 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1554110 37910 ) ( * 1688780 )
+ NEW met2 ( 1226130 1700 0 ) ( * 18530 )
+ NEW met1 ( 1226130 18530 ) ( 1372870 * )
+ NEW met1 ( 1372870 37910 ) ( 1554110 * )
+ NEW met1 ( 1372870 18530 ) M1M2_PR
+ NEW met1 ( 1372870 37910 ) M1M2_PR
+ NEW met1 ( 1554110 37910 ) M1M2_PR
+ NEW met1 ( 1226130 18530 ) M1M2_PR ;
+ - la_oenb[34] ( PIN la_oenb[34] ) ( mprj la_oenb[34] ) + USE SIGNAL
+ + ROUTED met2 ( 1244070 1700 0 ) ( * 19550 )
+ NEW met1 ( 1553650 1652570 ) ( 1558710 * )
+ NEW met2 ( 1376550 19550 ) ( * 38250 )
+ NEW met2 ( 1553650 38250 ) ( * 1652570 )
+ NEW met2 ( 1558710 1688780 ) ( 1558870 * )
+ NEW met2 ( 1558870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1558710 1652570 ) ( * 1688780 )
+ NEW met1 ( 1244070 19550 ) ( 1376550 * )
+ NEW met1 ( 1376550 38250 ) ( 1553650 * )
+ NEW met1 ( 1244070 19550 ) M1M2_PR
+ NEW met1 ( 1376550 19550 ) M1M2_PR
+ NEW met1 ( 1553650 1652570 ) M1M2_PR
+ NEW met1 ( 1558710 1652570 ) M1M2_PR
+ NEW met1 ( 1376550 38250 ) M1M2_PR
+ NEW met1 ( 1553650 38250 ) M1M2_PR ;
+ - la_oenb[35] ( PIN la_oenb[35] ) ( mprj la_oenb[35] ) + USE SIGNAL
+ + ROUTED met2 ( 1262010 1700 0 ) ( * 19210 )
+ NEW met1 ( 1560090 1688950 ) ( 1564390 * )
+ NEW met2 ( 1564390 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1560090 38590 ) ( * 1688950 )
+ NEW met1 ( 1262010 19210 ) ( 1387590 * )
+ NEW met2 ( 1387590 19210 ) ( * 38590 )
+ NEW met1 ( 1387590 38590 ) ( 1560090 * )
+ NEW met1 ( 1262010 19210 ) M1M2_PR
+ NEW met1 ( 1560090 38590 ) M1M2_PR
+ NEW met1 ( 1560090 1688950 ) M1M2_PR
+ NEW met1 ( 1564390 1688950 ) M1M2_PR
+ NEW met1 ( 1387590 19210 ) M1M2_PR
+ NEW met1 ( 1387590 38590 ) M1M2_PR ;
+ - la_oenb[36] ( PIN la_oenb[36] ) ( mprj la_oenb[36] ) + USE SIGNAL
+ + ROUTED met2 ( 1279490 1700 0 ) ( * 18870 )
+ NEW met2 ( 1567450 38930 ) ( * 1580100 )
+ NEW met2 ( 1567450 1580100 ) ( 1569290 * )
+ NEW met2 ( 1569290 1688780 ) ( 1569910 * )
+ NEW met2 ( 1569910 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1569290 1580100 ) ( * 1688780 )
+ NEW met2 ( 1419330 18870 ) ( * 38930 )
+ NEW met1 ( 1279490 18870 ) ( 1419330 * )
+ NEW met1 ( 1419330 38930 ) ( 1567450 * )
+ NEW met1 ( 1279490 18870 ) M1M2_PR
+ NEW met1 ( 1567450 38930 ) M1M2_PR
+ NEW met1 ( 1419330 18870 ) M1M2_PR
+ NEW met1 ( 1419330 38930 ) M1M2_PR ;
+ - la_oenb[37] ( PIN la_oenb[37] ) ( mprj la_oenb[37] ) + USE SIGNAL
+ + ROUTED met2 ( 1342050 16150 ) ( * 1681810 )
+ NEW met2 ( 1532030 1678070 ) ( * 1681810 )
+ NEW met1 ( 1532030 1678070 ) ( 1575270 * )
+ NEW met2 ( 1575270 1678070 ) ( * 1688780 )
+ NEW met2 ( 1575270 1688780 ) ( 1575430 * )
+ NEW met2 ( 1575430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1297430 1700 0 ) ( * 16150 )
+ NEW met1 ( 1297430 16150 ) ( 1342050 * )
+ NEW met1 ( 1342050 1681810 ) ( 1532030 * )
+ NEW met1 ( 1342050 16150 ) M1M2_PR
+ NEW met1 ( 1342050 1681810 ) M1M2_PR
+ NEW met1 ( 1532030 1681810 ) M1M2_PR
+ NEW met1 ( 1532030 1678070 ) M1M2_PR
+ NEW met1 ( 1575270 1678070 ) M1M2_PR
+ NEW met1 ( 1297430 16150 ) M1M2_PR ;
+ - la_oenb[38] ( PIN la_oenb[38] ) ( mprj la_oenb[38] ) + USE SIGNAL
+ + ROUTED met2 ( 1312610 1700 ) ( 1314910 * 0 )
+ NEW met2 ( 1312610 1700 ) ( * 2380 )
+ NEW met2 ( 1311230 2380 ) ( 1312610 * )
+ NEW met2 ( 1311230 2380 ) ( * 1679940 )
+ NEW met2 ( 1580330 1679940 ) ( * 1689460 )
+ NEW met2 ( 1580330 1689460 ) ( 1580950 * )
+ NEW met2 ( 1580950 1689460 ) ( * 1690140 0 )
+ NEW met3 ( 1311230 1679940 ) ( 1580330 * )
+ NEW met2 ( 1311230 1679940 ) M2M3_PR
+ NEW met2 ( 1580330 1679940 ) M2M3_PR ;
+ - la_oenb[39] ( PIN la_oenb[39] ) ( mprj la_oenb[39] ) + USE SIGNAL
+ + ROUTED met1 ( 1555490 1680450 ) ( * 1681130 )
+ NEW met2 ( 1332850 1700 0 ) ( 1333770 * )
+ NEW met2 ( 1333770 1700 ) ( * 1680450 )
+ NEW met1 ( 1333770 1680450 ) ( 1555490 * )
+ NEW met2 ( 1586310 1681130 ) ( * 1688780 )
+ NEW met2 ( 1586310 1688780 ) ( 1586470 * )
+ NEW met2 ( 1586470 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1555490 1681130 ) ( 1586310 * )
+ NEW met1 ( 1333770 1680450 ) M1M2_PR
+ NEW met1 ( 1586310 1681130 ) M1M2_PR ;
+ - la_oenb[3] ( PIN la_oenb[3] ) ( mprj la_oenb[3] ) + USE SIGNAL
+ + ROUTED met2 ( 694370 1700 0 ) ( * 60010 )
+ NEW met1 ( 694370 60010 ) ( 1388510 * )
+ NEW met2 ( 1388510 1688780 ) ( 1389130 * )
+ NEW met2 ( 1389130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1388510 60010 ) ( * 1688780 )
+ NEW met1 ( 694370 60010 ) M1M2_PR
+ NEW met1 ( 1388510 60010 ) M1M2_PR ;
+ - la_oenb[40] ( PIN la_oenb[40] ) ( mprj la_oenb[40] ) + USE SIGNAL
+ + ROUTED met2 ( 1347110 82800 ) ( 1350330 * )
+ NEW met2 ( 1350330 1700 0 ) ( * 82800 )
+ NEW met2 ( 1347110 82800 ) ( * 1681470 )
+ NEW met1 ( 1532490 1681470 ) ( * 1681810 )
+ NEW met1 ( 1532490 1681810 ) ( 1551350 * )
+ NEW met2 ( 1551350 1681810 ) ( * 1681980 )
+ NEW met2 ( 1551350 1681980 ) ( 1551810 * )
+ NEW met2 ( 1551810 1681980 ) ( * 1682830 )
+ NEW met1 ( 1347110 1681470 ) ( 1532490 * )
+ NEW met2 ( 1591830 1682830 ) ( * 1688780 )
+ NEW met2 ( 1591830 1688780 ) ( 1591990 * )
+ NEW met2 ( 1591990 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1551810 1682830 ) ( 1591830 * )
+ NEW met1 ( 1347110 1681470 ) M1M2_PR
+ NEW met1 ( 1551350 1681810 ) M1M2_PR
+ NEW met1 ( 1551810 1682830 ) M1M2_PR
+ NEW met1 ( 1591830 1682830 ) M1M2_PR ;
+ - la_oenb[41] ( PIN la_oenb[41] ) ( mprj la_oenb[41] ) + USE SIGNAL
+ + ROUTED met2 ( 1368270 1700 0 ) ( * 1682150 )
+ NEW met2 ( 1596890 1682150 ) ( * 1688780 )
+ NEW met2 ( 1596890 1688780 ) ( 1597050 * )
+ NEW met2 ( 1597050 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1368270 1682150 ) ( 1596890 * )
+ NEW met1 ( 1368270 1682150 ) M1M2_PR
+ NEW met1 ( 1596890 1682150 ) M1M2_PR ;
+ - la_oenb[42] ( PIN la_oenb[42] ) ( mprj la_oenb[42] ) + USE SIGNAL
+ + ROUTED met2 ( 1383910 1700 ) ( 1385750 * 0 )
+ NEW met1 ( 1380230 58650 ) ( 1383910 * )
+ NEW met2 ( 1383910 1700 ) ( * 58650 )
+ NEW met2 ( 1380230 58650 ) ( * 1682490 )
+ NEW met2 ( 1601030 1682490 ) ( * 1689460 )
+ NEW met2 ( 1601030 1689460 ) ( 1602570 * )
+ NEW met2 ( 1602570 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1380230 1682490 ) ( 1601030 * )
+ NEW met1 ( 1380230 58650 ) M1M2_PR
+ NEW met1 ( 1383910 58650 ) M1M2_PR
+ NEW met1 ( 1380230 1682490 ) M1M2_PR
+ NEW met1 ( 1601030 1682490 ) M1M2_PR ;
+ - la_oenb[43] ( PIN la_oenb[43] ) ( mprj la_oenb[43] ) + USE SIGNAL
+ + ROUTED met2 ( 1400930 82800 ) ( 1403690 * )
+ NEW met2 ( 1403690 1700 0 ) ( * 82800 )
+ NEW met2 ( 1400930 82800 ) ( * 1683170 )
+ NEW met2 ( 1607930 1683170 ) ( * 1689460 )
+ NEW met2 ( 1607930 1689460 ) ( 1608090 * )
+ NEW met2 ( 1608090 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1400930 1683170 ) ( 1607930 * )
+ NEW met1 ( 1400930 1683170 ) M1M2_PR
+ NEW met1 ( 1607930 1683170 ) M1M2_PR ;
+ - la_oenb[44] ( PIN la_oenb[44] ) ( mprj la_oenb[44] ) + USE SIGNAL
+ + ROUTED met1 ( 1608390 1688950 ) ( 1613610 * )
+ NEW met2 ( 1613610 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1608390 18870 ) ( * 1688950 )
+ NEW met2 ( 1421630 1700 0 ) ( * 18870 )
+ NEW met1 ( 1421630 18870 ) ( 1608390 * )
+ NEW met1 ( 1608390 18870 ) M1M2_PR
+ NEW met1 ( 1608390 1688950 ) M1M2_PR
+ NEW met1 ( 1613610 1688950 ) M1M2_PR
+ NEW met1 ( 1421630 18870 ) M1M2_PR ;
+ - la_oenb[45] ( PIN la_oenb[45] ) ( mprj la_oenb[45] ) + USE SIGNAL
+ + ROUTED met2 ( 1616210 1688780 ) ( 1619130 * )
+ NEW met2 ( 1619130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1616210 19210 ) ( * 1688780 )
+ NEW met2 ( 1439110 1700 0 ) ( * 19210 )
+ NEW met1 ( 1439110 19210 ) ( 1616210 * )
+ NEW met1 ( 1616210 19210 ) M1M2_PR
+ NEW met1 ( 1439110 19210 ) M1M2_PR ;
+ - la_oenb[46] ( PIN la_oenb[46] ) ( mprj la_oenb[46] ) + USE SIGNAL
+ + ROUTED met1 ( 1456130 1683510 ) ( 1469470 * )
+ NEW met1 ( 1469470 1683510 ) ( * 1683850 )
+ NEW met1 ( 1469470 1683850 ) ( 1473610 * )
+ NEW met1 ( 1473610 1683510 ) ( * 1683850 )
+ NEW met2 ( 1624490 1683510 ) ( * 1688780 )
+ NEW met2 ( 1624490 1688780 ) ( 1624650 * )
+ NEW met2 ( 1624650 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1473610 1683510 ) ( 1624490 * )
+ NEW met2 ( 1457050 1700 0 ) ( * 13800 )
+ NEW met2 ( 1456130 13800 ) ( 1457050 * )
+ NEW met2 ( 1456130 13800 ) ( * 1683510 )
+ NEW met1 ( 1456130 1683510 ) M1M2_PR
+ NEW met1 ( 1624490 1683510 ) M1M2_PR ;
+ - la_oenb[47] ( PIN la_oenb[47] ) ( mprj la_oenb[47] ) + USE SIGNAL
+ + ROUTED met2 ( 1474530 1700 0 ) ( * 16150 )
+ NEW met2 ( 1563310 82800 ) ( 1563770 * )
+ NEW met2 ( 1563770 16150 ) ( * 82800 )
+ NEW met2 ( 1563310 82800 ) ( * 1678410 )
+ NEW met2 ( 1628630 1678410 ) ( * 1689460 )
+ NEW met2 ( 1628630 1689460 ) ( 1630170 * )
+ NEW met2 ( 1630170 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1474530 16150 ) ( 1563770 * )
+ NEW met1 ( 1563310 1678410 ) ( 1628630 * )
+ NEW met1 ( 1474530 16150 ) M1M2_PR
+ NEW met1 ( 1563770 16150 ) M1M2_PR
+ NEW met1 ( 1563310 1678410 ) M1M2_PR
+ NEW met1 ( 1628630 1678410 ) M1M2_PR ;
+ - la_oenb[48] ( PIN la_oenb[48] ) ( mprj la_oenb[48] ) + USE SIGNAL
+ + ROUTED met2 ( 1576650 16830 ) ( * 1681810 )
+ NEW met2 ( 1635530 1681810 ) ( * 1689460 )
+ NEW met2 ( 1635530 1689460 ) ( 1635690 * )
+ NEW met2 ( 1635690 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 1492470 1700 0 ) ( * 16830 )
+ NEW met1 ( 1492470 16830 ) ( 1576650 * )
+ NEW met1 ( 1576650 1681810 ) ( 1635530 * )
+ NEW met1 ( 1576650 16830 ) M1M2_PR
+ NEW met1 ( 1576650 1681810 ) M1M2_PR
+ NEW met1 ( 1635530 1681810 ) M1M2_PR
+ NEW met1 ( 1492470 16830 ) M1M2_PR ;
+ - la_oenb[49] ( PIN la_oenb[49] ) ( mprj la_oenb[49] ) + USE SIGNAL
+ + ROUTED met1 ( 1635990 1688950 ) ( 1641210 * )
+ NEW met2 ( 1641210 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1635990 18020 ) ( * 1688950 )
+ NEW met2 ( 1509950 1700 0 ) ( * 16660 )
+ NEW met3 ( 1509950 16660 ) ( 1580100 * )
+ NEW met3 ( 1580100 16660 ) ( * 18020 )
+ NEW met3 ( 1580100 18020 ) ( 1635990 * )
+ NEW met2 ( 1635990 18020 ) M2M3_PR
+ NEW met1 ( 1635990 1688950 ) M1M2_PR
+ NEW met1 ( 1641210 1688950 ) M1M2_PR
+ NEW met2 ( 1509950 16660 ) M2M3_PR ;
+ - la_oenb[4] ( PIN la_oenb[4] ) ( mprj la_oenb[4] ) + USE SIGNAL
+ + ROUTED met2 ( 710930 1700 ) ( 712310 * 0 )
+ NEW met1 ( 710930 86190 ) ( 1394490 * )
+ NEW met2 ( 710930 1700 ) ( * 86190 )
+ NEW met2 ( 1394490 1688780 ) ( 1394650 * )
+ NEW met2 ( 1394650 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1394490 86190 ) ( * 1688780 )
+ NEW met1 ( 710930 86190 ) M1M2_PR
+ NEW met1 ( 1394490 86190 ) M1M2_PR ;
+ - la_oenb[50] ( PIN la_oenb[50] ) ( mprj la_oenb[50] ) + USE SIGNAL
+ + ROUTED met1 ( 1642430 1652230 ) ( * 1653250 )
+ NEW met1 ( 1642430 1653250 ) ( 1642890 * )
+ NEW met2 ( 1642430 19890 ) ( * 1652230 )
+ NEW met1 ( 1642890 1688270 ) ( 1646730 * )
+ NEW met1 ( 1646730 1688270 ) ( * 1689290 )
+ NEW met2 ( 1646730 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1642890 1653250 ) ( * 1688270 )
+ NEW met2 ( 1527890 1700 0 ) ( * 19890 )
+ NEW met1 ( 1527890 19890 ) ( 1642430 * )
+ NEW met1 ( 1642430 19890 ) M1M2_PR
+ NEW met1 ( 1642430 1652230 ) M1M2_PR
+ NEW met1 ( 1642890 1653250 ) M1M2_PR
+ NEW met1 ( 1642890 1688270 ) M1M2_PR
+ NEW met1 ( 1646730 1689290 ) M1M2_PR
+ NEW met1 ( 1527890 19890 ) M1M2_PR ;
+ - la_oenb[51] ( PIN la_oenb[51] ) ( mprj la_oenb[51] ) + USE SIGNAL
+ + ROUTED met2 ( 1545370 1700 0 ) ( * 20570 )
+ NEW met2 ( 1650710 1688780 ) ( 1652250 * )
+ NEW met2 ( 1652250 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1650710 20570 ) ( * 1688780 )
+ NEW met1 ( 1545370 20570 ) ( 1650710 * )
+ NEW met1 ( 1545370 20570 ) M1M2_PR
+ NEW met1 ( 1650710 20570 ) M1M2_PR ;
+ - la_oenb[52] ( PIN la_oenb[52] ) ( mprj la_oenb[52] ) + USE SIGNAL
+ + ROUTED met2 ( 1563310 1700 0 ) ( * 17510 )
+ NEW met2 ( 1657610 17510 ) ( * 34500 )
+ NEW met2 ( 1657610 34500 ) ( 1658070 * )
+ NEW met2 ( 1657380 1688780 ) ( 1658070 * )
+ NEW met2 ( 1657380 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1658070 34500 ) ( * 1688780 )
+ NEW met1 ( 1563310 17510 ) ( 1657610 * )
+ NEW met1 ( 1563310 17510 ) M1M2_PR
+ NEW met1 ( 1657610 17510 ) M1M2_PR ;
+ - la_oenb[53] ( PIN la_oenb[53] ) ( mprj la_oenb[53] ) + USE SIGNAL
+ + ROUTED met1 ( 1657150 1652570 ) ( 1662670 * )
+ NEW met2 ( 1657150 16830 ) ( * 1652570 )
+ NEW met2 ( 1662670 1688780 ) ( 1662830 * )
+ NEW met2 ( 1662830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1662670 1652570 ) ( * 1688780 )
+ NEW met2 ( 1581250 1700 0 ) ( * 16830 )
+ NEW met1 ( 1581250 16830 ) ( 1657150 * )
+ NEW met1 ( 1657150 16830 ) M1M2_PR
+ NEW met1 ( 1657150 1652570 ) M1M2_PR
+ NEW met1 ( 1662670 1652570 ) M1M2_PR
+ NEW met1 ( 1581250 16830 ) M1M2_PR ;
+ - la_oenb[54] ( PIN la_oenb[54] ) ( mprj la_oenb[54] ) + USE SIGNAL
+ + ROUTED met2 ( 1668190 1682830 ) ( * 1688780 )
+ NEW met2 ( 1668190 1688780 ) ( 1668350 * )
+ NEW met2 ( 1668350 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1595970 82800 ) ( 1598730 * )
+ NEW met2 ( 1598730 1700 0 ) ( * 82800 )
+ NEW met2 ( 1595970 82800 ) ( * 1682830 )
+ NEW met1 ( 1595970 1682830 ) ( 1668190 * )
+ NEW met1 ( 1668190 1682830 ) M1M2_PR
+ NEW met1 ( 1595970 1682830 ) M1M2_PR ;
+ - la_oenb[55] ( PIN la_oenb[55] ) ( mprj la_oenb[55] ) + USE SIGNAL
+ + ROUTED met2 ( 1644730 15810 ) ( * 18190 )
+ NEW met1 ( 1644730 18190 ) ( 1670030 * )
+ NEW met1 ( 1670030 1652910 ) ( 1673710 * )
+ NEW met2 ( 1670030 18190 ) ( * 1652910 )
+ NEW met2 ( 1673710 1688780 ) ( 1673870 * )
+ NEW met2 ( 1673870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1673710 1652910 ) ( * 1688780 )
+ NEW met2 ( 1616670 1700 0 ) ( * 15810 )
+ NEW met1 ( 1616670 15810 ) ( 1644730 * )
+ NEW met1 ( 1644730 15810 ) M1M2_PR
+ NEW met1 ( 1644730 18190 ) M1M2_PR
+ NEW met1 ( 1670030 18190 ) M1M2_PR
+ NEW met1 ( 1670030 1652910 ) M1M2_PR
+ NEW met1 ( 1673710 1652910 ) M1M2_PR
+ NEW met1 ( 1616670 15810 ) M1M2_PR ;
+ - la_oenb[56] ( PIN la_oenb[56] ) ( mprj la_oenb[56] ) + USE SIGNAL
+ + ROUTED met2 ( 1634150 1700 0 ) ( * 19550 )
+ NEW met1 ( 1634150 19550 ) ( 1642890 * )
+ NEW met1 ( 1642890 19550 ) ( * 19890 )
+ NEW met1 ( 1642890 19890 ) ( 1677850 * )
+ NEW met2 ( 1677850 1688780 ) ( 1679390 * )
+ NEW met2 ( 1679390 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1677850 19890 ) ( * 1688780 )
+ NEW met1 ( 1634150 19550 ) M1M2_PR
+ NEW met1 ( 1677850 19890 ) M1M2_PR ;
+ - la_oenb[57] ( PIN la_oenb[57] ) ( mprj la_oenb[57] ) + USE SIGNAL
+ + ROUTED met2 ( 1652090 1700 0 ) ( * 20230 )
+ NEW met1 ( 1652090 20230 ) ( 1684750 * )
+ NEW met2 ( 1684750 1688780 ) ( 1684910 * )
+ NEW met2 ( 1684910 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1684750 20230 ) ( * 1688780 )
+ NEW met1 ( 1652090 20230 ) M1M2_PR
+ NEW met1 ( 1684750 20230 ) M1M2_PR ;
+ - la_oenb[58] ( PIN la_oenb[58] ) ( mprj la_oenb[58] ) + USE SIGNAL
+ + ROUTED met2 ( 1669570 1700 0 ) ( * 20570 )
+ NEW met1 ( 1669570 20570 ) ( 1685210 * )
+ NEW met2 ( 1685210 20570 ) ( * 1580100 )
+ NEW met2 ( 1685210 1580100 ) ( 1690270 * )
+ NEW met2 ( 1690270 1688780 ) ( 1690430 * )
+ NEW met2 ( 1690430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1690270 1580100 ) ( * 1688780 )
+ NEW met1 ( 1669570 20570 ) M1M2_PR
+ NEW met1 ( 1685210 20570 ) M1M2_PR ;
+ - la_oenb[59] ( PIN la_oenb[59] ) ( mprj la_oenb[59] ) + USE SIGNAL
+ + ROUTED met2 ( 1687510 1700 0 ) ( * 17510 )
+ NEW met1 ( 1687510 17510 ) ( 1691650 * )
+ NEW met2 ( 1691650 17510 ) ( * 1580100 )
+ NEW met2 ( 1691650 1580100 ) ( 1693950 * )
+ NEW met2 ( 1693950 1688780 ) ( 1695950 * )
+ NEW met2 ( 1695950 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1693950 1580100 ) ( * 1688780 )
+ NEW met1 ( 1687510 17510 ) M1M2_PR
+ NEW met1 ( 1691650 17510 ) M1M2_PR ;
+ - la_oenb[5] ( PIN la_oenb[5] ) ( mprj la_oenb[5] ) + USE SIGNAL
+ + ROUTED met2 ( 727490 1700 ) ( 729790 * 0 )
+ NEW met1 ( 724730 96050 ) ( 1395410 * )
+ NEW met2 ( 724730 82800 ) ( * 96050 )
+ NEW met2 ( 724730 82800 ) ( 727490 * )
+ NEW met2 ( 727490 1700 ) ( * 82800 )
+ NEW met2 ( 1395410 96050 ) ( * 1580100 )
+ NEW met2 ( 1395410 1580100 ) ( 1399550 * )
+ NEW met2 ( 1399550 1688780 ) ( 1400170 * )
+ NEW met2 ( 1400170 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1399550 1580100 ) ( * 1688780 )
+ NEW met1 ( 724730 96050 ) M1M2_PR
+ NEW met1 ( 1395410 96050 ) M1M2_PR ;
+ - la_oenb[60] ( PIN la_oenb[60] ) ( mprj la_oenb[60] ) + USE SIGNAL
+ + ROUTED met2 ( 1704990 1700 0 ) ( * 16830 )
+ NEW met1 ( 1698550 16830 ) ( 1704990 * )
+ NEW met2 ( 1698550 1688780 ) ( 1701470 * )
+ NEW met2 ( 1701470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1698550 16830 ) ( * 1688780 )
+ NEW met1 ( 1704990 16830 ) M1M2_PR
+ NEW met1 ( 1698550 16830 ) M1M2_PR ;
+ - la_oenb[61] ( PIN la_oenb[61] ) ( mprj la_oenb[61] ) + USE SIGNAL
+ + ROUTED met2 ( 1722930 1700 0 ) ( * 17510 )
+ NEW met1 ( 1704990 17510 ) ( 1722930 * )
+ NEW met2 ( 1704990 17510 ) ( * 1676700 )
+ NEW met2 ( 1704530 1676700 ) ( 1704990 * )
+ NEW met2 ( 1704530 1676700 ) ( * 1689290 )
+ NEW met1 ( 1704530 1689290 ) ( 1706990 * )
+ NEW met2 ( 1706990 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 1722930 17510 ) M1M2_PR
+ NEW met1 ( 1704990 17510 ) M1M2_PR
+ NEW met1 ( 1704530 1689290 ) M1M2_PR
+ NEW met1 ( 1706990 1689290 ) M1M2_PR ;
+ - la_oenb[62] ( PIN la_oenb[62] ) ( mprj la_oenb[62] ) + USE SIGNAL
+ + ROUTED met2 ( 1740410 1700 0 ) ( * 17850 )
+ NEW met1 ( 1712350 17850 ) ( 1740410 * )
+ NEW met2 ( 1712350 1688780 ) ( 1712510 * )
+ NEW met2 ( 1712510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1712350 17850 ) ( * 1688780 )
+ NEW met1 ( 1740410 17850 ) M1M2_PR
+ NEW met1 ( 1712350 17850 ) M1M2_PR ;
+ - la_oenb[63] ( PIN la_oenb[63] ) ( mprj la_oenb[63] ) + USE SIGNAL
+ + ROUTED met2 ( 1758350 1700 0 ) ( * 15810 )
+ NEW met1 ( 1725000 15810 ) ( 1758350 * )
+ NEW met1 ( 1711430 16150 ) ( 1725000 * )
+ NEW met1 ( 1725000 15810 ) ( * 16150 )
+ NEW met1 ( 1711430 1688950 ) ( 1717570 * )
+ NEW met2 ( 1717570 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1711430 16150 ) ( * 1688950 )
+ NEW met1 ( 1758350 15810 ) M1M2_PR
+ NEW met1 ( 1711430 16150 ) M1M2_PR
+ NEW met1 ( 1711430 1688950 ) M1M2_PR
+ NEW met1 ( 1717570 1688950 ) M1M2_PR ;
+ - la_oenb[64] ( PIN la_oenb[64] ) ( mprj la_oenb[64] ) + USE SIGNAL
+ + ROUTED met2 ( 1776290 1700 0 ) ( * 20230 )
+ NEW met1 ( 1719250 20230 ) ( 1776290 * )
+ NEW met2 ( 1719250 20230 ) ( * 1676700 )
+ NEW met2 ( 1719250 1676700 ) ( 1722930 * )
+ NEW met2 ( 1722930 1676700 ) ( * 1688780 )
+ NEW met2 ( 1722930 1688780 ) ( 1723090 * )
+ NEW met2 ( 1723090 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1719250 20230 ) M1M2_PR
+ NEW met1 ( 1776290 20230 ) M1M2_PR ;
+ - la_oenb[65] ( PIN la_oenb[65] ) ( mprj la_oenb[65] ) + USE SIGNAL
+ + ROUTED met2 ( 1725230 1688780 ) ( 1728610 * )
+ NEW met2 ( 1728610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1725230 18530 ) ( * 1688780 )
+ NEW met2 ( 1793770 1700 0 ) ( * 18530 )
+ NEW met1 ( 1725230 18530 ) ( 1793770 * )
+ NEW met1 ( 1725230 18530 ) M1M2_PR
+ NEW met1 ( 1793770 18530 ) M1M2_PR ;
+ - la_oenb[66] ( PIN la_oenb[66] ) ( mprj la_oenb[66] ) + USE SIGNAL
+ + ROUTED met2 ( 1733050 1688780 ) ( 1734130 * )
+ NEW met2 ( 1734130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1733050 20570 ) ( * 1688780 )
+ NEW met2 ( 1811710 1700 0 ) ( * 20570 )
+ NEW met1 ( 1733050 20570 ) ( 1811710 * )
+ NEW met1 ( 1733050 20570 ) M1M2_PR
+ NEW met1 ( 1811710 20570 ) M1M2_PR ;
+ - la_oenb[67] ( PIN la_oenb[67] ) ( mprj la_oenb[67] ) + USE SIGNAL
+ + ROUTED met2 ( 1829190 1700 0 ) ( * 16490 )
+ NEW met2 ( 1739950 1683510 ) ( * 1689460 )
+ NEW met2 ( 1739720 1689460 ) ( 1739950 * )
+ NEW met2 ( 1739720 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1797450 16830 ) ( 1806190 * )
+ NEW met1 ( 1806190 16490 ) ( * 16830 )
+ NEW met1 ( 1806190 16490 ) ( 1829190 * )
+ NEW met1 ( 1739950 1683510 ) ( 1797450 * )
+ NEW met2 ( 1797450 16830 ) ( * 1683510 )
+ NEW met1 ( 1829190 16490 ) M1M2_PR
+ NEW met1 ( 1739950 1683510 ) M1M2_PR
+ NEW met1 ( 1797450 16830 ) M1M2_PR
+ NEW met1 ( 1797450 1683510 ) M1M2_PR ;
+ - la_oenb[68] ( PIN la_oenb[68] ) ( mprj la_oenb[68] ) + USE SIGNAL
+ + ROUTED met2 ( 1847130 1700 0 ) ( * 18870 )
+ NEW met2 ( 1739490 18870 ) ( * 1580100 )
+ NEW met2 ( 1739490 1580100 ) ( 1744550 * )
+ NEW met2 ( 1744550 1688780 ) ( 1745170 * )
+ NEW met2 ( 1745170 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1744550 1580100 ) ( * 1688780 )
+ NEW met1 ( 1739490 18870 ) ( 1847130 * )
+ NEW met1 ( 1739490 18870 ) M1M2_PR
+ NEW met1 ( 1847130 18870 ) M1M2_PR ;
+ - la_oenb[69] ( PIN la_oenb[69] ) ( mprj la_oenb[69] ) + USE SIGNAL
+ + ROUTED met2 ( 1864610 1700 0 ) ( * 17850 )
+ NEW met2 ( 1746390 17850 ) ( * 1580100 )
+ NEW met2 ( 1746390 1580100 ) ( 1750070 * )
+ NEW met2 ( 1750070 1688780 ) ( 1750690 * )
+ NEW met2 ( 1750690 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1750070 1580100 ) ( * 1688780 )
+ NEW met1 ( 1746390 17850 ) ( 1864610 * )
+ NEW met1 ( 1746390 17850 ) M1M2_PR
+ NEW met1 ( 1864610 17850 ) M1M2_PR ;
+ - la_oenb[6] ( PIN la_oenb[6] ) ( mprj la_oenb[6] ) + USE SIGNAL
+ + ROUTED met1 ( 745430 96390 ) ( 1402770 * )
+ NEW met2 ( 745430 82800 ) ( * 96390 )
+ NEW met2 ( 745430 82800 ) ( 747730 * )
+ NEW met2 ( 747730 1700 0 ) ( * 82800 )
+ NEW met2 ( 1402770 1688780 ) ( 1405690 * )
+ NEW met2 ( 1405690 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1402770 96390 ) ( * 1688780 )
+ NEW met1 ( 745430 96390 ) M1M2_PR
+ NEW met1 ( 1402770 96390 ) M1M2_PR ;
+ - la_oenb[70] ( PIN la_oenb[70] ) ( mprj la_oenb[70] ) + USE SIGNAL
+ + ROUTED met2 ( 1752830 17170 ) ( * 1580100 )
+ NEW met2 ( 1752830 1580100 ) ( 1755590 * )
+ NEW met2 ( 1755590 1688780 ) ( 1756210 * )
+ NEW met2 ( 1756210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1755590 1580100 ) ( * 1688780 )
+ NEW met2 ( 1882550 1700 0 ) ( * 17170 )
+ NEW met1 ( 1752830 17170 ) ( 1882550 * )
+ NEW met1 ( 1752830 17170 ) M1M2_PR
+ NEW met1 ( 1882550 17170 ) M1M2_PR ;
+ - la_oenb[71] ( PIN la_oenb[71] ) ( mprj la_oenb[71] ) + USE SIGNAL
+ + ROUTED met2 ( 1762030 1681470 ) ( * 1688780 )
+ NEW met2 ( 1761800 1688780 ) ( 1762030 * )
+ NEW met2 ( 1761800 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1900030 1700 0 ) ( * 18870 )
+ NEW met1 ( 1852650 18870 ) ( 1900030 * )
+ NEW met1 ( 1762030 1681470 ) ( 1852650 * )
+ NEW met2 ( 1852650 18870 ) ( * 1681470 )
+ NEW met1 ( 1852650 18870 ) M1M2_PR
+ NEW met1 ( 1762030 1681470 ) M1M2_PR
+ NEW met1 ( 1900030 18870 ) M1M2_PR
+ NEW met1 ( 1852650 1681470 ) M1M2_PR ;
+ - la_oenb[72] ( PIN la_oenb[72] ) ( mprj la_oenb[72] ) + USE SIGNAL
+ + ROUTED met2 ( 1766630 1688780 ) ( 1767250 * )
+ NEW met2 ( 1767250 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1766630 17510 ) ( * 1688780 )
+ NEW met2 ( 1917970 1700 0 ) ( * 17510 )
+ NEW met1 ( 1766630 17510 ) ( 1917970 * )
+ NEW met1 ( 1766630 17510 ) M1M2_PR
+ NEW met1 ( 1917970 17510 ) M1M2_PR ;
+ - la_oenb[73] ( PIN la_oenb[73] ) ( mprj la_oenb[73] ) + USE SIGNAL
+ + ROUTED met2 ( 1935910 1700 0 ) ( * 15470 )
+ NEW met2 ( 1773070 1681130 ) ( * 1688780 )
+ NEW met2 ( 1772840 1688780 ) ( 1773070 * )
+ NEW met2 ( 1772840 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1918200 15470 ) ( 1935910 * )
+ NEW met1 ( 1918200 15130 ) ( * 15470 )
+ NEW met1 ( 1859550 15130 ) ( 1918200 * )
+ NEW met1 ( 1773070 1681130 ) ( 1859550 * )
+ NEW met2 ( 1859550 15130 ) ( * 1681130 )
+ NEW met1 ( 1859550 15130 ) M1M2_PR
+ NEW met1 ( 1935910 15470 ) M1M2_PR
+ NEW met1 ( 1773070 1681130 ) M1M2_PR
+ NEW met1 ( 1859550 1681130 ) M1M2_PR ;
+ - la_oenb[74] ( PIN la_oenb[74] ) ( mprj la_oenb[74] ) + USE SIGNAL
+ + ROUTED met2 ( 1953390 1700 0 ) ( * 15810 )
+ NEW met1 ( 1866450 15470 ) ( 1869900 * )
+ NEW met1 ( 1869900 15470 ) ( * 15810 )
+ NEW met1 ( 1869900 15810 ) ( 1877030 * )
+ NEW met2 ( 1877030 15810 ) ( * 15980 )
+ NEW met2 ( 1877030 15980 ) ( 1878410 * )
+ NEW met2 ( 1878410 15810 ) ( * 15980 )
+ NEW met1 ( 1878410 15810 ) ( 1953390 * )
+ NEW met2 ( 1778130 1680450 ) ( * 1688780 )
+ NEW met2 ( 1777900 1688780 ) ( 1778130 * )
+ NEW met2 ( 1777900 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1778130 1680450 ) ( 1866450 * )
+ NEW met2 ( 1866450 15470 ) ( * 1680450 )
+ NEW met1 ( 1866450 15470 ) M1M2_PR
+ NEW met1 ( 1953390 15810 ) M1M2_PR
+ NEW met1 ( 1877030 15810 ) M1M2_PR
+ NEW met1 ( 1878410 15810 ) M1M2_PR
+ NEW met1 ( 1778130 1680450 ) M1M2_PR
+ NEW met1 ( 1866450 1680450 ) M1M2_PR ;
+ - la_oenb[75] ( PIN la_oenb[75] ) ( mprj la_oenb[75] ) + USE SIGNAL
+ + ROUTED met1 ( 1873350 15470 ) ( 1877490 * )
+ NEW met1 ( 1877490 15470 ) ( * 16150 )
+ NEW met2 ( 1971330 1700 0 ) ( * 16150 )
+ NEW met1 ( 1877490 16150 ) ( 1971330 * )
+ NEW met2 ( 1783650 1681810 ) ( * 1688780 )
+ NEW met2 ( 1783420 1688780 ) ( 1783650 * )
+ NEW met2 ( 1783420 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1783650 1681810 ) ( 1873350 * )
+ NEW met2 ( 1873350 15470 ) ( * 1681810 )
+ NEW met1 ( 1873350 15470 ) M1M2_PR
+ NEW met1 ( 1971330 16150 ) M1M2_PR
+ NEW met1 ( 1783650 1681810 ) M1M2_PR
+ NEW met1 ( 1873350 1681810 ) M1M2_PR ;
+ - la_oenb[76] ( PIN la_oenb[76] ) ( mprj la_oenb[76] ) + USE SIGNAL
+ + ROUTED met2 ( 1787330 1652740 ) ( 1788250 * )
+ NEW met2 ( 1988810 1700 0 ) ( * 21930 )
+ NEW met1 ( 1787330 21930 ) ( 1988810 * )
+ NEW met2 ( 1787330 21930 ) ( * 1652740 )
+ NEW met2 ( 1788250 1688780 ) ( 1788870 * )
+ NEW met2 ( 1788870 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1788250 1652740 ) ( * 1688780 )
+ NEW met1 ( 1787330 21930 ) M1M2_PR
+ NEW met1 ( 1988810 21930 ) M1M2_PR ;
+ - la_oenb[77] ( PIN la_oenb[77] ) ( mprj la_oenb[77] ) + USE SIGNAL
+ + ROUTED met2 ( 2006750 1700 0 ) ( * 18190 )
+ NEW met1 ( 1860010 18190 ) ( 2006750 * )
+ NEW met2 ( 1794230 1678750 ) ( * 1689460 )
+ NEW met2 ( 1794230 1689460 ) ( 1794390 * )
+ NEW met2 ( 1794390 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1794230 1678750 ) ( 1860010 * )
+ NEW met2 ( 1860010 18190 ) ( * 1678750 )
+ NEW met1 ( 1860010 18190 ) M1M2_PR
+ NEW met1 ( 2006750 18190 ) M1M2_PR
+ NEW met1 ( 1794230 1678750 ) M1M2_PR
+ NEW met1 ( 1860010 1678750 ) M1M2_PR ;
+ - la_oenb[78] ( PIN la_oenb[78] ) ( mprj la_oenb[78] ) + USE SIGNAL
+ + ROUTED met2 ( 2024230 1700 0 ) ( * 16660 )
+ NEW met2 ( 1794230 22100 ) ( 1794690 * )
+ NEW met2 ( 1794690 16660 ) ( * 22100 )
+ NEW met1 ( 1794230 1652570 ) ( 1799750 * )
+ NEW met3 ( 1794690 16660 ) ( 2024230 * )
+ NEW met2 ( 1794230 22100 ) ( * 1652570 )
+ NEW met2 ( 1799750 1688780 ) ( 1799910 * )
+ NEW met2 ( 1799910 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1799750 1652570 ) ( * 1688780 )
+ NEW met2 ( 2024230 16660 ) M2M3_PR
+ NEW met2 ( 1794690 16660 ) M2M3_PR
+ NEW met1 ( 1794230 1652570 ) M1M2_PR
+ NEW met1 ( 1799750 1652570 ) M1M2_PR ;
+ - la_oenb[79] ( PIN la_oenb[79] ) ( mprj la_oenb[79] ) + USE SIGNAL
+ + ROUTED met2 ( 2042170 1700 0 ) ( * 17170 )
+ NEW met1 ( 1887150 17170 ) ( 2042170 * )
+ NEW met2 ( 1805730 1679090 ) ( * 1688780 )
+ NEW met2 ( 1805500 1688780 ) ( 1805730 * )
+ NEW met2 ( 1805500 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1805730 1679090 ) ( 1887150 * )
+ NEW met2 ( 1887150 17170 ) ( * 1679090 )
+ NEW met1 ( 2042170 17170 ) M1M2_PR
+ NEW met1 ( 1887150 17170 ) M1M2_PR
+ NEW met1 ( 1805730 1679090 ) M1M2_PR
+ NEW met1 ( 1887150 1679090 ) M1M2_PR ;
+ - la_oenb[7] ( PIN la_oenb[7] ) ( mprj la_oenb[7] ) + USE SIGNAL
+ + ROUTED met2 ( 759230 48300 ) ( * 92650 )
+ NEW met2 ( 765210 1700 0 ) ( * 48110 )
+ NEW met1 ( 759230 92650 ) ( 1408750 * )
+ NEW met2 ( 758770 48110 ) ( * 48300 )
+ NEW met1 ( 758770 48110 ) ( 765210 * )
+ NEW met2 ( 758770 48300 ) ( 759230 * )
+ NEW met2 ( 1408750 92650 ) ( * 1580100 )
+ NEW met2 ( 1408750 1580100 ) ( 1410590 * )
+ NEW met2 ( 1410590 1688780 ) ( 1411210 * )
+ NEW met2 ( 1411210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1410590 1580100 ) ( * 1688780 )
+ NEW met1 ( 759230 92650 ) M1M2_PR
+ NEW met1 ( 765210 48110 ) M1M2_PR
+ NEW met1 ( 1408750 92650 ) M1M2_PR
+ NEW met1 ( 758770 48110 ) M1M2_PR ;
+ - la_oenb[80] ( PIN la_oenb[80] ) ( mprj la_oenb[80] ) + USE SIGNAL
+ + ROUTED met2 ( 2059650 1700 0 ) ( * 18870 )
+ NEW met1 ( 1908310 18870 ) ( 2059650 * )
+ NEW met2 ( 1811250 1679770 ) ( * 1688780 )
+ NEW met2 ( 1811020 1688780 ) ( 1811250 * )
+ NEW met2 ( 1811020 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1908310 18870 ) ( * 1679770 )
+ NEW met1 ( 1811250 1679770 ) ( 1908310 * )
+ NEW met1 ( 2059650 18870 ) M1M2_PR
+ NEW met1 ( 1908310 18870 ) M1M2_PR
+ NEW met1 ( 1811250 1679770 ) M1M2_PR
+ NEW met1 ( 1908310 1679770 ) M1M2_PR ;
+ - la_oenb[81] ( PIN la_oenb[81] ) ( mprj la_oenb[81] ) + USE SIGNAL
+ + ROUTED met2 ( 1938670 20570 ) ( * 26690 )
+ NEW met1 ( 1814930 26690 ) ( 1938670 * )
+ NEW met2 ( 2077590 1700 0 ) ( * 20570 )
+ NEW met1 ( 1938670 20570 ) ( 2077590 * )
+ NEW met2 ( 1814930 1688780 ) ( 1816470 * )
+ NEW met2 ( 1816470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1814930 26690 ) ( * 1688780 )
+ NEW met1 ( 1938670 26690 ) M1M2_PR
+ NEW met1 ( 1938670 20570 ) M1M2_PR
+ NEW met1 ( 1814930 26690 ) M1M2_PR
+ NEW met1 ( 2077590 20570 ) M1M2_PR ;
+ - la_oenb[82] ( PIN la_oenb[82] ) ( mprj la_oenb[82] ) + USE SIGNAL
+ + ROUTED met2 ( 1822290 1679430 ) ( * 1689460 )
+ NEW met2 ( 1822060 1689460 ) ( 1822290 * )
+ NEW met2 ( 1822060 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 2095070 1700 0 ) ( * 17850 )
+ NEW met1 ( 1907850 17850 ) ( 2095070 * )
+ NEW met2 ( 1907850 17850 ) ( * 1679430 )
+ NEW met1 ( 1822290 1679430 ) ( 1907850 * )
+ NEW met1 ( 1822290 1679430 ) M1M2_PR
+ NEW met1 ( 1907850 17850 ) M1M2_PR
+ NEW met1 ( 2095070 17850 ) M1M2_PR
+ NEW met1 ( 1907850 1679430 ) M1M2_PR ;
+ - la_oenb[83] ( PIN la_oenb[83] ) ( mprj la_oenb[83] ) + USE SIGNAL
+ + ROUTED met1 ( 1956150 18530 ) ( 1959830 * )
+ NEW met2 ( 1959830 18530 ) ( * 19550 )
+ NEW met2 ( 2113010 1700 0 ) ( * 19550 )
+ NEW met1 ( 1844370 1683510 ) ( * 1683850 )
+ NEW met1 ( 1843450 1683850 ) ( 1844370 * )
+ NEW met1 ( 1843450 1683510 ) ( * 1683850 )
+ NEW met1 ( 1827810 1683510 ) ( 1843450 * )
+ NEW met2 ( 1827810 1683510 ) ( * 1688780 )
+ NEW met2 ( 1827580 1688780 ) ( 1827810 * )
+ NEW met2 ( 1827580 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1938670 1683510 ) ( * 1683850 )
+ NEW met1 ( 1938670 1683850 ) ( 1944650 * )
+ NEW met1 ( 1944650 1683510 ) ( * 1683850 )
+ NEW met1 ( 1944650 1683510 ) ( 1956150 * )
+ NEW met2 ( 1956150 18530 ) ( * 1683510 )
+ NEW met1 ( 1959830 19550 ) ( 2113010 * )
+ NEW met1 ( 1844370 1683510 ) ( 1938670 * )
+ NEW met1 ( 1956150 18530 ) M1M2_PR
+ NEW met1 ( 1959830 18530 ) M1M2_PR
+ NEW met1 ( 1959830 19550 ) M1M2_PR
+ NEW met1 ( 2113010 19550 ) M1M2_PR
+ NEW met1 ( 1827810 1683510 ) M1M2_PR
+ NEW met1 ( 1956150 1683510 ) M1M2_PR ;
+ - la_oenb[84] ( PIN la_oenb[84] ) ( mprj la_oenb[84] ) + USE SIGNAL
+ + ROUTED met2 ( 1942350 17510 ) ( * 27030 )
+ NEW met1 ( 1942350 17510 ) ( 1960290 * )
+ NEW met2 ( 1960290 17510 ) ( * 18530 )
+ NEW met2 ( 2130950 1700 0 ) ( * 18530 )
+ NEW met1 ( 1828730 1688950 ) ( 1833030 * )
+ NEW met2 ( 1833030 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1828730 27030 ) ( * 1688950 )
+ NEW met1 ( 1828730 27030 ) ( 1942350 * )
+ NEW met1 ( 1960290 18530 ) ( 2130950 * )
+ NEW met1 ( 1828730 27030 ) M1M2_PR
+ NEW met1 ( 1942350 27030 ) M1M2_PR
+ NEW met1 ( 1942350 17510 ) M1M2_PR
+ NEW met1 ( 1960290 17510 ) M1M2_PR
+ NEW met1 ( 1960290 18530 ) M1M2_PR
+ NEW met1 ( 2130950 18530 ) M1M2_PR
+ NEW met1 ( 1828730 1688950 ) M1M2_PR
+ NEW met1 ( 1833030 1688950 ) M1M2_PR ;
+ - la_oenb[85] ( PIN la_oenb[85] ) ( mprj la_oenb[85] ) + USE SIGNAL
+ + ROUTED met2 ( 2148430 1700 0 ) ( * 15810 )
+ NEW met1 ( 2114850 15810 ) ( 2148430 * )
+ NEW met1 ( 1848050 1682830 ) ( * 1683170 )
+ NEW met1 ( 1838390 1682830 ) ( 1848050 * )
+ NEW met2 ( 1838390 1682830 ) ( * 1688780 )
+ NEW met2 ( 1838160 1688780 ) ( 1838390 * )
+ NEW met2 ( 1838160 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2114850 15810 ) ( * 1683170 )
+ NEW met1 ( 1848050 1683170 ) ( 2114850 * )
+ NEW met1 ( 2148430 15810 ) M1M2_PR
+ NEW met1 ( 2114850 15810 ) M1M2_PR
+ NEW met1 ( 1838390 1682830 ) M1M2_PR
+ NEW met1 ( 2114850 1683170 ) M1M2_PR ;
+ - la_oenb[86] ( PIN la_oenb[86] ) ( mprj la_oenb[86] ) + USE SIGNAL
+ + ROUTED met2 ( 2128650 15130 ) ( * 1682830 )
+ NEW met2 ( 2166370 1700 0 ) ( * 15130 )
+ NEW met1 ( 2128650 15130 ) ( 2166370 * )
+ NEW met1 ( 1848510 1682490 ) ( * 1682830 )
+ NEW met1 ( 1843910 1682490 ) ( 1848510 * )
+ NEW met2 ( 1843910 1682490 ) ( * 1688780 )
+ NEW met2 ( 1843680 1688780 ) ( 1843910 * )
+ NEW met2 ( 1843680 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1848510 1682830 ) ( 2128650 * )
+ NEW met1 ( 2128650 15130 ) M1M2_PR
+ NEW met1 ( 2128650 1682830 ) M1M2_PR
+ NEW met1 ( 2166370 15130 ) M1M2_PR
+ NEW met1 ( 1843910 1682490 ) M1M2_PR ;
+ - la_oenb[87] ( PIN la_oenb[87] ) ( mprj la_oenb[87] ) + USE SIGNAL
+ + ROUTED met2 ( 2129110 19550 ) ( * 1682490 )
+ NEW met2 ( 2183850 1700 0 ) ( * 19550 )
+ NEW met1 ( 2129110 19550 ) ( 2183850 * )
+ NEW met1 ( 1865530 1682150 ) ( * 1682490 )
+ NEW met1 ( 1848970 1682150 ) ( 1865530 * )
+ NEW met2 ( 1848970 1682150 ) ( * 1688780 )
+ NEW met2 ( 1848970 1688780 ) ( 1849130 * )
+ NEW met2 ( 1849130 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1865530 1682490 ) ( 2129110 * )
+ NEW met1 ( 2129110 19550 ) M1M2_PR
+ NEW met1 ( 2129110 1682490 ) M1M2_PR
+ NEW met1 ( 2183850 19550 ) M1M2_PR
+ NEW met1 ( 1848970 1682150 ) M1M2_PR ;
+ - la_oenb[88] ( PIN la_oenb[88] ) ( mprj la_oenb[88] ) + USE SIGNAL
+ + ROUTED met2 ( 2201790 1700 0 ) ( * 16490 )
+ NEW met1 ( 2163610 16490 ) ( 2201790 * )
+ NEW met2 ( 2163610 16490 ) ( * 1680790 )
+ NEW met2 ( 1854950 1680790 ) ( * 1688780 )
+ NEW met2 ( 1854720 1688780 ) ( 1854950 * )
+ NEW met2 ( 1854720 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1854950 1680790 ) ( 2163610 * )
+ NEW met1 ( 2201790 16490 ) M1M2_PR
+ NEW met1 ( 2163610 16490 ) M1M2_PR
+ NEW met1 ( 2163610 1680790 ) M1M2_PR
+ NEW met1 ( 1854950 1680790 ) M1M2_PR ;
+ - la_oenb[89] ( PIN la_oenb[89] ) ( mprj la_oenb[89] ) + USE SIGNAL
+ + ROUTED met2 ( 2216970 1700 ) ( 2219270 * 0 )
+ NEW met2 ( 1857710 80070 ) ( * 1580100 )
+ NEW met2 ( 1857710 1580100 ) ( 1858630 * )
+ NEW met2 ( 2216970 1700 ) ( * 80070 )
+ NEW met1 ( 1857710 80070 ) ( 2216970 * )
+ NEW met2 ( 1858630 1688780 ) ( 1860170 * )
+ NEW met2 ( 1860170 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1858630 1580100 ) ( * 1688780 )
+ NEW met1 ( 1857710 80070 ) M1M2_PR
+ NEW met1 ( 2216970 80070 ) M1M2_PR ;
+ - la_oenb[8] ( PIN la_oenb[8] ) ( mprj la_oenb[8] ) + USE SIGNAL
+ + ROUTED met2 ( 780850 1700 ) ( 783150 * 0 )
+ NEW met2 ( 780850 1700 ) ( * 64770 )
+ NEW met1 ( 780850 64770 ) ( 1416110 * )
+ NEW met2 ( 1416110 1688780 ) ( 1416270 * )
+ NEW met2 ( 1416270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1416110 64770 ) ( * 1688780 )
+ NEW met1 ( 780850 64770 ) M1M2_PR
+ NEW met1 ( 1416110 64770 ) M1M2_PR ;
+ - la_oenb[90] ( PIN la_oenb[90] ) ( mprj la_oenb[90] ) + USE SIGNAL
+ + ROUTED met2 ( 2237210 1700 0 ) ( * 20570 )
+ NEW met1 ( 2163150 20570 ) ( 2237210 * )
+ NEW met2 ( 2163150 20570 ) ( * 1682150 )
+ NEW met2 ( 1865990 1682150 ) ( * 1689460 )
+ NEW met2 ( 1865760 1689460 ) ( 1865990 * )
+ NEW met2 ( 1865760 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1865990 1682150 ) ( 2163150 * )
+ NEW met1 ( 2237210 20570 ) M1M2_PR
+ NEW met1 ( 2163150 20570 ) M1M2_PR
+ NEW met1 ( 2163150 1682150 ) M1M2_PR
+ NEW met1 ( 1865990 1682150 ) M1M2_PR ;
+ - la_oenb[91] ( PIN la_oenb[91] ) ( mprj la_oenb[91] ) + USE SIGNAL
+ + ROUTED met2 ( 2254690 1700 0 ) ( * 19210 )
+ NEW met1 ( 1870130 19210 ) ( 2254690 * )
+ NEW met2 ( 1870130 1689460 ) ( 1871210 * )
+ NEW met2 ( 1871210 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 1870130 19210 ) ( * 1689460 )
+ NEW met1 ( 2254690 19210 ) M1M2_PR
+ NEW met1 ( 1870130 19210 ) M1M2_PR ;
+ - la_oenb[92] ( PIN la_oenb[92] ) ( mprj la_oenb[92] ) + USE SIGNAL
+ + ROUTED met2 ( 2272630 1700 0 ) ( * 19550 )
+ NEW met1 ( 2184310 19550 ) ( 2272630 * )
+ NEW met2 ( 2183850 82800 ) ( 2184310 * )
+ NEW met2 ( 2184310 19550 ) ( * 82800 )
+ NEW met2 ( 2183850 82800 ) ( * 1681130 )
+ NEW met2 ( 1876570 1681130 ) ( * 1689460 )
+ NEW met2 ( 1876570 1689460 ) ( 1876730 * )
+ NEW met2 ( 1876730 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1876570 1681130 ) ( 2183850 * )
+ NEW met1 ( 2184310 19550 ) M1M2_PR
+ NEW met1 ( 2272630 19550 ) M1M2_PR
+ NEW met1 ( 2183850 1681130 ) M1M2_PR
+ NEW met1 ( 1876570 1681130 ) M1M2_PR ;
+ - la_oenb[93] ( PIN la_oenb[93] ) ( mprj la_oenb[93] ) + USE SIGNAL
+ + ROUTED met1 ( 2176950 16830 ) ( 2202250 * )
+ NEW met1 ( 2202250 16490 ) ( * 16830 )
+ NEW met2 ( 2290570 1700 0 ) ( * 16490 )
+ NEW met1 ( 2202250 16490 ) ( 2290570 * )
+ NEW met2 ( 2176950 16830 ) ( * 1681810 )
+ NEW met2 ( 1882550 1681810 ) ( * 1688780 )
+ NEW met2 ( 1882320 1688780 ) ( 1882550 * )
+ NEW met2 ( 1882320 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1882550 1681810 ) ( 2176950 * )
+ NEW met1 ( 2176950 16830 ) M1M2_PR
+ NEW met1 ( 2290570 16490 ) M1M2_PR
+ NEW met1 ( 2176950 1681810 ) M1M2_PR
+ NEW met1 ( 1882550 1681810 ) M1M2_PR ;
+ - la_oenb[94] ( PIN la_oenb[94] ) ( mprj la_oenb[94] ) + USE SIGNAL
+ + ROUTED met2 ( 2308050 1700 0 ) ( * 16150 )
+ NEW met2 ( 2211450 82800 ) ( 2213750 * )
+ NEW met2 ( 2213750 15810 ) ( * 82800 )
+ NEW met2 ( 2211450 82800 ) ( * 1680450 )
+ NEW met1 ( 2213750 15810 ) ( 2256300 * )
+ NEW met1 ( 2256300 15810 ) ( * 16150 )
+ NEW met1 ( 2256300 16150 ) ( 2308050 * )
+ NEW met2 ( 1888070 1680450 ) ( * 1688780 )
+ NEW met2 ( 1887840 1688780 ) ( 1888070 * )
+ NEW met2 ( 1887840 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1888070 1680450 ) ( 2211450 * )
+ NEW met1 ( 2213750 15810 ) M1M2_PR
+ NEW met1 ( 2308050 16150 ) M1M2_PR
+ NEW met1 ( 2211450 1680450 ) M1M2_PR
+ NEW met1 ( 1888070 1680450 ) M1M2_PR ;
+ - la_oenb[95] ( PIN la_oenb[95] ) ( mprj la_oenb[95] ) + USE SIGNAL
+ + ROUTED met2 ( 2325990 1700 0 ) ( * 79730 )
+ NEW met1 ( 1892210 79730 ) ( 2325990 * )
+ NEW met2 ( 1892210 1688780 ) ( 1893290 * )
+ NEW met2 ( 1893290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1892210 79730 ) ( * 1688780 )
+ NEW met1 ( 2325990 79730 ) M1M2_PR
+ NEW met1 ( 1892210 79730 ) M1M2_PR ;
+ - la_oenb[96] ( PIN la_oenb[96] ) ( mprj la_oenb[96] ) + USE SIGNAL
+ + ROUTED met2 ( 2343470 1700 0 ) ( * 16830 )
+ NEW met1 ( 2204550 16830 ) ( 2343470 * )
+ NEW met2 ( 1898650 1681470 ) ( * 1689460 )
+ NEW met2 ( 1898420 1689460 ) ( 1898650 * )
+ NEW met2 ( 1898420 1689460 ) ( * 1690140 0 )
+ NEW met1 ( 1898650 1681470 ) ( 2204550 * )
+ NEW met2 ( 2204550 16830 ) ( * 1681470 )
+ NEW met1 ( 2343470 16830 ) M1M2_PR
+ NEW met1 ( 2204550 16830 ) M1M2_PR
+ NEW met1 ( 1898650 1681470 ) M1M2_PR
+ NEW met1 ( 2204550 1681470 ) M1M2_PR ;
+ - la_oenb[97] ( PIN la_oenb[97] ) ( mprj la_oenb[97] ) + USE SIGNAL
+ + ROUTED met2 ( 2361410 1700 0 ) ( * 20230 )
+ NEW met1 ( 1897730 20230 ) ( 2361410 * )
+ NEW met1 ( 1897730 1688950 ) ( 1903870 * )
+ NEW met2 ( 1903870 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1897730 20230 ) ( * 1688950 )
+ NEW met1 ( 1897730 20230 ) M1M2_PR
+ NEW met1 ( 2361410 20230 ) M1M2_PR
+ NEW met1 ( 1897730 1688950 ) M1M2_PR
+ NEW met1 ( 1903870 1688950 ) M1M2_PR ;
+ - la_oenb[98] ( PIN la_oenb[98] ) ( mprj la_oenb[98] ) + USE SIGNAL
+ + ROUTED met2 ( 2239050 20570 ) ( * 1680110 )
+ NEW met2 ( 2378890 1700 0 ) ( * 20570 )
+ NEW met1 ( 2239050 20570 ) ( 2378890 * )
+ NEW met2 ( 1909690 1680110 ) ( * 1688780 )
+ NEW met2 ( 1909460 1688780 ) ( 1909690 * )
+ NEW met2 ( 1909460 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 1909690 1680110 ) ( 2239050 * )
+ NEW met1 ( 2239050 20570 ) M1M2_PR
+ NEW met1 ( 2239050 1680110 ) M1M2_PR
+ NEW met1 ( 2378890 20570 ) M1M2_PR
+ NEW met1 ( 1909690 1680110 ) M1M2_PR ;
+ - la_oenb[99] ( PIN la_oenb[99] ) ( mprj la_oenb[99] ) + USE SIGNAL
+ + ROUTED met2 ( 2396830 1700 0 ) ( * 19890 )
+ NEW met1 ( 1911530 19890 ) ( 2396830 * )
+ NEW met2 ( 1911530 1689460 ) ( 1911990 * )
+ NEW met2 ( 1911990 1689460 ) ( * 1689630 )
+ NEW met1 ( 1911990 1689630 ) ( 1914910 * )
+ NEW met2 ( 1914910 1689630 ) ( * 1690140 0 )
+ NEW met2 ( 1911530 19890 ) ( * 1689460 )
+ NEW met1 ( 1911530 19890 ) M1M2_PR
+ NEW met1 ( 2396830 19890 ) M1M2_PR
+ NEW met1 ( 1911990 1689630 ) M1M2_PR
+ NEW met1 ( 1914910 1689630 ) M1M2_PR ;
+ - la_oenb[9] ( PIN la_oenb[9] ) ( mprj la_oenb[9] ) + USE SIGNAL
+ + ROUTED met2 ( 800630 1700 0 ) ( * 64430 )
+ NEW met1 ( 800630 64430 ) ( 1422550 * )
+ NEW met2 ( 1421860 1688780 ) ( 1422550 * )
+ NEW met2 ( 1421860 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1422550 64430 ) ( * 1688780 )
+ NEW met1 ( 800630 64430 ) M1M2_PR
+ NEW met1 ( 1422550 64430 ) M1M2_PR ;
+ - user_clock2 ( PIN user_clock2 ) + USE SIGNAL ;
+ - user_irq[0] ( PIN user_irq[0] ) ( mprj irq[0] ) + USE SIGNAL
+ + ROUTED met2 ( 2905130 1700 0 ) ( * 19210 )
+ NEW met2 ( 2252850 82800 ) ( 2255150 * )
+ NEW met2 ( 2255150 19210 ) ( * 82800 )
+ NEW met2 ( 2252850 82800 ) ( * 1683510 )
+ NEW met1 ( 2255150 19210 ) ( 2905130 * )
+ NEW met2 ( 2070690 1683510 ) ( * 1688780 )
+ NEW met2 ( 2070460 1688780 ) ( 2070690 * )
+ NEW met2 ( 2070460 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 2070690 1683510 ) ( 2252850 * )
+ NEW met1 ( 2255150 19210 ) M1M2_PR
+ NEW met1 ( 2905130 19210 ) M1M2_PR
+ NEW met1 ( 2252850 1683510 ) M1M2_PR
+ NEW met1 ( 2070690 1683510 ) M1M2_PR ;
+ - user_irq[1] ( PIN user_irq[1] ) ( mprj irq[1] ) + USE SIGNAL
+ + ROUTED met2 ( 2911110 1700 0 ) ( * 16660 )
+ NEW met3 ( 2070230 16660 ) ( 2911110 * )
+ NEW met2 ( 2070230 16660 ) ( * 1580100 )
+ NEW met2 ( 2070230 1580100 ) ( 2071150 * )
+ NEW met2 ( 2071150 1688780 ) ( 2072230 * )
+ NEW met2 ( 2072230 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 2071150 1580100 ) ( * 1688780 )
+ NEW met2 ( 2911110 16660 ) M2M3_PR
+ NEW met2 ( 2070230 16660 ) M2M3_PR ;
+ - user_irq[2] ( PIN user_irq[2] ) ( mprj irq[2] ) + USE SIGNAL
+ + ROUTED met2 ( 2917090 1700 0 ) ( * 19550 )
+ NEW met1 ( 2273550 19550 ) ( 2917090 * )
+ NEW met2 ( 2074370 1679940 ) ( * 1688780 )
+ NEW met2 ( 2074140 1688780 ) ( 2074370 * )
+ NEW met2 ( 2074140 1688780 ) ( * 1690140 0 )
+ NEW met3 ( 2074370 1679940 ) ( 2273550 * )
+ NEW met2 ( 2273550 19550 ) ( * 1679940 )
+ NEW met1 ( 2917090 19550 ) M1M2_PR
+ NEW met1 ( 2273550 19550 ) M1M2_PR
+ NEW met2 ( 2074370 1679940 ) M2M3_PR
+ NEW met2 ( 2273550 1679940 ) M2M3_PR ;
+ - wb_clk_i ( PIN wb_clk_i ) ( mprj wb_clk_i ) + USE SIGNAL
+ + ROUTED met2 ( 2990 1700 0 ) ( * 30940 )
+ NEW met2 ( 1174150 1688780 ) ( 1175690 * )
+ NEW met2 ( 1175690 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1174150 30940 ) ( * 1688780 )
+ NEW met3 ( 2990 30940 ) ( 1174150 * )
+ NEW met2 ( 2990 30940 ) M2M3_PR
+ NEW met2 ( 1174150 30940 ) M2M3_PR ;
+ - wb_rst_i ( PIN wb_rst_i ) ( mprj wb_rst_i ) + USE SIGNAL
+ + ROUTED met2 ( 8510 1700 0 ) ( * 30770 )
+ NEW met1 ( 1173690 1688950 ) ( 1177070 * )
+ NEW met2 ( 1177070 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1173690 30770 ) ( * 1688950 )
+ NEW met1 ( 8510 30770 ) ( 1173690 * )
+ NEW met1 ( 8510 30770 ) M1M2_PR
+ NEW met1 ( 1173690 30770 ) M1M2_PR
+ NEW met1 ( 1173690 1688950 ) M1M2_PR
+ NEW met1 ( 1177070 1688950 ) M1M2_PR ;
+ - wbs_ack_o ( PIN wbs_ack_o ) ( mprj wbs_ack_o ) + USE SIGNAL
+ + ROUTED met2 ( 14490 1700 0 ) ( * 31110 )
+ NEW met1 ( 1173230 1689290 ) ( 1178910 * )
+ NEW met2 ( 1178910 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1173230 31110 ) ( * 1689290 )
+ NEW met1 ( 14490 31110 ) ( 1173230 * )
+ NEW met1 ( 14490 31110 ) M1M2_PR
+ NEW met1 ( 1173230 31110 ) M1M2_PR
+ NEW met1 ( 1173230 1689290 ) M1M2_PR
+ NEW met1 ( 1178910 1689290 ) M1M2_PR ;
+ - wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ( mprj wbs_adr_i[0] ) + USE SIGNAL
+ + ROUTED met1 ( 1180590 1652570 ) ( 1186110 * )
+ NEW met2 ( 1180590 31450 ) ( * 1652570 )
+ NEW met2 ( 1186110 1688780 ) ( 1186270 * )
+ NEW met2 ( 1186270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1186110 1652570 ) ( * 1688780 )
+ NEW met2 ( 38410 1700 0 ) ( * 31450 )
+ NEW met1 ( 38410 31450 ) ( 1180590 * )
+ NEW met1 ( 1180590 31450 ) M1M2_PR
+ NEW met1 ( 1180590 1652570 ) M1M2_PR
+ NEW met1 ( 1186110 1652570 ) M1M2_PR
+ NEW met1 ( 38410 31450 ) M1M2_PR ;
+ - wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ( mprj wbs_adr_i[10] ) + USE SIGNAL
+ + ROUTED met1 ( 1242690 1652570 ) ( 1248210 * )
+ NEW met2 ( 1242690 32130 ) ( * 1652570 )
+ NEW met2 ( 1248210 1688780 ) ( 1248370 * )
+ NEW met2 ( 1248370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1248210 1652570 ) ( * 1688780 )
+ NEW met2 ( 239430 1700 0 ) ( * 32130 )
+ NEW met1 ( 239430 32130 ) ( 1242690 * )
+ NEW met1 ( 1242690 32130 ) M1M2_PR
+ NEW met1 ( 1242690 1652570 ) M1M2_PR
+ NEW met1 ( 1248210 1652570 ) M1M2_PR
+ NEW met1 ( 239430 32130 ) M1M2_PR ;
+ - wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ( mprj wbs_adr_i[11] ) + USE SIGNAL
+ + ROUTED met1 ( 1249130 1688950 ) ( 1253890 * )
+ NEW met2 ( 1253890 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1249130 32470 ) ( * 1688950 )
+ NEW met2 ( 256910 1700 0 ) ( * 32470 )
+ NEW met1 ( 256910 32470 ) ( 1249130 * )
+ NEW met1 ( 1249130 32470 ) M1M2_PR
+ NEW met1 ( 1249130 1688950 ) M1M2_PR
+ NEW met1 ( 1253890 1688950 ) M1M2_PR
+ NEW met1 ( 256910 32470 ) M1M2_PR ;
+ - wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ( mprj wbs_adr_i[12] ) + USE SIGNAL
+ + ROUTED met2 ( 1256030 1689290 ) ( 1256490 * )
+ NEW met1 ( 1256490 1689290 ) ( 1259410 * )
+ NEW met2 ( 1259410 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1256030 32810 ) ( * 1689290 )
+ NEW met2 ( 274850 1700 0 ) ( * 32810 )
+ NEW met1 ( 274850 32810 ) ( 1256030 * )
+ NEW met1 ( 1256030 32810 ) M1M2_PR
+ NEW met1 ( 1256490 1689290 ) M1M2_PR
+ NEW met1 ( 1259410 1689290 ) M1M2_PR
+ NEW met1 ( 274850 32810 ) M1M2_PR ;
+ - wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ( mprj wbs_adr_i[13] ) + USE SIGNAL
+ + ROUTED met2 ( 292330 1700 0 ) ( * 33150 )
+ NEW met1 ( 1262930 1688270 ) ( 1264930 * )
+ NEW met1 ( 1264930 1688270 ) ( * 1689290 )
+ NEW met2 ( 1264930 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1262930 33150 ) ( * 1688270 )
+ NEW met1 ( 292330 33150 ) ( 1262930 * )
+ NEW met1 ( 292330 33150 ) M1M2_PR
+ NEW met1 ( 1262930 33150 ) M1M2_PR
+ NEW met1 ( 1262930 1688270 ) M1M2_PR
+ NEW met1 ( 1264930 1689290 ) M1M2_PR ;
+ - wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ( mprj wbs_adr_i[14] ) + USE SIGNAL
+ + ROUTED met2 ( 310270 1700 0 ) ( * 33490 )
+ NEW met2 ( 1269830 1688780 ) ( 1270450 * )
+ NEW met2 ( 1270450 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1269830 33490 ) ( * 1688780 )
+ NEW met1 ( 310270 33490 ) ( 1269830 * )
+ NEW met1 ( 310270 33490 ) M1M2_PR
+ NEW met1 ( 1269830 33490 ) M1M2_PR ;
+ - wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ( mprj wbs_adr_i[15] ) + USE SIGNAL
+ + ROUTED met1 ( 1270290 1652570 ) ( 1275810 * )
+ NEW met2 ( 1270290 33830 ) ( * 1652570 )
+ NEW met2 ( 1275810 1688780 ) ( 1275970 * )
+ NEW met2 ( 1275970 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1275810 1652570 ) ( * 1688780 )
+ NEW met2 ( 327750 1700 0 ) ( * 33830 )
+ NEW met1 ( 327750 33830 ) ( 1270290 * )
+ NEW met1 ( 1270290 33830 ) M1M2_PR
+ NEW met1 ( 1270290 1652570 ) M1M2_PR
+ NEW met1 ( 1275810 1652570 ) M1M2_PR
+ NEW met1 ( 327750 33830 ) M1M2_PR ;
+ - wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ( mprj wbs_adr_i[16] ) + USE SIGNAL
+ + ROUTED met1 ( 1276730 1688950 ) ( 1281490 * )
+ NEW met2 ( 1281490 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1276730 34170 ) ( * 1688950 )
+ NEW met2 ( 345690 1700 0 ) ( * 34170 )
+ NEW met1 ( 345690 34170 ) ( 1276730 * )
+ NEW met1 ( 1276730 34170 ) M1M2_PR
+ NEW met1 ( 1276730 1688950 ) M1M2_PR
+ NEW met1 ( 1281490 1688950 ) M1M2_PR
+ NEW met1 ( 345690 34170 ) M1M2_PR ;
+ - wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ( mprj wbs_adr_i[17] ) + USE SIGNAL
+ + ROUTED met1 ( 1283630 1688950 ) ( 1287010 * )
+ NEW met2 ( 1287010 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1283630 46410 ) ( * 1688950 )
+ NEW met2 ( 363170 1700 0 ) ( * 46410 )
+ NEW met1 ( 363170 46410 ) ( 1283630 * )
+ NEW met1 ( 1283630 46410 ) M1M2_PR
+ NEW met1 ( 1283630 1688950 ) M1M2_PR
+ NEW met1 ( 1287010 1688950 ) M1M2_PR
+ NEW met1 ( 363170 46410 ) M1M2_PR ;
+ - wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ( mprj wbs_adr_i[18] ) + USE SIGNAL
+ + ROUTED met2 ( 381110 1700 0 ) ( * 46750 )
+ NEW met1 ( 381110 46750 ) ( 1291910 * )
+ NEW met2 ( 1291910 1688780 ) ( 1292530 * )
+ NEW met2 ( 1292530 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1291910 46750 ) ( * 1688780 )
+ NEW met1 ( 381110 46750 ) M1M2_PR
+ NEW met1 ( 1291910 46750 ) M1M2_PR ;
+ - wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ( mprj wbs_adr_i[19] ) + USE SIGNAL
+ + ROUTED met2 ( 396290 1700 ) ( 398590 * 0 )
+ NEW met2 ( 396290 1700 ) ( * 51340 )
+ NEW met3 ( 396290 51340 ) ( 1297890 * )
+ NEW met2 ( 1297660 1688780 ) ( 1297890 * )
+ NEW met2 ( 1297660 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1297890 51340 ) ( * 1688780 )
+ NEW met2 ( 396290 51340 ) M2M3_PR
+ NEW met2 ( 1297890 51340 ) M2M3_PR ;
+ - wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ( mprj wbs_adr_i[1] ) + USE SIGNAL
+ + ROUTED met1 ( 1188410 1652570 ) ( 1193470 * )
+ NEW met2 ( 1188410 31790 ) ( * 1652570 )
+ NEW met2 ( 1193470 1689290 ) ( 1193630 * )
+ NEW met2 ( 1193630 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1193470 1652570 ) ( * 1689290 )
+ NEW met2 ( 61870 1700 0 ) ( * 31790 )
+ NEW met1 ( 61870 31790 ) ( 1188410 * )
+ NEW met1 ( 1188410 31790 ) M1M2_PR
+ NEW met1 ( 1188410 1652570 ) M1M2_PR
+ NEW met1 ( 1193470 1652570 ) M1M2_PR
+ NEW met1 ( 61870 31790 ) M1M2_PR ;
+ - wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ( mprj wbs_adr_i[20] ) + USE SIGNAL
+ + ROUTED met2 ( 416530 1700 0 ) ( * 51510 )
+ NEW met1 ( 416530 51510 ) ( 1298810 * )
+ NEW met2 ( 1298810 51510 ) ( * 1676700 )
+ NEW met2 ( 1298810 1676700 ) ( 1300190 * )
+ NEW met2 ( 1300190 1676700 ) ( * 1688780 )
+ NEW met2 ( 1300190 1688780 ) ( 1303110 * )
+ NEW met2 ( 1303110 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 416530 51510 ) M1M2_PR
+ NEW met1 ( 1298810 51510 ) M1M2_PR ;
+ - wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ( mprj wbs_adr_i[21] ) + USE SIGNAL
+ + ROUTED met2 ( 432170 1700 ) ( 434470 * 0 )
+ NEW met2 ( 432170 1700 ) ( * 51850 )
+ NEW met1 ( 432170 51850 ) ( 1305710 * )
+ NEW met2 ( 1305710 51850 ) ( * 1580100 )
+ NEW met2 ( 1305710 1580100 ) ( 1307090 * )
+ NEW met2 ( 1307090 1688780 ) ( 1308630 * )
+ NEW met2 ( 1308630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1307090 1580100 ) ( * 1688780 )
+ NEW met1 ( 432170 51850 ) M1M2_PR
+ NEW met1 ( 1305710 51850 ) M1M2_PR ;
+ - wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ( mprj wbs_adr_i[22] ) + USE SIGNAL
+ + ROUTED met2 ( 449650 1700 ) ( 451950 * 0 )
+ NEW met2 ( 449650 1700 ) ( * 52190 )
+ NEW met1 ( 449650 52190 ) ( 1312150 * )
+ NEW met1 ( 1312150 1688270 ) ( * 1689290 )
+ NEW met1 ( 1312150 1689290 ) ( 1314150 * )
+ NEW met2 ( 1314150 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1312150 52190 ) ( * 1688270 )
+ NEW met1 ( 449650 52190 ) M1M2_PR
+ NEW met1 ( 1312150 52190 ) M1M2_PR
+ NEW met1 ( 1312150 1688270 ) M1M2_PR
+ NEW met1 ( 1314150 1689290 ) M1M2_PR ;
+ - wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ( mprj wbs_adr_i[23] ) + USE SIGNAL
+ + ROUTED met2 ( 469890 1700 0 ) ( * 66470 )
+ NEW met1 ( 469890 66470 ) ( 1318590 * )
+ NEW met2 ( 1318590 1688780 ) ( 1319670 * )
+ NEW met2 ( 1319670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1318590 66470 ) ( * 1688780 )
+ NEW met1 ( 469890 66470 ) M1M2_PR
+ NEW met1 ( 1318590 66470 ) M1M2_PR ;
+ - wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ( mprj wbs_adr_i[24] ) + USE SIGNAL
+ + ROUTED met2 ( 487370 1700 0 ) ( * 66810 )
+ NEW met1 ( 487370 66810 ) ( 1325490 * )
+ NEW met2 ( 1325260 1688780 ) ( 1325490 * )
+ NEW met2 ( 1325260 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1325490 66810 ) ( * 1688780 )
+ NEW met1 ( 487370 66810 ) M1M2_PR
+ NEW met1 ( 1325490 66810 ) M1M2_PR ;
+ - wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ( mprj wbs_adr_i[25] ) + USE SIGNAL
+ + ROUTED met2 ( 503930 1700 ) ( 505310 * 0 )
+ NEW met2 ( 503930 1700 ) ( * 67150 )
+ NEW met1 ( 1326410 1636250 ) ( 1330550 * )
+ NEW met1 ( 503930 67150 ) ( 1326410 * )
+ NEW met2 ( 1326410 67150 ) ( * 1636250 )
+ NEW met2 ( 1330550 1688780 ) ( 1330710 * )
+ NEW met2 ( 1330710 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1330550 1636250 ) ( * 1688780 )
+ NEW met1 ( 503930 67150 ) M1M2_PR
+ NEW met1 ( 1326410 1636250 ) M1M2_PR
+ NEW met1 ( 1330550 1636250 ) M1M2_PR
+ NEW met1 ( 1326410 67150 ) M1M2_PR ;
+ - wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ( mprj wbs_adr_i[26] ) + USE SIGNAL
+ + ROUTED met2 ( 520490 1700 ) ( 522790 * 0 )
+ NEW met2 ( 520490 1700 ) ( * 67490 )
+ NEW met1 ( 520490 67490 ) ( 1332390 * )
+ NEW met2 ( 1332390 67490 ) ( * 1676700 )
+ NEW met2 ( 1331930 1676700 ) ( 1332390 * )
+ NEW met2 ( 1331930 1676700 ) ( * 1689290 )
+ NEW met1 ( 1331930 1689290 ) ( 1336230 * )
+ NEW met2 ( 1336230 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 520490 67490 ) M1M2_PR
+ NEW met1 ( 1332390 67490 ) M1M2_PR
+ NEW met1 ( 1331930 1689290 ) M1M2_PR
+ NEW met1 ( 1336230 1689290 ) M1M2_PR ;
+ - wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ( mprj wbs_adr_i[27] ) + USE SIGNAL
+ + ROUTED met2 ( 1339750 1688780 ) ( 1341750 * )
+ NEW met2 ( 1341750 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1339750 67830 ) ( * 1688780 )
+ NEW met2 ( 540730 1700 0 ) ( * 67830 )
+ NEW met1 ( 540730 67830 ) ( 1339750 * )
+ NEW met1 ( 1339750 67830 ) M1M2_PR
+ NEW met1 ( 540730 67830 ) M1M2_PR ;
+ - wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ( mprj wbs_adr_i[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1346190 1688780 ) ( 1347270 * )
+ NEW met2 ( 1347270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1346190 68170 ) ( * 1688780 )
+ NEW met2 ( 558210 1700 0 ) ( * 16490 )
+ NEW met1 ( 552230 16490 ) ( 558210 * )
+ NEW met2 ( 552230 16490 ) ( * 68170 )
+ NEW met1 ( 552230 68170 ) ( 1346190 * )
+ NEW met1 ( 1346190 68170 ) M1M2_PR
+ NEW met1 ( 558210 16490 ) M1M2_PR
+ NEW met1 ( 552230 16490 ) M1M2_PR
+ NEW met1 ( 552230 68170 ) M1M2_PR ;
+ - wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ( mprj wbs_adr_i[29] ) + USE SIGNAL
+ + ROUTED met2 ( 573850 1700 ) ( 576150 * 0 )
+ NEW met2 ( 573850 1700 ) ( * 68510 )
+ NEW met2 ( 1352860 1688780 ) ( 1353090 * )
+ NEW met2 ( 1352860 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1353090 68510 ) ( * 1688780 )
+ NEW met1 ( 573850 68510 ) ( 1353090 * )
+ NEW met1 ( 573850 68510 ) M1M2_PR
+ NEW met1 ( 1353090 68510 ) M1M2_PR ;
+ - wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ( mprj wbs_adr_i[2] ) + USE SIGNAL
+ + ROUTED met2 ( 85330 1700 0 ) ( * 44540 )
+ NEW met3 ( 85330 44540 ) ( 1201290 * )
+ NEW met2 ( 1201060 1688780 ) ( 1201290 * )
+ NEW met2 ( 1201060 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1201290 44540 ) ( * 1688780 )
+ NEW met2 ( 85330 44540 ) M2M3_PR
+ NEW met2 ( 1201290 44540 ) M2M3_PR ;
+ - wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ( mprj wbs_adr_i[30] ) + USE SIGNAL
+ + ROUTED met2 ( 594090 1700 0 ) ( * 68850 )
+ NEW met2 ( 1354010 68850 ) ( * 1580100 )
+ NEW met2 ( 1354010 1580100 ) ( 1357230 * )
+ NEW met2 ( 1357230 1688780 ) ( 1357850 * )
+ NEW met2 ( 1357850 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1357230 1580100 ) ( * 1688780 )
+ NEW met1 ( 594090 68850 ) ( 1354010 * )
+ NEW met1 ( 594090 68850 ) M1M2_PR
+ NEW met1 ( 1354010 68850 ) M1M2_PR ;
+ - wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ( mprj wbs_adr_i[31] ) + USE SIGNAL
+ + ROUTED met2 ( 611570 1700 0 ) ( * 65110 )
+ NEW met2 ( 1360910 65110 ) ( * 1580100 )
+ NEW met2 ( 1360910 1580100 ) ( 1362750 * )
+ NEW met2 ( 1362750 1688780 ) ( 1363370 * )
+ NEW met2 ( 1363370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1362750 1580100 ) ( * 1688780 )
+ NEW met1 ( 611570 65110 ) ( 1360910 * )
+ NEW met1 ( 611570 65110 ) M1M2_PR
+ NEW met1 ( 1360910 65110 ) M1M2_PR ;
+ - wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ( mprj wbs_adr_i[3] ) + USE SIGNAL
+ + ROUTED met2 ( 109250 1700 0 ) ( * 45050 )
+ NEW met1 ( 109250 45050 ) ( 1208650 * )
+ NEW met2 ( 1208420 1688780 ) ( 1208650 * )
+ NEW met2 ( 1208420 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1208650 45050 ) ( * 1688780 )
+ NEW met1 ( 109250 45050 ) M1M2_PR
+ NEW met1 ( 1208650 45050 ) M1M2_PR ;
+ - wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ( mprj wbs_adr_i[4] ) + USE SIGNAL
+ + ROUTED met2 ( 132710 1700 0 ) ( * 45390 )
+ NEW met1 ( 132710 45390 ) ( 1215550 * )
+ NEW met2 ( 1215550 1688780 ) ( 1215710 * )
+ NEW met2 ( 1215710 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1215550 45390 ) ( * 1688780 )
+ NEW met1 ( 132710 45390 ) M1M2_PR
+ NEW met1 ( 1215550 45390 ) M1M2_PR ;
+ - wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ( mprj wbs_adr_i[5] ) + USE SIGNAL
+ + ROUTED met2 ( 150650 1700 0 ) ( * 45730 )
+ NEW met1 ( 150650 45730 ) ( 1215090 * )
+ NEW met1 ( 1215090 1689630 ) ( 1221230 * )
+ NEW met2 ( 1221230 1689630 ) ( * 1690140 0 )
+ NEW met2 ( 1215090 45730 ) ( * 1689630 )
+ NEW met1 ( 150650 45730 ) M1M2_PR
+ NEW met1 ( 1215090 45730 ) M1M2_PR
+ NEW met1 ( 1215090 1689630 ) M1M2_PR
+ NEW met1 ( 1221230 1689630 ) M1M2_PR ;
+ - wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ( mprj wbs_adr_i[6] ) + USE SIGNAL
+ + ROUTED met2 ( 168130 1700 0 ) ( * 46070 )
+ NEW met1 ( 168130 46070 ) ( 1221990 * )
+ NEW met1 ( 1221990 1689290 ) ( 1226750 * )
+ NEW met2 ( 1226750 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1221990 46070 ) ( * 1689290 )
+ NEW met1 ( 168130 46070 ) M1M2_PR
+ NEW met1 ( 1221990 46070 ) M1M2_PR
+ NEW met1 ( 1221990 1689290 ) M1M2_PR
+ NEW met1 ( 1226750 1689290 ) M1M2_PR ;
+ - wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ( mprj wbs_adr_i[7] ) + USE SIGNAL
+ + ROUTED met2 ( 183770 1700 ) ( 186070 * 0 )
+ NEW met2 ( 183770 1700 ) ( * 59330 )
+ NEW met1 ( 183770 59330 ) ( 1229810 * )
+ NEW met2 ( 1229810 59330 ) ( * 1580100 )
+ NEW met2 ( 1229810 1580100 ) ( 1231190 * )
+ NEW met2 ( 1231190 1688780 ) ( 1232270 * )
+ NEW met2 ( 1232270 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1231190 1580100 ) ( * 1688780 )
+ NEW met1 ( 183770 59330 ) M1M2_PR
+ NEW met1 ( 1229810 59330 ) M1M2_PR ;
+ - wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ( mprj wbs_adr_i[8] ) + USE SIGNAL
+ + ROUTED met2 ( 201250 1700 ) ( 203550 * 0 )
+ NEW met2 ( 201250 1700 ) ( * 64940 )
+ NEW met3 ( 201250 64940 ) ( 1235790 * )
+ NEW met2 ( 1235790 1688780 ) ( 1237330 * )
+ NEW met2 ( 1237330 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1235790 64940 ) ( * 1688780 )
+ NEW met2 ( 201250 64940 ) M2M3_PR
+ NEW met2 ( 1235790 64940 ) M2M3_PR ;
+ - wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ( mprj wbs_adr_i[9] ) + USE SIGNAL
+ + ROUTED met2 ( 221490 1700 0 ) ( * 65450 )
+ NEW met2 ( 1242920 1688780 ) ( 1243150 * )
+ NEW met2 ( 1242920 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1243150 65450 ) ( * 1688780 )
+ NEW met1 ( 221490 65450 ) ( 1243150 * )
+ NEW met1 ( 221490 65450 ) M1M2_PR
+ NEW met1 ( 1243150 65450 ) M1M2_PR ;
+ - wbs_cyc_i ( PIN wbs_cyc_i ) ( mprj wbs_cyc_i ) + USE SIGNAL
+ + ROUTED met2 ( 20470 1700 0 ) ( * 44710 )
+ NEW met2 ( 1180820 1688780 ) ( 1181050 * )
+ NEW met2 ( 1180820 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1181050 44710 ) ( * 1688780 )
+ NEW met1 ( 20470 44710 ) ( 1181050 * )
+ NEW met1 ( 20470 44710 ) M1M2_PR
+ NEW met1 ( 1181050 44710 ) M1M2_PR ;
+ - wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ( mprj wbs_dat_i[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1187490 1688780 ) ( 1188110 * )
+ NEW met2 ( 1188110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1187490 58140 ) ( * 1688780 )
+ NEW met2 ( 43930 1700 0 ) ( * 58140 )
+ NEW met3 ( 43930 58140 ) ( 1187490 * )
+ NEW met2 ( 1187490 58140 ) M2M3_PR
+ NEW met2 ( 43930 58140 ) M2M3_PR ;
+ - wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ( mprj wbs_dat_i[10] ) + USE SIGNAL
+ + ROUTED met2 ( 1250050 1688780 ) ( 1250210 * )
+ NEW met2 ( 1250210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1250050 65790 ) ( * 1688780 )
+ NEW met2 ( 242650 1700 ) ( 244950 * 0 )
+ NEW met2 ( 242650 1700 ) ( * 65790 )
+ NEW met1 ( 242650 65790 ) ( 1250050 * )
+ NEW met1 ( 1250050 65790 ) M1M2_PR
+ NEW met1 ( 242650 65790 ) M1M2_PR ;
+ - wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ( mprj wbs_dat_i[11] ) + USE SIGNAL
+ + ROUTED met1 ( 1249590 1652570 ) ( 1255570 * )
+ NEW met2 ( 1249590 66130 ) ( * 1652570 )
+ NEW met2 ( 1255570 1688780 ) ( 1255730 * )
+ NEW met2 ( 1255730 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1255570 1652570 ) ( * 1688780 )
+ NEW met2 ( 262890 1700 0 ) ( * 66130 )
+ NEW met1 ( 262890 66130 ) ( 1249590 * )
+ NEW met1 ( 1249590 1652570 ) M1M2_PR
+ NEW met1 ( 1255570 1652570 ) M1M2_PR
+ NEW met1 ( 1249590 66130 ) M1M2_PR
+ NEW met1 ( 262890 66130 ) M1M2_PR ;
+ - wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ( mprj wbs_dat_i[12] ) + USE SIGNAL
+ + ROUTED met2 ( 276230 82800 ) ( * 94690 )
+ NEW met2 ( 276230 82800 ) ( 280370 * )
+ NEW met2 ( 280370 1700 0 ) ( * 82800 )
+ NEW met2 ( 1256950 94690 ) ( * 1580100 )
+ NEW met2 ( 1256950 1580100 ) ( 1258330 * )
+ NEW met2 ( 1258330 1688780 ) ( 1261250 * )
+ NEW met2 ( 1261250 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1258330 1580100 ) ( * 1688780 )
+ NEW met1 ( 276230 94690 ) ( 1256950 * )
+ NEW met1 ( 276230 94690 ) M1M2_PR
+ NEW met1 ( 1256950 94690 ) M1M2_PR ;
+ - wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ( mprj wbs_dat_i[13] ) + USE SIGNAL
+ + ROUTED met2 ( 296930 1700 ) ( 298310 * 0 )
+ NEW met2 ( 296930 1700 ) ( * 95370 )
+ NEW met2 ( 1263850 1688780 ) ( 1266770 * )
+ NEW met2 ( 1266770 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1263850 95370 ) ( * 1688780 )
+ NEW met1 ( 296930 95370 ) ( 1263850 * )
+ NEW met1 ( 296930 95370 ) M1M2_PR
+ NEW met1 ( 1263850 95370 ) M1M2_PR ;
+ - wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ( mprj wbs_dat_i[14] ) + USE SIGNAL
+ + ROUTED met2 ( 310730 82800 ) ( * 95710 )
+ NEW met2 ( 310730 82800 ) ( 316250 * )
+ NEW met2 ( 316250 1700 0 ) ( * 82800 )
+ NEW met2 ( 1270750 1688780 ) ( 1272290 * )
+ NEW met2 ( 1272290 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1270750 95710 ) ( * 1688780 )
+ NEW met1 ( 310730 95710 ) ( 1270750 * )
+ NEW met1 ( 310730 95710 ) M1M2_PR
+ NEW met1 ( 1270750 95710 ) M1M2_PR ;
+ - wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ( mprj wbs_dat_i[15] ) + USE SIGNAL
+ + ROUTED met2 ( 1277650 1688780 ) ( 1277810 * )
+ NEW met2 ( 1277810 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1277650 72250 ) ( * 1688780 )
+ NEW met2 ( 333730 1700 0 ) ( * 72250 )
+ NEW met1 ( 333730 72250 ) ( 1277650 * )
+ NEW met1 ( 1277650 72250 ) M1M2_PR
+ NEW met1 ( 333730 72250 ) M1M2_PR ;
+ - wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ( mprj wbs_dat_i[16] ) + USE SIGNAL
+ + ROUTED met1 ( 1277190 1689630 ) ( 1283330 * )
+ NEW met2 ( 1283330 1689630 ) ( * 1690140 0 )
+ NEW met2 ( 1277190 72590 ) ( * 1689630 )
+ NEW met2 ( 349370 1700 ) ( 351670 * 0 )
+ NEW met2 ( 349370 1700 ) ( * 72590 )
+ NEW met1 ( 349370 72590 ) ( 1277190 * )
+ NEW met1 ( 1277190 72590 ) M1M2_PR
+ NEW met1 ( 1277190 1689630 ) M1M2_PR
+ NEW met1 ( 1283330 1689630 ) M1M2_PR
+ NEW met1 ( 349370 72590 ) M1M2_PR ;
+ - wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ( mprj wbs_dat_i[17] ) + USE SIGNAL
+ + ROUTED met1 ( 1284090 1689290 ) ( 1288850 * )
+ NEW met2 ( 1288850 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1284090 72930 ) ( * 1689290 )
+ NEW met2 ( 366850 1700 ) ( 369150 * 0 )
+ NEW met2 ( 366850 1700 ) ( * 72930 )
+ NEW met1 ( 366850 72930 ) ( 1284090 * )
+ NEW met1 ( 1284090 72930 ) M1M2_PR
+ NEW met1 ( 1284090 1689290 ) M1M2_PR
+ NEW met1 ( 1288850 1689290 ) M1M2_PR
+ NEW met1 ( 366850 72930 ) M1M2_PR ;
+ - wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ( mprj wbs_dat_i[18] ) + USE SIGNAL
+ + ROUTED met2 ( 387090 1700 0 ) ( * 73270 )
+ NEW met1 ( 387090 73270 ) ( 1290990 * )
+ NEW met1 ( 1290990 1684190 ) ( 1294210 * )
+ NEW met2 ( 1294210 1684190 ) ( * 1688780 )
+ NEW met2 ( 1294210 1688780 ) ( 1294370 * )
+ NEW met2 ( 1294370 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1290990 73270 ) ( * 1684190 )
+ NEW met1 ( 387090 73270 ) M1M2_PR
+ NEW met1 ( 1290990 73270 ) M1M2_PR
+ NEW met1 ( 1290990 1684190 ) M1M2_PR
+ NEW met1 ( 1294210 1684190 ) M1M2_PR ;
+ - wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ( mprj wbs_dat_i[19] ) + USE SIGNAL
+ + ROUTED met2 ( 404570 1700 0 ) ( * 73610 )
+ NEW met1 ( 404570 73610 ) ( 1298350 * )
+ NEW met2 ( 1298350 1688780 ) ( 1299430 * )
+ NEW met2 ( 1299430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1298350 73610 ) ( * 1688780 )
+ NEW met1 ( 404570 73610 ) M1M2_PR
+ NEW met1 ( 1298350 73610 ) M1M2_PR ;
+ - wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ( mprj wbs_dat_i[1] ) + USE SIGNAL
+ + ROUTED met2 ( 67850 1700 0 ) ( * 58650 )
+ NEW met1 ( 67850 58650 ) ( 1194850 * )
+ NEW met2 ( 1194850 1688780 ) ( 1195470 * )
+ NEW met2 ( 1195470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1194850 58650 ) ( * 1688780 )
+ NEW met1 ( 67850 58650 ) M1M2_PR
+ NEW met1 ( 1194850 58650 ) M1M2_PR ;
+ - wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ( mprj wbs_dat_i[20] ) + USE SIGNAL
+ + ROUTED met2 ( 421130 1700 ) ( 422510 * 0 )
+ NEW met2 ( 421130 1700 ) ( * 73950 )
+ NEW met1 ( 421130 73950 ) ( 1305250 * )
+ NEW met2 ( 1305020 1688780 ) ( 1305250 * )
+ NEW met2 ( 1305020 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1305250 73950 ) ( * 1688780 )
+ NEW met1 ( 421130 73950 ) M1M2_PR
+ NEW met1 ( 1305250 73950 ) M1M2_PR ;
+ - wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ( mprj wbs_dat_i[21] ) + USE SIGNAL
+ + ROUTED met2 ( 437690 1700 ) ( 439990 * 0 )
+ NEW met1 ( 1304790 1652570 ) ( 1310310 * )
+ NEW met2 ( 437690 1700 ) ( * 74290 )
+ NEW met1 ( 437690 74290 ) ( 1304790 * )
+ NEW met2 ( 1304790 74290 ) ( * 1652570 )
+ NEW met2 ( 1310310 1688780 ) ( 1310470 * )
+ NEW met2 ( 1310470 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1310310 1652570 ) ( * 1688780 )
+ NEW met1 ( 1304790 1652570 ) M1M2_PR
+ NEW met1 ( 1310310 1652570 ) M1M2_PR
+ NEW met1 ( 437690 74290 ) M1M2_PR
+ NEW met1 ( 1304790 74290 ) M1M2_PR ;
+ - wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ( mprj wbs_dat_i[22] ) + USE SIGNAL
+ + ROUTED met2 ( 457930 1700 0 ) ( * 74630 )
+ NEW met1 ( 457930 74630 ) ( 1312610 * )
+ NEW met2 ( 1312610 1688780 ) ( 1315990 * )
+ NEW met2 ( 1315990 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1312610 74630 ) ( * 1688780 )
+ NEW met1 ( 457930 74630 ) M1M2_PR
+ NEW met1 ( 1312610 74630 ) M1M2_PR ;
+ - wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ( mprj wbs_dat_i[23] ) + USE SIGNAL
+ + ROUTED met2 ( 474030 1700 ) ( 475870 * 0 )
+ NEW met2 ( 474030 1700 ) ( * 16830 )
+ NEW met1 ( 469430 16830 ) ( 474030 * )
+ NEW met2 ( 469430 16830 ) ( * 74970 )
+ NEW met1 ( 469430 74970 ) ( 1319050 * )
+ NEW met2 ( 1319050 74970 ) ( * 1580100 )
+ NEW met2 ( 1319050 1580100 ) ( 1320890 * )
+ NEW met2 ( 1320890 1688780 ) ( 1321510 * )
+ NEW met2 ( 1321510 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1320890 1580100 ) ( * 1688780 )
+ NEW met1 ( 474030 16830 ) M1M2_PR
+ NEW met1 ( 469430 16830 ) M1M2_PR
+ NEW met1 ( 469430 74970 ) M1M2_PR
+ NEW met1 ( 1319050 74970 ) M1M2_PR ;
+ - wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ( mprj wbs_dat_i[24] ) + USE SIGNAL
+ + ROUTED met2 ( 491050 1700 ) ( 493350 * 0 )
+ NEW met2 ( 491050 1700 ) ( * 75310 )
+ NEW met1 ( 491050 75310 ) ( 1325950 * )
+ NEW met2 ( 1325950 1688780 ) ( 1327030 * )
+ NEW met2 ( 1327030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1325950 75310 ) ( * 1688780 )
+ NEW met1 ( 491050 75310 ) M1M2_PR
+ NEW met1 ( 1325950 75310 ) M1M2_PR ;
+ - wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ( mprj wbs_dat_i[25] ) + USE SIGNAL
+ + ROUTED met2 ( 511290 1700 0 ) ( * 75650 )
+ NEW met1 ( 511290 75650 ) ( 1332850 * )
+ NEW met2 ( 1332620 1688780 ) ( 1332850 * )
+ NEW met2 ( 1332620 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1332850 75650 ) ( * 1688780 )
+ NEW met1 ( 511290 75650 ) M1M2_PR
+ NEW met1 ( 1332850 75650 ) M1M2_PR ;
+ - wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ( mprj wbs_dat_i[26] ) + USE SIGNAL
+ + ROUTED met2 ( 528770 1700 0 ) ( * 71910 )
+ NEW met1 ( 528770 71910 ) ( 1333310 * )
+ NEW met1 ( 1333310 1688950 ) ( 1338070 * )
+ NEW met2 ( 1338070 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1333310 71910 ) ( * 1688950 )
+ NEW met1 ( 528770 71910 ) M1M2_PR
+ NEW met1 ( 1333310 71910 ) M1M2_PR
+ NEW met1 ( 1333310 1688950 ) M1M2_PR
+ NEW met1 ( 1338070 1688950 ) M1M2_PR ;
+ - wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ( mprj wbs_dat_i[27] ) + USE SIGNAL
+ + ROUTED met1 ( 1339290 1688950 ) ( 1343590 * )
+ NEW met2 ( 1343590 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1339290 71570 ) ( * 1688950 )
+ NEW met2 ( 545330 1700 ) ( 546710 * 0 )
+ NEW met2 ( 545330 1700 ) ( * 71570 )
+ NEW met1 ( 545330 71570 ) ( 1339290 * )
+ NEW met1 ( 1339290 71570 ) M1M2_PR
+ NEW met1 ( 1339290 1688950 ) M1M2_PR
+ NEW met1 ( 1343590 1688950 ) M1M2_PR
+ NEW met1 ( 545330 71570 ) M1M2_PR ;
+ - wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ( mprj wbs_dat_i[28] ) + USE SIGNAL
+ + ROUTED met2 ( 1346650 1683340 ) ( 1347570 * )
+ NEW met2 ( 1347570 1683340 ) ( * 1688780 )
+ NEW met2 ( 1347570 1688780 ) ( 1349110 * )
+ NEW met2 ( 1349110 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1346650 71230 ) ( * 1683340 )
+ NEW met2 ( 561890 1700 ) ( 564190 * 0 )
+ NEW met2 ( 561890 1700 ) ( * 71230 )
+ NEW met1 ( 561890 71230 ) ( 1346650 * )
+ NEW met1 ( 1346650 71230 ) M1M2_PR
+ NEW met1 ( 561890 71230 ) M1M2_PR ;
+ - wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ( mprj wbs_dat_i[29] ) + USE SIGNAL
+ + ROUTED met2 ( 582130 1700 0 ) ( * 80070 )
+ NEW met2 ( 1353550 1688780 ) ( 1354630 * )
+ NEW met2 ( 1354630 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1353550 80070 ) ( * 1688780 )
+ NEW met1 ( 582130 80070 ) ( 1353550 * )
+ NEW met1 ( 582130 80070 ) M1M2_PR
+ NEW met1 ( 1353550 80070 ) M1M2_PR ;
+ - wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ( mprj wbs_dat_i[2] ) + USE SIGNAL
+ + ROUTED met2 ( 89930 1700 ) ( 91310 * 0 )
+ NEW met2 ( 89930 1700 ) ( * 58990 )
+ NEW met1 ( 89930 58990 ) ( 1201750 * )
+ NEW met2 ( 1201750 1688780 ) ( 1202830 * )
+ NEW met2 ( 1202830 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1201750 58990 ) ( * 1688780 )
+ NEW met1 ( 89930 58990 ) M1M2_PR
+ NEW met1 ( 1201750 58990 ) M1M2_PR ;
+ - wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ( mprj wbs_dat_i[30] ) + USE SIGNAL
+ + ROUTED met2 ( 599610 1700 0 ) ( * 16150 )
+ NEW met1 ( 593630 16150 ) ( 599610 * )
+ NEW met2 ( 593630 16150 ) ( * 80410 )
+ NEW met2 ( 1359760 1688780 ) ( 1360450 * )
+ NEW met2 ( 1359760 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1360450 80410 ) ( * 1688780 )
+ NEW met1 ( 593630 80410 ) ( 1360450 * )
+ NEW met1 ( 599610 16150 ) M1M2_PR
+ NEW met1 ( 593630 16150 ) M1M2_PR
+ NEW met1 ( 593630 80410 ) M1M2_PR
+ NEW met1 ( 1360450 80410 ) M1M2_PR ;
+ - wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ( mprj wbs_dat_i[31] ) + USE SIGNAL
+ + ROUTED met1 ( 1359990 1652570 ) ( 1365050 * )
+ NEW met2 ( 1359990 80750 ) ( * 1652570 )
+ NEW met2 ( 1365050 1688780 ) ( 1365210 * )
+ NEW met2 ( 1365210 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1365050 1652570 ) ( * 1688780 )
+ NEW met2 ( 615250 1700 ) ( 617550 * 0 )
+ NEW met2 ( 615250 1700 ) ( * 80750 )
+ NEW met1 ( 615250 80750 ) ( 1359990 * )
+ NEW met1 ( 1359990 1652570 ) M1M2_PR
+ NEW met1 ( 1365050 1652570 ) M1M2_PR
+ NEW met1 ( 1359990 80750 ) M1M2_PR
+ NEW met1 ( 615250 80750 ) M1M2_PR ;
+ - wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ( mprj wbs_dat_i[3] ) + USE SIGNAL
+ + ROUTED met2 ( 112930 1700 ) ( 115230 * 0 )
+ NEW met2 ( 112930 1700 ) ( * 72420 )
+ NEW met3 ( 112930 72420 ) ( 1209110 * )
+ NEW met2 ( 1209110 1688780 ) ( 1210190 * )
+ NEW met2 ( 1210190 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1209110 72420 ) ( * 1688780 )
+ NEW met2 ( 112930 72420 ) M2M3_PR
+ NEW met2 ( 1209110 72420 ) M2M3_PR ;
+ - wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ( mprj wbs_dat_i[4] ) + USE SIGNAL
+ + ROUTED met2 ( 138690 1700 0 ) ( * 79220 )
+ NEW met3 ( 138690 79220 ) ( 1216010 * )
+ NEW met2 ( 1216010 1688780 ) ( 1217550 * )
+ NEW met2 ( 1217550 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1216010 79220 ) ( * 1688780 )
+ NEW met2 ( 138690 79220 ) M2M3_PR
+ NEW met2 ( 1216010 79220 ) M2M3_PR ;
+ - wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ( mprj wbs_dat_i[5] ) + USE SIGNAL
+ + ROUTED met2 ( 154330 1700 ) ( 156630 * 0 )
+ NEW met2 ( 154330 1700 ) ( * 79390 )
+ NEW met1 ( 154330 79390 ) ( 1222450 * )
+ NEW met2 ( 1222450 1688780 ) ( 1223070 * )
+ NEW met2 ( 1223070 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1222450 79390 ) ( * 1688780 )
+ NEW met1 ( 154330 79390 ) M1M2_PR
+ NEW met1 ( 1222450 79390 ) M1M2_PR ;
+ - wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ( mprj wbs_dat_i[6] ) + USE SIGNAL
+ + ROUTED met2 ( 172730 1700 ) ( 174110 * 0 )
+ NEW met2 ( 172730 1700 ) ( * 79730 )
+ NEW met1 ( 172730 79730 ) ( 1228890 * )
+ NEW met2 ( 1228660 1688780 ) ( 1228890 * )
+ NEW met2 ( 1228660 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1228890 79730 ) ( * 1688780 )
+ NEW met1 ( 172730 79730 ) M1M2_PR
+ NEW met1 ( 1228890 79730 ) M1M2_PR ;
+ - wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ( mprj wbs_dat_i[7] ) + USE SIGNAL
+ + ROUTED met2 ( 186530 82800 ) ( * 92990 )
+ NEW met2 ( 186530 82800 ) ( 192050 * )
+ NEW met2 ( 192050 1700 0 ) ( * 82800 )
+ NEW met1 ( 186530 92990 ) ( 1229350 * )
+ NEW met1 ( 1229350 1688950 ) ( 1234110 * )
+ NEW met2 ( 1234110 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1229350 92990 ) ( * 1688950 )
+ NEW met1 ( 186530 92990 ) M1M2_PR
+ NEW met1 ( 1229350 92990 ) M1M2_PR
+ NEW met1 ( 1229350 1688950 ) M1M2_PR
+ NEW met1 ( 1234110 1688950 ) M1M2_PR ;
+ - wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ( mprj wbs_dat_i[8] ) + USE SIGNAL
+ + ROUTED met2 ( 207230 82800 ) ( * 93330 )
+ NEW met2 ( 207230 82800 ) ( 209530 * )
+ NEW met2 ( 209530 1700 0 ) ( * 82800 )
+ NEW met1 ( 207230 93330 ) ( 1236250 * )
+ NEW met2 ( 1236250 93330 ) ( * 1676700 )
+ NEW met2 ( 1236250 1676700 ) ( 1237630 * )
+ NEW met2 ( 1237630 1676700 ) ( * 1688780 )
+ NEW met2 ( 1237630 1688780 ) ( 1239170 * )
+ NEW met2 ( 1239170 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 207230 93330 ) M1M2_PR
+ NEW met1 ( 1236250 93330 ) M1M2_PR ;
+ - wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ( mprj wbs_dat_i[9] ) + USE SIGNAL
+ + ROUTED met2 ( 225630 1700 ) ( 227470 * 0 )
+ NEW met2 ( 225630 1700 ) ( * 16830 )
+ NEW met1 ( 221030 16830 ) ( 225630 * )
+ NEW met2 ( 221030 16830 ) ( * 93670 )
+ NEW met2 ( 1243610 1688780 ) ( 1244690 * )
+ NEW met2 ( 1244690 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1243610 93670 ) ( * 1688780 )
+ NEW met1 ( 221030 93670 ) ( 1243610 * )
+ NEW met1 ( 225630 16830 ) M1M2_PR
+ NEW met1 ( 221030 16830 ) M1M2_PR
+ NEW met1 ( 221030 93670 ) M1M2_PR
+ NEW met1 ( 1243610 93670 ) M1M2_PR ;
+ - wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ( mprj wbs_dat_o[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1187950 92820 ) ( * 1676700 )
+ NEW met2 ( 1187950 1676700 ) ( 1188410 * )
+ NEW met2 ( 1188410 1676700 ) ( * 1688780 )
+ NEW met2 ( 1188410 1688780 ) ( 1189950 * )
+ NEW met2 ( 1189950 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 48530 1700 ) ( 49910 * 0 )
+ NEW met3 ( 48530 92820 ) ( 1187950 * )
+ NEW met2 ( 48530 1700 ) ( * 92820 )
+ NEW met2 ( 1187950 92820 ) M2M3_PR
+ NEW met2 ( 48530 92820 ) M2M3_PR ;
+ - wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ( mprj wbs_dat_o[10] ) + USE SIGNAL
+ + ROUTED met2 ( 1250510 1688780 ) ( 1252050 * )
+ NEW met2 ( 1252050 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1250510 94010 ) ( * 1688780 )
+ NEW met1 ( 248630 94010 ) ( 1250510 * )
+ NEW met2 ( 248630 82800 ) ( * 94010 )
+ NEW met2 ( 248630 82800 ) ( 250930 * )
+ NEW met2 ( 250930 1700 0 ) ( * 82800 )
+ NEW met1 ( 1250510 94010 ) M1M2_PR
+ NEW met1 ( 248630 94010 ) M1M2_PR ;
+ - wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ( mprj wbs_dat_o[11] ) + USE SIGNAL
+ + ROUTED met2 ( 1256490 1688780 ) ( 1257570 * )
+ NEW met2 ( 1257570 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1256490 94350 ) ( * 1688780 )
+ NEW met2 ( 267030 1700 ) ( 268870 * 0 )
+ NEW met2 ( 267030 1700 ) ( * 16830 )
+ NEW met1 ( 262430 16830 ) ( 267030 * )
+ NEW met1 ( 262430 94350 ) ( 1256490 * )
+ NEW met2 ( 262430 16830 ) ( * 94350 )
+ NEW met1 ( 1256490 94350 ) M1M2_PR
+ NEW met1 ( 267030 16830 ) M1M2_PR
+ NEW met1 ( 262430 16830 ) M1M2_PR
+ NEW met1 ( 262430 94350 ) M1M2_PR ;
+ - wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ( mprj wbs_dat_o[12] ) + USE SIGNAL
+ + ROUTED met2 ( 284050 1700 ) ( 286350 * 0 )
+ NEW met2 ( 283130 82800 ) ( * 95030 )
+ NEW met2 ( 283130 82800 ) ( 284050 * )
+ NEW met2 ( 284050 1700 ) ( * 82800 )
+ NEW met2 ( 1263160 1688780 ) ( 1263390 * )
+ NEW met2 ( 1263160 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1263390 95030 ) ( * 1688780 )
+ NEW met1 ( 283130 95030 ) ( 1263390 * )
+ NEW met1 ( 283130 95030 ) M1M2_PR
+ NEW met1 ( 1263390 95030 ) M1M2_PR ;
+ - wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ( mprj wbs_dat_o[13] ) + USE SIGNAL
+ + ROUTED met2 ( 303830 82800 ) ( * 99790 )
+ NEW met2 ( 303830 82800 ) ( 304290 * )
+ NEW met2 ( 304290 1700 0 ) ( * 82800 )
+ NEW met2 ( 1264310 99790 ) ( * 1580100 )
+ NEW met2 ( 1264310 1580100 ) ( 1267990 * )
+ NEW met2 ( 1267990 1688780 ) ( 1268610 * )
+ NEW met2 ( 1268610 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1267990 1580100 ) ( * 1688780 )
+ NEW met1 ( 303830 99790 ) ( 1264310 * )
+ NEW met1 ( 303830 99790 ) M1M2_PR
+ NEW met1 ( 1264310 99790 ) M1M2_PR ;
+ - wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ( mprj wbs_dat_o[14] ) + USE SIGNAL
+ + ROUTED met2 ( 317630 82800 ) ( * 100130 )
+ NEW met2 ( 317630 82800 ) ( 321770 * )
+ NEW met2 ( 321770 1700 0 ) ( * 82800 )
+ NEW met2 ( 1271210 100130 ) ( * 1580100 )
+ NEW met2 ( 1271210 1580100 ) ( 1273510 * )
+ NEW met2 ( 1273510 1688780 ) ( 1274130 * )
+ NEW met2 ( 1274130 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1273510 1580100 ) ( * 1688780 )
+ NEW met1 ( 317630 100130 ) ( 1271210 * )
+ NEW met1 ( 317630 100130 ) M1M2_PR
+ NEW met1 ( 1271210 100130 ) M1M2_PR ;
+ - wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ( mprj wbs_dat_o[15] ) + USE SIGNAL
+ + ROUTED met2 ( 1278110 1688780 ) ( 1279650 * )
+ NEW met2 ( 1279650 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1278110 100470 ) ( * 1688780 )
+ NEW met2 ( 338330 1700 ) ( 339710 * 0 )
+ NEW met1 ( 338330 100470 ) ( 1278110 * )
+ NEW met2 ( 338330 1700 ) ( * 100470 )
+ NEW met1 ( 1278110 100470 ) M1M2_PR
+ NEW met1 ( 338330 100470 ) M1M2_PR ;
+ - wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ( mprj wbs_dat_o[16] ) + USE SIGNAL
+ + ROUTED met2 ( 1284550 1688780 ) ( 1285170 * )
+ NEW met2 ( 1285170 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1284550 100810 ) ( * 1688780 )
+ NEW met1 ( 352130 100810 ) ( 1284550 * )
+ NEW met2 ( 352130 82800 ) ( * 100810 )
+ NEW met2 ( 352130 82800 ) ( 357650 * )
+ NEW met2 ( 357650 1700 0 ) ( * 82800 )
+ NEW met1 ( 1284550 100810 ) M1M2_PR
+ NEW met1 ( 352130 100810 ) M1M2_PR ;
+ - wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ( mprj wbs_dat_o[17] ) + USE SIGNAL
+ + ROUTED met2 ( 375130 1700 0 ) ( * 24990 )
+ NEW met1 ( 375130 24990 ) ( 727950 * )
+ NEW met2 ( 727950 24990 ) ( * 1681810 )
+ NEW met2 ( 1290530 1681810 ) ( * 1688780 )
+ NEW met2 ( 1290530 1688780 ) ( 1290690 * )
+ NEW met2 ( 1290690 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 727950 1681810 ) ( 1290530 * )
+ NEW met1 ( 375130 24990 ) M1M2_PR
+ NEW met1 ( 727950 24990 ) M1M2_PR
+ NEW met1 ( 727950 1681810 ) M1M2_PR
+ NEW met1 ( 1290530 1681810 ) M1M2_PR ;
+ - wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ( mprj wbs_dat_o[18] ) + USE SIGNAL
+ + ROUTED met2 ( 391230 1700 ) ( 393070 * 0 )
+ NEW met2 ( 391230 1700 ) ( * 16830 )
+ NEW met1 ( 386630 16830 ) ( 391230 * )
+ NEW met2 ( 386630 16830 ) ( * 101150 )
+ NEW met1 ( 386630 101150 ) ( 1291450 * )
+ NEW met1 ( 1291450 1688950 ) ( 1295750 * )
+ NEW met2 ( 1295750 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1291450 101150 ) ( * 1688950 )
+ NEW met1 ( 391230 16830 ) M1M2_PR
+ NEW met1 ( 386630 16830 ) M1M2_PR
+ NEW met1 ( 386630 101150 ) M1M2_PR
+ NEW met1 ( 1291450 101150 ) M1M2_PR
+ NEW met1 ( 1291450 1688950 ) M1M2_PR
+ NEW met1 ( 1295750 1688950 ) M1M2_PR ;
+ - wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ( mprj wbs_dat_o[19] ) + USE SIGNAL
+ + ROUTED met2 ( 410550 1700 0 ) ( * 26690 )
+ NEW met1 ( 410550 26690 ) ( 748650 * )
+ NEW met2 ( 748650 26690 ) ( * 1682150 )
+ NEW met2 ( 1299730 1682150 ) ( * 1689290 )
+ NEW met2 ( 1299730 1689290 ) ( 1301270 * )
+ NEW met2 ( 1301270 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 748650 1682150 ) ( 1299730 * )
+ NEW met1 ( 410550 26690 ) M1M2_PR
+ NEW met1 ( 748650 26690 ) M1M2_PR
+ NEW met1 ( 748650 1682150 ) M1M2_PR
+ NEW met1 ( 1299730 1682150 ) M1M2_PR ;
+ - wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ( mprj wbs_dat_o[1] ) + USE SIGNAL
+ + ROUTED met2 ( 73830 1700 0 ) ( * 17510 )
+ NEW met1 ( 73830 17510 ) ( 1193930 * )
+ NEW met1 ( 1193930 1688950 ) ( 1197310 * )
+ NEW met2 ( 1197310 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1193930 17510 ) ( * 1688950 )
+ NEW met1 ( 73830 17510 ) M1M2_PR
+ NEW met1 ( 1193930 17510 ) M1M2_PR
+ NEW met1 ( 1193930 1688950 ) M1M2_PR
+ NEW met1 ( 1197310 1688950 ) M1M2_PR ;
+ - wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ( mprj wbs_dat_o[20] ) + USE SIGNAL
+ + ROUTED met2 ( 769350 27030 ) ( * 1682490 )
+ NEW met2 ( 428490 1700 0 ) ( * 27030 )
+ NEW met1 ( 428490 27030 ) ( 769350 * )
+ NEW met2 ( 1306630 1682490 ) ( * 1688780 )
+ NEW met2 ( 1306630 1688780 ) ( 1306790 * )
+ NEW met2 ( 1306790 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 769350 1682490 ) ( 1306630 * )
+ NEW met1 ( 769350 27030 ) M1M2_PR
+ NEW met1 ( 769350 1682490 ) M1M2_PR
+ NEW met1 ( 428490 27030 ) M1M2_PR
+ NEW met1 ( 1306630 1682490 ) M1M2_PR ;
+ - wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ( mprj wbs_dat_o[21] ) + USE SIGNAL
+ + ROUTED met2 ( 445970 1700 0 ) ( * 16660 )
+ NEW met3 ( 445970 16660 ) ( 1311690 * )
+ NEW met2 ( 1311690 1688780 ) ( 1312310 * )
+ NEW met2 ( 1312310 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1311690 16660 ) ( * 1688780 )
+ NEW met2 ( 445970 16660 ) M2M3_PR
+ NEW met2 ( 1311690 16660 ) M2M3_PR ;
+ - wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ( mprj wbs_dat_o[22] ) + USE SIGNAL
+ + ROUTED met2 ( 463910 1700 0 ) ( * 24650 )
+ NEW met1 ( 463910 24650 ) ( 817650 * )
+ NEW met2 ( 817650 24650 ) ( * 1682830 )
+ NEW met2 ( 1317670 1682830 ) ( * 1689290 )
+ NEW met2 ( 1317670 1689290 ) ( 1317830 * )
+ NEW met2 ( 1317830 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 817650 1682830 ) ( 1317670 * )
+ NEW met1 ( 463910 24650 ) M1M2_PR
+ NEW met1 ( 817650 24650 ) M1M2_PR
+ NEW met1 ( 817650 1682830 ) M1M2_PR
+ NEW met1 ( 1317670 1682830 ) M1M2_PR ;
+ - wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ( mprj wbs_dat_o[23] ) + USE SIGNAL
+ + ROUTED met2 ( 481390 1700 0 ) ( * 20570 )
+ NEW met1 ( 481390 20570 ) ( 1318130 * )
+ NEW met1 ( 1318130 1688950 ) ( 1323350 * )
+ NEW met2 ( 1323350 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1318130 20570 ) ( * 1688950 )
+ NEW met1 ( 481390 20570 ) M1M2_PR
+ NEW met1 ( 1318130 20570 ) M1M2_PR
+ NEW met1 ( 1318130 1688950 ) M1M2_PR
+ NEW met1 ( 1323350 1688950 ) M1M2_PR ;
+ - wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ( mprj wbs_dat_o[24] ) + USE SIGNAL
+ + ROUTED met2 ( 499330 1700 0 ) ( * 26350 )
+ NEW met1 ( 499330 26350 ) ( 838350 * )
+ NEW met2 ( 838350 26350 ) ( * 1683170 )
+ NEW met1 ( 1290690 1683170 ) ( * 1683510 )
+ NEW met1 ( 1290690 1683510 ) ( 1294670 * )
+ NEW met1 ( 1294670 1683170 ) ( * 1683510 )
+ NEW met1 ( 1294670 1683170 ) ( 1328710 * )
+ NEW met2 ( 1328710 1683170 ) ( * 1688780 )
+ NEW met2 ( 1328710 1688780 ) ( 1328870 * )
+ NEW met2 ( 1328870 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 838350 1683170 ) ( 1290690 * )
+ NEW met1 ( 499330 26350 ) M1M2_PR
+ NEW met1 ( 838350 26350 ) M1M2_PR
+ NEW met1 ( 838350 1683170 ) M1M2_PR
+ NEW met1 ( 1328710 1683170 ) M1M2_PR ;
+ - wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ( mprj wbs_dat_o[25] ) + USE SIGNAL
+ + ROUTED met2 ( 516810 1700 0 ) ( * 16830 )
+ NEW met2 ( 1183350 16830 ) ( * 1678410 )
+ NEW met1 ( 516810 16830 ) ( 1183350 * )
+ NEW met2 ( 1334230 1678410 ) ( * 1689290 )
+ NEW met2 ( 1334230 1689290 ) ( 1334390 * )
+ NEW met2 ( 1334390 1689290 ) ( * 1690140 0 )
+ NEW met1 ( 1183350 1678410 ) ( 1334230 * )
+ NEW met1 ( 516810 16830 ) M1M2_PR
+ NEW met1 ( 1183350 16830 ) M1M2_PR
+ NEW met1 ( 1183350 1678410 ) M1M2_PR
+ NEW met1 ( 1334230 1678410 ) M1M2_PR ;
+ - wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ( mprj wbs_dat_o[26] ) + USE SIGNAL
+ + ROUTED met2 ( 1190250 16490 ) ( * 1678070 )
+ NEW met2 ( 1338830 1678070 ) ( * 1689460 )
+ NEW met2 ( 1338830 1689460 ) ( 1339910 * )
+ NEW met2 ( 1339910 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 534750 1700 0 ) ( * 16150 )
+ NEW met1 ( 534750 16150 ) ( 565800 * )
+ NEW met1 ( 565800 16150 ) ( * 16490 )
+ NEW met1 ( 565800 16490 ) ( 1190250 * )
+ NEW met1 ( 1190250 1678070 ) ( 1338830 * )
+ NEW met1 ( 1190250 16490 ) M1M2_PR
+ NEW met1 ( 1190250 1678070 ) M1M2_PR
+ NEW met1 ( 1338830 1678070 ) M1M2_PR
+ NEW met1 ( 534750 16150 ) M1M2_PR ;
+ - wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ( mprj wbs_dat_o[27] ) + USE SIGNAL
+ + ROUTED met2 ( 886650 27370 ) ( * 1683510 )
+ NEW met2 ( 1345270 1683510 ) ( * 1688780 )
+ NEW met2 ( 1345270 1688780 ) ( 1345430 * )
+ NEW met2 ( 1345430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 552690 1700 0 ) ( * 27370 )
+ NEW met1 ( 552690 27370 ) ( 886650 * )
+ NEW met1 ( 886650 1683510 ) ( 1290300 * )
+ NEW met1 ( 1290300 1683510 ) ( * 1683850 )
+ NEW met1 ( 1290300 1683850 ) ( 1295130 * )
+ NEW met1 ( 1295130 1683510 ) ( * 1683850 )
+ NEW met1 ( 1295130 1683510 ) ( 1345270 * )
+ NEW met1 ( 886650 27370 ) M1M2_PR
+ NEW met1 ( 886650 1683510 ) M1M2_PR
+ NEW met1 ( 1345270 1683510 ) M1M2_PR
+ NEW met1 ( 552690 27370 ) M1M2_PR ;
+ - wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ( mprj wbs_dat_o[28] ) + USE SIGNAL
+ + ROUTED met2 ( 570170 1700 0 ) ( * 15810 )
+ NEW met2 ( 1350790 1677390 ) ( * 1688780 )
+ NEW met2 ( 1350790 1688780 ) ( 1350950 * )
+ NEW met2 ( 1350950 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 570170 15810 ) ( 614100 * )
+ NEW met1 ( 614100 15810 ) ( * 16150 )
+ NEW met1 ( 614100 16150 ) ( 1204050 * )
+ NEW met2 ( 1204050 16150 ) ( * 1677390 )
+ NEW met1 ( 1204050 1677390 ) ( 1350790 * )
+ NEW met1 ( 570170 15810 ) M1M2_PR
+ NEW met1 ( 1350790 1677390 ) M1M2_PR
+ NEW met1 ( 1204050 16150 ) M1M2_PR
+ NEW met1 ( 1204050 1677390 ) M1M2_PR ;
+ - wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ( mprj wbs_dat_o[29] ) + USE SIGNAL
+ + ROUTED met2 ( 588110 1700 0 ) ( * 25670 )
+ NEW met2 ( 1355850 1679770 ) ( * 1688780 )
+ NEW met2 ( 1355850 1688780 ) ( 1356010 * )
+ NEW met2 ( 1356010 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 588110 25670 ) ( 928050 * )
+ NEW met2 ( 928050 25670 ) ( * 1679770 )
+ NEW met1 ( 928050 1679770 ) ( 1355850 * )
+ NEW met1 ( 588110 25670 ) M1M2_PR
+ NEW met1 ( 1355850 1679770 ) M1M2_PR
+ NEW met1 ( 928050 25670 ) M1M2_PR
+ NEW met1 ( 928050 1679770 ) M1M2_PR ;
+ - wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ( mprj wbs_dat_o[2] ) + USE SIGNAL
+ + ROUTED met2 ( 97290 1700 0 ) ( * 18190 )
+ NEW met1 ( 97290 18190 ) ( 1202210 * )
+ NEW met2 ( 1202210 18190 ) ( * 1580100 )
+ NEW met2 ( 1202210 1580100 ) ( 1203590 * )
+ NEW met2 ( 1203590 1688780 ) ( 1204670 * )
+ NEW met2 ( 1204670 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1203590 1580100 ) ( * 1688780 )
+ NEW met1 ( 97290 18190 ) M1M2_PR
+ NEW met1 ( 1202210 18190 ) M1M2_PR ;
+ - wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ( mprj wbs_dat_o[30] ) + USE SIGNAL
+ + ROUTED met2 ( 605590 1700 0 ) ( * 25330 )
+ NEW met2 ( 1361370 1679430 ) ( * 1688780 )
+ NEW met2 ( 1361370 1688780 ) ( 1361530 * )
+ NEW met2 ( 1361530 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 605590 25330 ) ( 941850 * )
+ NEW met2 ( 941850 25330 ) ( * 1679430 )
+ NEW met1 ( 941850 1679430 ) ( 1361370 * )
+ NEW met1 ( 605590 25330 ) M1M2_PR
+ NEW met1 ( 1361370 1679430 ) M1M2_PR
+ NEW met1 ( 941850 25330 ) M1M2_PR
+ NEW met1 ( 941850 1679430 ) M1M2_PR ;
+ - wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ( mprj wbs_dat_o[31] ) + USE SIGNAL
+ + ROUTED met2 ( 969450 26010 ) ( * 1679090 )
+ NEW met2 ( 1366890 1679090 ) ( * 1689460 )
+ NEW met2 ( 1366890 1689460 ) ( 1367050 * )
+ NEW met2 ( 1367050 1689460 ) ( * 1690140 0 )
+ NEW met2 ( 623530 1700 0 ) ( * 26010 )
+ NEW met1 ( 623530 26010 ) ( 969450 * )
+ NEW met1 ( 969450 1679090 ) ( 1366890 * )
+ NEW met1 ( 969450 26010 ) M1M2_PR
+ NEW met1 ( 969450 1679090 ) M1M2_PR
+ NEW met1 ( 1366890 1679090 ) M1M2_PR
+ NEW met1 ( 623530 26010 ) M1M2_PR ;
+ - wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ( mprj wbs_dat_o[3] ) + USE SIGNAL
+ + ROUTED met2 ( 121210 1700 0 ) ( * 18530 )
+ NEW met1 ( 121210 18530 ) ( 1208190 * )
+ NEW met1 ( 1208190 1652570 ) ( 1211870 * )
+ NEW met2 ( 1208190 18530 ) ( * 1652570 )
+ NEW met2 ( 1211870 1688780 ) ( 1212030 * )
+ NEW met2 ( 1212030 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1211870 1652570 ) ( * 1688780 )
+ NEW met1 ( 121210 18530 ) M1M2_PR
+ NEW met1 ( 1208190 18530 ) M1M2_PR
+ NEW met1 ( 1208190 1652570 ) M1M2_PR
+ NEW met1 ( 1211870 1652570 ) M1M2_PR ;
+ - wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ( mprj wbs_dat_o[4] ) + USE SIGNAL
+ + ROUTED met2 ( 144670 1700 0 ) ( * 19210 )
+ NEW met1 ( 144670 19210 ) ( 1214630 * )
+ NEW met1 ( 1214630 1688950 ) ( 1219390 * )
+ NEW met2 ( 1219390 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1214630 19210 ) ( * 1688950 )
+ NEW met1 ( 144670 19210 ) M1M2_PR
+ NEW met1 ( 1214630 19210 ) M1M2_PR
+ NEW met1 ( 1214630 1688950 ) M1M2_PR
+ NEW met1 ( 1219390 1688950 ) M1M2_PR ;
+ - wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ( mprj wbs_dat_o[5] ) + USE SIGNAL
+ + ROUTED met2 ( 162150 1700 0 ) ( * 19550 )
+ NEW met1 ( 162150 19550 ) ( 1221530 * )
+ NEW met1 ( 1221530 1688950 ) ( 1224910 * )
+ NEW met2 ( 1224910 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1221530 19550 ) ( * 1688950 )
+ NEW met1 ( 162150 19550 ) M1M2_PR
+ NEW met1 ( 1221530 19550 ) M1M2_PR
+ NEW met1 ( 1221530 1688950 ) M1M2_PR
+ NEW met1 ( 1224910 1688950 ) M1M2_PR ;
+ - wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ( mprj wbs_dat_o[6] ) + USE SIGNAL
+ + ROUTED met2 ( 179630 82800 ) ( 180090 * )
+ NEW met2 ( 180090 1700 0 ) ( * 82800 )
+ NEW met2 ( 179630 82800 ) ( * 1681130 )
+ NEW met2 ( 1230270 1681130 ) ( * 1688780 )
+ NEW met2 ( 1230270 1688780 ) ( 1230430 * )
+ NEW met2 ( 1230430 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 179630 1681130 ) ( 1230270 * )
+ NEW met1 ( 179630 1681130 ) M1M2_PR
+ NEW met1 ( 1230270 1681130 ) M1M2_PR ;
+ - wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ( mprj wbs_dat_o[7] ) + USE SIGNAL
+ + ROUTED met2 ( 198030 1700 0 ) ( * 19890 )
+ NEW met1 ( 198030 19890 ) ( 1236710 * )
+ NEW met1 ( 1235330 1660050 ) ( 1236710 * )
+ NEW met2 ( 1236710 19890 ) ( * 1660050 )
+ NEW met2 ( 1235330 1688780 ) ( 1235490 * )
+ NEW met2 ( 1235490 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1235330 1660050 ) ( * 1688780 )
+ NEW met1 ( 198030 19890 ) M1M2_PR
+ NEW met1 ( 1236710 19890 ) M1M2_PR
+ NEW met1 ( 1235330 1660050 ) M1M2_PR
+ NEW met1 ( 1236710 1660050 ) M1M2_PR ;
+ - wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ( mprj wbs_dat_o[8] ) + USE SIGNAL
+ + ROUTED met2 ( 214130 1700 ) ( 215510 * 0 )
+ NEW met2 ( 214130 1700 ) ( * 1681470 )
+ NEW met2 ( 1240850 1681470 ) ( * 1688780 )
+ NEW met2 ( 1240850 1688780 ) ( 1241010 * )
+ NEW met2 ( 1241010 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 214130 1681470 ) ( 1240850 * )
+ NEW met1 ( 214130 1681470 ) M1M2_PR
+ NEW met1 ( 1240850 1681470 ) M1M2_PR ;
+ - wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ( mprj wbs_dat_o[9] ) + USE SIGNAL
+ + ROUTED met1 ( 1242230 1688950 ) ( 1246530 * )
+ NEW met2 ( 1246530 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1242230 20230 ) ( * 1688950 )
+ NEW met2 ( 233450 1700 0 ) ( * 20230 )
+ NEW met1 ( 233450 20230 ) ( 1242230 * )
+ NEW met1 ( 1242230 20230 ) M1M2_PR
+ NEW met1 ( 1242230 1688950 ) M1M2_PR
+ NEW met1 ( 1246530 1688950 ) M1M2_PR
+ NEW met1 ( 233450 20230 ) M1M2_PR ;
+ - wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ( mprj wbs_sel_i[0] ) + USE SIGNAL
+ + ROUTED met2 ( 1191630 1680450 ) ( * 1688780 )
+ NEW met2 ( 1191630 1688780 ) ( 1191790 * )
+ NEW met2 ( 1191790 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 55430 82800 ) ( 55890 * )
+ NEW met2 ( 55890 1700 0 ) ( * 82800 )
+ NEW met2 ( 55430 82800 ) ( * 1680450 )
+ NEW met1 ( 55430 1680450 ) ( 1191630 * )
+ NEW met1 ( 1191630 1680450 ) M1M2_PR
+ NEW met1 ( 55430 1680450 ) M1M2_PR ;
+ - wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ( mprj wbs_sel_i[1] ) + USE SIGNAL
+ + ROUTED met2 ( 79810 1700 0 ) ( * 17850 )
+ NEW met1 ( 79810 17850 ) ( 1194390 * )
+ NEW met1 ( 1194390 1689290 ) ( 1199150 * )
+ NEW met2 ( 1199150 1689290 ) ( * 1690140 0 )
+ NEW met2 ( 1194390 17850 ) ( * 1689290 )
+ NEW met1 ( 79810 17850 ) M1M2_PR
+ NEW met1 ( 1194390 17850 ) M1M2_PR
+ NEW met1 ( 1194390 1689290 ) M1M2_PR
+ NEW met1 ( 1199150 1689290 ) M1M2_PR ;
+ - wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ( mprj wbs_sel_i[2] ) + USE SIGNAL
+ + ROUTED met2 ( 100970 1700 ) ( 103270 * 0 )
+ NEW met2 ( 96830 82800 ) ( 100970 * )
+ NEW met2 ( 100970 1700 ) ( * 82800 )
+ NEW met2 ( 96830 82800 ) ( * 1680790 )
+ NEW met2 ( 1206350 1680790 ) ( * 1688780 )
+ NEW met2 ( 1206350 1688780 ) ( 1206510 * )
+ NEW met2 ( 1206510 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 96830 1680790 ) ( 1206350 * )
+ NEW met1 ( 96830 1680790 ) M1M2_PR
+ NEW met1 ( 1206350 1680790 ) M1M2_PR ;
+ - wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ( mprj wbs_sel_i[3] ) + USE SIGNAL
+ + ROUTED met2 ( 126730 1700 0 ) ( * 18870 )
+ NEW met1 ( 126730 18870 ) ( 1207730 * )
+ NEW met1 ( 1207730 1688950 ) ( 1213870 * )
+ NEW met2 ( 1213870 1688950 ) ( * 1690140 0 )
+ NEW met2 ( 1207730 18870 ) ( * 1688950 )
+ NEW met1 ( 126730 18870 ) M1M2_PR
+ NEW met1 ( 1207730 18870 ) M1M2_PR
+ NEW met1 ( 1207730 1688950 ) M1M2_PR
+ NEW met1 ( 1213870 1688950 ) M1M2_PR ;
+ - wbs_stb_i ( PIN wbs_stb_i ) ( mprj wbs_stb_i ) + USE SIGNAL
+ + ROUTED met2 ( 20930 82800 ) ( 26450 * )
+ NEW met2 ( 26450 1700 0 ) ( * 82800 )
+ NEW met2 ( 20930 82800 ) ( * 1680110 )
+ NEW met2 ( 1182430 1680110 ) ( * 1688780 )
+ NEW met2 ( 1182430 1688780 ) ( 1182590 * )
+ NEW met2 ( 1182590 1688780 ) ( * 1690140 0 )
+ NEW met1 ( 20930 1680110 ) ( 1182430 * )
+ NEW met1 ( 20930 1680110 ) M1M2_PR
+ NEW met1 ( 1182430 1680110 ) M1M2_PR ;
+ - wbs_we_i ( PIN wbs_we_i ) ( mprj wbs_we_i ) + USE SIGNAL
+ + ROUTED met2 ( 32430 1700 0 ) ( * 17170 )
+ NEW met2 ( 1181510 17170 ) ( * 1580100 )
+ NEW met2 ( 1181510 1580100 ) ( 1182890 * )
+ NEW met2 ( 1182890 1688780 ) ( 1184430 * )
+ NEW met2 ( 1184430 1688780 ) ( * 1690140 0 )
+ NEW met2 ( 1182890 1580100 ) ( * 1688780 )
+ NEW met1 ( 32430 17170 ) ( 1181510 * )
+ NEW met1 ( 32430 17170 ) M1M2_PR
+ NEW met1 ( 1181510 17170 ) M1M2_PR ;
+END NETS
+END DESIGN
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
old mode 100644
new mode 100755
index ccfa729..1f6639d
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -1,7 +1,5 @@
-#!/usr/bin/tclsh
-# SPDX-FileCopyrightText: 2020 Efabless Corporation
-# Copyright 2020 Efabless Corporation
-# Copyright 2020 Sylvain Munaut
+#!/usr/bin/env tclsh
+# Copyright 2020-2022 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -14,358 +12,335 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
-# SPDX-License-Identifier: Apache-2.0
-package require openlane;
+package require openlane; # provides the utils as well
+
proc run_placement_step {args} {
if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
}
+
run_placement
}
+
proc run_cts_step {args} {
if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
}
+
run_cts
run_resizer_timing
}
+
proc run_routing_step {args} {
if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
}
- run_routing
+ if { $::env(ECO_ENABLE) == 0 } {
+ run_routing
+ }
}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) && ($::env(ECO_ENABLE) == 0)} {
+ run_parasitics_sta
+ }
+}
+
proc run_diode_insertion_2_5_step {args} {
if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
}
- if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
- run_antenna_check
- heal_antenna_violators; # modifies the routed DEF
- }
+ if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+ run_antenna_check
+ heal_antenna_violators; # modifies the routed DEF
+ }
+
}
+
+proc run_irdrop_report_step {args} {
+ if { $::env(RUN_IRDROP_REPORT) } {
+ run_irdrop_report
+ }
+}
+
proc run_lvs_step {{ lvs_enabled 1 }} {
if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
}
- if { $lvs_enabled } {
- run_magic_spice_export
- run_lvs; # requires run_magic_spice_export
- }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
+ run_lvs; # requires run_magic_spice_export
+ }
+
}
+
proc run_drc_step {{ drc_enabled 1 }} {
if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
}
- if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
- }
+ if { $drc_enabled } {
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
+ }
}
+
proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
} else {
set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
}
- if { $antenna_check_enabled } {
- run_antenna_check
- }
-}
-proc run_eco_step {args} {
- if { $::env(ECO_ENABLE) == 1 } {
- run_eco
+ if { $antenna_check_enabled } {
+ run_antenna_check
}
}
-proc save_final_views {args} {
- set options {
- {-save_path optional}
- }
- set flags {}
- parse_key_args "save_final_views" args arg_values $options flags_map $flags
- set arg_list [list]
- # If they don't exist, save_views will simply not copy them
- lappend arg_list -lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef
- lappend arg_list -gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds
- lappend arg_list -mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag
- lappend arg_list -maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag
- lappend arg_list -spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice
-
- # Guaranteed to have default values
- lappend arg_list -def_path $::env(CURRENT_DEF)
- lappend arg_list -verilog_path $::env(CURRENT_NETLIST)
- # Not guaranteed to have default values
- if { [info exists ::env(SPEF_TYPICAL)] } {
- lappend arg_list -spef_path $::env(SPEF_TYPICAL)
- }
- if { [info exists ::env(CURRENT_SDF)] } {
- lappend arg_list -sdf_path $::env(CURRENT_SDF)
- }
- if { [info exists ::env(CURRENT_SDC)] } {
- lappend arg_list -sdc_path $::env(CURRENT_SDC)
- }
- # Add the path if it exists...
- if { [info exists arg_values(-save_path) ] } {
- lappend arg_list -save_path $arg_values(-save_path)
- }
- # Aaand fire!
- save_views {*}$arg_list
+
+proc run_eco_step {args} {
+ if { $::env(ECO_ENABLE) == 1 } {
+ run_eco_flow
+ }
}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
+}
+
proc run_post_run_hooks {} {
- if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
- puts_info "Running post run hook"
- set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
- puts_info "$result"
- } else {
- puts_info "hooks/post_run.py not found, skipping"
- }
+ if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} {
+ puts_info "Running post run hook"
+ set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py]
+ puts_info "$result"
+ } else {
+ puts_info "hooks/post_run.py not found, skipping"
+ }
}
-proc gen_pdn {args} {
- puts_info "Generating PDN..."
- TIMER::timer_start
-
- set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles).def]
- set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles).pga.rpt]
- run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
- |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log]
- TIMER::timer_stop
- exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "pdn generation - openroad"
- quit_on_unconnected_pdn_nodes
- set_def $::env(SAVE_DEF)
+
+proc run_magic_drc_batch {args} {
+ set options {
+ {-magicrc optional}
+ {-tech optional}
+ {-report required}
+ {-design required}
+ {-gds required}
+ }
+ set flags {}
+ parse_key_args "run_magic_drc_batch" args arg_values $options flags_mag $flags
+ if { [info exists arg_values(-magicrc)] } {
+ set magicrc [file normalize $arg_values(-magicrc)]
+ }
+ if { [info exists arg_values(-tech)] } {
+ set ::env(TECH) [file normalize $arg_values(-tech)]
+ }
+ set ::env(GDS_INPUT) [file normalize $arg_values(-gds)]
+ set ::env(REPORT_OUTPUT) [file normalize $arg_values(-report)]
+ set ::env(DESIGN_NAME) $arg_values(-design)
+
+ if { [info exists magicrc] } {
+ exec magic \
+ -noconsole \
+ -dnull \
+ -rcfile $magicrc \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ } else {
+ exec magic \
+ -noconsole \
+ -dnull \
+ $::env(OPENLANE_ROOT)/scripts/magic/drc_batch.tcl \
+ </dev/null |& tee /dev/tty
+ }
}
-proc run_power_grid_generation {args} {
- if {[info exists ::env(FP_PDN_POWER_STRAPS)]} {
- set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","]
- }
- # internal macros power connections
- if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
- set macro_hooks [dict create]
- set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
- foreach pdn_hook $pdn_hooks {
- set instance_name [lindex $pdn_hook 0]
- set power_net [lindex $pdn_hook 1]
- set ground_net [lindex $pdn_hook 2]
- dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
- }
-
- set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
- set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
- # make sure that the specified power domains exist.
- if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
- puts_err "Can't find $power_net and $ground_net domain. \
- Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
- }
- }
-
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach domain $power_domains {
- set ::env(VDD_NET) [lindex $domain 0]
- set ::env(GND_NET) [lindex $domain 1]
- set ::env(_WITH_STRAPS) [lindex $domain 2]
- puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros."
- # internal macros power connections
- set ::env(FP_PDN_MACROS) ""
- if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
- # if macros connections to power are explicitly set
- # default behavoir macro pins will be connected to the first power domain
- if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- foreach {instance_name hooks} $macro_hooks {
- set power [lindex $hooks 0]
- set ground [lindex $hooks 1]
- if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
- set ::env(FP_PDN_IRDROP) "0"
- puts_info "Connecting $instance_name to $power and $ground nets."
- lappend ::env(FP_PDN_MACROS) $instance_name
- }
- }
- }
- } else {
- puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)."
- }
-
- gen_pdn
- set ::env(FP_PDN_ENABLE_RAILS) 0
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- set ::env(FP_PDN_IRDROP) "0"
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)"
- puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
- puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
- }
- set ::env(FP_PDN_ENABLE_RAILS) 1
+
+proc run_lvs_batch {args} {
+ # runs device level lvs on -gds/CURRENT_GDS and -net/CURRENT_NETLIST
+ # extracts gds only if EXT_NETLIST does not exist
+ set options {
+ {-design required}
+ {-gds optional}
+ {-net optional}
+ }
+ set flags {}
+ parse_key_args "run_lvs_batch" args arg_values $options flags_lvs $flags -no_consume
+
+ prep {*}$args
+
+ if { [info exists arg_values(-gds)] } {
+ set ::env(CURRENT_GDS) [file normalize $arg_values(-gds)]
+ } else {
+ set ::env(CURRENT_GDS) $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ }
+ if { [info exists arg_values(-net)] } {
+ set ::env(CURRENT_NETLIST) [file normalize $arg_values(-net)]
+ }
+
+ assert_files_exist "$::env(CURRENT_GDS) $::env(CURRENT_NETLIST)"
+
+ set ::env(MAGIC_EXT_USE_GDS) 1
+ set ::env(EXT_NETLIST) $::env(signoff_results)/$::env(DESIGN_NAME).gds.spice
+ if { [file exists $::env(EXT_NETLIST)] } {
+ puts_warn "The file $::env(EXT_NETLIST) will be used. If you would like the file re-exported, please delete it."
+ } else {
+ run_magic_spice_export
+ }
+
+ run_lvs
}
-proc run_floorplan {args} {
- puts_info "Running Floorplanning..."
- # |----------------------------------------------------|
- # |---------------- 2. FLOORPLAN ------------------|
- # |----------------------------------------------------|
- #
- # intial fp
- init_floorplan
- # check for deprecated io variables
- if { [info exists ::env(FP_IO_HMETAL)]} {
- set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]]
- puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future."
- puts_warn "We recommend you update your configuration as follows:"
- puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}"
- }
- if { [info exists ::env(FP_IO_VMETAL)]} {
- set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]]
- puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future."
- puts_warn "We recommend you update your configuration as follows:"
- puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}"
- }
- # place io
- if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
- place_io_ol
- } else {
- if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
- place_io
- global_placement_or
- place_contextualized_io \
- -lef $::env(FP_CONTEXT_LEF) \
- -def $::env(FP_CONTEXT_DEF)
- } else {
- place_io
- }
- }
- apply_def_template
- if { [info exist ::env(EXTRA_LEFS)] } {
- if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
- file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
- manual_macro_placement f
- } else {
- global_placement_or
- basic_macro_placement
- }
- }
- tap_decap_or
- scrot_klayout -layout $::env(CURRENT_DEF) $::env(floorplan_logs)/screenshot.log
- run_power_grid_generation
+
+
+proc run_file {args} {
+ set ::env(TCLLIBPATH) $::auto_path
+ exec tclsh {*}$args >&@stdout
}
+
+
+
proc run_flow {args} {
- set options {
- {-design required}
- {-from optional}
- {-to optional}
- {-save_path optional}
- {-override_env optional}
- }
- set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck }
- parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
- prep {*}$args
+ set options {
+ {-design optional}
+ {-from optional}
+ {-to optional}
+ {-save_path optional}
+ {-override_env optional}
+ }
+ set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck -gui}
+ parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume
+
+ prep {*}$args
# signal trap SIGINT save_state;
- if { [info exists arg_values(-override_env)] } {
- set env_overrides [split $arg_values(-override_env) ',']
- foreach override $env_overrides {
- set kva [split $override '=']
- set key [lindex $kva 0]
- set value [lindex $kva 1]
- set ::env(${key}) $value
- }
- }
+
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
+ if { [info exists arg_values(-override_env)] } {
+ load_overrides $arg_values(-override_env)
+ }
+
set LVS_ENABLED 1
set DRC_ENABLED 0
- set ANTENNACHECK_ENABLED 1
+
+ set ANTENNACHECK_ENABLED [expr ![info exists flags_map(-no_antennacheck)] ]
+
set steps [dict create \
- "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "eco" {run_eco_step ""} \
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "irdrop" "run_irdrop_report_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
]
- set_if_unset arg_values(-to) "cvc";
- if { [info exists ::env(CURRENT_STEP) ] } {
- puts "\[INFO\]:Picking up where last execution left off"
- puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+
+ if { [info exists arg_values(-from) ]} {
+ puts_info "Starting flow at $arg_values(-from)..."
+ set ::env(CURRENT_STEP) $arg_values(-from)
+ } elseif { [info exists ::env(CURRENT_STEP) ] } {
+ puts_info "Resuming flow from $::env(CURRENT_STEP)..."
} else {
- set ::env(CURRENT_STEP) "synthesis";
+ set ::env(CURRENT_STEP) "synthesis"
}
- set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+
+ set_if_unset arg_values(-from) $::env(CURRENT_STEP)
+ set_if_unset arg_values(-to) "cvc"
+
set exe 0;
dict for {step_name step_exe} $steps {
if { [ string equal $arg_values(-from) $step_name ] } {
set exe 1;
}
+
if { $exe } {
# For when it fails
set ::env(CURRENT_STEP) $step_name
[lindex $step_exe 0] [lindex $step_exe 1] ;
}
+
if { [ string equal $arg_values(-to) $step_name ] } {
set exe 0:
break;
}
+
}
+
# for when it resumes
set steps_as_list [dict keys $steps]
set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
- # Saves to <RUN_DIR>/results/final
- if { $::env(SAVE_FINAL_VIEWS) == "1" } {
- save_final_views
- }
- # Saves to design directory or custom
- if { [info exists flags_map(-save) ] } {
- if { ! [info exists arg_values(-save_path)] } {
- set arg_values(-save_path) $::env(DESIGN_DIR)
- }
- save_final_views\
- -save_path $arg_values(-save_path)\
- -tag $::env(RUN_TAG)
- }
- calc_total_runtime
- save_state
- generate_final_summary_report
-
- check_timing_violations
-
- if { [info exists arg_values(-save_path)]\
- && $arg_values(-save_path) != "" } {
- set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
- } else {
- set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
- }
-
- if {[info exists flags_map(-run_hooks)]} {
- run_post_run_hooks
- }
-
- puts_success "Flow complete."
- show_warnings "Note that the following warnings have been generated:"
+
+ # Saves to <RUN_DIR>/results/final
+ save_final_views
+
+ # Saves to design directory or custom
+ if { [info exists flags_map(-save) ] } {
+ if { ! [info exists arg_values(-save_path)] } {
+ set arg_values(-save_path) $::env(DESIGN_DIR)
+ }
+ save_final_views\
+ -save_path $arg_values(-save_path)\
+ -tag $::env(RUN_TAG)
+ }
+ calc_total_runtime
+ save_state
+ generate_final_summary_report
+
+ check_timing_violations
+
+ if { [info exists arg_values(-save_path)]\
+ && $arg_values(-save_path) != "" } {
+ set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
+ } else {
+ set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
+ }
+
+ if {[info exists flags_map(-run_hooks)]} {
+ run_post_run_hooks
+ }
+
+ puts_success "Flow complete."
+
+ show_warnings "Note that the following warnings have been generated:"
}
+
run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index d82daa9..994428f 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -13,4 +13,4 @@
u_intercon 1850 650 N
u_wb_host 1750 100 N
-u_pll 2300 100 N
+u_pll 2305 105 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index 552a90e..79a0f85 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -1,82 +1,161 @@
# Power nets
-if { ! [info exists ::env(VDD_NET)] } {
- set ::env(VDD_NET) $::env(VDD_PIN)
-}
-if { ! [info exists ::env(GND_NET)] } {
- set ::env(GND_NET) $::env(GND_PIN)
-}
-set ::power_nets $::env(VDD_NET)
-set ::ground_nets $::env(GND_NET)
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
foreach power_pin $::env(STD_CELL_POWER_PINS) {
- add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
+ add_global_connection \
+ -net $::env(VDD_NET) \
+ -inst_pattern .* \
+ -pin_pattern $power_pin \
+ -power
}
foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
- add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
+ add_global_connection \
+ -net $::env(GND_NET) \
+ -inst_pattern .* \
+ -pin_pattern $ground_pin \
+ -ground
}
}
}
-set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
-# Assesses whether the deisgn is the core of the chip or not based on the
+
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+ [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ set power_pin [lindex $pdn_hook 3]
+ set ground_pin [lindex $pdn_hook 4]
+
+ if { $power_pin == "" || $ground_pin == "" } {
+ puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
+ exit -1
+ }
+
+ add_global_connection \
+ -net $power_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $power_pin \
+ -power
+
+ add_global_connection \
+ -net $ground_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $ground_pin \
+ -ground
+ }
+}
+
+set secondary []
+
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+ if { $vdd != $::env(VDD_NET)} {
+ lappend secondary $vdd
+
+ set db_net [[ord::get_db_block] findNet $vdd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $vdd]
+ $net setSpecial
+ $net setSigType "POWER"
+ }
+ }
+
+ if { $gnd != $::env(GND_NET)} {
+ lappend secondary $gnd
+
+ set db_net [[ord::get_db_block] findNet $gnd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $gnd]
+ $net setSpecial
+ $net setSigType "GROUND"
+ }
+ }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+ -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
if { $::env(DESIGN_IS_CORE) == 1 } {
# Used if the design is the core of the chip
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
- if { $::env(_WITH_STRAPS) } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
- }
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_UPPER_LAYER) \
+ -width $::env(FP_PDN_HWIDTH) \
+ -pitch $::env(FP_PDN_HPITCH) \
+ -offset $::env(FP_PDN_HOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
} else {
# Used if the design is a macro in the core
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins $::env(FP_PDN_LOWER_LAYER)
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER
}
+
# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
-}
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_RAILS_LAYER) \
+ -width $::env(FP_PDN_RAIL_WIDTH) \
+ -followpins \
+ -starts_with POWER
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
+}
+
+
# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
- add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
- -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
- -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
- -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
-# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
-# The macro power pin names are assumed to match the VDD and GND net names
-# TODO: parameterize the power pin names
-set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins $::env(VDD_NET)
- ground_pins $::env(GND_NET)
- blockages $::env(MACRO_BLOCKAGES_LAYER)
- straps {
- }
- connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
-}
-if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
- if { [llength $::env(FP_PDN_MACROS)] > 0 } {
- # generate automatically per instance:
- foreach macro_instance $::env(FP_PDN_MACROS) {
- set macro_instance_grid [subst $macro]
- dict append $macro_instance_grid instance $macro_instance
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro_instance_grid]
- }
- } else {
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro]
- }
- # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
- # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
- # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
-} else {
- define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
-}
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
+
+define_pdn_grid \
+ -macro \
+ -default \
+ -name macro \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
+
+add_pdn_connect \
+ -grid macro \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index a5b2325..3c8cdc9 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc
@@ -16,7 +16,7 @@
create_clock -name usb_ref_clk -period 10.0000 [get_pins {u_usb_ref_clkbuf.u_buf/X}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 4b29f05..527f4cc 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -40,31 +40,31 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
- $script_dir/../../verilog/rtl/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/lib/async_wb.sv \
- $script_dir/../../verilog/rtl/lib/clk_ctl.v \
- $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/lib/registers.v \
- $script_dir/../../verilog/rtl/lib/reset_sync.sv \
- $script_dir/../../verilog/rtl/lib/async_reg_bus.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \
- $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \
- $script_dir/../../verilog/rtl/lib/double_sync_low.v \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart2wb.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart2_core.sv \
- $script_dir/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
- $script_dir/../../verilog/rtl/sspis/src/sspis_top.sv \
- $script_dir/../../verilog/rtl/sspis/src/sspis_if.sv \
- $script_dir/../../verilog/rtl/sspis/src/spi2wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_if.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/spi2wb.sv \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -102,7 +102,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index d815c04..d4e6271 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc
@@ -9,7 +9,7 @@
create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
#Clock Skew adjustment
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 55b38f4..c58574a 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -40,23 +40,23 @@
# Local sources + no2usb sources
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/lib/sync_wbb.sv \
- $script_dir/../../verilog/rtl/lib/sync_fifo2.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \
- $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\
- CH_DATA_WD 37 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\
+ CH_DATA_WD=37 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -88,7 +88,7 @@
set ::env(USE_ARC_ANTENNA_CHECK) "0"
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
## CTS
@@ -104,14 +104,17 @@
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2
## Routing
-set ::env(GLB_RT_ADJUSTMENT) 0
-set ::env(GLB_RT_L2_ADJUSTMENT) 0.21
-set ::env(GLB_RT_L3_ADJUSTMENT) 0.21
-set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
-set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
-set ::env(GLB_RT_ALLOW_CONGESTION) 0
-set ::env(GLB_RT_OVERFLOW_ITERS) 200
+set ::env(GRT_ADJUSTMENT) 0.1
+set ::env(DPL_CELL_PADDING) 1
+
+#set ::env(GLB_RT_ADJUSTMENT) 0
+#set ::env(GLB_RT_L2_ADJUSTMENT) 0.21
+#set ::env(GLB_RT_L3_ADJUSTMENT) 0.21
+#set ::env(GLB_RT_L4_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1
+#set ::env(GLB_RT_ALLOW_CONGESTION) 0
+#set ::env(GLB_RT_OVERFLOW_ITERS) 200
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index fe3302c..2d8237e 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -731,6 +731,7 @@
s2_wbd_stb_o 1600 0 2
s2_wbd_we_o
+s2_wbd_adr_o\[8\]
s2_wbd_adr_o\[7\]
s2_wbd_adr_o\[6\]
s2_wbd_adr_o\[5\]
diff --git a/openlane/ycr2_iconnect/base.sdc b/openlane/ycr2_iconnect/base.sdc
index a8461ed..4889e25 100644
--- a/openlane/ycr2_iconnect/base.sdc
+++ b/openlane/ycr2_iconnect/base.sdc
@@ -1,10 +1,10 @@
###############################################################################
# Timing Constraints
###############################################################################
-create_clock -name core_clk -period 8.0000 [get_ports {core_clk}]
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
@@ -13,10 +13,10 @@
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
#CORE-0 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
@@ -30,11 +30,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
#CORE-0 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
@@ -49,10 +49,10 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
#CORE-1 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
@@ -66,11 +66,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
#CORE-1 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl
index cf9debf..a8f0493 100644
--- a/openlane/ycr2_iconnect/config.tcl
+++ b/openlane/ycr2_iconnect/config.tcl
@@ -34,42 +34,50 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_router.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr2_router.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_tcm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_timer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_arb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 390 1100"
-#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
-#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) "14"
+set ::env(CELL_PAD) 2
+set ::env(GRT_ADJUSTMENT) {0.2}
+
+#set ::env(GLB_RT_ADJUSTMENT) {0.2}
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLB_OPTIMIZE_MIRRORING) {1}
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
+
### PDN
#set ::env(FP_PDN_CHECK_NODES) "0"
#set ::env(FP_PDN_HORIZONTAL_HALO) "10"
@@ -88,7 +96,7 @@
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index 32fd5d0..f804cf0 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -4,8 +4,8 @@
create_clock -name core_clk -period 10.0000 [get_ports {clk}]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
-set_clock_uncertainty -hold 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
@@ -14,28 +14,29 @@
#IMEM Constraints
set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
#DMEM Constraints
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
-set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
@@ -43,8 +44,9 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 70e8196..bc6ed3e 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -33,38 +33,38 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_core_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_scu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dmi.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_core_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_scu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/ycr_dmi.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -72,17 +72,19 @@
set ::env(GND_PIN) [list {vssd1}]
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 550 950 "
+set ::env(DIE_AREA) "0 0 540 950 "
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.43
set ::env(CELL_PAD) "4"
+## Routing
+set ::env(GRT_ADJUSTMENT) 0.2
+
#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg
index 8ec6301..e69de29 100644
--- a/openlane/ycr_core_top/macro_placement.cfg
+++ b/openlane/ycr_core_top/macro_placement.cfg
@@ -1,2 +0,0 @@
-u_icache.u_cmem_2kb 285.000 291.000 FS
-u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index 2774794..db8fbe6 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -11,7 +11,7 @@
create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
set_clock_transition 0.1500 [all_clocks]
-set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 2ef0b86..524afd3 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -34,27 +34,27 @@
set ::env(LEC_ENABLE) 0
set ::env(VERILOG_FILES) "\
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_intf.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv \
- $script_dir/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_intf.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/lib/async_fifo.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv \
"
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr2c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SDC_FILE) "$script_dir/base.sdc"
-set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(LEC_ENABLE) 0
@@ -62,12 +62,11 @@
set ::env(GND_PIN) [list {vssd1}]
## Floorplan
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 810 640 "
set ::env(CELL_PAD) "6"
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.37
set ::env(FP_IO_VEXTEND) {6}
@@ -75,7 +74,7 @@
set ::env(RT_MAX_LAYER) {met4}
#set ::env(GLB_RT_MAXLAYER) "5"
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/pinmux/OPENLANE_VERSION
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
new file mode 100644
index 0000000..d5588cd
--- /dev/null
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -0,0 +1 @@
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
new file mode 100644
index 0000000..e8e14ea
--- /dev/null
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -0,0 +1 @@
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index cf40e34..d5588cd 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 8120faaedf752714e65fb7ff91993a8e6630a664
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index 80c7664..d5588cd 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 22e7dc1..e8e14ea 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr2_iconnect/OPENLANE_VERSION b/signoff/ycr2_iconnect/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/ycr2_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr2_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr2_iconnect/PDK_SOURCES b/signoff/ycr2_iconnect/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr2_iconnect/PDK_SOURCES
+++ b/signoff/ycr2_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index 078e9d2..d5588cd 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
+openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index b08beb4..e8e14ea 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
+open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index 6b787ac..0593e3b 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -50,7 +50,7 @@
read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
- read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v
read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
@@ -150,7 +150,7 @@
read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef
read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef
read_spef -path mprj/u_riscv_top.i_core_top_1 $::env(USER_ROOT)/spef/ycr_core_top.spef
- read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
+ read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux_top.spef
read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef
read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 84ee8f8..141381b 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec user_cache_bypass user_gpio arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial user_spi_isp
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema user_mcore_test1 user_mcore_test2
all: ${PATTERNS}
for i in ${PATTERNS}; do \
diff --git a/verilog/dv/arduino_arrays/Makefile b/verilog/dv/arduino_arrays/Makefile
new file mode 100644
index 0000000..dad099c
--- /dev/null
+++ b/verilog/dv/arduino_arrays/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_arrays
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_arrays/arduino_arrays.ino b/verilog/dv/arduino_arrays/arduino_arrays.ino
new file mode 100644
index 0000000..dbbb4b4
--- /dev/null
+++ b/verilog/dv/arduino_arrays/arduino_arrays.ino
@@ -0,0 +1,56 @@
+/*
+ Arrays
+
+ Demonstrates the use of an array to hold pin numbers in order to iterate over
+ the pins in a sequence. Lights multiple LEDs in sequence, then in reverse.
+
+ Unlike the For Loop tutorial, where the pins have to be contiguous, here the
+ pins can be in any random order.
+
+ The circuit:
+ - LEDs from pins 2 through 7 to ground
+
+ created 2006
+ by David A. Mellis
+ modified 30 Aug 2011
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/Arrays
+*/
+
+int timer = 100; // The higher the number, the slower the timing.
+int ledPins[] = {
+ 2, 7, 4, 6, 5, 3
+}; // an array of pin numbers to which LEDs are attached
+int pinCount = 6; // the number of pins (i.e. the length of the array)
+
+void setup() {
+ // the array elements are numbered from 0 to (pinCount - 1).
+ // use a for loop to initialize each pin as an output:
+ for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+ pinMode(ledPins[thisPin], OUTPUT);
+ }
+}
+
+void loop() {
+ // loop from the lowest pin to the highest:
+ for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+ // turn the pin on:
+ digitalWrite(ledPins[thisPin], HIGH);
+ delay(timer);
+ // turn the pin off:
+ digitalWrite(ledPins[thisPin], LOW);
+
+ }
+
+ // loop from the highest pin to the lowest:
+ for (int thisPin = pinCount - 1; thisPin >= 0; thisPin--) {
+ // turn the pin on:
+ digitalWrite(ledPins[thisPin], HIGH);
+ delay(timer);
+ // turn the pin off:
+ digitalWrite(ledPins[thisPin], LOW);
+ }
+}
diff --git a/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp b/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp
new file mode 100644
index 0000000..ebcb90b
--- /dev/null
+++ b/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp
@@ -0,0 +1,63 @@
+#include <Arduino.h>
+/*
+ Arrays
+
+ Demonstrates the use of an array to hold pin numbers in order to iterate over
+ the pins in a sequence. Lights multiple LEDs in sequence, then in reverse.
+
+ Unlike the For Loop tutorial, where the pins have to be contiguous, here the
+ pins can be in any random order.
+
+ The circuit:
+ - LEDs from pins 2 through 7 to ground
+
+ created 2006
+ by David A. Mellis
+ modified 30 Aug 2011
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/Arrays
+*/
+
+int timer = 10; // In Milli Second - The higher the number, the slower the timing.
+int ledPins[] = {
+ 2, 7, 4, 6, 5, 3
+}; // an array of pin numbers to which LEDs are attached
+int pinCount = 6; // the number of pins (i.e. the length of the array)
+
+void setup();
+void loop();
+void setup() {
+ // the array elements are numbered from 0 to (pinCount - 1).
+ // use a for loop to initialize each pin as an output:
+ for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+ pinMode(ledPins[thisPin], OUTPUT);
+ }
+}
+
+void loop() {
+ // loop from the lowest pin to the highest:
+ for (int thisPin = 0; thisPin < pinCount; thisPin++) {
+ // turn the pin on:
+ digitalWrite(ledPins[thisPin], HIGH);
+ //delay(timer);
+ delayMicroseconds(timer);
+ // turn the pin off:
+ digitalWrite(ledPins[thisPin], LOW);
+ delayMicroseconds(timer);
+
+ }
+
+ // loop from the highest pin to the lowest:
+ for (int thisPin = pinCount - 1; thisPin >= 0; thisPin--) {
+ // turn the pin on:
+ digitalWrite(ledPins[thisPin], HIGH);
+ delayMicroseconds(timer);
+ // turn the pin off:
+ digitalWrite(ledPins[thisPin], LOW);
+ delayMicroseconds(timer);
+ }
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
similarity index 65%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_arrays/arduino_arrays_tb.v
index b43dcba..169337d 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -18,20 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the riscduino cores project ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core multi-core behaviour. ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><05.control><Arrays> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -65,7 +68,9 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "is62wvs1288.v"
+
+module arduino_arrays_tb;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -92,18 +97,48 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ reg flag ;
+
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR = 4'b1100; // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD = 2'b10;
+parameter P_QDDR = 2'b11;
+
+
integer d_risc_id;
+ integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
initial begin
clock = 0;
+ flag = 0;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -115,69 +150,125 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(3, arduino_arrays_tb);
+ //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.i_core_top_0);
+ //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_connect);
+ //$dumpvars(0, arduino_arrays_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_arrays_tb.u_top.u_pinmux);
end
`endif
- initial begin
+ /************* Port-D Mapping **********************************
+ * Arduino-No
+ * Pin-2 0 PD0/RXD[0] digital_io[1]
+ * Pin-3 1 PD1/TXD[0] digital_io[2]
+ * Pin-4 2 PD2/RXD[1]/INT0 digital_io[3]
+ * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[4]
+ * Pin-6 4 PD4/TXD[1] digital_io[5]
+ * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+ * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+ * Pin-13 7 PD7/A1N1 digital_io[10]/analog_io[3]
+ * ********************************************************/
- $value$plusargs("risc_core_id=%d", d_risc_id);
+ wire [7:0] port_d_in = { io_out[10],
+ io_out[9],
+ io_out[8],
+ io_out[5],
+ io_out[4],
+ io_out[3],
+ io_out[2],
+ io_out[1]
+ };
+
+
+ initial begin
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
+ $value$plusargs("risc_core_id=%d", d_risc_id);
// Remove Wb Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- repeat (2) @(posedge clock);
+ repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+
+ // Remove WB and SPI Reset and CORE under Reset
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+ // QSPI SRAM:CS#2 Switch to QSPI Mode
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ repeat (20000) @(posedge clock); // wait for Processor Get Ready
+ flag = 1;
+ fork
+ begin
+ // Refer C code,
+ // Wait for toggle in following sequency 2,7,4,6,5,3
+
+ portd_detect_pin_toggle(2);
+ portd_detect_pin_toggle(7);
+ portd_detect_pin_toggle(4);
+ portd_detect_pin_toggle(6);
+ portd_detect_pin_toggle(5);
+ portd_detect_pin_toggle(3);
+
+
+ // Wait for toggle in following sequency 3,5,6,4,7,2
+ portd_detect_pin_toggle(3);
+ portd_detect_pin_toggle(5);
+ portd_detect_pin_toggle(6);
+ portd_detect_pin_toggle(4);
+ portd_detect_pin_toggle(7);
+ portd_detect_pin_toggle(2);
+
+ test_fail = 0;
+ end
+ begin
+ repeat (30000) @(posedge clock); // wait for Processor Get Ready
+ test_fail = 1;
+ end
+ join_any
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
-
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ #100
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: Ardunio arrays (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: Ardunio arrays (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: Ardunio arrays (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: Ardunio arrays (RTL) Failed");
`endif
end
$display("###################################################");
@@ -257,7 +348,7 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
+ s25fl256s #(.mem_file_name("arduino_arrays.ino.hex"),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
@@ -273,7 +364,32 @@
);
+ wire spiram_csb = io_out[27];
+ is62wvs1288 #(.mem_file_name("none"))
+ u_sram (
+ // Data Inputs/Outputs
+ .io0 (flash_io0),
+ .io1 (flash_io1),
+ // Controls
+ .clk (flash_clk),
+ .csb (spiram_csb),
+ .io2 (flash_io2),
+ .io3 (flash_io3)
+ );
+
+//-------------------------------------
+
+// detect pin toggle
+task portd_detect_pin_toggle;
+input [7:0] pin_n;
+begin
+ wait(port_d_in[pin_n] == 1'b1);
+ wait(port_d_in[pin_n] == 1'b0);
+ $display("PORT-D Pin : %x Toggle Detected",pin_n);
+
+end
+endtask
task wb_user_core_write;
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
index 07a49d4..a2d7001 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp
@@ -1,5 +1,4 @@
#include <Arduino.h>
-#line 1 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
/*
ASCII table
@@ -21,11 +20,8 @@
https://www.arduino.cc/en/Tutorial/BuiltInExamples/ASCIITable
*/
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
void setup();
-#line 39 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
void loop();
-#line 22 "/tmp/.arduinoIDE-unsaved202265-51666-197w8ma.2pxu/ASCIITable/ASCIITable.ino"
// first visible ASCIIcharacter '!' is number 33:
int thisByte = 33;
void setup() {
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index af4e082..e6fa954 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -18,30 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><ASCIITable> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -188,14 +181,14 @@
initial begin
- uart_data_bit = 2'b11;
- uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
- uart_stick_parity = 0; // 1: force even parity
- uart_parity_en = 0; // parity enable
- uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
- tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
- uart_timeout = 2000;// wait time limit
- uart_fifo_enable = 0; // fifo mode disable
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
@@ -208,61 +201,59 @@
repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- if(d_risc_id == 0) begin
- $display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
- end else if(d_risc_id == 1) begin
- $display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
- end else if(d_risc_id == 2) begin
- $display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
- end else if(d_risc_id == 3) begin
- $display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
- end
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
- repeat (100) @(posedge clock); // wait for Processor Get Ready
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
- tb_uart.debug_mode = 0; // disable debug display
- tb_uart.uart_init;
- tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
- uart_stick_parity, uart_timeout, uart_divisor);
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
- repeat (45000) @(posedge clock); // wait for Processor Get Ready
- flag = 0;
+ repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
check_sum = 0;
-
-
- fork
- begin
- while(flag == 0)
- begin
- tb_uart.read_char(read_data,flag);
- if(flag == 0) begin
- $write ("%c",read_data);
- check_sum = check_sum+read_data;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
end
- end
- end
- begin
- repeat (3000000) @(posedge clock); // wait for Processor Get Ready
- end
- join_any
-
- #100
- tb_uart.report_status(uart_rx_nu, uart_tx_nu);
-
- test_fail = 0;
+ end
+ end
+ begin
+ repeat (3000000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
$display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
- // Check
- // if all the 4224 byte received
- // if no error
- if(uart_rx_nu != 4224) test_fail = 1;
- if(check_sum != 32'h3f01b) test_fail = 1;
- if(tb_uart.err_cnt != 0) test_fail = 1;
+ // Check
+ // if all the 4224 byte received
+ // if no error
+ if(uart_rx_nu != 4224) test_fail = 1;
+ if(check_sum != 32'h3f01b) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
$display("###################################################");
diff --git a/verilog/dv/arduino_character_analysis/Makefile b/verilog/dv/arduino_character_analysis/Makefile
new file mode 100644
index 0000000..9293db4
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_character_analysis
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino
new file mode 100644
index 0000000..e7a3c23
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino
@@ -0,0 +1,85 @@
+/*
+ Character analysis operators
+
+ Examples using the character analysis operators.
+ Send any byte and the sketch will tell you about it.
+
+ created 29 Nov 2010
+ modified 2 Apr 2012
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/CharacterAnalysis
+*/
+
+void setup() {
+ // Open serial communications and wait for port to open:
+ Serial.begin(9600);
+ while (!Serial) {
+ ; // wait for serial port to connect. Needed for native USB port only
+ }
+
+ // send an intro:
+ Serial.println("send any byte and I'll tell you everything I can about it");
+ Serial.println();
+}
+
+void loop() {
+ // get any incoming bytes:
+ if (Serial.available() > 0) {
+ int thisChar = Serial.read();
+
+ // say what was sent:
+ Serial.print("You sent me: \'");
+ Serial.write(thisChar);
+ Serial.print("\' ASCII Value: ");
+ Serial.println(thisChar);
+
+ // analyze what was sent:
+ if (isAlphaNumeric(thisChar)) {
+ Serial.println("it's alphanumeric");
+ }
+ if (isAlpha(thisChar)) {
+ Serial.println("it's alphabetic");
+ }
+ if (isAscii(thisChar)) {
+ Serial.println("it's ASCII");
+ }
+ if (isWhitespace(thisChar)) {
+ Serial.println("it's whitespace");
+ }
+ if (isControl(thisChar)) {
+ Serial.println("it's a control character");
+ }
+ if (isDigit(thisChar)) {
+ Serial.println("it's a numeric digit");
+ }
+ if (isGraph(thisChar)) {
+ Serial.println("it's a printable character that's not whitespace");
+ }
+ if (isLowerCase(thisChar)) {
+ Serial.println("it's lower case");
+ }
+ if (isPrintable(thisChar)) {
+ Serial.println("it's printable");
+ }
+ if (isPunct(thisChar)) {
+ Serial.println("it's punctuation");
+ }
+ if (isSpace(thisChar)) {
+ Serial.println("it's a space character");
+ }
+ if (isUpperCase(thisChar)) {
+ Serial.println("it's upper case");
+ }
+ if (isHexadecimalDigit(thisChar)) {
+ Serial.println("it's a valid hexadecimaldigit (i.e. 0 - 9, a - F, or A - F)");
+ }
+
+ // add some space and ask for another byte:
+ Serial.println();
+ Serial.println("Give me another byte:");
+ Serial.println();
+ }
+}
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp
new file mode 100644
index 0000000..ff39e85
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp
@@ -0,0 +1,89 @@
+#include <Arduino.h>
+/*
+ Character analysis operators
+
+ Examples using the character analysis operators.
+ Send any byte and the sketch will tell you about it.
+
+ created 29 Nov 2010
+ modified 2 Apr 2012
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/CharacterAnalysis
+*/
+
+void setup();
+void loop();
+void setup() {
+ // Open serial communications and wait for port to open:
+ Serial.begin(1152000);
+ while (!Serial) {
+ ; // wait for serial port to connect. Needed for native USB port only
+ }
+
+ // send an intro:
+ Serial.println("send any byte and I'll tell you everything I can about it");
+ Serial.println();
+}
+
+void loop() {
+ // get any incoming bytes:
+ if (Serial.available() > 0) {
+ int thisChar = Serial.read();
+
+ // say what was sent:
+ Serial.print("You sent me: \'");
+ Serial.write(thisChar);
+ Serial.print("\' ASCII Value: ");
+ Serial.println(thisChar);
+
+ // analyze what was sent:
+ if (isAlphaNumeric(thisChar)) {
+ Serial.println("it's alphanumeric");
+ }
+ if (isAlpha(thisChar)) {
+ Serial.println("it's alphabetic");
+ }
+ if (isAscii(thisChar)) {
+ Serial.println("it's ASCII");
+ }
+ if (isWhitespace(thisChar)) {
+ Serial.println("it's whitespace");
+ }
+ if (isControl(thisChar)) {
+ Serial.println("it's a control character");
+ }
+ if (isDigit(thisChar)) {
+ Serial.println("it's a numeric digit");
+ }
+ if (isGraph(thisChar)) {
+ Serial.println("it's a printable character that's not whitespace");
+ }
+ if (isLowerCase(thisChar)) {
+ Serial.println("it's lower case");
+ }
+ if (isPrintable(thisChar)) {
+ Serial.println("it's printable");
+ }
+ if (isPunct(thisChar)) {
+ Serial.println("it's punctuation");
+ }
+ if (isSpace(thisChar)) {
+ Serial.println("it's a space character");
+ }
+ if (isUpperCase(thisChar)) {
+ Serial.println("it's upper case");
+ }
+ if (isHexadecimalDigit(thisChar)) {
+ Serial.println("it's a valid hexadecimaldigit (i.e. 0 - 9, a - F, or A - F)");
+ }
+
+ // add some space and ask for another byte:
+ Serial.println();
+ Serial.println("Give me another byte:");
+ Serial.println();
+ }
+}
+
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
new file mode 100644
index 0000000..af8c31f
--- /dev/null
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -0,0 +1,571 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><08.strings><CharacterAnalysis> ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
+//// ////
+//// Revision : ////
+//// 0.1 - 29th July 2022, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "is62wvs1288.v"
+
+module arduino_character_analysis;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR = 4'b1100; // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD = 2'b10;
+parameter P_QDDR = 2'b11;
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, arduino_character_analysis);
+ $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_character_analysis.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_character_analysis.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ end
+ `endif
+
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
+ initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove WB and SPI Reset and CORE under Reset
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+ // QSPI SRAM:CS#2 Switch to QSPI Mode
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ repeat (40000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ fork
+ begin
+ fork
+ begin
+ tb_uart.write_char ("A");
+ tb_uart.write_char (" ");
+ tb_uart.write_char ("\n");
+ tb_uart.write_char ("b");
+ tb_uart.write_char (";");
+ tb_uart.write_char ("F");
+ end
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ join
+ end
+ begin
+ repeat (3000000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
+
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 4224 byte received
+ // if no error
+ if(uart_rx_nu != 1236) test_fail = 1;
+ if(check_sum != 32'h180b7) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: character_analysis (GL) Passed");
+ `else
+ $display("Monitor: character_analysis (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: character_analysis (GL) Failed");
+ `else
+ $display("Monitor: character_analysis (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("arduino_character_analysis.ino.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+ wire spiram_csb = io_out[27];
+
+ is62wvs1288 #(.mem_file_name("none"))
+ u_sram (
+ // Data Inputs/Outputs
+ .io0 (flash_io0),
+ .io1 (flash_io1),
+ // Controls
+ .clk (flash_clk),
+ .csb (spiram_csb),
+ .io2 (flash_io2),
+ .io3 (flash_io3)
+ );
+
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/arduino_digital_port_control/Makefile b/verilog/dv/arduino_digital_port_control/Makefile
new file mode 100644
index 0000000..7168229
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/Makefile
@@ -0,0 +1,142 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_digital_port_control
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/SPI/src ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/SPI/src ${RISCDUINO_BOARD}/libraries/SPI/src/SPI.cpp -o SPI.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a SPI.cpp.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino
new file mode 100644
index 0000000..c7afcc0
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino
@@ -0,0 +1,71 @@
+/*
+ Digital Pot Control
+
+ This example controls an Analog Devices AD5206 digital potentiometer.
+ The AD5206 has 6 potentiometer channels. Each channel's pins are labeled
+ A - connect this to voltage
+ W - this is the pot's wiper, which changes when you set it
+ B - connect this to ground.
+
+ The AD5206 is SPI-compatible,and to command it, you send two bytes,
+ one with the channel number (0 - 5) and one with the resistance value for the
+ channel (0 - 255).
+
+ The circuit:
+ * All A pins of AD5206 connected to +5V
+ * All B pins of AD5206 connected to ground
+ * An LED and a 220-ohm resisor in series connected from each W pin to ground
+ * CS - to digital pin 10 (SS pin)
+ * SDI - to digital pin 11 (MOSI pin)
+ * CLK - to digital pin 13 (SCK pin)
+
+ created 10 Aug 2010
+ by Tom Igoe
+
+ Thanks to Heather Dewey-Hagborg for the original tutorial, 2005
+
+*/
+
+
+// inslude the SPI library:
+#include <SPI.h>
+
+
+// set pin 10 as the slave select for the digital pot:
+const int slaveSelectPin = 10;
+
+void setup() {
+ // set the slaveSelectPin as an output:
+ pinMode(slaveSelectPin, OUTPUT);
+ // initialize SPI:
+ SPI.begin();
+}
+
+void loop() {
+ // go through the six channels of the digital pot:
+ for (int channel = 0; channel < 6; channel++) {
+ // change the resistance on this channel from min to max:
+ for (int level = 0; level < 255; level++) {
+ digitalPotWrite(channel, level);
+ delay(10);
+ }
+ // wait a second at the top:
+ delay(100);
+ // change the resistance on this channel from max to min:
+ for (int level = 0; level < 255; level++) {
+ digitalPotWrite(channel, 255 - level);
+ delay(10);
+ }
+ }
+
+}
+
+void digitalPotWrite(int address, int value) {
+ // take the SS pin low to select the chip:
+ digitalWrite(slaveSelectPin, LOW);
+ // send in the address and value via SPI:
+ SPI.transfer(address);
+ SPI.transfer(value);
+ // take the SS pin high to de-select the chip:
+ digitalWrite(slaveSelectPin, HIGH);
+}
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
new file mode 100644
index 0000000..d4dd6f5
--- /dev/null
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp
@@ -0,0 +1,76 @@
+#include <Arduino.h>
+/*
+ Digital Pot Control
+
+ This example controls an Analog Devices AD5206 digital potentiometer.
+ The AD5206 has 6 potentiometer channels. Each channel's pins are labeled
+ A - connect this to voltage
+ W - this is the pot's wiper, which changes when you set it
+ B - connect this to ground.
+
+ The AD5206 is SPI-compatible,and to command it, you send two bytes,
+ one with the channel number (0 - 5) and one with the resistance value for the
+ channel (0 - 255).
+
+ The circuit:
+ * All A pins of AD5206 connected to +5V
+ * All B pins of AD5206 connected to ground
+ * An LED and a 220-ohm resisor in series connected from each W pin to ground
+ * CS - to digital pin 10 (SS pin)
+ * SDI - to digital pin 11 (MOSI pin)
+ * CLK - to digital pin 13 (SCK pin)
+
+ created 10 Aug 2010
+ by Tom Igoe
+
+ Thanks to Heather Dewey-Hagborg for the original tutorial, 2005
+
+*/
+
+
+// inslude the SPI library:
+#include <SPI.h>
+
+
+// set pin 10 as the slave select for the digital pot:
+const int slaveSelectPin = 10;
+
+void setup();
+void loop();
+void digitalPotWrite(int address, int value);
+void setup() {
+ // set the slaveSelectPin as an output:
+ pinMode(slaveSelectPin, OUTPUT);
+ // initialize SPI:
+ SPI.begin();
+}
+
+void loop() {
+ // go through the six channels of the digital pot:
+ for (int channel = 0; channel < 6; channel++) {
+ // change the resistance on this channel from min to max:
+ for (int level = 0; level < 255; level++) {
+ digitalPotWrite(channel, level);
+ delayMicroseconds(10);
+ }
+ // wait a second at the top:
+ delayMicroseconds(100);
+ // change the resistance on this channel from max to min:
+ for (int level = 0; level < 255; level++) {
+ digitalPotWrite(channel, 255 - level);
+ delayMicroseconds(10);
+ }
+ }
+
+}
+
+void digitalPotWrite(int address, int value) {
+ // take the SS pin low to select the chip:
+ digitalWrite(slaveSelectPin, LOW);
+ // send in the address and value via SPI:
+ SPI.transfer(address);
+ SPI.transfer(value);
+ // take the SS pin high to de-select the chip:
+ digitalWrite(slaveSelectPin, HIGH);
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
similarity index 64%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index b43dcba..1b1cbe1 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -18,20 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the riscduino cores project ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core multi-core behaviour. ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><SPi><DigitalPortControl> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -65,7 +68,10 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "is62wvs1288.v"
+`include "bfm_ad5205.sv"
+
+module arduino_digital_port_control_tb;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -92,18 +98,49 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ reg flag ;
+
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR = 4'b1100; // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD = 2'b10;
+parameter P_QDDR = 2'b11;
+
+
integer d_risc_id;
+ integer channel,level;
+
+ integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
initial begin
clock = 0;
+ flag = 0;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -115,72 +152,100 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(3, arduino_digital_port_control_tb);
+ //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.i_core_top_0);
+ //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_connect);
+ //$dumpvars(0, arduino_digital_port_control_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_digital_port_control_tb.u_top.u_pinmux);
+ $dumpvars(0, arduino_digital_port_control_tb.u_top.u_uart_i2c_usb_spi);
end
`endif
- initial begin
+
- $value$plusargs("risc_core_id=%d", d_risc_id);
+ initial begin
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
+ $value$plusargs("risc_core_id=%d", d_risc_id);
// Remove Wb Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- repeat (2) @(posedge clock);
+ repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+
+ // Remove WB and SPI Reset and CORE under Reset
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+ // QSPI SRAM:CS#2 Switch to QSPI Mode
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ repeat (20000) @(posedge clock); // wait for Processor Get Ready
+ flag = 1;
+ fork
+ begin
+ for (channel = 0; channel < 1; channel = channel+1) begin
+ // change the resistance on this channel from min to max:
+ for (level = 0; level < 255; level = level+1) begin
+ wait(u_ad5205.channel == channel && u_ad5205.position == level);
+ $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
+ end
+ // change the resistance on this channel from min to max:
+ for (level = 0; level < 255; level = level+1) begin
+ wait((u_ad5205.channel == channel) && (u_ad5205.position == (255 -level)));
+ $display("Channel: %x and Position: %x",u_ad5205.channel,u_ad5205.position);
+ end
+ end
+ test_fail = 0;
+ end
+ begin
+ repeat (6000000) @(posedge clock); // wait for Processor Get Ready
+ test_fail = 1;
+ end
+ join_any
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ #100
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
-
-
- $display("###################################################");
- if(test_fail == 0) begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
- `endif
- end else begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
- `endif
- end
- $display("###################################################");
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Ardunio Digital Port Control (GL) Passed");
+ `else
+ $display("Monitor: Ardunio Digital Port Control (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Ardunio Digital Port Control (GL) Failed");
+ `else
+ $display("Monitor: Ardunio Digital Port Control (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
$finish;
end
@@ -227,6 +292,26 @@
);
+//-------------------------------------------------------------------------------------
+// Integrate the Serial SPI to ad5204/5206 (4-/6-Channel Digital Potentiometers)
+// https://www.analog.com/media/en/technical-documentation/data-sheets/ad5204_5206.pdf
+// -----------------------------------------------------------------------------------
+ wire sspi_sck = io_out[16];
+ wire sspi_sdi = io_out[15];
+ wire sspi_ssn = io_out[13];
+
+ wire [2:0] p_channel; // potentiometer channel
+ wire [7:0] p_position; // potentiometer position
+
+ bfm_ad5205 u_ad5205(
+ .sck (sspi_sck ),
+ .sdi (sspi_sdi ),
+ .ssn (sspi_ssn ),
+
+ .channel (p_channel ),
+ .position (p_position )
+ );
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
@@ -257,7 +342,7 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
+ s25fl256s #(.mem_file_name("arduino_digital_port_control.ino.hex"),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
@@ -273,6 +358,21 @@
);
+ wire spiram_csb = io_out[27];
+
+ is62wvs1288 #(.mem_file_name("none"))
+ u_sram (
+ // Data Inputs/Outputs
+ .io0 (flash_io0),
+ .io1 (flash_io1),
+ // Controls
+ .clk (flash_clk),
+ .csb (spiram_csb),
+ .io2 (flash_io2),
+ .io3 (flash_io3)
+ );
+
+//-------------------------------------
diff --git a/verilog/dv/arduino_hello_world/Makefile b/verilog/dv/arduino_hello_world/Makefile
index 3eed1a1..497a39e 100644
--- a/verilog/dv/arduino_hello_world/Makefile
+++ b/verilog/dv/arduino_hello_world/Makefile
@@ -52,6 +52,7 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 051b224..344e480 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -18,30 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -209,16 +202,16 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end else if(d_risc_id == 2) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
end else if(d_risc_id == 3) begin
$display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile
new file mode 100644
index 0000000..e6d5947
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -0,0 +1,142 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_i2c_scaner
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/Wire.cpp -o Wire.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard -I${RISCDUINO_BOARD}/libraries/Wire -I${RISCDUINO_BOARD}/libraries/Wire/utility ${RISCDUINO_BOARD}/libraries/Wire/utility/twi.c -o twi.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o Wire.cpp.o twi.c.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
new file mode 100644
index 0000000..295edf7
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino
@@ -0,0 +1,75 @@
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+// This program (or code that looks like it)
+// can be found in many places.
+// For example on the Arduino.cc forum.
+// The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+// Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26 2013
+// V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+// by Arduino.cc user Krodal.
+// Changes by louarnold removed.
+// Scanning addresses changed from 0...127 to 1...119,
+// according to the i2c scanner by Nick Gammon
+// https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+// As version 4, but address scans now to 127.
+// A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+// Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup() {
+ Wire.begin();
+
+ Serial.begin(9600);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+ int nDevices = 0;
+
+ Serial.println("Scanning...");
+
+ for (byte address = 1; address < 127; ++address) {
+ // The i2c_scanner uses the return value of
+ // the Wire.endTransmission to see if
+ // a device did acknowledge to the address.
+ Wire.beginTransmission(address);
+ byte error = Wire.endTransmission();
+
+ if (error == 0) {
+ Serial.print("I2C device found at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.print(address, HEX);
+ Serial.println(" !");
+
+ ++nDevices;
+ } else if (error == 4) {
+ Serial.print("Unknown error at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.println(address, HEX);
+ }
+ }
+ if (nDevices == 0) {
+ Serial.println("No I2C devices found\n");
+ } else {
+ Serial.println("done\n");
+ }
+ delay(5000); // Wait 5 seconds for next scan
+}
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
new file mode 100644
index 0000000..dc656cb
--- /dev/null
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp
@@ -0,0 +1,79 @@
+#include <Arduino.h>
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+// This program (or code that looks like it)
+// can be found in many places.
+// For example on the Arduino.cc forum.
+// The original author is not known.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+// Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26 2013
+// V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+// by Arduino.cc user Krodal.
+// Changes by louarnold removed.
+// Scanning addresses changed from 0...127 to 1...119,
+// according to the i2c scanner by Nick Gammon
+// https://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+// As version 4, but address scans now to 127.
+// A sensor seems to use address 120.
+// Version 6, November 27, 2015.
+// Added waiting for the Leonardo serial communication.
+//
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire.h>
+
+void setup();
+void loop();
+void setup() {
+ Wire.begin();
+
+ Serial.begin(1152000);
+ while (!Serial); // Leonardo: wait for Serial Monitor
+ Serial.println("\nI2C Scanner");
+}
+
+void loop() {
+ int nDevices = 0;
+
+ Serial.println("Scanning...");
+
+ for (byte address = 1; address < 127; ++address) {
+ // The i2c_scanner uses the return value of
+ // the Wire.endTransmission to see if
+ // a device did acknowledge to the address.
+ Wire.beginTransmission(address);
+ byte error = Wire.endTransmission();
+
+ if (error == 0) {
+ Serial.print("I2C device found at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.print(address, HEX);
+ Serial.println(" !");
+
+ ++nDevices;
+ } else if (error == 4) {
+ Serial.print("Unknown error at address 0x");
+ if (address < 16) {
+ Serial.print("0");
+ }
+ Serial.println(address, HEX);
+ }
+ }
+ if (nDevices == 0) {
+ Serial.println("No I2C devices found\n");
+ } else {
+ Serial.println("done\n");
+ }
+ delay(5000); // Wait 5 seconds for next scan
+}
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
similarity index 61%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index b43dcba..98948a9 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -18,20 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the riscduino cores project ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core multi-core behaviour. ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><Wire><i2c_scanner> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -65,7 +68,10 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+`include "i2c_slave_model.v"
+
+module arduino_i2c_scaner_tb;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -92,92 +98,182 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] check_sum ;
+
integer d_risc_id;
+ integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
initial begin
clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(3, arduino_i2c_scaner_tb);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ $dumpvars(0, arduino_i2c_scaner_tb.u_top.u_uart_i2c_usb_spi.u_i2cm);
end
`endif
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
#200; // Wait for reset removal
- repeat (10) @(posedge clock);
+ repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- repeat (2) @(posedge clock);
+ repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ end
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+ repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (200000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
-
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 102 byte received
+ // if no error
+ if(uart_rx_nu != 102) test_fail = 1;
+ if(check_sum != 32'h1fab) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: Standalone String (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: Standalone String (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: Standalone String (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: Standalone String (RTL) Failed");
`endif
end
$display("###################################################");
@@ -227,6 +323,25 @@
);
+//---------------------------
+// I2C
+// --------------------------
+tri scl,sda;
+
+assign sda = (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
+assign scl = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
+assign io_in[22] = sda;
+assign io_in[23] = scl;
+
+pullup p1(scl); // pullup scl line
+pullup p2(sda); // pullup sda line
+
+
+i2c_slave_model #(.I2C_ADR(7'h4)) u_i2c_slave (
+ .scl (scl),
+ .sda (sda)
+ );
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
@@ -257,8 +372,8 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
- .otp_file_name("none"),
+ s25fl256s #(.mem_file_name("arduino_i2c_scaner.ino.hex"),
+ .otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
// Data Inputs/Outputs
@@ -274,6 +389,19 @@
);
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
task wb_user_core_write;
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index f0cf862..6ad86a1 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -18,30 +18,24 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><MultiSerial> ////
+//// ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -213,16 +207,16 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end else if(d_risc_id == 2) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
end else if(d_risc_id == 3) begin
$display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
index ca5efa0..c663a26 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
@@ -1,34 +1,18 @@
#include <Arduino.h>
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
@@ -36,12 +20,12 @@
void loop();
void setup() {
// put your setup code here, to run once:
- reg_mprj_globl_reg22 = 0x11223344;
- reg_mprj_globl_reg23 = 0x22334455;
- reg_mprj_globl_reg24 = 0x33445566;
- reg_mprj_globl_reg25 = 0x44556677;
- reg_mprj_globl_reg26 = 0x55667788;
- reg_mprj_globl_reg27 = 0x66778899;
+ reg_mprj_globl_soft0 = 0x11223344;
+ reg_mprj_globl_soft1 = 0x22334455;
+ reg_mprj_globl_soft2 = 0x33445566;
+ reg_mprj_globl_soft3 = 0x44556677;
+ reg_mprj_globl_soft4 = 0x55667788;
+ reg_mprj_globl_soft5 = 0x66778899;
}
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index c435c40..0349606 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -18,30 +18,22 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the YIFive cores project ////
-//// https://github.com/dineshannayya/yifive_r0.git ////
-//// http://www.opencores.org/cores/yifive/ ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
//// Digital core. ////
-//// 1. User Risc core is booted using compiled code of ////
-//// user_risc_boot.c ////
-//// 2. User Risc core uses Serial Flash and SDRAM to boot ////
-//// 3. After successful boot, Risc core will write signature ////
-//// in to user register from 0x1003_0058 to 0x1003_006C ////
-//// 4. Through the External Wishbone Interface we read back ////
-//// from 0x3003_0058 to 0x3003_006C ////
-//// and validate the user register to declared pass fail ////
+//// This test bench to valid Arduino example: ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -145,10 +137,10 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
@@ -170,12 +162,12 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
diff --git a/verilog/dv/arduino_string/Makefile b/verilog/dv/arduino_string/Makefile
new file mode 100644
index 0000000..78fc16e
--- /dev/null
+++ b/verilog/dv/arduino_string/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_string
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_string/arduino_string.ino b/verilog/dv/arduino_string/arduino_string.ino
new file mode 100644
index 0000000..3a4ea08
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino
@@ -0,0 +1,28 @@
+void setup() {
+ String my_str = "This is my string.";
+
+ Serial.begin(9600);
+
+ // (1) print the string
+ Serial.println(my_str);
+
+ // (2) change the string to upper-case
+ my_str.toUpperCase();
+ Serial.println(my_str);
+
+ // (3) overwrite the string
+ my_str = "My new string.";
+ Serial.println(my_str);
+
+ // (4) replace a word in the string
+ my_str.replace("string", "Arduino sketch");
+ Serial.println(my_str);
+
+ // (5) get the length of the string
+ Serial.print("String length is: ");
+ Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
diff --git a/verilog/dv/arduino_string/arduino_string.ino.cpp b/verilog/dv/arduino_string/arduino_string.ino.cpp
new file mode 100644
index 0000000..6cdd523
--- /dev/null
+++ b/verilog/dv/arduino_string/arduino_string.ino.cpp
@@ -0,0 +1,32 @@
+#include <Arduino.h>
+void setup();
+void loop();
+void setup() {
+ String my_str = "This is my string.";
+
+ Serial.begin(1152000);
+
+ // (1) print the string
+ Serial.println(my_str);
+
+ // (2) change the string to upper-case
+ my_str.toUpperCase();
+ Serial.println(my_str);
+
+ // (3) overwrite the string
+ my_str = "My new string.";
+ Serial.println(my_str);
+
+ // (4) replace a word in the string
+ my_str.replace("string", "Arduino sketch");
+ Serial.println(my_str);
+
+ // (5) get the length of the string
+ Serial.print("String length is: ");
+ Serial.println(my_str.length());
+}
+
+void loop() {
+}
+
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
similarity index 63%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/arduino_string/arduino_string_tb.v
index b43dcba..1bd4b91 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -18,20 +18,23 @@
//// ////
//// Standalone User validation Test bench ////
//// ////
-//// This file is part of the riscduino cores project ////
+//// This file is part of the riscdunio cores project ////
+//// https://github.com/dineshannayya/riscdunio.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core multi-core behaviour. ////
+//// Digital core. ////
+//// This test bench to valid Arduino example: ////
+//// <example><04.Communication><String> ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
+//// - Dinesh Annayya, dinesh.annayya@gmail.com ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 29th July 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -65,7 +68,9 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+
+module arduino_string_tb;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -92,92 +97,181 @@
wire [7:0] mprj_io_0;
reg test_fail;
reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+ reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
+
+ reg [31:0] check_sum ;
+
integer d_risc_id;
+ integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
initial begin
clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
+ flag = 0;
+ compare_start = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(3, arduino_string_tb);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_string_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_string_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
end
`endif
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 20000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
#200; // Wait for reset removal
- repeat (10) @(posedge clock);
+ repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- repeat (2) @(posedge clock);
+ repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+ repeat (60000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
+ compare_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (200000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+ test_fail = 0;
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
-
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 102 byte received
+ // if no error
+ if(uart_rx_nu != 102) test_fail = 1;
+ if(check_sum != 32'h1fab) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: Standalone String (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: Standalone String (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: Standalone String (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: Standalone String (RTL) Failed");
`endif
end
$display("###################################################");
@@ -257,8 +351,8 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
- .otp_file_name("none"),
+ s25fl256s #(.mem_file_name("arduino_string.ino.hex"),
+ .otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
// Data Inputs/Outputs
@@ -274,6 +368,19 @@
);
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
task wb_user_core_write;
diff --git a/verilog/dv/arduino_switchCase2/Makefile b/verilog/dv/arduino_switchCase2/Makefile
new file mode 100644
index 0000000..2533931
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/Makefile
@@ -0,0 +1,140 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = arduino_switchCase2
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${PATTERN}.ino.cpp -o ${PATTERN}.ino.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/Print.cpp -o Print.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WMath.cpp -o WMath.cpp.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WString.cpp -o WString.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/WInterrupts.c -o WInterrupts.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/fe300prci/fe300prci_driver.c -o fe300prci_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/abi.cpp -o abi.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/drivers/plic/plic_driver.c -o plic_driver.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/UARTClass.cpp -o UARTClass.cpp.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/entry.S -o entry.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/hooks.c -o hooks.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/init.S -o init.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/itoa.c -o itoa.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/main.cpp -o main.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/malloc.c -o malloc.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/new.cpp -o new.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/sbrk.c -o sbrk.c.o
+ ${GCC_PREFIX}-gcc -c -march=rv32imac -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/start.S -o start.S.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring.c -o wiring.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_analog.c -o wiring_analog.c.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_digital.c -o wiring_digital.c.o
+ ${GCC_PREFIX}-g++ -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -fpermissive -Wall -fno-rtti -fno-exceptions -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_pulse.cpp -o wiring_pulse.cpp.o
+ ${GCC_PREFIX}-gcc -c -O2 -march=rv32imac -fpeel-loops -ffreestanding -ffunction-sections -fdata-sections -Wall -I${RISCDUINO_BOARD}/system/include -I${RISCDUINO_BOARD}/sdk/bsp/include -I${RISCDUINO_BOARD}/sdk/bsp/env -I${RISCDUINO_BOARD}/sdk/bsp/drivers -I${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score -include sys/cdefs.h -g -DARDUINO=10607 -DF_CPU=50000000LL -DRISCDUINO_SCORE_DEVKIT -I${RISCDUINO_BOARD}/cores/arduino -I${RISCDUINO_BOARD}/variants/standard ${RISCDUINO_BOARD}/cores/arduino/wiring_shift.c -o wiring_shift.c.o
+ ${GCC_PREFIX}-ar rcs core.a Print.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a UARTClass.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WInterrupts.c.o
+ ${GCC_PREFIX}-ar rcs core.a WMath.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a WString.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a abi.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a fe300prci_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a plic_driver.c.o
+ ${GCC_PREFIX}-ar rcs core.a entry.S.o
+ ${GCC_PREFIX}-ar rcs core.a hooks.c.o
+ ${GCC_PREFIX}-ar rcs core.a init.S.o
+ ${GCC_PREFIX}-ar rcs core.a itoa.c.o
+ ${GCC_PREFIX}-ar rcs core.a main.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a malloc.c.o
+ ${GCC_PREFIX}-ar rcs core.a new.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a sbrk.c.o
+ ${GCC_PREFIX}-ar rcs core.a start.S.o
+ ${GCC_PREFIX}-ar rcs core.a wiring.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_analog.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_digital.c.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_pulse.cpp.o
+ ${GCC_PREFIX}-ar rcs core.a wiring_shift.c.o
+ ${GCC_PREFIX}-g++ -T ${RISCDUINO_BOARD}/sdk/bsp/env/riscduino_score/link.lds -nostartfiles -Wl,-N -Wl,--gc-sections -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=sbrk ${PATTERN}.ino.cpp.o -nostdlib -Wl,--start-group core.a -lm -lstdc++ -lc -lgloss -Wl,--end-group -lgcc -o ${PATTERN}.ino.elf
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O binary ${PATTERN}.ino.elf ${PATTERN}.ino.bin
+ ${GCC_PREFIX}-objcopy -R .rel.dyn -O verilog ${PATTERN}.ino.elf ${PATTERN}.ino.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.ino.elf > ${PATTERN}.ino.dump
+ rm *.o *.a
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.a *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino
new file mode 100644
index 0000000..48cbaa4
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino
@@ -0,0 +1,65 @@
+/*
+ Switch statement with serial input
+
+ Demonstrates the use of a switch statement. The switch statement allows you
+ to choose from among a set of discrete values of a variable. It's like a
+ series of if statements.
+
+ To see this sketch in action, open the Serial monitor and send any character.
+ The characters a, b, c, d, and e, will turn on LEDs. Any other character will
+ turn the LEDs off.
+
+ The circuit:
+ - five LEDs attached to digital pins 2 through 6 through 220 ohm resistors
+
+ created 1 Jul 2009
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/SwitchCase2
+*/
+
+void setup() {
+ // initialize serial communication:
+ Serial.begin(9600);
+ // initialize the LED pins:
+ for (int thisPin = 2; thisPin < 7; thisPin++) {
+ pinMode(thisPin, OUTPUT);
+ }
+}
+
+void loop() {
+ // read the sensor:
+ if (Serial.available() > 0) {
+ int inByte = Serial.read();
+ // do something different depending on the character received.
+ // The switch statement expects single number values for each case; in this
+ // example, though, you're using single quotes to tell the controller to get
+ // the ASCII value for the character. For example 'a' = 97, 'b' = 98,
+ // and so forth:
+
+ switch (inByte) {
+ case 'a':
+ digitalWrite(2, HIGH);
+ break;
+ case 'b':
+ digitalWrite(3, HIGH);
+ break;
+ case 'c':
+ digitalWrite(4, HIGH);
+ break;
+ case 'd':
+ digitalWrite(5, HIGH);
+ break;
+ case 'e':
+ digitalWrite(6, HIGH);
+ break;
+ default:
+ // turn all the LEDs off:
+ for (int thisPin = 2; thisPin < 7; thisPin++) {
+ digitalWrite(thisPin, LOW);
+ }
+ }
+ }
+}
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp
new file mode 100644
index 0000000..e6c0924
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp
@@ -0,0 +1,69 @@
+#include <Arduino.h>
+/*
+ Switch statement with serial input
+
+ Demonstrates the use of a switch statement. The switch statement allows you
+ to choose from among a set of discrete values of a variable. It's like a
+ series of if statements.
+
+ To see this sketch in action, open the Serial monitor and send any character.
+ The characters a, b, c, d, and e, will turn on LEDs. Any other character will
+ turn the LEDs off.
+
+ The circuit:
+ - five LEDs attached to digital pins 2 through 6 through 220 ohm resistors
+
+ created 1 Jul 2009
+ by Tom Igoe
+
+ This example code is in the public domain.
+
+ https://www.arduino.cc/en/Tutorial/BuiltInExamples/SwitchCase2
+*/
+
+void setup();
+void loop();
+void setup() {
+ // initialize serial communication:
+ Serial.begin(1152000);
+ // initialize the LED pins:
+ for (int thisPin = 2; thisPin < 7; thisPin++) {
+ pinMode(thisPin, OUTPUT);
+ }
+}
+
+void loop() {
+ // read the sensor:
+ if (Serial.available() > 0) {
+ int inByte = Serial.read();
+ // do something different depending on the character received.
+ // The switch statement expects single number values for each case; in this
+ // example, though, you're using single quotes to tell the controller to get
+ // the ASCII value for the character. For example 'a' = 97, 'b' = 98,
+ // and so forth:
+
+ switch (inByte) {
+ case 'a':
+ digitalWrite(2, HIGH);
+ break;
+ case 'b':
+ digitalWrite(3, HIGH);
+ break;
+ case 'c':
+ digitalWrite(4, HIGH);
+ break;
+ case 'd':
+ digitalWrite(5, HIGH);
+ break;
+ case 'e':
+ digitalWrite(6, HIGH);
+ break;
+ default:
+ // turn all the LEDs off:
+ for (int thisPin = 2; thisPin < 7; thisPin++) {
+ digitalWrite(thisPin, LOW);
+ }
+ }
+ }
+}
+
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
new file mode 100644
index 0000000..c3e9ffb
--- /dev/null
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -0,0 +1,587 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Standalone User validation Test bench ////
+//// ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description ////
+//// This is a standalone test bench to validate the ////
+//// Digital core. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+`include "is62wvs1288.v"
+
+module arduino_switchCase2_tb;
+ reg clock;
+ reg wb_rst_i;
+ reg power1, power2;
+ reg power3, power4;
+
+ reg wbd_ext_cyc_i; // strobe/request
+ reg wbd_ext_stb_i; // strobe/request
+ reg [31:0] wbd_ext_adr_i; // address
+ reg wbd_ext_we_i; // write
+ reg [31:0] wbd_ext_dat_i; // data output
+ reg [3:0] wbd_ext_sel_i; // byte enable
+
+ wire [31:0] wbd_ext_dat_o; // data input
+ wire wbd_ext_ack_o; // acknowlegement
+ wire wbd_ext_err_o; // error
+
+ // User I/O
+ wire [37:0] io_oeb;
+ wire [37:0] io_out;
+ wire [37:0] io_in;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [7:0] mprj_io_0;
+ reg test_fail;
+ reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+
+ reg [31:0] check_sum ;
+
+ integer d_risc_id;
+
+ integer i,j;
+
+parameter P_FSM_C = 4'b0000; // Command Phase Only
+parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
+parameter P_FSM_CA = 4'b0010; // Command -> Address Phase Only
+
+parameter P_FSM_CAR = 4'b0011; // Command -> Address -> Read Data
+parameter P_FSM_CADR = 4'b0100; // Command -> Address -> Dummy -> Read Data
+parameter P_FSM_CAMR = 4'b0101; // Command -> Address -> Mode -> Read Data
+parameter P_FSM_CAMDR = 4'b0110; // Command -> Address -> Mode -> Dummy -> Read Data
+
+parameter P_FSM_CAW = 4'b0111; // Command -> Address ->Write Data
+parameter P_FSM_CADW = 4'b1000; // Command -> Address -> DUMMY + Write Data
+parameter P_FSM_CAMW = 4'b1001; // Command -> Address -> MODE + Write Data
+
+parameter P_FSM_CDR = 4'b1010; // COMMAND -> DUMMY -> READ
+parameter P_FSM_CDW = 4'b1011; // COMMAND -> DUMMY -> WRITE
+parameter P_FSM_CR = 4'b1100; // COMMAND -> READ
+
+parameter P_MODE_SWITCH_IDLE = 2'b00;
+parameter P_MODE_SWITCH_AT_ADDR = 2'b01;
+parameter P_MODE_SWITCH_AT_DATA = 2'b10;
+
+parameter P_SINGLE = 2'b00;
+parameter P_DOUBLE = 2'b01;
+parameter P_QUAD = 2'b10;
+parameter P_QDDR = 2'b11;
+
+
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ flag = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ end
+
+ `ifdef WFDUMP
+ initial begin
+ $dumpfile("simx.vcd");
+ $dumpvars(3, arduino_switchCase2_tb);
+ $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.i_core_top_0);
+ $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_connect);
+ $dumpvars(0, arduino_switchCase2_tb.u_top.u_riscv_top.u_intf);
+ $dumpvars(0, arduino_switchCase2_tb.u_top.u_uart_i2c_usb_spi.u_uart0_core);
+ end
+ `endif
+
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
+ /************* Port-D Mapping **********************************
+ * Arduino-No
+ * Pin-2 0 PD0/RXD[0] digital_io[1]
+ * Pin-3 1 PD1/TXD[0] digital_io[2]
+ * Pin-4 2 PD2/RXD[1]/INT0 digital_io[3]
+ * Pin-5 3 PD3/INT1/OC2B(PWM0) digital_io[4]
+ * Pin-6 4 PD4/TXD[1] digital_io[5]
+ * Pin-11 5 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8]
+ * Pin-12 6 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
+ * Pin-13 7 PD7/A1N1 digital_io[10]/analog_io[3]
+ * ********************************************************/
+
+ wire [7:0] port_d_in = { io_out[10],
+ io_out[9],
+ io_out[8],
+ io_out[5],
+ io_out[4],
+ io_out[3],
+ io_out[2],
+ io_out[1]
+ };
+ initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
+
+ $value$plusargs("risc_core_id=%d", d_risc_id);
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Risc Boot Test Started");
+
+ // Remove Wb Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ repeat (2) @(posedge clock);
+ #1;
+ // Remove WB and SPI Reset, Keep SDARM and CORE under Reset
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+
+ // QSPI SRAM:CS#2 Switch to QSPI Mode
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+ wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
+
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ uart_stick_parity, uart_timeout, uart_divisor);
+
+ repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ flag = 1;
+ check_sum = 0;
+ fork
+ begin
+ fork
+ begin
+ tb_uart.write_char ("a");
+ tb_uart.write_char ("b");
+ tb_uart.write_char ("c");
+ tb_uart.write_char ("d");
+ tb_uart.write_char ("e");
+ end
+ begin
+ wait(port_d_in[2] == 1'b1);
+ $display("PORT-D Pin-2 High Detected");
+ wait(port_d_in[3] == 1'b1);
+ $display("PORT-D Pin-3 High Detected");
+ wait(port_d_in[4] == 1'b1);
+ $display("PORT-D Pin-4 High Detected");
+ wait(port_d_in[5] == 1'b1);
+ $display("PORT-D Pin-5 High Detected");
+ wait(port_d_in[6] == 1'b1);
+ $display("PORT-D Pin-6 High Detected");
+ test_fail =0;
+ end
+ join
+ end
+ begin
+ repeat (3000000) @(posedge clock); // wait for Processor Get Ready
+ test_fail =1;
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: arduino_switchCase2 (GL) Passed");
+ `else
+ $display("Monitor: arduino_switchCase2 (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: arduino_switchCase2 (GL) Failed");
+ `else
+ $display("Monitor: arduino_switchCase2 (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ $finish;
+ end
+
+ initial begin
+ wb_rst_i <= 1'b1;
+ #100;
+ wb_rst_i <= 1'b0; // Release reset
+ end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (1'b1), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in ('1) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+ // All standard cell need power hook-up for functionality work
+ initial begin
+
+ end
+`endif
+
+//------------------------------------------------------
+// Integrate the Serial flash with qurd support to
+// user core using the gpio pads
+// ----------------------------------------------------
+
+ wire flash_clk = io_out[24];
+ wire flash_csb = io_out[25];
+ // Creating Pad Delay
+ wire #1 io_oeb_29 = io_oeb[29];
+ wire #1 io_oeb_30 = io_oeb[30];
+ wire #1 io_oeb_31 = io_oeb[31];
+ wire #1 io_oeb_32 = io_oeb[32];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+ assign io_in[29] = flash_io0;
+ assign io_in[30] = flash_io1;
+ assign io_in[31] = flash_io2;
+ assign io_in[32] = flash_io3;
+
+ // Quard flash
+ s25fl256s #(.mem_file_name("arduino_switchCase2.ino.hex"),
+ .otp_file_name("none"),
+ .TimingModel("S25FL512SAGMFI010_F_30pF"))
+ u_spi_flash_256mb (
+ // Data Inputs/Outputs
+ .SI (flash_io0),
+ .SO (flash_io1),
+ // Controls
+ .SCK (flash_clk),
+ .CSNeg (flash_csb),
+ .WPNeg (flash_io2),
+ .HOLDNeg (flash_io3),
+ .RSTNeg (!wb_rst_i)
+
+ );
+
+
+ wire spiram_csb = io_out[27];
+
+ is62wvs1288 #(.mem_file_name("none"))
+ u_sram (
+ // Data Inputs/Outputs
+ .io0 (flash_io0),
+ .io1 (flash_io1),
+ // Controls
+ .clk (flash_clk),
+ .csb (spiram_csb),
+ .io2 (flash_io2),
+ .io3 (flash_io3)
+ );
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
+wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
+wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
+
+wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/bfm/bfm_ad5205.sv b/verilog/dv/bfm/bfm_ad5205.sv
new file mode 100644
index 0000000..d2ea131
--- /dev/null
+++ b/verilog/dv/bfm/bfm_ad5205.sv
@@ -0,0 +1,28 @@
+module bfm_ad5205 (
+ input logic sck ,
+ input logic sdi ,
+ input logic ssn ,
+
+ output logic [2:0] channel ,
+ output logic [7:0] position
+ );
+
+
+logic [10:0] shift_reg;
+logic [10:0] load_reg;
+
+
+always @(posedge ssn)
+ load_reg = shift_reg;
+
+
+always @(posedge sck)
+ shift_reg = {shift_reg[9:0],sdi};
+
+
+assign channel = load_reg[10:8];
+assign position = load_reg[7:0];
+
+
+endmodule
+
diff --git a/verilog/dv/c_func/inc/ext_reg_map.h b/verilog/dv/c_func/inc/ext_reg_map.h
new file mode 100644
index 0000000..cdb04f3
--- /dev/null
+++ b/verilog/dv/c_func/inc/ext_reg_map.h
@@ -0,0 +1,83 @@
+//--------------------------------------------------------------------
+// Register Address Map As Seen By the External/Caravel RISCV Core
+//--------------------------------------------------------------------
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_glbl_chip_id (*(volatile uint32_t*)0x30020000) // reg_0 - Chip ID
+#define reg_glbl_cfg0 (*(volatile uint32_t*)0x30020004) // reg_1 - Global Config-0
+#define reg_glbl_cfg1 (*(volatile uint32_t*)0x30020008) // reg_2 - Global Config-1
+#define reg_glbl_intr_msk (*(volatile uint32_t*)0x3002000C) // reg_3 - Global Interrupt Mask
+#define reg_glbl_intr (*(volatile uint32_t*)0x30020010) // reg_4 - Global Interrupt
+#define reg_glbl_multi_func (*(volatile uint32_t*)0x30020014) // reg_5 - GPIO Multi Function
+#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x30020018) // reg_6 - Soft Register-0
+#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x3002001C) // reg_7 - Sof Register-1
+#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x30020020) // reg_8 - Sof Register-2
+#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x30020024) // reg_9 - Sof Register-3
+#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x30020028) // reg_10 - Sof Register-4
+#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x3002002C) // reg_11 - Sof Register-5
+
+#define reg_gpio_dsel (*(volatile uint32_t*)0x30020040) // reg_0 - GPIO Direction Select
+#define reg_gpio_type (*(volatile uint32_t*)0x30020044) // reg_1 - GPIO TYPE - Static/Waveform
+#define reg_gpio_idata (*(volatile uint32_t*)0x30020048) // reg_2 - GPIO Data In
+#define reg_gpio_odata (*(volatile uint32_t*)0x3002004C) // reg_3 - GPIO Data Out
+#define reg_gpio_intr_stat (*(volatile uint32_t*)0x30020050) // reg_4 - GPIO Interrupt status
+#define reg_gpio_intr_clr (*(volatile uint32_t*)0x30020050) // reg_5 - GPIO Interrupt Clear
+#define reg_gpio_intr_set (*(volatile uint32_t*)0x30020054) // reg_6 - GPIO Interrupt Set
+#define reg_gpio_intr_mask (*(volatile uint32_t*)0x30020058) // reg_7 - GPIO Interrupt Mask
+#define reg_gpio_pos_intr (*(volatile uint32_t*)0x3002005C) // reg_8 - GPIO Posedge Interrupt
+#define reg_gpio_neg_intr (*(volatile uint32_t*)0x30020060) // reg_9 - GPIO Neg Interrupt
+
+#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x30020080) // reg_0 - PWM Reg-0
+#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x30020084) // reg_1 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x30020088) // reg_2 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x3002008C) // reg_3 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x30020090) // reg_4 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x30020094) // reg_5 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x30020098) // reg_6 - PWM Reg-5
+
+#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x300200C0) // reg_0 - Global config
+#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x300200C4) // reg_1 - Timer-0
+#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x300200C8) // reg_2 - Timer-1
+#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x300200CC) // reg_3 - Timer-2
+
+#define reg_sema_lock0 (*(volatile uint32_t*)0x30020100) // reg_0 - Hardware Lock-0
+#define reg_sema_lock1 (*(volatile uint32_t*)0x30020104) // reg_1 - Hardware Lock-1
+#define reg_sema_lock2 (*(volatile uint32_t*)0x30020108) // reg_2 - Hardware Lock-2
+#define reg_sema_lock3 (*(volatile uint32_t*)0x3002010C) // reg_3 - Hardware Lock-3
+#define reg_sema_lock4 (*(volatile uint32_t*)0x30020110) // reg_4 - Hardware Lock-4
+#define reg_sema_lock5 (*(volatile uint32_t*)0x30020114) // reg_5 - Hardware Lock-5
+#define reg_sema_lock6 (*(volatile uint32_t*)0x30020118) // reg_6 - Hardware Lock-6
+#define reg_sema_lock7 (*(volatile uint32_t*)0x3002011C) // reg_7 - Hardware Lock-7
+#define reg_sema_lock8 (*(volatile uint32_t*)0x30020120) // reg_8 - Hardware Lock-8
+#define reg_sema_lock9 (*(volatile uint32_t*)0x30020124) // reg_9 - Hardware Lock-9
+#define reg_sema_lock10 (*(volatile uint32_t*)0x30020128) // reg_10 - Hardware Lock-10
+#define reg_sema_lock11 (*(volatile uint32_t*)0x3002012C) // reg_11 - Hardware Lock-11
+#define reg_sema_lock12 (*(volatile uint32_t*)0x30020130) // reg_12 - Hardware Lock-12
+#define reg_sema_lock13 (*(volatile uint32_t*)0x30020134) // reg_13 - Hardware Lock-13
+#define reg_sema_lock14 (*(volatile uint32_t*)0x30020138) // reg_14 - Hardware Lock-14
+#define reg_sema_lock_cfg (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock config
+#define reg_sema_lock_stat (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock Status
+
+
+#define reg_uart0_ctrl (*(volatile uint32_t*)0x30010000) // Reg-0
+#define reg_uart0_intr_stat (*(volatile uint32_t*)0x30010004) // Reg-1
+#define reg_uart0_baud_ctrl1 (*(volatile uint32_t*)0x30010008) // Reg-2
+#define reg_uart0_baud_ctrl2 (*(volatile uint32_t*)0x3001000C) // Reg-3
+#define reg_uart0_status (*(volatile uint32_t*)0x30010010) // Reg-4
+#define reg_uart0_txdata (*(volatile uint32_t*)0x30010014) // Reg-5
+#define reg_uart0_rxdata (*(volatile uint32_t*)0x30010018) // Reg-6
+#define reg_uart0_txfifo_stat (*(volatile uint32_t*)0x3001001C) // Reg-7
+#define reg_uart0_rxfifo_stat (*(volatile uint32_t*)0x30010020) // Reg-8
+
+#define reg_uart1_ctrl (*(volatile uint32_t*)0x30010100) // Reg-0
+#define reg_uart1_intr_stat (*(volatile uint32_t*)0x30010104) // Reg-1
+#define reg_uart1_baud_ctrl1 (*(volatile uint32_t*)0x30010108) // Reg-2
+#define reg_uart1_baud_ctrl2 (*(volatile uint32_t*)0x3001010C) // Reg-3
+#define reg_uart1_status (*(volatile uint32_t*)0x30010110) // Reg-4
+#define reg_uart1_txdata (*(volatile uint32_t*)0x30010114) // Reg-5
+#define reg_uart1_rxdata (*(volatile uint32_t*)0x30010118) // Reg-6
+#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x3001011C) // Reg-7
+#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x30010120) // Reg-8
+
diff --git a/verilog/dv/c_func/inc/int_reg_map.h b/verilog/dv/c_func/inc/int_reg_map.h
new file mode 100644
index 0000000..669499d
--- /dev/null
+++ b/verilog/dv/c_func/inc/int_reg_map.h
@@ -0,0 +1,83 @@
+//--------------------------------------------------------------------
+// Register Address Map As Seen By the Internal RISCV Core
+//--------------------------------------------------------------------
+
+//-------------------------------------
+// PinMux Register
+// ------------------------------------
+#define reg_glbl_chip_id (*(volatile uint32_t*)0x10020000) // reg_0 - Chip ID
+#define reg_glbl_cfg0 (*(volatile uint32_t*)0x10020004) // reg_1 - Global Config-0
+#define reg_glbl_cfg1 (*(volatile uint32_t*)0x10020008) // reg_2 - Global Config-1
+#define reg_glbl_intr_msk (*(volatile uint32_t*)0x1002000C) // reg_3 - Global Interrupt Mask
+#define reg_glbl_intr (*(volatile uint32_t*)0x10020010) // reg_4 - Global Interrupt
+#define reg_glbl_multi_func (*(volatile uint32_t*)0x10020014) // reg_5 - GPIO Multi Function
+#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x10020018) // reg_6 - Soft Register-0
+#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x1002001C) // reg_7 - Sof Register-1
+#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x10020020) // reg_8 - Sof Register-2
+#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x10020024) // reg_9 - Sof Register-3
+#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x10020028) // reg_10 - Sof Register-4
+#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x1002002C) // reg_11 - Sof Register-5
+
+#define reg_gpio_dsel (*(volatile uint32_t*)0x10020040) // reg_0 - GPIO Direction Select
+#define reg_gpio_type (*(volatile uint32_t*)0x10020044) // reg_1 - GPIO TYPE - Static/Waveform
+#define reg_gpio_idata (*(volatile uint32_t*)0x10020048) // reg_2 - GPIO Data In
+#define reg_gpio_odata (*(volatile uint32_t*)0x1002004C) // reg_3 - GPIO Data Out
+#define reg_gpio_intr_stat (*(volatile uint32_t*)0x10020050) // reg_4 - GPIO Interrupt status
+#define reg_gpio_intr_clr (*(volatile uint32_t*)0x10020050) // reg_5 - GPIO Interrupt Clear
+#define reg_gpio_intr_set (*(volatile uint32_t*)0x10020054) // reg_6 - GPIO Interrupt Set
+#define reg_gpio_intr_mask (*(volatile uint32_t*)0x10020058) // reg_7 - GPIO Interrupt Mask
+#define reg_gpio_pos_intr (*(volatile uint32_t*)0x1002005C) // reg_8 - GPIO Posedge Interrupt
+#define reg_gpio_neg_intr (*(volatile uint32_t*)0x10020060) // reg_9 - GPIO Neg Interrupt
+
+#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x10020080) // reg_0 - PWM Reg-0
+#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x10020084) // reg_1 - PWM Reg-0
+#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x10020088) // reg_2 - PWM Reg-1
+#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x1002008C) // reg_3 - PWM Reg-2
+#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x10020090) // reg_4 - PWM Reg-3
+#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x10020094) // reg_5 - PWM Reg-4
+#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x10020098) // reg_6 - PWM Reg-5
+
+#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x100200C0) // reg_0 - Global config
+#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x100200C4) // reg_1 - Timer-0
+#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x100200C8) // reg_2 - Timer-1
+#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x100200CC) // reg_3 - Timer-2
+
+#define reg_sema_lock0 (*(volatile uint32_t*)0x10020100) // reg_0 - Hardware Lock-0
+#define reg_sema_lock1 (*(volatile uint32_t*)0x10020104) // reg_1 - Hardware Lock-1
+#define reg_sema_lock2 (*(volatile uint32_t*)0x10020108) // reg_2 - Hardware Lock-2
+#define reg_sema_lock3 (*(volatile uint32_t*)0x1002010C) // reg_3 - Hardware Lock-3
+#define reg_sema_lock4 (*(volatile uint32_t*)0x10020110) // reg_4 - Hardware Lock-4
+#define reg_sema_lock5 (*(volatile uint32_t*)0x10020114) // reg_5 - Hardware Lock-5
+#define reg_sema_lock6 (*(volatile uint32_t*)0x10020118) // reg_6 - Hardware Lock-6
+#define reg_sema_lock7 (*(volatile uint32_t*)0x1002011C) // reg_7 - Hardware Lock-7
+#define reg_sema_lock8 (*(volatile uint32_t*)0x10020120) // reg_8 - Hardware Lock-8
+#define reg_sema_lock9 (*(volatile uint32_t*)0x10020124) // reg_9 - Hardware Lock-9
+#define reg_sema_lock10 (*(volatile uint32_t*)0x10020128) // reg_10 - Hardware Lock-10
+#define reg_sema_lock11 (*(volatile uint32_t*)0x1002012C) // reg_11 - Hardware Lock-11
+#define reg_sema_lock12 (*(volatile uint32_t*)0x10020130) // reg_12 - Hardware Lock-12
+#define reg_sema_lock13 (*(volatile uint32_t*)0x10020134) // reg_13 - Hardware Lock-13
+#define reg_sema_lock14 (*(volatile uint32_t*)0x10020138) // reg_14 - Hardware Lock-14
+#define reg_sema_lock_cfg (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock config
+#define reg_sema_lock_stat (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock Status
+
+
+#define reg_uart0_ctrl (*(volatile uint32_t*)0x10010000) // Reg-0
+#define reg_uart0_intr_stat (*(volatile uint32_t*)0x10010004) // Reg-1
+#define reg_uart0_baud_ctrl1 (*(volatile uint32_t*)0x10010008) // Reg-2
+#define reg_uart0_baud_ctrl2 (*(volatile uint32_t*)0x1001000C) // Reg-3
+#define reg_uart0_status (*(volatile uint32_t*)0x10010010) // Reg-4
+#define reg_uart0_txdata (*(volatile uint32_t*)0x10010014) // Reg-5
+#define reg_uart0_rxdata (*(volatile uint32_t*)0x10010018) // Reg-6
+#define reg_uart0_txfifo_stat (*(volatile uint32_t*)0x1001001C) // Reg-7
+#define reg_uart0_rxfifo_stat (*(volatile uint32_t*)0x10010020) // Reg-8
+
+#define reg_uart1_ctrl (*(volatile uint32_t*)0x10010100) // Reg-0
+#define reg_uart1_intr_stat (*(volatile uint32_t*)0x10010104) // Reg-1
+#define reg_uart1_baud_ctrl1 (*(volatile uint32_t*)0x10010108) // Reg-2
+#define reg_uart1_baud_ctrl2 (*(volatile uint32_t*)0x1001010C) // Reg-3
+#define reg_uart1_status (*(volatile uint32_t*)0x10010110) // Reg-4
+#define reg_uart1_txdata (*(volatile uint32_t*)0x10010114) // Reg-5
+#define reg_uart1_rxdata (*(volatile uint32_t*)0x10010118) // Reg-6
+#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x1001011C) // Reg-7
+#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x10010120) // Reg-8
+
diff --git a/verilog/dv/c_func/inc/user_reg_map.h b/verilog/dv/c_func/inc/user_reg_map.h
deleted file mode 100644
index 4508fb2..0000000
--- a/verilog/dv/c_func/inc/user_reg_map.h
+++ /dev/null
@@ -1,38 +0,0 @@
-
-
-//-------------------------------------
-// PinMux Register
-// ------------------------------------
-#define reg_pinmux_chip_id (*(volatile uint32_t*)0x30020000) // reg_0 - Chip ID
-#define reg_pinmux_gbl_cfg0 (*(volatile uint32_t*)0x30020004) // reg_1 - Global Config-2
-#define reg_pinmux_gbl_cfg1 (*(volatile uint32_t*)0x30020008) // reg_2 - Global Config-1
-#define reg_pinmux_gbl_intr_msk (*(volatile uint32_t*)0x3002000C) // reg_3 - Global Interrupt Mask
-#define reg_pinmux_gbl_intr (*(volatile uint32_t*)0x30020010) // reg_4 - Global Interrupt
-#define reg_pinmux_gpio_idata (*(volatile uint32_t*)0x30020014) // reg_5 - GPIO Data In
-#define reg_pinmux_gpio_odata (*(volatile uint32_t*)0x30020018) // reg_6 - GPIO Data Out
-#define reg_pinmux_gpio_dsel (*(volatile uint32_t*)0x3002001C) // reg_7 - GPIO Direction Select
-#define reg_pinmux_gpio_type (*(volatile uint32_t*)0x30020020) // reg_8 - GPIO TYPE - Static/Waveform
-#define reg_pinmux_gpio_intr_stat (*(volatile uint32_t*)0x30020024) // reg_9 - GPIO Interrupt status
-#define reg_pinmux_gpio_intr_clr (*(volatile uint32_t*)0x30020024) // reg_9 - GPIO Interrupt Clear
-#define reg_pinmux_gpio_intr_set (*(volatile uint32_t*)0x30020028) // reg_10 - GPIO Interrupt Set
-#define reg_pinmux_gpio_intr_mask (*(volatile uint32_t*)0x3002002C) // reg_11 - GPIO Interrupt Mask
-#define reg_pinmux_gpio_pos_intr (*(volatile uint32_t*)0x30020030) // reg_12 - GPIO Posedge Interrupt
-#define reg_pinmux_gpio_neg_intr (*(volatile uint32_t*)0x30020034) // reg_13 - GPIO Neg Interrupt
-#define reg_pinmux_gpio_multi_func (*(volatile uint32_t*)0x30020038) // reg_14 - GPIO Multi Function
-#define reg_pinmux_soft_reg_0 (*(volatile uint32_t*)0x3002003C) // reg_15 - Soft Register
-#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x30020040) // reg_16 - PWM Reg-0
-#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x30020044) // reg_17 - PWM Reg-1
-#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x30020048) // reg_18 - PWM Reg-2
-#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x3002004C) // reg_19 - PWM Reg-3
-#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x30020050) // reg_20 - PWM Reg-4
-#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x30020054) // reg_21 - PWM Reg-5
-#define reg_pinmux_soft_reg_1 (*(volatile uint32_t*)0x30020058) // reg_22 - Sof Register
-#define reg_pinmux_soft_reg_2 (*(volatile uint32_t*)0x3002005C) // reg_23 - Sof Register
-#define reg_pinmux_soft_reg_3 (*(volatile uint32_t*)0x30020060) // reg_24 - Sof Register
-#define reg_pinmux_soft_reg_4 (*(volatile uint32_t*)0x30020064) // reg_25 - Sof Register
-#define reg_pinmux_soft_reg_5 (*(volatile uint32_t*)0x30020068) // reg_26 - Sof Register
-#define reg_pinmux_soft_reg_6 (*(volatile uint32_t*)0x3002006C) // reg_27 - Sof Register
-#define reg_pinmux_cfg_timer0 (*(volatile uint32_t*)0x30020070) // reg_28 - Timer-0
-#define reg_pinmux_cfg_timer1 (*(volatile uint32_t*)0x30020074) // reg_28 - Timer-1
-#define reg_pinmux_cfg_timer2 (*(volatile uint32_t*)0x30020078) // reg_28 - Timer-2
-
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index 5888540..09f42e8 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit 5888540bf2ae57d8c0326778a6d0c25b6ef95d35
+Subproject commit 09f42e80c78b05785fb7088fb3bff16b2044c6c8
diff --git a/verilog/dv/firmware/sc_print.c b/verilog/dv/firmware/sc_print.c
index b736d42..f2a1192 100644
--- a/verilog/dv/firmware/sc_print.c
+++ b/verilog/dv/firmware/sc_print.c
@@ -20,16 +20,37 @@
#include <stdarg.h>
#include "sc_print.h"
-#define SC_SIM_OUTPORT (0xf0000000)
-#define CHAR_BIT (8)
+#define SC_SIM_OUTPORT (0xf0000000)
+#define REG_MPRJ_UART_CTRL (0x10010000)
+#define REG_MPRJ_UART_INTR_STAT (0x10010004)
+#define REG_MPRJ_UART_BAUD_CTRL1 (0x10010008)
+#define REG_MPRJ_UART_BAUD_CTRL2 (0x1001000C)
+#define REG_MPRJ_UART_STAT (0x10010010)
+#define REG_MPRJ_UART_TXDATA (0x10010014)
+#define REG_MPRJ_UART_RXDATA (0x10010018)
+#define REG_MPRJ_UART_TFIFO_STAT (0x1001001C)
+#define REG_MPRJ_UART_RFIFO_STAT (0x10010020)
-static void
-sc_puts(long str, long strlen) {
+#define CHAR_BIT (8)
+/**
+static void sc_puts(long str, long strlen) {
volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT;
const char *in_ptr = (const char*)str;
for (long len = strlen; len > 0; --len)
*out_ptr = *in_ptr++;
}
+**/
+static void sc_puts(long str, long strlen) {
+ volatile char *out_ptr = (volatile char*)REG_MPRJ_UART_TXDATA;
+ volatile char *status = (volatile char*)REG_MPRJ_UART_STAT;
+ const char *in_ptr = (const char*)str;
+ for (long len = strlen; len > 0; --len) {
+ //if((*status & 0x1) != 0x1) { // check UART TX fifo is not full
+ *out_ptr = *in_ptr++;
+ //}
+ }
+
+}
#undef putchar
int
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index a4e04d4..2601fc5 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -53,7 +53,7 @@
export TOOLS ?= /opt/riscv32i
export GCC_PATH ?= $(TOOLS)/bin
-export GCC_PREFIX?= riscv32-unknown-linux-gnu
+GCC_PREFIX?=riscv32-unknown-elf
############## USER SPECIFIC DEFINE ##################
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 00d308d..8ff48ff 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c
@@ -160,11 +160,11 @@
// Remove All Reset
- reg_pinmux_gbl_cfg0 = 0x11F;
+ reg_glbl_cfg0 = 0x11F;
// Enable UART Multi Functional Ports
- reg_pinmux_gpio_multi_func = 0x100;
+ reg_glbl_multi_func = 0x100;
// configure the user uart
reg_mprj_uart_reg0 = 0x7;
diff --git a/verilog/dv/risc_boot/user_uart.dump b/verilog/dv/risc_boot/user_uart.dump
new file mode 100644
index 0000000..4d5b8b2
--- /dev/null
+++ b/verilog/dv/risc_boot/user_uart.dump
@@ -0,0 +1,212 @@
+
+user_uart.elf: file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <SIM_EXIT-0xf4>:
+ ...
+
+000000f4 <SIM_EXIT>:
+ f4: 00000013 nop
+
+000000f8 <SIM_STOP>:
+ f8: 0000006f j f8 <SIM_STOP>
+ fc: ffff 0xffff
+ fe: ffff 0xffff
+
+Disassembly of section .text:
+
+00000100 <machine_trap_entry-0xc0>:
+ ...
+
+000001c0 <machine_trap_entry>:
+ 1c0: 1200006f j 2e0 <trap_entry>
+ 1c4: 00000013 nop
+ 1c8: 00000013 nop
+ 1cc: 00000013 nop
+ 1d0: 00000013 nop
+ 1d4: 00000013 nop
+ 1d8: 00000013 nop
+ 1dc: 00000013 nop
+ 1e0: 00000013 nop
+ 1e4: 00000013 nop
+ 1e8: 00000013 nop
+ 1ec: 00000013 nop
+ 1f0: 00000013 nop
+ 1f4: 00000013 nop
+ 1f8: 00000013 nop
+ 1fc: 00000013 nop
+
+00000200 <_start>:
+ 200: 00000093 li ra,0
+ 204: 00000113 li sp,0
+ 208: 00000193 li gp,0
+ 20c: 00000213 li tp,0
+ 210: 00000293 li t0,0
+ 214: 00000313 li t1,0
+ 218: 00000393 li t2,0
+ 21c: 00000413 li s0,0
+ 220: 00000493 li s1,0
+ 224: 00000513 li a0,0
+ 228: 00000593 li a1,0
+ 22c: 00000613 li a2,0
+ 230: 00000693 li a3,0
+ 234: 00000713 li a4,0
+ 238: 00000793 li a5,0
+ 23c: 00000813 li a6,0
+ 240: 00000893 li a7,0
+ 244: 00000913 li s2,0
+ 248: 00000993 li s3,0
+ 24c: 00000a13 li s4,0
+ 250: 00000a93 li s5,0
+ 254: 00000b13 li s6,0
+ 258: 00000b93 li s7,0
+ 25c: 00000c13 li s8,0
+ 260: 00000c93 li s9,0
+ 264: 00000d13 li s10,0
+ 268: 00000d93 li s11,0
+ 26c: 00000e13 li t3,0
+ 270: 00000e93 li t4,0
+ 274: 00000f13 li t5,0
+ 278: 00000f93 li t6,0
+ 27c: 08000197 auipc gp,0x8000
+ 280: 58418193 addi gp,gp,1412 # 8000800 <__global_pointer$>
+ 284: 08000597 auipc a1,0x8000
+ 288: d7c58593 addi a1,a1,-644 # 8000000 <__BSS_START__>
+ 28c: 08000617 auipc a2,0x8000
+ 290: d7460613 addi a2,a2,-652 # 8000000 <__BSS_START__>
+ 294: a021 j 29c <_start+0x9c>
+ 296: 0005a023 sw zero,0(a1)
+ 29a: 0591 addi a1,a1,4
+ 29c: fec59de3 bne a1,a2,296 <_start+0x96>
+ 2a0: 0c480117 auipc sp,0xc480
+ 2a4: 56010113 addi sp,sp,1376 # c480800 <__C_STACK_TOP__>
+ 2a8: 0c4902b7 lui t0,0xc490
+ 2ac: 4305 li t1,1
+ 2ae: 0062a023 sw t1,0(t0) # c490000 <__C_STACK_TOP__+0xf800>
+ 2b2: 0c4902b7 lui t0,0xc490
+ 2b6: 00428293 addi t0,t0,4 # c490004 <__C_STACK_TOP__+0xf804>
+ 2ba: 06300313 li t1,99
+ 2be: 0062a023 sw t1,0(t0)
+ 2c2: 0c4902b7 lui t0,0xc490
+ 2c6: 01028293 addi t0,t0,16 # c490010 <__C_STACK_TOP__+0xf810>
+ 2ca: 537d li t1,-1
+ 2cc: 0062a023 sw t1,0(t0)
+ 2d0: 0062a223 sw t1,4(t0)
+ 2d4: 4501 li a0,0
+ 2d6: 4581 li a1,0
+ 2d8: 0a8000ef jal ra,380 <main>
+ 2dc: 0c40006f j 3a0 <sc_exit>
+
+000002e0 <trap_entry>:
+ 2e0: 716d addi sp,sp,-272
+ 2e2: c206 sw ra,4(sp)
+ 2e4: c40a sw sp,8(sp)
+ 2e6: c60e sw gp,12(sp)
+ 2e8: c812 sw tp,16(sp)
+ 2ea: ca16 sw t0,20(sp)
+ 2ec: cc1a sw t1,24(sp)
+ 2ee: ce1e sw t2,28(sp)
+ 2f0: d022 sw s0,32(sp)
+ 2f2: d226 sw s1,36(sp)
+ 2f4: d42a sw a0,40(sp)
+ 2f6: d62e sw a1,44(sp)
+ 2f8: d832 sw a2,48(sp)
+ 2fa: da36 sw a3,52(sp)
+ 2fc: dc3a sw a4,56(sp)
+ 2fe: de3e sw a5,60(sp)
+ 300: c0c2 sw a6,64(sp)
+ 302: c2c6 sw a7,68(sp)
+ 304: c4ca sw s2,72(sp)
+ 306: c6ce sw s3,76(sp)
+ 308: c8d2 sw s4,80(sp)
+ 30a: cad6 sw s5,84(sp)
+ 30c: ccda sw s6,88(sp)
+ 30e: cede sw s7,92(sp)
+ 310: d0e2 sw s8,96(sp)
+ 312: d2e6 sw s9,100(sp)
+ 314: d4ea sw s10,104(sp)
+ 316: d6ee sw s11,108(sp)
+ 318: d8f2 sw t3,112(sp)
+ 31a: daf6 sw t4,116(sp)
+ 31c: dcfa sw t5,120(sp)
+ 31e: defe sw t6,124(sp)
+ 320: 34202573 csrr a0,mcause
+ 324: 341025f3 csrr a1,mepc
+ 328: 860a mv a2,sp
+ 32a: 048000ef jal ra,372 <handle_trap>
+ 32e: 4092 lw ra,4(sp)
+ 330: 4122 lw sp,8(sp)
+ 332: 41b2 lw gp,12(sp)
+ 334: 4242 lw tp,16(sp)
+ 336: 42d2 lw t0,20(sp)
+ 338: 4362 lw t1,24(sp)
+ 33a: 43f2 lw t2,28(sp)
+ 33c: 5402 lw s0,32(sp)
+ 33e: 5492 lw s1,36(sp)
+ 340: 5522 lw a0,40(sp)
+ 342: 55b2 lw a1,44(sp)
+ 344: 5642 lw a2,48(sp)
+ 346: 56d2 lw a3,52(sp)
+ 348: 5762 lw a4,56(sp)
+ 34a: 57f2 lw a5,60(sp)
+ 34c: 4806 lw a6,64(sp)
+ 34e: 4896 lw a7,68(sp)
+ 350: 4926 lw s2,72(sp)
+ 352: 49b6 lw s3,76(sp)
+ 354: 4a46 lw s4,80(sp)
+ 356: 4ad6 lw s5,84(sp)
+ 358: 4b66 lw s6,88(sp)
+ 35a: 4bf6 lw s7,92(sp)
+ 35c: 5c06 lw s8,96(sp)
+ 35e: 5c96 lw s9,100(sp)
+ 360: 5d26 lw s10,104(sp)
+ 362: 5db6 lw s11,108(sp)
+ 364: 5e46 lw t3,112(sp)
+ 366: 5ed6 lw t4,116(sp)
+ 368: 5f66 lw t5,120(sp)
+ 36a: 5ff6 lw t6,124(sp)
+ 36c: 6151 addi sp,sp,272
+ 36e: 30200073 mret
+
+00000372 <handle_trap>:
+ 372: d83ff06f j f4 <SIM_EXIT>
+ ...
+
+00000380 <main>:
+ 380: 10010737 lui a4,0x10010
+ 384: 531c lw a5,32(a4)
+ 386: dffd beqz a5,384 <main+0x4>
+ 388: 01872283 lw t0,24(a4) # 10010018 <__C_STACK_TOP__+0x3b8f818>
+ 38c: 00572a23 sw t0,20(a4)
+ 390: bfd5 j 384 <main+0x4>
+ ...
+
+000003a0 <sc_exit>:
+ 3a0: 00000297 auipc t0,0x0
+ 3a4: d5428293 addi t0,t0,-684 # f4 <SIM_EXIT>
+ 3a8: 8282 jr t0
+ 3aa: 00000013 nop
+ 3ae: 00000013 nop
+ 3b2: 00000013 nop
+ 3b6: 00000013 nop
+ 3ba: 00000013 nop
+ 3be: 0001 nop
+ ...
+
+Disassembly of section .stack:
+
+0c480400 <__C_STACK_TOP__-0x400>:
+ ...
+
+Disassembly of section .comment:
+
+00000000 <.comment>:
+ 0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
+ 4: 2820 fld fs0,80(s0)
+ 6: 29554e47 fmsub.s ft8,fa0,fs5,ft5,rmm
+ a: 3620 fld fs0,104(a2)
+ c: 312e fld ft2,232(sp)
+ e: 302e fld ft0,232(sp)
+ ...
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index 609b7fe..d52ebf4 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -16,7 +16,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-GCC_PREFIX?=riscv32-unknown-elf
+GCC_PREFIX?=riscv64-unknown-elf
## Simulation mode: RTL/GL
@@ -158,7 +158,7 @@
todo_list := $(bld_dir)/todo.txt
# Environment
-export CROSS_PREFIX ?= riscv32-unknown-elf-
+export CROSS_PREFIX ?= riscv64-unknown-elf-
export RISCV_GCC ?= $(CROSS_PREFIX)gcc
export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D
export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/timer.h b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
index 827b849..c306b2f 100644
--- a/verilog/dv/riscv_regress/tests/isr_sample/timer.h
+++ b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
@@ -78,7 +78,7 @@
.macro _run_timer
li TMP, MEM_MTIME_CTRL
lw TMP2, 0(TMP)
- li TMP3, (1 << YCR1_MTIME_CTRL_EN)
+ li TMP3, (1 << YCR_MTIME_CTRL_EN)
or TMP2, TMP2, TMP3
sw TMP2, 0(TMP)
.endm
@@ -86,7 +86,7 @@
.macro _stop_timer
li TMP, MEM_MTIME_CTRL
lw TMP2, 0(TMP)
- li TMP3, (1 << YCR1_MTIME_CTRL_EN)
+ li TMP3, (1 << YCR_MTIME_CTRL_EN)
not TMP3, TMP3
and TMP2, TMP2, TMP3
sw TMP2, 0(TMP)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index ceaec71..e444404 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -291,7 +291,7 @@
repeat (2) @(posedge clock);
#1;
// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
// CS#2 Switch to QSPI Mode
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
@@ -305,10 +305,10 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
end
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile
index 7bcd2b7..3ec839e 100644
--- a/verilog/dv/uart_master/Makefile
+++ b/verilog/dv/uart_master/Makefile
@@ -51,15 +51,12 @@
## Compiler Information
#######################################################################
-export GCC_PATH?= $(TOOLS)/bin
-export GCC_PREFIX?= riscv32-unknown-linux-gnu
+export TOOLS ?= /opt/riscv32i
+export GCC_PATH ?= $(TOOLS)/bin
+GCC_PREFIX?=riscv32-unknown-elf
-############## USER SPECIFIC DEFINE ##################
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
-
-######################################################
@@ -153,28 +150,30 @@
##############################################################################
%.vvp: %_tb.v %.hex
+
+## RTL
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
else
- iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
endif
-endif
+endif
-## GL
+##GL
ifeq ($(SIM),GL)
- ifeq ($(CONFIG),caravel_user_project)
- iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+ ifeq ($(DUMP),OFF)
+ iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
-f$(VERILOG_PATH)/includes/includes.gl.caravel \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
else
- iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
- -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
- -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+ iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+ -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
endif
endif
@@ -223,3 +222,9 @@
\rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
.PHONY: clean hex all
+
+
+
+
+
+
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index 2b021ee..f49daab 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -138,19 +138,19 @@
$display("Monitor: Writing expected value");
test_fail = 0;
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
$display("###################################################");
if(test_fail == 0) begin
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c
index f78b8fe..cd1bfec 100644
--- a/verilog/dv/user_aes/user_aes.c
+++ b/verilog/dv/user_aes/user_aes.c
@@ -40,36 +40,20 @@
static int test_decrypt_ecb(void);
static void test_encrypt_ecb_verbose(void);
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
-#define reg_mprg_pinmux_gpio_odata (*(volatile uint32_t*)0x10020018)
+#define reg_mprg_gpio_odata (*(volatile uint32_t*)0x1002004C)
int main(void)
{
@@ -86,34 +70,34 @@
return 0;
#endif
- reg_mprg_pinmux_gpio_odata = 0x00000100;
- reg_mprj_globl_reg23 = 0x00000000;
+ reg_mprg_gpio_odata = 0x00000100;
+ reg_mprj_globl_soft0 = 0x00000000;
exit = test_encrypt_cbc();
- reg_mprg_pinmux_gpio_odata = 0x00000200;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000200;
+ reg_mprj_globl_soft0 = exit;
exit += test_decrypt_cbc();
- reg_mprg_pinmux_gpio_odata = 0x00000300;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000300;
+ reg_mprj_globl_soft0 = exit;
exit += test_encrypt_ctr();
- reg_mprg_pinmux_gpio_odata = 0x00000400;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000400;
+ reg_mprj_globl_soft0 = exit;
exit += test_decrypt_ctr();
- reg_mprg_pinmux_gpio_odata = 0x00000500;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000500;
+ reg_mprj_globl_soft0 = exit;
exit += test_decrypt_ecb();
- reg_mprg_pinmux_gpio_odata = 0x00000600;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000600;
+ reg_mprj_globl_soft0 = exit;
exit += test_encrypt_ecb();
- reg_mprg_pinmux_gpio_odata = 0x00000700;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000700;
+ reg_mprj_globl_soft0 = exit;
test_encrypt_ecb_verbose();
- reg_mprg_pinmux_gpio_odata = 0x00000800;
- reg_mprj_globl_reg23 = exit;
+ reg_mprg_gpio_odata = 0x00000800;
+ reg_mprj_globl_soft0 = exit;
if(exit == 0) {
- reg_mprg_pinmux_gpio_odata = 0x00001800;
+ reg_mprg_gpio_odata = 0x00001800;
} else {
- reg_mprg_pinmux_gpio_odata = 0x0000A800;
+ reg_mprg_gpio_odata = 0x0000A800;
}
return exit;
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 3c46014..8d236d4 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -183,17 +183,17 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable UART Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
@@ -204,9 +204,9 @@
uart_stick_parity, uart_timeout, uart_divisor);
// Set the PORT-B Direction as Output
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h0000FF00);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
// Set the GPIO Output data: 0x00000000
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h0000000);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
fork
begin
@@ -217,7 +217,7 @@
end
join_any
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h00000000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
$display("###################################################");
if(test_fail == 0) begin
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index bcd24cd..5f1c60b 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -150,10 +150,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(0, user_basic_tb);
+ $dumpvars(1, user_basic_tb);
//$dumpvars(1, user_basic_tb.u_top);
//$dumpvars(0, user_basic_tb.u_top.u_pll);
- //$dumpvars(1, user_basic_tb.u_top.u_wb_host);
+ $dumpvars(0, user_basic_tb.u_top.u_wb_host);
//$dumpvars(1, user_basic_tb.u_top.u_intercon);
//$dumpvars(1, user_basic_tb.u_top.u_intercon);
//$dumpvars(1, user_basic_tb.u_top.u_pinmux);
@@ -167,10 +167,6 @@
end
-// Hook to pll clock
-wire pll_clock = u_top.u_wb_host.u_clkbuf_pll.X;
-
-
initial
begin
@@ -244,35 +240,37 @@
test_step = 10;
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
-
- $display("###################################################");
- $display("Monitor: Checking the PLL:");
- $display("###################################################");
+
+ `ifndef GL
+ $display("###################################################");
+ $display("Monitor: Checking the PLL:");
+ $display("###################################################");
test_step = 11;
// Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
- repeat (100) @(posedge clock);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
+ repeat (100) @(posedge clock);
pll_clock_monitor(5);
test_step = 12;
// Set PLL enable, DCO mode ; Set PLL output divider to 0x01
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
- repeat (100) @(posedge clock);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+ repeat (100) @(posedge clock);
pll_clock_monitor(4);
- $display("###################################################");
- $display("Monitor: Monitor Clock output:");
- $display("###################################################");
+ $display("###################################################");
+ $display("Monitor: Monitor Clock output:");
+ $display("###################################################");
$display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
test_step = 13;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
// Set PLL enable, DCO mode ; Set PLL output divider to 0x01
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
+ `endif
$display("###################################################");
$display("Monitor: Checking the chip signature :");
@@ -281,9 +279,9 @@
// Remove Wb/PinMux Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2007_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_8000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h1508_2022);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_0000);
end
@@ -347,7 +345,7 @@
// IOs
- .io_in (io_in) ,
+ .io_in ('h0) ,
.io_out (io_out) ,
.io_oeb (io_oeb) ,
@@ -391,7 +389,12 @@
task pll_clock_monitor;
input [15:0] exp_period;
begin
- force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+ //force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+ `ifdef GL
+ force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+ `else
+ force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+ `endif
check_clock_period("PLL CLock",exp_period);
release clock_mon;
end
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c
index 9c99cd9..a3e9b0d 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass.c
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -19,42 +19,28 @@
#define uint32_t long
#define uint16_t int
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
+
+
// -------------------------------------------------------------------------
// Test copying code into SRAM and running it from there.
// -------------------------------------------------------------------------
void test_function()
{
- reg_mprj_globl_reg24 = 0x33445566; // Sig-3
- reg_mprj_globl_reg25 = 0x44556677; // Sig-4
+ reg_mprj_globl_soft2 = 0x33445566; // Sig-2
+ reg_mprj_globl_soft3 = 0x44556677; // Sig-3
return;
}
@@ -69,18 +55,18 @@
src_ptr = &test_function;
dst_ptr = func;
- reg_mprj_globl_reg22 = 0x11223344; // Sig-1
+ reg_mprj_globl_soft0 = 0x11223344; // Sig-0
while (src_ptr < &main) {
*(dst_ptr++) = *(src_ptr++);
}
// Call the routine in SRAM
- reg_mprj_globl_reg23 = 0x22334455; // Sig-2
+ reg_mprj_globl_soft1 = 0x22334455; // Sig-1
((void(*)())func)();
- reg_mprj_globl_reg26 = 0x55667788;
- reg_mprj_globl_reg27 = 0x66778899;
+ reg_mprj_globl_soft4 = 0x55667788;
+ reg_mprj_globl_soft5 = 0x66778899;
// Signal end of test
}
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
index c5d1478..45a24d3 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -135,15 +135,15 @@
repeat (2) @(posedge clock);
#1;
// Set the icahce and dcache bypass
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0});
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0});
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
@@ -165,12 +165,12 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index 5a30dd9..0451459 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -217,7 +217,7 @@
/*****************************/
- wire [15:0] irq_lines = u_top.u_pinmux.u_pinmux_reg.irq_lines;
+ wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines;
initial begin
clock = 0;
@@ -252,34 +252,34 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Disable Multi func
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000);
/************* GPIO As Output ******************/
$display("#####################################");
$display("Step-1: Testing GPIO As Output ");
// Set the Direction as Output
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'hFFFFFFFF);
// Set the GPIO Output data: 0x55555555
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h55555555);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h55555555);
cmp_gpio_output(8'h55,8'h55,8'h55,8'h55);
// Set the GPIO Output data: 0xAAAAAAAA
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hAAAAAAAA);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hAAAAAAAA);
cmp_gpio_output(8'hAA,8'hAA,8'hAA,8'hAA);
// Set the GPIO Output data: 0x5A5A5A5A5A5A
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h5A5A5A5A);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h5A5A5A5A);
cmp_gpio_output(8'h5A,8'h5A,8'h5A,8'h5A);
// Set the GPIO Output data: 0xA5A5A5A5A5A5
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hA5A5A5A5);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hA5A5A5A5);
cmp_gpio_output(8'hA5,8'hA5,8'hA5,8'hA5);
/************* GPIO As Input ******************/
$display("#####################################");
$display("Step-2: Testing GPIO As Input ");
// Set the Direction as Input
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
cmp_gpio_input(8'h55,8'h55,8'h55,8'h55);
cmp_gpio_input(8'hAA,8'hAA,8'hAA,8'hAA);
@@ -290,12 +290,12 @@
$display("#####################################");
$display("Step-3: Testing GPIO As Posedge Interrupt ");
// Set the Direction as Input
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
// Set GPIO for posedge Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'hFFFFFFFF);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'h00000000);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'h00000000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF);
// Drive GPIO with 0x55
cmp_gpio_pos_intr(8'h55,8'h55,8'h55,8'h55);
@@ -314,12 +314,12 @@
$display("#####################################");
$display("Step-3: Testing GPIO As Negedge Interrupt ");
// Set the Direction as Input
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000);
// Set GPIO for negedge Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'h00000000);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'hFFFFFFFF);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'h00000000);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF);
// Drive GPIO with 0x55
cmp_gpio_neg_intr(8'h55,8'h55,8'h55,8'h55);
@@ -506,7 +506,7 @@
port_c_out = port_c;
port_d_out = port_d;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
end
endtask
@@ -523,12 +523,12 @@
cmp_gpio_input(8'h00,8'h00,8'h00,8'h00);
// Clear Global Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000);
// Clear all the Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
// Drive Ports
cmp_gpio_input(port_d,port_c,port_b,port_a);
@@ -544,10 +544,10 @@
repeat (20) @(posedge clock);
// Check the GPIO Interrupt
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0});
// Check The Global Interrupt
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000);
if(irq_lines[15] != 1'b1) begin
$display("ERROR: Global GPIO Interrupt not detected");
@@ -555,15 +555,15 @@
end
// Clear The GPIO Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF);
// Clear GPIO Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000);
// Check Interrupt are cleared
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0);
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
if(irq_lines[15] != 1'b0) begin
$display("ERROR: Global GPIO Interrupt is not cleared");
`TB_GLBL.test_fail = 1;
@@ -584,11 +584,11 @@
cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF);
// Clear Global Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000);
// Clear all the Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF);
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
// Drive Ports
cmp_gpio_input(port_d,port_c,port_b,port_a);
@@ -603,10 +603,10 @@
repeat (20) @(posedge clock);
// Neg edge interrupt is will compliment of input value
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0});
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0});
// Check The Global Interrupt
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000);
if(irq_lines[15] != 1'b1) begin
$display("ERROR: Global GPIO Interrupt not detected");
@@ -614,14 +614,14 @@
end
// Clear The GPIO Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF);
+ wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF);
// Clear GPIO Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000);
// Check Interrupt are cleared
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0);
+ wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0);
if(irq_lines[15] != 1'b0) begin
$display("ERROR: Global GPIO Interrupt is not cleared");
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index e41e0d2..87b94a3 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,10 +146,10 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);
// Enable I2C Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h8000);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h8000);
// Remove i2m reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h010);
repeat (100) @(posedge clock);
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore_test1/Makefile
similarity index 89%
copy from verilog/dv/user_mcore/Makefile
copy to verilog/dv/user_mcore_test1/Makefile
index f635413..9aa71f1 100644
--- a/verilog/dv/user_mcore/Makefile
+++ b/verilog/dv/user_mcore_test1/Makefile
@@ -43,7 +43,7 @@
.SUFFIXES:
-PATTERN = user_mcore
+PATTERN = user_mcore_test1
all: ${PATTERN:=.vcd}
@@ -51,13 +51,13 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_mcore.c -o user_mcore.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/common_bthread.c -o common_bthread.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
- ${GCC_PREFIX}-gcc -o user_mcore.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_mcore.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
- ${GCC_PREFIX}-objcopy -O verilog user_mcore.elf user_mcore.hex
- ${GCC_PREFIX}-objdump -D user_mcore.elf > user_mcore.dump
- rm crt.o user_mcore.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_mcore/user_mcore.c b/verilog/dv/user_mcore_test1/user_mcore_test1.c
similarity index 66%
rename from verilog/dv/user_mcore/user_mcore.c
rename to verilog/dv/user_mcore_test1/user_mcore_test1.c
index 4a5e14d..a77f439 100644
--- a/verilog/dv/user_mcore/user_mcore.c
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1.c
@@ -24,34 +24,18 @@
#define uint16_t int
#define size 10
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
// -------------------------------------------------------------------------
// Multi-core test, Two Array is filled with below data, destination hold sum
// source result remark
@@ -124,12 +108,12 @@
arg_t arg0 = { dest, src0, src1, 0, buf_size/2 };
arg_t arg1 = { dest, src0, src1, buf_size/2, buf_size };
- reg_mprj_globl_reg22 = 0x11223344; // Sig-1
+ reg_mprj_globl_soft0 = 0x11223344; // Sig-0
// Initialize bare threads (bthread).
bthread_init();
- reg_mprj_globl_reg23 = 0x22334455; // Sig-2
+ reg_mprj_globl_soft1 = 0x22334455; // Sig-1
// Start counting stats.
//test_stats_on();
@@ -137,18 +121,18 @@
// Spawn work onto core 1
bthread_spawn( 1, &vvadd_mt, &arg1 );
- reg_mprj_globl_reg24 = 0x33445566; // Sig-3
+ reg_mprj_globl_soft2 = 0x33445566; // Sig-2
// Have core 0 also do some work.
vvadd_mt(&arg0);
- reg_mprj_globl_reg25 = 0x44556677; // Sig-4
+ reg_mprj_globl_soft3 = 0x44556677; // Sig-3
// Wait for core 1 to finish.
bthread_join(1);
// Stop counting stats
//test_stats_off();
- reg_mprj_globl_reg26 = 0x55667788; // sig-5
+ reg_mprj_globl_soft4 = 0x55667788; // sig-4
// Core 0 will verify the results.
if ( bthread_get_core_id() == 0 ) {
@@ -159,7 +143,7 @@
test_pass &= 0;
}
if(test_pass == 0x1) {
- reg_mprj_globl_reg27 = 0x66778899; // sig-6
+ reg_mprj_globl_soft5 = 0x66778899; // sig-5
}
}
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
similarity index 94%
rename from verilog/dv/user_mcore/user_mcore_tb.v
rename to verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
index b43dcba..a4bda85 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
@@ -65,7 +65,11 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+
+`define TB_HEX_FILE "user_mcore_test1.hex"
+`define TB_TOP user_mcore_test1_tb
+
+module `TB_TOP;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -115,9 +119,9 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top);
end
`endif
@@ -136,11 +140,11 @@
#1;
// Remove all the reset
$display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
+ repeat (23) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -157,12 +161,12 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
@@ -257,7 +261,7 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
+ s25fl256s #(.mem_file_name(`TB_HEX_FILE),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore_test2/Makefile
similarity index 89%
rename from verilog/dv/user_mcore/Makefile
rename to verilog/dv/user_mcore_test2/Makefile
index f635413..1c301e2 100644
--- a/verilog/dv/user_mcore/Makefile
+++ b/verilog/dv/user_mcore_test2/Makefile
@@ -43,7 +43,7 @@
.SUFFIXES:
-PATTERN = user_mcore
+PATTERN = user_mcore_test2
all: ${PATTERN:=.vcd}
@@ -51,13 +51,13 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_mcore.c -o user_mcore.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/common_bthread.c -o common_bthread.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
- ${GCC_PREFIX}-gcc -o user_mcore.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_mcore.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
- ${GCC_PREFIX}-objcopy -O verilog user_mcore.elf user_mcore.hex
- ${GCC_PREFIX}-objdump -D user_mcore.elf > user_mcore.dump
- rm crt.o user_mcore.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o common_bthread.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2.c b/verilog/dv/user_mcore_test2/user_mcore_test2.c
new file mode 100644
index 0000000..4ba53eb
--- /dev/null
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include "common_misc.h"
+#include "common_bthread.h"
+#include "../c_func/inc/int_reg_map.h"
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t long
+#define uint16_t int
+#define size 10
+
+ print_message(const char *fmt) {
+ char ch;
+ // Wait for Semaphore-lock=0
+ while((reg_sema_lock0 & 0x1) == 0x0);
+ while(ch = *(unsigned char *)fmt) {
+
+ while((reg_uart0_status & 0x1) == 0x1);
+
+ reg_uart0_txdata = ch;
+ ++fmt;
+ }
+ // Release Semaphore Lock
+ reg_sema_lock0 = 0x1;
+
+ // Added nop to Semaphore to acquire by other core
+ asm ("nop");
+ asm ("nop");
+ asm ("nop");
+ asm ("nop");
+
+
+ }
+
+
+ int main( int argc, char* argv[] )
+ {
+ char ch;
+
+ // Common Sub-Routine
+ if ( bthread_get_core_id() == 0 ) {
+
+ // Enable the GPIO UART I/F
+ reg_glbl_multi_func = 0x100;
+
+ // Enable the UART TX/RX & STOP=2
+ reg_uart0_ctrl = 0x7;
+ // 1152000 Baud at 50Mhz System clock
+ reg_uart0_baud_ctrl1 = 0x0;
+ reg_uart0_baud_ctrl2 = 0x0;
+
+ reg_glbl_soft_reg_5 = 0x1; // Test Start Indication
+ }
+ // Core 0 thread
+ if ( bthread_get_core_id() == 0 ) {
+ print_message("UART command-0 from core-0\n");
+ print_message("UART command-1 from core-0\n");
+ print_message("UART command-2 from core-0\n");
+ print_message("UART command-3 from core-0\n");
+
+ }
+ // Core 1 thread
+ if ( bthread_get_core_id() == 1 ) {
+
+ while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+ print_message("UART command-0 from core-1\n");
+ print_message("UART command-1 from core-1\n");
+ print_message("UART command-2 from core-1\n");
+ print_message("UART command-3 from core-1\n");
+
+ }
+ // Core 2 thread
+ if ( bthread_get_core_id() == 2 ) {
+ while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+ print_message("UART command-0 from core-2\n");
+ print_message("UART command-1 from core-2\n");
+ print_message("UART command-2 from core-2\n");
+ print_message("UART command-3 from core-2\n");
+
+ }
+ // Core 3 thread
+ if ( bthread_get_core_id() == 3 ) {
+ while((reg_glbl_soft_reg_5 & 0x1) == 0x0); // wait for test start
+ print_message("UART command-0 from core-3\n");
+ print_message("UART command-1 from core-3\n");
+ print_message("UART command-2 from core-3\n");
+ print_message("UART command-3 from core-3\n");
+
+ }
+
+ return 0;
+ }
+
+
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
similarity index 68%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
index b43dcba..7ee2ba2 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
@@ -65,7 +65,12 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
+`include "uart_agent.v"
+
+`define TB_HEX_FILE "user_mcore_test2.hex"
+`define TB_TOP user_mcore_test2_tb
+
+module `TB_TOP;
reg clock;
reg wb_rst_i;
reg power1, power2;
@@ -90,38 +95,105 @@
wire gpio;
wire [37:0] mprj_io;
wire [7:0] mprj_io_0;
- reg test_fail;
+ reg test_fail;
+ reg test_start;
reg [31:0] read_data;
+ //----------------------------------
+ // Uart Configuration
+ // ---------------------------------
+ reg [1:0] uart_data_bit ;
+ reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+ reg uart_stick_parity ; // 1: force even parity
+ reg uart_parity_en ; // parity enable
+ reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+ reg [7:0] uart_data ;
+ reg [15:0] uart_divisor ; // divided by n * 16
+ reg [15:0] uart_timeout ;// wait time limit
+
+ reg [15:0] uart_rx_nu ;
+ reg [15:0] uart_tx_nu ;
+ reg [7:0] uart_write_data [0:39];
+ reg uart_fifo_enable ; // fifo mode disable
+ reg flag ;
+
+ reg [31:0] check_sum ;
+
integer d_risc_id;
+ integer i,j;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+
+ // 50Mhz CLock
+ always #10 clock <= (clock === 1'b0);
initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
+ clock = 0;
+ test_start = 0;
+ flag = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(0, `TB_TOP.tb_uart);
+ $dumpvars(1, `TB_TOP.u_top);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+ $dumpvars(0, `TB_TOP.u_top.u_uart_i2c_usb_spi);
end
`endif
+ /*************************************************************************
+ * This is Baud Rate to clock divider conversion for Test Bench
+ * Note: DUT uses 16x baud clock, where are test bench uses directly
+ * baud clock, Due to 16x Baud clock requirement at RTL, there will be
+ * some resolution loss, we expect at lower baud rate this resolution
+ * loss will be less. For Quick simulation perpose higher baud rate used
+ * *************************************************************************/
+ task tb_set_uart_baud;
+ input [31:0] ref_clk;
+ input [31:0] baud_rate;
+ output [31:0] baud_div;
+ reg [31:0] baud_div;
+ begin
+ // for 230400 Baud = (50Mhz/230400) = 216.7
+ baud_div = ref_clk/baud_rate; // Get the Bit Baud rate
+ // Baud 16x = 216/16 = 13
+ baud_div = baud_div/16; // To find the RTL baud 16x div value to find similar resolution loss in test bench
+ // Test bench baud clock , 16x of above value
+ // 13 * 16 = 208,
+ // (Note if you see original value was 216, now it's 208 )
+ baud_div = baud_div * 16;
+ // Test bench half cycle counter to toggle it
+ // 208/2 = 104
+ baud_div = baud_div/2;
+ //As counter run's from 0 , substract from 1
+ baud_div = baud_div-1;
+ end
+ endtask
+
+
initial begin
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 200;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
@@ -136,48 +208,64 @@
#1;
// Remove all the reset
$display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
+ read_data = 0;
+ // Wait for Software Reg-5 = 1 Set by the RiscV core
+ while (read_data !== 32'h1) begin
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data);
+ end
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ tb_uart.debug_mode = 0; // disable debug display
+ tb_uart.uart_init;
+ tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
+ flag = 0;
+ check_sum = 0;
+ test_start = 1;
+
+ fork
+ begin
+ while(flag == 0)
+ begin
+ tb_uart.read_char(read_data,flag);
+ if(flag == 0) begin
+ $write ("%c",read_data);
+ check_sum = check_sum+read_data;
+ end
+ end
+ end
+ begin
+ repeat (300000) @(posedge clock); // wait for Processor Get Ready
+ end
+ join_any
+
+ #100
+ tb_uart.report_status(uart_rx_nu, uart_tx_nu);
+
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
-
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
+ test_fail = 0;
+ $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum);
+ // Check
+ // if all the 4224 byte received
+ // if no error
+ if(uart_rx_nu != 216) test_fail = 1;
+ if(check_sum != 32'h44f0) test_fail = 1;
+ if(tb_uart.err_cnt != 0) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: multi core test (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: multi core test (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: multi core test (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: multi core test (RTL) Failed");
`endif
end
$display("###################################################");
@@ -257,7 +345,7 @@
assign io_in[32] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
+ s25fl256s #(.mem_file_name(`TB_HEX_FILE),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
@@ -274,6 +362,19 @@
);
+//---------------------------
+// UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd = io_out[2];
+assign io_in[1] = uart_rxd ;
+
+uart_agent tb_uart(
+ .mclk (clock ),
+ .txd (uart_rxd ),
+ .rxd (uart_txd )
+ );
task wb_user_core_write;
@@ -326,7 +427,7 @@
wbd_ext_we_i ='h0; // write
wbd_ext_dat_i ='h0; // data output
wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ //$display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
repeat (2) @(posedge clock);
end
endtask
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index e5222cc..c6f24b7 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -144,17 +144,17 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable PWM Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h03F);
repeat (2) @(posedge clock);
#1;
// Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
// config 1us based on system clock - 1000/25ns = 40
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
test_fail = 0;
repeat (200) @(posedge clock);
@@ -162,12 +162,12 @@
$display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7");
test_step = 1;
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002);
+ wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003);
pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7);
repeat (100) @(posedge clock);
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 4fd07e5..8f984e1 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -203,7 +203,7 @@
repeat (2) @(posedge clock);
#1;
// Remove only WB and SPI Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h2);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h2);
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000
diff --git a/verilog/dv/user_qspi/user_risc_boot.c b/verilog/dv/user_qspi/user_risc_boot.c
index 0711b7b..83fb41b 100644
--- a/verilog/dv/user_qspi/user_risc_boot.c
+++ b/verilog/dv/user_qspi/user_risc_boot.c
@@ -18,34 +18,18 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
int main()
{
@@ -57,12 +41,12 @@
//*out_ptr = 0xDDEEFF00;
// Write software Write & Read Register
- reg_mprj_globl_reg22 = 0x11223344;
- reg_mprj_globl_reg23 = 0x22334455;
- reg_mprj_globl_reg24 = 0x33445566;
- reg_mprj_globl_reg25 = 0x44556677;
- reg_mprj_globl_reg26 = 0x55667788;
- reg_mprj_globl_reg27 = 0x66778899;
+ reg_mprj_globl_soft0 = 0x11223344;
+ reg_mprj_globl_soft1 = 0x22334455;
+ reg_mprj_globl_soft2 = 0x33445566;
+ reg_mprj_globl_soft3 = 0x44556677;
+ reg_mprj_globl_soft4 = 0x55667788;
+ reg_mprj_globl_soft5 = 0x66778899;
while(1) {}
return 0;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index 37e424b..c14c9a7 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -18,34 +18,18 @@
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
int main()
{
@@ -57,12 +41,12 @@
//*out_ptr = 0xDDEEFF00;
// Write software Write & Read Register
- reg_mprj_globl_reg22 = 0x11223344;
- reg_mprj_globl_reg23 = 0x22334455;
- reg_mprj_globl_reg24 = 0x33445566;
- reg_mprj_globl_reg25 = 0x44556677;
- reg_mprj_globl_reg26 = 0x55667788;
- reg_mprj_globl_reg27 = 0x66778899;
+ reg_mprj_globl_soft0 = 0x11223344;
+ reg_mprj_globl_soft1 = 0x22334455;
+ reg_mprj_globl_soft2 = 0x33445566;
+ reg_mprj_globl_soft3 = 0x44556677;
+ reg_mprj_globl_soft4 = 0x55667788;
+ reg_mprj_globl_soft5 = 0x66778899;
//reg_mprj_globl_reg12 = 0x778899AA;
//reg_mprj_globl_reg13 = 0x8899AABB;
//reg_mprj_globl_reg14 = 0x99AABBCC;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index f8af2e8..79c705b 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -145,10 +145,10 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
@@ -170,12 +170,12 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
@@ -240,6 +240,11 @@
);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK
+
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
diff --git a/verilog/dv/user_sema/Makefile b/verilog/dv/user_sema/Makefile
new file mode 100644
index 0000000..c74412f
--- /dev/null
+++ b/verilog/dv/user_sema/Makefile
@@ -0,0 +1,84 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_sema
+
+all: ${PATTERN:=.vcd}
+
+
+vvp: ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
+ $< -o $@
+ endif
+else
+ ifeq ($(DUMP),OFF)
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ else
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+ $< -o $@
+ endif
+endif
+
+%.vcd: %.vvp
+ vvp $<
+
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_mcore/user_mcore_tb.v b/verilog/dv/user_sema/user_sema_tb.v
similarity index 66%
copy from verilog/dv/user_mcore/user_mcore_tb.v
copy to verilog/dv/user_sema/user_sema_tb.v
index b43dcba..9b61ce6 100644
--- a/verilog/dv/user_mcore/user_mcore_tb.v
+++ b/verilog/dv/user_sema/user_sema_tb.v
@@ -16,13 +16,14 @@
// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
//////////////////////////////////////////////////////////////////////
//// ////
-//// Standalone User validation Test bench ////
+//// Hardware Semaphore validation Test bench ////
//// ////
-//// This file is part of the riscduino cores project ////
+//// This file is part of the YIFive cores project ////
+//// https://github.com/dineshannayya/yifive_r0.git ////
//// ////
//// Description ////
//// This is a standalone test bench to validate the ////
-//// Digital core multi-core behaviour. ////
+//// Digital core. ////
//// ////
//// To Do: ////
//// nothing ////
@@ -31,7 +32,7 @@
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// 0.1 - 17th Aug 2022, Dinesh A ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -62,48 +63,61 @@
`default_nettype wire
-`timescale 1 ns / 1 ns
+`timescale 1 ns/10 ps
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_mcore_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`define TOP user_sema_tb
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
+module `TOP;
+parameter CLK1_PERIOD = 10;
+parameter CLK2_PERIOD = 2;
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
+reg clock ;
+reg clock2 ;
+reg wb_rst_i ;
+reg power1, power2;
+reg power3, power4;
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
+reg wbd_ext_cyc_i; // strobe/request
+reg wbd_ext_stb_i; // strobe/request
+reg [31:0] wbd_ext_adr_i; // address
+reg wbd_ext_we_i; // write
+reg [31:0] wbd_ext_dat_i; // data output
+reg [3:0] wbd_ext_sel_i; // byte enable
+wire [31:0] wbd_ext_dat_o; // data input
+wire wbd_ext_ack_o; // acknowlegement
+wire wbd_ext_err_o; // error
+// User I/O
+wire [37:0] io_oeb ;
+wire [37:0] io_out ;
+wire [37:0] io_in ;
+
+wire [37:0] mprj_io ;
+wire [7:0] mprj_io_0 ;
+reg test_fail ;
+reg [31:0] read_data ;
+reg [31:0] exp_data ;
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+integer test_step;
+
+integer i,j;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+ always #(CLK1_PERIOD/2) clock <= (clock === 1'b0);
+ always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
initial begin
+ test_step = 0;
clock = 0;
+ clock2 = 0;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -115,90 +129,119 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_mcore_tb);
- $dumpvars(1, user_mcore_tb.u_top);
- $dumpvars(0, user_mcore_tb.u_top.u_riscv_top);
+ $dumpvars(1, `TOP);
+ //$dumpvars(1, `TOP.u_top);
+ //$dumpvars(0, `TOP.u_top.u_pll);
+ $dumpvars(0, `TOP.u_top.u_wb_host);
+ //$dumpvars(1, `TOP.u_top.u_intercon);
+ //$dumpvars(1, `TOP.u_top.u_intercon);
+ $dumpvars(0, `TOP.u_top.u_pinmux);
end
`endif
initial begin
-
- $value$plusargs("risc_core_id=%d", d_risc_id);
-
- #200; // Wait for reset removal
- repeat (10) @(posedge clock);
- $display("Monitor: Standalone User Risc Boot Test Started");
-
- // Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
-
- repeat (2) @(posedge clock);
- #1;
- // Remove all the reset
- $display("STATUS: Working with Both core Risc core 0 & 1 ");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h31F);
-
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (22) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
-
-
- $display("Monitor: Reading Back the expected value");
- // User RISC core expect to write these value in global
- // register, read back and decide on pass fail
- // 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
-
- test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
-
-
-
- $display("###################################################");
- if(test_fail == 0) begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
- `endif
- end else begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
- `endif
- end
- $display("###################################################");
- $finish;
- end
-
- initial begin
wb_rst_i <= 1'b1;
#100;
wb_rst_i <= 1'b0; // Release reset
end
+
+
+initial
+begin
+
+ #200; // Wait for reset removal
+ repeat (10) @(posedge clock);
+ $display("Monitor: Standalone User Basic Test Started");
+
+ repeat (2) @(posedge clock);
+
+ test_fail=0;
+ fork
+ begin
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+ // Setting Lock Bit Individually and clearing it imediatly
+ for(i=0; i < 15; i = i+1) begin
+ read_data = 'h0;
+ // Step-1: Wait for Semaphore lock bit to '1'
+ while(read_data[0] == 0) begin
+ @(posedge clock) ;
+ wb_user_core_read(`ADDR_SPACE_SEMA+ (i*4),read_data);
+ end
+ // Step-2: Check is Really Lock Bit it Set the corresponding lock status
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 1<< i);
+ // Step-3: Clear the Lock Bit
+ wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),1);
+ // Step-4: Check is Really Lock Bit it Cleared the corresponding lock status
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 0);
+
+ end
+ // Setting all Lock Bit and clearing it end
+ exp_data = 'h0;
+ for(i=0; i < 15; i = i+1) begin
+ read_data = 'h0;
+ // Step-1: Wait for Semaphore lock bit to '1'
+ while(read_data[0] == 0) begin
+ @(posedge clock) ;
+ wb_user_core_read(`ADDR_SPACE_SEMA+(i*4),read_data);
+ end
+ exp_data = exp_data | (1<< i);
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data);
+ end
+ // Step-2: Check all 15 Sema bit set
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h7FFF);
+ exp_data = 32'h7FFF;
+ for(i=0; i < 15; i = i+1) begin
+ // Step-3: clear the Sema Bit
+ wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),32'h1);
+ exp_data = exp_data ^ (1<< i);
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data);
+ end
+ // Step-3: All hardware lock bit is cleared
+ wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h0);
+ end
+
+ begin
+ repeat (30000) @(posedge clock);
+ // $display("+1000 cycles");
+ test_fail = 1;
+ end
+ join_any
+ disable fork; //disable pending fork activity
+
+
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: Semaphore Test (GL) Passed");
+ `else
+ $display("Monitor: Semaphore Test (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: Semaphore Test (GL) Failed");
+ `else
+ $display("Monitor: Semaphore Test (RTL) Failed");
+ `endif
+ end
+ $display("###################################################");
+ #100
+ $finish;
+end
+
+
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;
+
user_project_wrapper u_top(
`ifdef USE_POWER_PINS
.vccd1(USER_VDD1V8), // User area 1 1.8V supply
.vssd1(VSS), // User area 1 digital ground
`endif
.wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
+ .user_clock2 (clock2), // Real-time clock
.wb_rst_i (wb_rst_i), // Regular Reset signal
.wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
@@ -231,47 +274,11 @@
// All standard cell need power hook-up for functionality work
initial begin
+
end
`endif
-//------------------------------------------------------
-// Integrate the Serial flash with qurd support to
-// user core using the gpio pads
-// ----------------------------------------------------
- wire flash_clk = io_out[24];
- wire flash_csb = io_out[25];
- // Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[29];
- wire #1 io_oeb_30 = io_oeb[30];
- wire #1 io_oeb_31 = io_oeb[31];
- wire #1 io_oeb_32 = io_oeb[32];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
-
- assign io_in[29] = flash_io0;
- assign io_in[30] = flash_io1;
- assign io_in[31] = flash_io2;
- assign io_in[32] = flash_io3;
-
- // Quard flash
- s25fl256s #(.mem_file_name("user_mcore.hex"),
- .otp_file_name("none"),
- .TimingModel("S25FL512SAGMFI010_F_30pF"))
- u_spi_flash_256mb (
- // Data Inputs/Outputs
- .SI (flash_io0),
- .SO (flash_io1),
- // Controls
- .SCK (flash_clk),
- .CSNeg (flash_csb),
- .WPNeg (flash_io2),
- .HOLDNeg (flash_io3),
- .RSTNeg (!wb_rst_i)
-
- );
@@ -406,5 +413,4 @@
`endif
**/
endmodule
-`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
index a0e0fb5..95e4e51 100644
--- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v
+++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -154,19 +154,19 @@
$display("Monitor: Writing expected value");
test_fail = 0;
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c
index 62546a8..3f36137 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec.c
+++ b/verilog/dv/user_sram_exec/user_sram_exec.c
@@ -20,42 +20,26 @@
#define uint32_t long
#define uint16_t int
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000)
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004)
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008)
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C)
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010)
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014)
-#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018)
-#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C)
-#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020)
-#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024)
-#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
-#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
-#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
-#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
-#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
-#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
-#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
-#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
-#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
-#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
-#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
-#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
-#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
-#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
-#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
-#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
-#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
-#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
+#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
+#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
+#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
+#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
+#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
+#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
+#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
+#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
+#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
+#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
+#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
// -------------------------------------------------------------------------
// Test copying code into SRAM and running it from there.
// -------------------------------------------------------------------------
void test_function()
{
- reg_mprj_globl_reg24 = 0x33445566; // Sig-3
- reg_mprj_globl_reg25 = 0x44556677; // Sig-4
+ reg_mprj_globl_soft2 = 0x33445566; // Sig-2
+ reg_mprj_globl_soft3 = 0x44556677; // Sig-3
return;
}
@@ -70,18 +54,18 @@
src_ptr = &test_function;
dst_ptr = func;
- reg_mprj_globl_reg22 = 0x11223344; // Sig-1
+ reg_mprj_globl_soft0 = 0x11223344; // Sig-0
while (src_ptr < &main) {
*(dst_ptr++) = *(src_ptr++);
}
// Call the routine in SRAM
- reg_mprj_globl_reg23 = 0x22334455; // Sig-2
+ reg_mprj_globl_soft1 = 0x22334455; // Sig-1
((void(*)())func)();
- reg_mprj_globl_reg26 = 0x55667788;
- reg_mprj_globl_reg27 = 0x66778899;
+ reg_mprj_globl_soft4 = 0x55667788; // Sig-4
+ reg_mprj_globl_soft5 = 0x66778899; // Sig-5
// Signal end of test
}
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index 2aaad02..a8f6568 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -137,10 +137,10 @@
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
@@ -162,12 +162,12 @@
// 0x3000002C = 0x66778899;
test_fail = 0;
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899);
diff --git a/verilog/dv/user_sspi/.sspi_task.v.swp b/verilog/dv/user_sspi/.sspi_task.v.swp
deleted file mode 100644
index ecd1440..0000000
--- a/verilog/dv/user_sspi/.sspi_task.v.swp
+++ /dev/null
Binary files differ
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index c8e3f5c..eee28ca 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -142,14 +142,14 @@
// Enable SPI Multi Functional Ports
// wire cfg_spim_enb = cfg_multi_func_sel[10];
// wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11];
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h7C00);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h7C00);
repeat (2) @(posedge clock);
#1;
// Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
test_fail = 0;
@@ -448,6 +448,11 @@
);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK
+
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
@@ -456,7 +461,7 @@
`endif
//------------------------------------------------------
-// Integrate the Serial flash with qurd support to
+// Integrate the Serial flash with quad support to
// user core using the gpio pads
// ----------------------------------------------------
wire flash_io1;
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index b27d655..5a4f0ab 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -146,13 +146,13 @@
// Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
// config 1us based on system clock - 1000/25ns = 40
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
// Enable Timer Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h700);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h700);
test_fail = 0;
repeat (200) @(posedge clock);
@@ -160,25 +160,25 @@
$display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us");
test_step = 1;
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_0063);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_00C7);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_012B);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_0063);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_012B);
timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300);
$display("Checking the Timer Interrupt generation and clearing");
// Disable the Timer - To avoid multiple interrupt generation
// during status check and interrupt clearing
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
- wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
$display("STATUS: Timer Interrupt detected ");
// Clearing the Timer Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
- wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700);
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
$display("ERROR: Timer Interrupt not cleared ");
test_fail = 1;
@@ -192,25 +192,25 @@
$display("Step-2, Timer-0: 1us * 200 = 200us; Timer-1: 300us; Timer-2: 400us");
test_step = 2;
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_00C7);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_012B);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_018F);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_012B);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_018F);
timer_monitor(OneUsPeriod*200,OneUsPeriod*300,OneUsPeriod*400);
$display("Checking the Timer Interrupt generation and clearing");
// Disable the Timer - To avoid multiple interrupt generation
// during status check and interrupt clearing
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7);
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
- wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin
$display("STATUS: Timer Interrupt detected ");
// Clearing the Timer Interrupt
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700);
- wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700);
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin
$display("ERROR: Timer Interrupt not cleared ");
test_fail = 1;
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index e0656e9..0096617 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -146,7 +146,8 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(0, user_uart_tb);
+ $dumpvars(1, user_uart_tb);
+ $dumpvars(1, user_uart_tb.u_top);
end
`endif
@@ -176,23 +177,23 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable UART Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end else if(d_risc_id == 2) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
end else if(d_risc_id == 3) begin
$display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
@@ -299,6 +300,11 @@
);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK
+
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 44587e4..6a2d3c5 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -176,23 +176,23 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable UART Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h200);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h143);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h243);
end else if(d_risc_id == 2) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h443);
end else if(d_risc_id == 3) begin
$display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h84F);
end
repeat (100) @(posedge clock); // wait for Processor Get Ready
@@ -299,6 +299,11 @@
);
+// SSPI Slave I/F
+assign io_in[0] = 1'b1; // RESET
+assign io_in[16] = 1'b0 ; // SPIS SCK
+
+
`ifndef GL // Drive Power for Hold Fix Buf
// All standard cell need power hook-up for functionality work
initial begin
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 40d7b07..4ed2f00 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -195,19 +195,19 @@
$display("Monitor: Writing expected value");
test_fail = 0;
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788);
- uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788);
+ uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899);
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index 5974990..98115f7 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -176,7 +176,7 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable SPI Multi Functional Ports
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h400);
repeat (2) @(posedge clock);
#1;
@@ -188,7 +188,7 @@
// Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
- wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h03F);
test_fail = 0;
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 5ae8623..3ec839e 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -53,7 +53,7 @@
export TOOLS ?= /opt/riscv32i
export GCC_PATH ?= $(TOOLS)/bin
-export GCC_PREFIX?= riscv32-unknown-linux-gnu
+GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 03a5799..642303c 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -98,31 +98,32 @@
reg_mprj_wbhost_reg0 = 0x1;
// Remove Reset
- reg_pinmux_gbl_cfg0 = 0x01f;
+ reg_glbl_cfg0 = 0x01f;
- if (reg_pinmux_chip_id != 0x82682301) bFail = 1;
+ if (reg_glbl_chip_id != 0x82682501) bFail = 1;
+ if (bFail == 1) reg_mprj_datal = 0xAB610000;
// write software write & read Register
- reg_pinmux_soft_reg_1 = 0x11223344;
- reg_pinmux_soft_reg_2 = 0x22334455;
- reg_pinmux_soft_reg_3 = 0x33445566;
- reg_pinmux_soft_reg_4 = 0x44556677;
- reg_pinmux_soft_reg_5 = 0x55667788;
- reg_pinmux_soft_reg_6 = 0x66778899;
+ reg_glbl_soft_reg_0 = 0x11223344;
+ reg_glbl_soft_reg_1 = 0x22334455;
+ reg_glbl_soft_reg_2 = 0x33445566;
+ reg_glbl_soft_reg_3 = 0x44556677;
+ reg_glbl_soft_reg_4 = 0x55667788;
+ reg_glbl_soft_reg_5 = 0x66778899;
- if (reg_pinmux_soft_reg_1 != 0x11223344) bFail = 1;
- if (bFail == 1) reg_mprj_datal = 0xAB610000;
- if (reg_pinmux_soft_reg_2 != 0x22334455) bFail = 1;
+ if (reg_glbl_soft_reg_0 != 0x11223344) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB620000;
- if (reg_pinmux_soft_reg_3 != 0x33445566) bFail = 1;
+ if (reg_glbl_soft_reg_1 != 0x22334455) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB630000;
- if (reg_pinmux_soft_reg_4 != 0x44556677) bFail = 1;
+ if (reg_glbl_soft_reg_2 != 0x33445566) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB640000;
- if (reg_pinmux_soft_reg_5 != 0x55667788) bFail = 1;
+ if (reg_glbl_soft_reg_3 != 0x44556677) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB650000;
- if (reg_pinmux_soft_reg_6 != 0x66778899) bFail = 1;
+ if (reg_glbl_soft_reg_4 != 0x55667788) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB660000;
+ if (reg_glbl_soft_reg_5 != 0x66778899) bFail = 1;
+ if (bFail == 1) reg_mprj_datal = 0xAB670000;
if(bFail == 0) {
reg_mprj_datal = 0xAB6A0000;
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 2876d64..d355b07 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -117,7 +117,7 @@
#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
#else
-$(USER_PROJECT_VERILOG)/gl/pinmux.v
+$(USER_PROJECT_VERILOG)/gl/pinmux_top.v
#endif
##################################################
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 5e4aeb0..01f8d3c 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -7,11 +7,19 @@
+incdir+$(USER_PROJECT_VERILOG)/dv/model
+incdir+$(USER_PROJECT_VERILOG)/dv/agents
$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
--v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
@@ -45,6 +53,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_clkgen.sv
-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v
index e4a87a1..b9a093e 100755
--- a/verilog/rtl/lib/registers.v
+++ b/verilog/rtl/lib/registers.v
@@ -288,6 +288,45 @@
endmodule
/*********************************************************************
+ module: generic 16b register
+***********************************************************************/
+module gen_16b_reg (
+ //List of Inputs
+ cs,
+ we,
+ data_in,
+ reset_n,
+ clk,
+
+ //List of Outs
+ data_out
+ );
+
+ parameter RESET_DEFAULT = 16'h0;
+ input [1:0] we;
+ input cs;
+ input [15:0] data_in;
+ input reset_n;
+ input clk;
+ output [15:0] data_out;
+
+
+ reg [15:0] data_out;
+
+always @ (posedge clk or negedge reset_n) begin
+ if (reset_n == 1'b0) begin
+ data_out <= RESET_DEFAULT ;
+ end
+ else begin
+ if(cs && we[0]) data_out[7:0] <= data_in[7:0];
+ if(cs && we[1]) data_out[15:8] <= data_in[15:8];
+ end
+end
+
+
+endmodule
+
+/*********************************************************************
module: generic 32b register
***********************************************************************/
module gen_32b_reg (
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
new file mode 100644
index 0000000..d91ff4e
--- /dev/null
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -0,0 +1,437 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Global Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// Hold all the Global and PinMux Register ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+module glbl_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Global Reset control
+ output logic [1:0] cpu_core_rst_n ,
+ output logic cpu_intf_rst_n ,
+ output logic qspim_rst_n ,
+ output logic sspim_rst_n ,
+ output logic [1:0] uart_rst_n ,
+ output logic i2cm_rst_n ,
+ output logic usb_rst_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [3:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ input logic [1:0] ext_intr_in ,
+
+ // Risc configuration
+ output logic [15:0] irq_lines ,
+ output logic soft_irq ,
+ output logic [2:0] user_irq ,
+ input logic usb_intr ,
+ input logic i2cm_intr ,
+
+ output logic [15:0] cfg_riscv_ctrl ,
+ output logic [31:0] cfg_multi_func_sel ,// multifunction pins
+
+
+ input logic [2:0] timer_intr ,
+ input logic gpio_intr
+ );
+
+
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en;
+logic [4:0] sw_addr; // addressing 16 registers
+logic [31:0] sw_reg_wdata;
+logic [3:0] wr_be ;
+
+logic [31:0] reg_out;
+logic [31:0] reg_0; // Chip ID
+logic [31:0] reg_1; // Global Reg-0
+logic [31:0] reg_2; // Global Reg-1
+logic [31:0] reg_3; // Global Interrupt Mask
+logic [31:0] reg_4; // Global Interrupt Status
+logic [31:0] reg_5; // Multi Function Sel
+logic [31:0] reg_6; // Software Reg-0
+logic [31:0] reg_7; // Software Reg-1
+logic [31:0] reg_8; // Software Reg-2
+logic [31:0] reg_9; // Software Reg-3
+logic [31:0] reg_10; // Software Reg-4
+logic [31:0] reg_11; // Software Reg-5
+
+
+logic cs_int;
+
+
+assign sw_addr = reg_addr ;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign wr_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
+wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
+wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
+
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
+wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
+wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
+wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
+
+//-----------------------------------------------------------------------
+// Individual register assignments
+//-----------------------------------------------------------------------
+
+// Chip ID
+// chip-id[3:0] mapping
+// 0 - YIFIVE (MPW-2)
+// 1 - Riscdunio (MPW-3)
+// 2 - Riscdunio (MPW-4)
+// 3 - Riscdunio (MPW-5)
+// 4 - Riscdunio (MPW-6)
+// 5 - Riscdunio (MPW-7)
+// 6 - Riscdunio (MPW-8)
+// 7 - Riscdunio (MPW-9)
+
+wire [15:0] manu_id = 16'h8268; // Asci value of RD
+wire [3:0] total_core = 4'h2;
+wire [3:0] chip_id = 4'h5;
+wire [7:0] chip_rev = 8'h01;
+
+assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
+
+
+//------------------------------------------
+// reg-1: GLBL_CFG_0
+//------------------------------------------
+wire [31:0] cfg_glb_ctrl = reg_1;
+
+ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
+ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
+ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
+ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0]));
+ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
+ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
+ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1]));
+
+ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
+ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
+
+gen_32b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1 )
+ );
+
+//----------------------------------------------
+// reg-2: GLBL_CFG_1
+//------------------------------------------
+
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2 )
+ );
+
+assign cfg_riscv_ctrl = reg_2[31:16];
+
+//-----------------------------------------------------------------------
+// reg-3 : Global Interrupt Mask
+//-----------------------------------------------------------------------
+
+gen_32b_reg #(32'h0) u_reg_3 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_3 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_3 )
+ );
+
+//-----------------------------------------------------------------------
+// reg-4 : Global Interrupt Status
+//-----------------------------------------------------------------
+assign irq_lines = reg_3[15:0] & reg_4[15:0];
+assign soft_irq = reg_3[16] & reg_4[16];
+assign user_irq = reg_3[19:17]& reg_4[19:17];
+
+
+generic_register #(8,0 ) u_reg4_be0 (
+ .we ({8{sw_wr_en_4 &
+ wr_be[0] }} ),
+ .data_in (sw_reg_wdata[7:0] ),
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_4[7:0] )
+ );
+
+
+wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]};
+
+generic_intr_stat_reg #(.WD(8),
+ .RESET_DEFAULT(0)) u_reg4_be1 (
+ //inputs
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .reg_we ({8{sw_wr_en_4 & reg_ack &
+ wr_be[1] }} ),
+ .reg_din (sw_reg_wdata[15:8] ),
+ .hware_req (hware_intr_req ),
+
+ //outputs
+ .data_out (reg_4[15:8] )
+ );
+
+
+
+generic_register #(4,0 ) u_reg4_be2 (
+ .we ({4{sw_wr_en_4 &
+ wr_be[2] }} ),
+ .data_in (sw_reg_wdata[19:16]),
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_4[19:16] )
+ );
+
+assign reg_4[31:20] = '0;
+
+
+//-----------------------------------------------------------------------
+// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins
+//-----------------------------------------------------------------------
+assign cfg_multi_func_sel = reg_5[31:0]; // to be used for read
+
+
+gen_32b_reg #(32'h0) u_reg_5 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_5 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_5 )
+ );
+
+//-----------------------------------------
+// Software Reg-0 : ASCI Representation of RISC = 32'h8273_8343
+// ----------------------------------------
+gen_32b_reg #(32'h8273_8343) u_reg_6 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_6 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_6 )
+ );
+
+//-----------------------------------------
+// Software Reg-1, Release date: <DAY><MONTH><YEAR>
+// ----------------------------------------
+gen_32b_reg #(32'h1508_2022) u_reg_7 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_7 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_7 )
+ );
+
+//-----------------------------------------
+// Software Reg-2: Poject Revison 5.0 = 0005000
+// ----------------------------------------
+gen_32b_reg #(32'h0005_0000) u_reg_8 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_8 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_8 )
+ );
+
+//-----------------------------------------
+// Software Reg-3
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_9 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_9 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_9 )
+ );
+
+//-----------------------------------------
+// Software Reg-4
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_10 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_10 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_10 )
+ );
+
+//-----------------------------------------
+// Software Reg-5
+// ----------------------------------------
+gen_32b_reg #(32'h0) u_reg_11 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_11 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_11 )
+ );
+
+
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ 4'b0011 : reg_out [31:0] = reg_3 [31:0];
+ 4'b0100 : reg_out [31:0] = reg_4 [31:0];
+ 4'b0101 : reg_out [31:0] = reg_5 [31:0];
+ 4'b0110 : reg_out [31:0] = reg_6 [31:0];
+ 4'b0111 : reg_out [31:0] = reg_7 [31:0];
+ 4'b1000 : reg_out [31:0] = reg_8 [31:0];
+ 4'b1001 : reg_out [31:0] = reg_9 [31:0];
+ 4'b1010 : reg_out [31:0] = reg_10 [31:0];
+ 4'b1011 : reg_out [31:0] = reg_11 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_control.sv b/verilog/rtl/pinmux/src/gpio_control.sv
deleted file mode 100644
index 4c917dc..0000000
--- a/verilog/rtl/pinmux/src/gpio_control.sv
+++ /dev/null
@@ -1,44 +0,0 @@
-
-// GPIO Interrupt Generation
-module gpio_intr (
- input logic mclk ,// System clk
- input logic h_reset_n ,// system reset
- input logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data
- input logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this
- input logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg
- input logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level
- input logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt
- input logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt
-
-
- output logic [31:0] pad_gpio_out ,// GPIO O/P to the gpio cfg reg
- output logic [31:0] gpio_int_event // to the cfg interrupt status reg
-
-);
-
-
-integer i;
-//-----------------------------------------------------------------------
-// Logic for interrupt detection
-//-----------------------------------------------------------------------
-
-reg [31:0] local_gpio_int_event; // to the cfg interrupt status reg
-always @(cfg_gpio_data_in or cfg_gpio_negedge_int_sel or cfg_gpio_posedge_int_sel
- or gpio_prev_indata)
-begin
- for (i=0; i<32; i=i+1)
- begin
- // looking for rising edge int
- local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i]
- & cfg_gpio_data_in[i]) |
- (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] &
- ~cfg_gpio_data_in[i]));
- // looking for falling edge int
- end
-end
-
-assign gpio_int_event = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg
-
-assign pad_gpio_out = cfg_gpio_out_data[31:0] ;// O/P on the GPIO bus
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv
new file mode 100644
index 0000000..be61923
--- /dev/null
+++ b/verilog/rtl/pinmux/src/gpio_reg.sv
@@ -0,0 +1,325 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// GPIO Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+module gpio_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [3:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+
+ input logic [31:0] gpio_in_data ,
+ output logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data
+ input logic [31:0] gpio_int_event ,
+ output logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg
+ output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
+ output logic [31:0] cfg_gpio_out_type ,// GPIO Type, Unused
+ output logic [31:0] cfg_multi_func_sel ,// GPIO Multi function type
+ output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt
+ output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt
+ output logic [31:00] cfg_gpio_data_in ,
+
+ output logic gpio_intr
+
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [3:0] sw_addr ; // addressing 16 registers
+logic [31:0] sw_reg_wdata ;
+logic [3:0] sw_be ;
+
+logic [31:0] reg_out ;
+logic [31:0] reg_0 ; // GPIO Direction Select
+logic [31:0] reg_1 ; // GPIO TYPE - Unused
+logic [31:0] reg_2 ; // GPIO IN DATA
+logic [31:0] reg_3 ; // GPIO OUT DATA
+logic [31:0] reg_4 ; // GPIO INTERRUPT STATUS/CLEAR
+logic [31:0] reg_5 ; // GPIO INTERRUPT SET
+logic [31:0] reg_6 ; // GPIO INTERRUPT MASK
+logic [31:0] reg_7 ; // GPIO POSEDGE INTERRUPT SEL
+logic [31:0] reg_8 ; // GPIO NEGEDGE INTERRUPT SEL
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
+wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
+wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
+wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
+wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_dir_sel
+//-----------------------------------------------------------------------
+assign cfg_gpio_dir_sel = reg_0[31:0]; // data to the GPIO O/P pins
+
+gen_32b_reg #(32'h0) u_reg_0 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_0 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_type
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_type = reg_1[31:0]; // Un-used
+
+gen_32b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1 )
+ );
+//-----------------------------------------------------------------------
+// Logic for gpio_data_in
+//-----------------------------------------------------------------------
+logic [31:0] gpio_in_data_s;
+logic [31:0] gpio_in_data_ss;
+// Double Sync the gpio pin data for edge detection
+always @ (posedge mclk or negedge h_reset_n)
+begin
+ if (h_reset_n == 1'b0) begin
+ reg_2 <= 'h0 ;
+ gpio_in_data_s <= 32'd0;
+ gpio_in_data_ss <= 32'd0;
+ end
+ else begin
+ gpio_in_data_s <= gpio_in_data;
+ gpio_in_data_ss <= gpio_in_data_s;
+ reg_2 <= gpio_in_data_ss;
+ end
+end
+
+
+assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect
+assign gpio_prev_indata = gpio_in_data_ss;
+
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_out_data
+//-----------------------------------------------------------------------
+assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk
+
+gen_32b_reg #(32'h0) u_reg_3 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_3 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_3 )
+ );
+
+
+
+//--------------------------------------------------------
+// Interrupt Status Generation
+// Note: Reg_4 --> Interrupt Status Register, Writting '1' will clear the
+// corresponding interrupt status bit. Writting '0' has no
+// effect
+// Reg_5 --> Writting one to this register will set the interrupt in
+// interrupt status register (reg_4), Writting '0' does not has any
+// effect.
+/// Always update int_status, even if no register write is occuring.
+// Interrupt posting is higher priority than int clear by host
+//--------------------------------------------------------
+wire [31:0] gpio_int_status = reg_4;
+
+generic_intr_stat_reg #(.WD(32),
+ .RESET_DEFAULT(0)) u_reg_4 (
+ //inputs
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .reg_we ({
+ {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
+ {8{sw_wr_en_4 & reg_ack & sw_be[2]}},
+ {8{sw_wr_en_4 & reg_ack & sw_be[1]}},
+ {8{sw_wr_en_4 & reg_ack & sw_be[0]}}
+ } ),
+ .reg_din (sw_reg_wdata[31:0] ),
+ .hware_req (gpio_int_event | {
+ {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[31:24],
+ {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[23:16],
+ {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[15:8] ,
+ {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[7:0]
+ } ),
+
+ //outputs
+ .data_out (reg_4[31:0] )
+ );
+//-------------------------------------------------
+// Returns same value as interrupt status register
+//------------------------------------------------
+
+assign reg_5 = reg_4;
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_int_mask : GPIO interrupt mask
+//-----------------------------------------------------------------------
+wire [31:0] cfg_gpio_int_mask = reg_6[31:0]; // to be used for read
+
+assign gpio_intr = ( | (reg_4 & reg_6) ); // interrupt pin to the RISC
+
+
+// Register-11
+gen_32b_reg #(32'h0) u_reg_6 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_6 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_6 )
+ );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_posedge_int_sel : Enable posedge GPIO interrupt
+//-----------------------------------------------------------------------
+assign cfg_gpio_posedge_int_sel = reg_7[31:0]; // to be used for read
+gen_32b_reg #(32'h0) u_reg_7 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_7 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_7 )
+ );
+//-----------------------------------------------------------------------
+// Logic for cfg_gpio_negedge_int_sel : Enable negedge GPIO interrupt
+//-----------------------------------------------------------------------
+assign cfg_gpio_negedge_int_sel = reg_8[31:0]; // to be used for read
+gen_32b_reg #(32'h0) u_reg_8 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_8 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_8 )
+ );
+
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [3:0])
+ 4'b0000 : reg_out [31:0] = reg_0 [31:0];
+ 4'b0001 : reg_out [31:0] = reg_1 [31:0];
+ 4'b0010 : reg_out [31:0] = reg_2 [31:0];
+ 4'b0011 : reg_out [31:0] = reg_3 [31:0];
+ 4'b0100 : reg_out [31:0] = reg_4 [31:0];
+ 4'b0101 : reg_out [31:0] = reg_5 [31:0];
+ 4'b0110 : reg_out [31:0] = reg_6 [31:0];
+ 4'b0111 : reg_out [31:0] = reg_7 [31:0];
+ 4'b1000 : reg_out [31:0] = reg_8 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv
new file mode 100644
index 0000000..0a7fd02
--- /dev/null
+++ b/verilog/rtl/pinmux/src/gpio_top.sv
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// GPIO Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+/// ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+module gpio_top (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [3:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ output logic [31:0] cfg_gpio_dir_sel,
+ input logic [31:0] pad_gpio_in,
+ output logic [31:0] pad_gpio_out,
+
+ output logic gpio_intr
+
+ );
+
+
+logic [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data
+logic [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg
+logic [31:0] cfg_gpio_out_type ;// GPIO Type, Unused
+logic [31:0] cfg_multi_func_sel ;// GPIO Multi function type
+logic [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt
+logic [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt
+logic [31:00] cfg_gpio_data_in ;
+logic [31:0] gpio_int_event ;
+
+
+gpio_reg u_reg (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_rdata ),
+ .reg_ack (reg_ack ),
+
+ // GPIO input pins
+ .gpio_in_data (pad_gpio_in ),
+ .gpio_prev_indata (gpio_prev_indata ),
+ .gpio_int_event (gpio_int_event ),
+
+ // GPIO config pins
+ .cfg_gpio_out_data (cfg_gpio_out_data ),
+ .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
+ .cfg_gpio_out_type (cfg_gpio_out_type ),
+ .cfg_gpio_posedge_int_sel (cfg_gpio_posedge_int_sel),
+ .cfg_gpio_negedge_int_sel (cfg_gpio_negedge_int_sel),
+ .cfg_multi_func_sel (cfg_multi_func_sel ),
+ .cfg_gpio_data_in (cfg_gpio_data_in ),
+
+ .gpio_intr (gpio_intr )
+
+
+ );
+
+
+gpio_intr_gen u_gpio_intr (
+ // System Signals
+ // Inputs
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // GPIO cfg input pins
+ .gpio_prev_indata (gpio_prev_indata ),
+ .cfg_gpio_data_in (cfg_gpio_data_in ),
+ .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
+ .cfg_gpio_out_data (cfg_gpio_out_data ),
+ .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel),
+ .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel),
+
+
+ // GPIO output pins
+ .pad_gpio_out (pad_gpio_out ),
+ .gpio_int_event (gpio_int_event )
+ );
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index e36556c..54c0ef9 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -17,13 +17,13 @@
//
//////////////////////////////////////////////////////////////////////
//// ////
-//// Pinmux ////
+//// Pinmux ////
//// ////
//// This file is part of the riscduino cores project ////
//// https://github.com/dineshannayya/riscduino.git ////
//// ////
//// Description ////
-//// PinMux Manages all the pin multiplexing ////
+//// Manages all the pin multiplexing ////
//// ////
//// To Do: ////
//// nothing ////
@@ -32,482 +32,9 @@
//// - Dinesh Annayya, dinesha@opencores.org ////
//// ////
//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
-//// initial version ////
-//// 0.2 - 6 April 2021, Dinesh A ////
-//// 1. SSPI CS# increased from 1 to 4 ////
-// 2. UART I/F increase from 1 to 2 ////
-//// 0.3 - 8 July 2022, Dinesh A ////
-//// In ardunio, SPI chip select are control through ////
-//// GPIO, So we have moved the Auto generated SPI CS ////
-//// different config bit. I2C config position moved from////
-//// bit[14] to bit [15] ////
-//// 0.4 - 20 July 2022, Dinesh A ////
-//// On Power On, If RESET* = 0, then system will enter ////
-//// in to SPIS slave mode to support boot ////
+//// 0.1 - 16th Aug 2022, Dinesh A ////
+//// Seperated the pinmux from pinmux_top module ////
//////////////////////////////////////////////////////////////////////
-
-module pinmux (
- `ifdef USE_POWER_PINS
- input logic vccd1,// User area 1 1.8V supply
- input logic vssd1,// User area 1 digital ground
- `endif
- // clock skew adjust
- input logic [3:0] cfg_cska_pinmux,
- input logic wbd_clk_int,
- output logic wbd_clk_pinmux,
- // System Signals
- // Inputs
- input logic mclk,
- input logic h_reset_n,
-
- // Global Reset control
- output logic [1:0] cpu_core_rst_n ,
- output logic cpu_intf_rst_n ,
- output logic qspim_rst_n ,
- output logic sspim_rst_n ,
- output logic [1:0] uart_rst_n ,
- output logic i2cm_rst_n ,
- output logic usb_rst_n ,
-
- output logic [15:0] cfg_riscv_ctrl,
-
- // Reg Bus Interface Signal
- input logic reg_cs,
- input logic reg_wr,
- input logic [7:0] reg_addr,
- input logic [31:0] reg_wdata,
- input logic [3:0] reg_be,
-
- // Outputs
- output logic [31:0] reg_rdata,
- output logic reg_ack,
-
- // Risc configuration
- output logic [15:0] irq_lines,
- output logic soft_irq,
- output logic [2:0] user_irq,
- input logic usb_intr,
- input logic i2cm_intr,
-
- // Digital IO
- output logic [37:0] digital_io_out,
- output logic [37:0] digital_io_oen,
- input logic [37:0] digital_io_in,
-
- // SFLASH I/F
- input logic sflash_sck,
- input logic [3:0] sflash_ss,
- input logic [3:0] sflash_oen,
- input logic [3:0] sflash_do,
- output logic [3:0] sflash_di,
-
- // SSRAM I/F - Temp Masked
- //input logic ssram_sck,
- //input logic ssram_ss,
- //input logic [3:0] ssram_oen,
- //input logic [3:0] ssram_do,
- //output logic [3:0] ssram_di,
-
- // USB I/F
- input logic usb_dp_o,
- input logic usb_dn_o,
- input logic usb_oen,
- output logic usb_dp_i,
- output logic usb_dn_i,
-
- // UART I/F
- input logic [1:0] uart_txd,
- output logic [1:0] uart_rxd,
-
- // I2CM I/F
- input logic i2cm_clk_o,
- output logic i2cm_clk_i,
- input logic i2cm_clk_oen,
- input logic i2cm_data_oen,
- input logic i2cm_data_o,
- output logic i2cm_data_i,
-
- // SPI MASTER
- input logic spim_sck,
- input logic [3:0] spim_ssn,
- input logic spim_miso,
- output logic spim_mosi,
-
- // SPI SLAVE
- output logic spis_sck,
- output logic spis_ssn,
- input logic spis_miso,
- output logic spis_mosi,
-
- // UART MASTER I/F
- output logic uartm_rxd ,
- input logic uartm_txd ,
-
- output logic pulse1m_mclk,
- output logic [31:0] pinmux_debug,
-
- input logic dbg_clk_mon
-
- );
-
-
-
-logic sreset_n; // Sync Reset
-
-/* clock pulse */
-//********************************************************
-logic pulse_1us ; // 1 UsSecond Pulse for waveform Generator
-logic pulse_1ms ; // 1 UsSecond Pulse for waveform Generator
-logic pulse_1s ; // 1Second Pulse for waveform Generator
-logic [9:0] cfg_pulse_1us ; // 1us pulse generation config
-
-
-//---------------------------------------------------------
-// Timer Register
-// -------------------------------------------------------
-logic [2:0] cfg_timer_update ; // CPU write to timer register
-logic [31:0] cfg_timer0 ; // Timer-0 register
-logic [31:0] cfg_timer1 ; // Timer-1 register
-logic [31:0] cfg_timer2 ; // Timer-2 register
-logic [2:0] timer_intr ;
-
-//---------------------------------------------------
-// 6 PWM variabled
-//---------------------------------------------------
-
-logic [5:0] pwm_wfm ;
-logic [5:0] cfg_pwm_enb ;
-logic [15:0] cfg_pwm0_high ;
-logic [15:0] cfg_pwm0_low ;
-logic [15:0] cfg_pwm1_high ;
-logic [15:0] cfg_pwm1_low ;
-logic [15:0] cfg_pwm2_high ;
-logic [15:0] cfg_pwm2_low ;
-logic [15:0] cfg_pwm3_high ;
-logic [15:0] cfg_pwm3_low ;
-logic [15:0] cfg_pwm4_high ;
-logic [15:0] cfg_pwm4_low ;
-logic [15:0] cfg_pwm5_high ;
-logic [15:0] cfg_pwm5_low ;
-
-
-wire [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data
-wire [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg
-wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
-wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused
-wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type
-wire [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt
-wire [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt
-wire [31:00] cfg_gpio_data_in ;
-
-
-reg [7:0] port_a_in; // PORT A Data In
-reg [7:0] port_b_in; // PORT B Data In
-reg [7:0] port_c_in; // PORT C Data In
-reg [7:0] port_d_in; // PORT D Data In
-
-wire [7:0] port_a_out; // PORT A Data Out
-wire [7:0] port_b_out; // PORT B Data Out
-wire [7:0] port_c_out; // PORT C Data Out
-wire [7:0] port_d_out; // PORT D Data Out
-wire [31:0] pad_gpio_in; // GPIO data input from PAD
-wire [31:0] pad_gpio_out; // GPIO Data out towards PAD
-wire [31:0] gpio_int_event; // GPIO Interrupt indication
-reg [1:0] ext_intr_in; // External PAD level interrupt
-
-// GPIO to PORT Mapping
-assign pad_gpio_in[7:0] = port_a_in;
-assign pad_gpio_in[15:8] = port_b_in;
-assign pad_gpio_in[23:16] = port_c_in;
-assign pad_gpio_in[31:24] = port_d_in;
-
-assign port_a_out = pad_gpio_out[7:0];
-assign port_b_out = pad_gpio_out[15:8];
-assign port_c_out = pad_gpio_out[23:16];
-assign port_d_out = pad_gpio_out[31:24];
-
-assign pinmux_debug = '0; // Todo: Need to fix
-
-// SSRAM I/F - Temp masked
-//input logic ssram_sck,
-//input logic ssram_ss,
-//input logic [3:0] ssram_oen,
-//input logic [3:0] ssram_do,
-//output logic [3:0] ssram_di,
-
-// pinmux clock skew control
-clk_skew_adjust u_skew_pinmux
- (
-`ifdef USE_POWER_PINS
- .vccd1 (vccd1 ),// User area 1 1.8V supply
- .vssd1 (vssd1 ),// User area 1 digital ground
-`endif
- .clk_in (wbd_clk_int ),
- .sel (cfg_cska_pinmux ),
- .clk_out (wbd_clk_pinmux )
- );
-
-reset_sync u_rst_sync (
- .scan_mode (1'b0 ),
- .dclk (mclk ), // Destination clock domain
- .arst_n (h_reset_n ), // active low async reset
- .srst_n (sreset_n )
- );
-
-gpio_intr_gen u_gpio_intr (
- // System Signals
- // Inputs
- .mclk (mclk ),
- .h_reset_n (sreset_n ),
-
- // GPIO cfg input pins
- .gpio_prev_indata (gpio_prev_indata ),
- .cfg_gpio_data_in (cfg_gpio_data_in ),
- .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
- .cfg_gpio_out_data (cfg_gpio_out_data ),
- .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel),
- .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel),
-
-
- // GPIO output pins
- .pad_gpio_out (pad_gpio_out ),
- .gpio_int_event (gpio_int_event )
- );
-
-
-// 1us pulse
-pulse_gen_type2 #(.WD(10)) u_pulse_1us (
-
- .clk_pulse_o (pulse_1us ),
- .clk (mclk ),
- .reset_n (sreset_n ),
- .cfg_max_cnt (cfg_pulse_1us )
-
- );
-
-// 1millisecond pulse
-pulse_gen_type1 u_pulse_1ms (
-
- .clk_pulse_o (pulse_1ms ),
- .clk (mclk ),
- .reset_n (sreset_n ),
- .trigger (pulse_1us )
-
- );
-
-// 1 second pulse
-pulse_gen_type1 u_pulse_1s (
-
- .clk_pulse_o (pulse_1s ),
- .clk (mclk ),
- .reset_n (sreset_n ),
- .trigger (pulse_1ms )
-
- );
-
-
-// Timer
-
-wire cfg_timer0_enb = cfg_timer0[16];
-wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17];
-wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
-
-timer u_timer_0
- (
- .reset_n (sreset_n ),// system syn reset
- .mclk (mclk ),// master clock
- .pulse_1us (pulse_1us ),
- .pulse_1ms (pulse_1ms ),
- .pulse_1s (pulse_1s ),
-
- .cfg_timer_update (cfg_timer_update[0] ),
- .cfg_timer_enb (cfg_timer0_enb ),
- .cfg_timer_compare (cfg_timer0_compare ),
- .cfg_timer_clksel (cfg_timer0_clksel ),// to select the timer 1us/1ms reference clock
-
- .timer_intr (timer_intr[0] )
- );
-
-// Timer
-wire cfg_timer1_enb = cfg_timer1[16];
-wire [1:0] cfg_timer1_clksel = cfg_timer1[18:17];
-wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
-timer u_timer_1
- (
- .reset_n (sreset_n ),// system syn reset
- .mclk (mclk ),// master clock
- .pulse_1us (pulse_1us ),
- .pulse_1ms (pulse_1ms ),
- .pulse_1s (pulse_1s ),
-
- .cfg_timer_update (cfg_timer_update[1] ),
- .cfg_timer_enb (cfg_timer1_enb ),
- .cfg_timer_compare (cfg_timer1_compare ),
- .cfg_timer_clksel (cfg_timer1_clksel ),// to select the timer 1us/1ms reference clock
-
- .timer_intr (timer_intr[1] )
- );
-
-// Timer
-wire cfg_timer2_enb = cfg_timer2[16];
-wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
-wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
-timer u_timer_2
- (
- .reset_n (sreset_n ),// system syn reset
- .mclk (mclk ),// master clock
- .pulse_1us (pulse_1us ),
- .pulse_1ms (pulse_1ms ),
- .pulse_1s (pulse_1s ),
-
- .cfg_timer_update (cfg_timer_update[2] ),
- .cfg_timer_enb (cfg_timer2_enb ),
- .cfg_timer_compare (cfg_timer2_compare ),
- .cfg_timer_clksel (cfg_timer2_clksel ),// to select the timer 1us/1ms reference clock
-
- .timer_intr (timer_intr[2] )
- );
-
-
-pinmux_reg u_pinmux_reg(
- // System Signals
- // Inputs
- .mclk (mclk ),
- .h_reset_n (sreset_n ),
-
- .cpu_core_rst_n (cpu_core_rst_n ),
- .cpu_intf_rst_n (cpu_intf_rst_n ),
- .qspim_rst_n (qspim_rst_n ),
- .sspim_rst_n (sspim_rst_n ),
- .uart_rst_n (uart_rst_n ),
- .i2cm_rst_n (i2cm_rst_n ),
- .usb_rst_n (usb_rst_n ),
-
- .cfg_riscv_ctrl (cfg_riscv_ctrl ),
-
-
- // Reg read/write Interface Inputs
- .reg_cs (reg_cs ),
- .reg_wr (reg_wr ),
- .reg_addr (reg_addr ),
- .reg_wdata (reg_wdata ),
- .reg_be (reg_be ),
-
- .reg_rdata (reg_rdata ),
- .reg_ack (reg_ack ),
-
- .ext_intr_in (ext_intr_in ),
-
- .irq_lines (irq_lines ),
- .soft_irq (soft_irq ),
- .user_irq (user_irq ),
- .usb_intr (usb_intr ),
- .i2cm_intr (i2cm_intr ),
-
- .cfg_pulse_1us (cfg_pulse_1us ),
-
-
- .cfg_pwm0_high (cfg_pwm0_high ),
- .cfg_pwm0_low (cfg_pwm0_low ),
- .cfg_pwm1_high (cfg_pwm1_high ),
- .cfg_pwm1_low (cfg_pwm1_low ),
- .cfg_pwm2_high (cfg_pwm2_high ),
- .cfg_pwm2_low (cfg_pwm2_low ),
- .cfg_pwm3_high (cfg_pwm3_high ),
- .cfg_pwm3_low (cfg_pwm3_low ),
- .cfg_pwm4_high (cfg_pwm4_high ),
- .cfg_pwm4_low (cfg_pwm4_low ),
- .cfg_pwm5_high (cfg_pwm5_high ),
- .cfg_pwm5_low (cfg_pwm5_low ),
-
- // GPIO input pins
- .gpio_in_data (pad_gpio_in ),
- .gpio_int_event (gpio_int_event ),
-
- // GPIO config pins
- .cfg_gpio_out_data (cfg_gpio_out_data ),
- .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
- .cfg_gpio_out_type (cfg_gpio_out_type ),
- .cfg_gpio_posedge_int_sel (cfg_gpio_posedge_int_sel),
- .cfg_gpio_negedge_int_sel (cfg_gpio_negedge_int_sel),
- .cfg_multi_func_sel (cfg_multi_func_sel ),
- .cfg_gpio_data_in (cfg_gpio_data_in ),
-
-
- // Outputs
- .gpio_prev_indata (gpio_prev_indata ) ,
-
-
- .timer_intr (timer_intr ),
- .cfg_timer_update (cfg_timer_update ),
- .cfg_timer0 (cfg_timer0 ),
- .cfg_timer1 (cfg_timer1 ),
- .cfg_timer2 (cfg_timer2 )
-
-
- );
-
-
-// 6 PWM Waveform Generator
-pwm u_pwm_0 (
- .waveform (pwm_wfm[0] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[0] ),
- .cfg_pwm_high (cfg_pwm0_high ),
- .cfg_pwm_low (cfg_pwm0_low )
- );
-
-pwm u_pwm_1 (
- .waveform (pwm_wfm[1] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[1] ),
- .cfg_pwm_high (cfg_pwm1_high ),
- .cfg_pwm_low (cfg_pwm1_low )
- );
-
-pwm u_pwm_2 (
- .waveform (pwm_wfm[2] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[2] ),
- .cfg_pwm_high (cfg_pwm2_high ),
- .cfg_pwm_low (cfg_pwm2_low )
- );
-
-pwm u_pwm_3 (
- .waveform (pwm_wfm[3] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[3] ),
- .cfg_pwm_high (cfg_pwm3_high ),
- .cfg_pwm_low (cfg_pwm3_low )
- );
-pwm u_pwm_4 (
- .waveform (pwm_wfm[4] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[4] ),
- .cfg_pwm_high (cfg_pwm4_high ),
- .cfg_pwm_low (cfg_pwm4_low )
- );
-pwm u_pwm_5 (
- .waveform (pwm_wfm[5] ),
- .h_reset_n (sreset_n ),
- .mclk (mclk ),
- .pulse1m_mclk (pulse_1ms ),
- .cfg_pwm_enb (cfg_pwm_enb[5] ),
- .cfg_pwm_high (cfg_pwm5_high ),
- .cfg_pwm_low (cfg_pwm5_low )
- );
-
/************************************************
* Pin Mapping ATMGE CONFIG
* ATMEGA328 caravel Pin Mapping
@@ -559,6 +86,99 @@
* Pin-1 RESET is not supported as there is no suppport for fuse config
**************/
+module pinmux (
+ // Digital IO
+ output logic [37:0] digital_io_out ,
+ output logic [37:0] digital_io_oen ,
+ input logic [37:0] digital_io_in ,
+
+ // Config
+ input logic [31:0] cfg_gpio_dir_sel ,
+ input logic [31:0] cfg_multi_func_sel ,
+
+ output logic[5:0] cfg_pwm_enb ,
+ input logic [5:0] pwm_wfm ,
+ output logic [1:0] ext_intr_in , // External PAD level interrupt
+ output logic [31:0] pad_gpio_in , // GPIO data input from PAD
+ input logic [31:0] pad_gpio_out , // GPIO Data out towards PAD
+
+ // SFLASH I/F
+ input logic sflash_sck ,
+ input logic [3:0] sflash_ss ,
+ input logic [3:0] sflash_oen ,
+ input logic [3:0] sflash_do ,
+ output logic [3:0] sflash_di ,
+
+ // SSRAM I/F - Temp Masked
+ //input logic ssram_sck,
+ //input logic ssram_ss,
+ //input logic [3:0] ssram_oen,
+ //input logic [3:0] ssram_do,
+ //output logic [3:0] ssram_di,
+
+ // USB I/F
+ input logic usb_dp_o,
+ input logic usb_dn_o,
+ input logic usb_oen,
+ output logic usb_dp_i,
+ output logic usb_dn_i,
+
+ // UART I/F
+ input logic [1:0] uart_txd,
+ output logic [1:0] uart_rxd,
+
+ // I2CM I/F
+ input logic i2cm_clk_o,
+ output logic i2cm_clk_i,
+ input logic i2cm_clk_oen,
+ input logic i2cm_data_oen,
+ input logic i2cm_data_o,
+ output logic i2cm_data_i,
+
+ // SPI MASTER
+ input logic spim_sck,
+ input logic [3:0] spim_ssn,
+ input logic spim_miso,
+ output logic spim_mosi,
+
+ // SPI SLAVE
+ output logic spis_sck,
+ output logic spis_ssn,
+ input logic spis_miso,
+ output logic spis_mosi,
+
+ // UART MASTER I/F
+ output logic uartm_rxd ,
+ input logic uartm_txd ,
+
+ input logic dbg_clk_mon
+
+ );
+
+
+
+reg [7:0] port_a_in; // PORT A Data In
+reg [7:0] port_b_in; // PORT B Data In
+reg [7:0] port_c_in; // PORT C Data In
+reg [7:0] port_d_in; // PORT D Data In
+
+wire [7:0] port_a_out; // PORT A Data Out
+wire [7:0] port_b_out; // PORT B Data Out
+wire [7:0] port_c_out; // PORT C Data Out
+wire [7:0] port_d_out; // PORT D Data Out
+
+// GPIO to PORT Mapping
+assign pad_gpio_in[7:0] = port_a_in;
+assign pad_gpio_in[15:8] = port_b_in;
+assign pad_gpio_in[23:16] = port_c_in;
+assign pad_gpio_in[31:24] = port_d_in;
+
+assign port_a_out = pad_gpio_out[7:0];
+assign port_b_out = pad_gpio_out[15:8];
+assign port_c_out = pad_gpio_out[23:16];
+assign port_d_out = pad_gpio_out[31:24];
+
+
assign cfg_pwm_enb = cfg_multi_func_sel[5:0];
wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6];
wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8];
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
deleted file mode 100644
index 744c07b..0000000
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ /dev/null
@@ -1,902 +0,0 @@
-//////////////////////////////////////////////////////////////////////////////
-// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
-//
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Pinmux Register ////
-//// ////
-//// This file is part of the riscduino cores project ////
-//// https://github.com/dineshannayya/riscduino.git ////
-//// ////
-//// Description ////
-//// Hold all the Global and PinMux Register ////
-//// ////
-//// To Do: ////
-//// nothing ////
-//// ////
-//// Author(s): ////
-//// - Dinesh Annayya, dinesha@opencores.org ////
-//// ////
-//// Revision : ////
-//// 0.1 - 16th Feb 2021, Dinesh A ////
-//// initial version ////
-//////////////////////////////////////////////////////////////////////
-//
-module pinmux_reg (
- // System Signals
- // Inputs
- input logic mclk,
- input logic h_reset_n,
-
- // Global Reset control
- output logic [1:0] cpu_core_rst_n ,
- output logic cpu_intf_rst_n ,
- output logic qspim_rst_n ,
- output logic sspim_rst_n ,
- output logic [1:0] uart_rst_n ,
- output logic i2cm_rst_n ,
- output logic usb_rst_n ,
-
- // Reg Bus Interface Signal
- input logic reg_cs,
- input logic reg_wr,
- input logic [7:0] reg_addr,
- input logic [31:0] reg_wdata,
- input logic [3:0] reg_be,
-
- // Outputs
- output logic [31:0] reg_rdata,
- output logic reg_ack,
-
- input logic [1:0] ext_intr_in,
-
- // Risc configuration
- output logic [15:0] irq_lines,
- output logic soft_irq,
- output logic [2:0] user_irq,
- input logic usb_intr,
- input logic i2cm_intr,
-
- output logic [9:0] cfg_pulse_1us,
- output logic [15:0] cfg_riscv_ctrl,
-
- //---------------------------------------------------
- // 6 PWM Configuration
- //---------------------------------------------------
-
- output logic [15:0] cfg_pwm0_high ,
- output logic [15:0] cfg_pwm0_low ,
- output logic [15:0] cfg_pwm1_high ,
- output logic [15:0] cfg_pwm1_low ,
- output logic [15:0] cfg_pwm2_high ,
- output logic [15:0] cfg_pwm2_low ,
- output logic [15:0] cfg_pwm3_high ,
- output logic [15:0] cfg_pwm3_low ,
- output logic [15:0] cfg_pwm4_high ,
- output logic [15:0] cfg_pwm4_low ,
- output logic [15:0] cfg_pwm5_high ,
- output logic [15:0] cfg_pwm5_low ,
-
- // GPIO input pins
- input logic [31:0] gpio_in_data ,// GPIO I/P pins
- input logic [31:0] gpio_int_event ,// from gpio control blk
-
-
-
- // GPIO config pins
- output logic [31:0] cfg_gpio_out_data ,// to the GPIO control block
- output logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this
- output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level
- output logic [31:0] cfg_gpio_out_type ,// O/P is static , '1' : waveform
- output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt
- output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt
- output logic [31:0] cfg_multi_func_sel ,// multifunction pins
-
- // Outputs
- output logic [31:0] gpio_prev_indata ,// prv data from GPIO I/P pins
-
- input logic [2:0] timer_intr ,
- output logic [2:0] cfg_timer_update ,
- output logic [31:0] cfg_timer0 ,
- output logic [31:0] cfg_timer1 ,
- output logic [31:0] cfg_timer2
- );
-
-
-
-//-----------------------------------------------------------------------
-// Internal Wire Declarations
-//-----------------------------------------------------------------------
-
-logic sw_rd_en ;
-logic sw_wr_en;
-logic [4:0] sw_addr; // addressing 16 registers
-logic [31:0] sw_reg_wdata;
-logic [3:0] wr_be ;
-
-logic [31:0] reg_out;
-logic [31:0] reg_0; // Chip ID
-logic [31:0] reg_1; // Risc Fuse Id
-logic [31:0] reg_2; // Global config-1
-logic [31:0] reg_3; // Global config-2
-logic [31:0] reg_4; // GPIO Read Data
-logic [31:0] reg_5; // GPIO Output Data
-logic [31:0] reg_6; // GPIO Dir Sel
-logic [31:0] reg_7; // GPIO Type
-logic [31:0] reg_8; // Interrupt
-logic [31:0] reg_9; // GPIO Interrupt Status
-logic [31:0] reg_10; // GPIO Interrupt Status
-logic [31:0] reg_11; // GPIO Interrupt Mask
-logic [31:0] reg_12; // GPIO Posedge Interrupt Select
-logic [31:0] reg_13; // GPIO Negedge Interrupt Select
-logic [31:0] reg_14; // Software-Reg_14
-logic [31:0] reg_15; // Software-Reg_15
-logic [31:0] reg_16; // PWN-0 Config
-logic [31:0] reg_17; // PWN-1 Config
-logic [31:0] reg_18; // PWN-2 Config
-logic [31:0] reg_19; // PWN-3 Config
-logic [31:0] reg_20; // PWN-4 Config
-logic [31:0] reg_21; // PWN-5 Config
-logic [31:0] reg_22; // Software-Reg1
-logic [31:0] reg_23; // Software-Reg2
-logic [31:0] reg_24; // Software-Reg3
-logic [31:0] reg_25; // Software-Reg4
-logic [31:0] reg_26; // Software-Reg5
-logic [31:0] reg_27; // Software-Reg6
-logic [31:0] reg_28; // Software-Reg6
-logic [31:0] reg_29; // Software-Reg6
-logic [31:0] reg_30; // Software-Reg6
-
-
-logic cs_int;
-logic gpio_intr;
-
-
-assign sw_addr = reg_addr [6:2];
-assign sw_rd_en = reg_cs & !reg_wr;
-assign sw_wr_en = reg_cs & reg_wr;
-assign wr_be = reg_be;
-assign sw_reg_wdata = reg_wdata;
-
-
-//-----------------------------------
-// Edge detection for Logic Bist
-// ----------------------------------
-
-logic wb_req;
-logic wb_req_d;
-logic wb_req_pedge;
-
-always_ff @(negedge h_reset_n or posedge mclk) begin
- if ( h_reset_n == 1'b0 ) begin
- wb_req <= '0;
- wb_req_d <= '0;
- end else begin
- wb_req <= reg_cs && (reg_ack == 0) ;
- wb_req_d <= wb_req;
- end
-end
-
-// Detect pos edge of request
-assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1);
-
-
-always @ (posedge mclk or negedge h_reset_n)
-begin : preg_out_Seq
- if (h_reset_n == 1'b0) begin
- reg_rdata <= 'h0;
- reg_ack <= 1'b0;
- end else if (reg_cs && !reg_ack) begin
- reg_rdata <= reg_out ;
- reg_ack <= 1'b1;
- end else begin
- reg_ack <= 1'b0;
- end
-end
-
-
-
-//-----------------------------------------------------------------------
-// register read enable and write enable decoding logic
-//-----------------------------------------------------------------------
-wire sw_wr_en_0 = sw_wr_en & (sw_addr == 5'h0);
-wire sw_wr_en_1 = sw_wr_en & (sw_addr == 5'h1);
-wire sw_wr_en_2 = sw_wr_en & (sw_addr == 5'h2);
-wire sw_wr_en_3 = sw_wr_en & (sw_addr == 5'h3);
-wire sw_wr_en_4 = sw_wr_en & (sw_addr == 5'h4);
-wire sw_wr_en_5 = sw_wr_en & (sw_addr == 5'h5);
-wire sw_wr_en_6 = sw_wr_en & (sw_addr == 5'h6);
-wire sw_wr_en_7 = sw_wr_en & (sw_addr == 5'h7);
-wire sw_wr_en_8 = sw_wr_en & (sw_addr == 5'h8);
-wire sw_wr_en_9 = sw_wr_en & (sw_addr == 5'h9);
-wire sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA);
-wire sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB);
-wire sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC);
-wire sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD);
-wire sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE);
-wire sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF);
-wire sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10);
-wire sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11);
-wire sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12);
-wire sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13);
-wire sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14);
-wire sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15);
-
-wire sw_wr_en_22 = sw_wr_en & (sw_addr == 5'h16);
-wire sw_wr_en_23 = sw_wr_en & (sw_addr == 5'h17);
-wire sw_wr_en_24 = sw_wr_en & (sw_addr == 5'h18);
-wire sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19);
-wire sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A);
-wire sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B);
-wire sw_wr_en_28 = sw_wr_en & (sw_addr == 5'h1C);
-wire sw_wr_en_29 = sw_wr_en & (sw_addr == 5'h1D);
-wire sw_wr_en_30 = sw_wr_en & (sw_addr == 5'h1E);
-wire sw_wr_en_31 = sw_wr_en & (sw_addr == 5'h1F);
-
-wire sw_rd_en_28 = sw_rd_en & (sw_addr == 5'h1C);
-wire sw_rd_en_29 = sw_rd_en & (sw_addr == 5'h1D);
-wire sw_rd_en_30 = sw_rd_en & (sw_addr == 5'h1E);
-wire sw_rd_en_31 = sw_rd_en & (sw_addr == 5'h1F);
-
-
-//-----------------------------------------------------------------------
-// Individual register assignments
-//-----------------------------------------------------------------------
-
-
-// Chip ID
-// chip-id[3:0] mapping
-// 0 - YIFIVE (MPW-2)
-// 1 - Riscdunio (MPW-3)
-// 2 - Riscdunio (MPW-4)
-// 3 - Riscdunio (MPW-5)
-
-wire [15:0] manu_id = 16'h8268; // Asci value of RD
-wire [3:0] total_core = 4'h2;
-wire [3:0] chip_id = 4'h3;
-wire [7:0] chip_rev = 8'h01;
-
-assign reg_0 = {manu_id,total_core,chip_id,chip_rev};
-
-
-//------------------------------------------
-// reg-2: GLBL_CFG_0
-//------------------------------------------
-wire [31:0] cfg_glb_ctrl = reg_1;
-
-ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n));
-ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n));
-ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n));
-ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0]));
-ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n));
-ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n));
-ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1]));
-
-ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0]));
-ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1]));
-
-gen_32b_reg #(32'h0) u_reg_1 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_1 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_1 )
- );
-
-//----------------------------------------------
-// reg-2: GLBL_CFG_1
-//------------------------------------------
-
-gen_32b_reg #(32'h0) u_reg_2 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_2 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_2 )
- );
-
-assign cfg_pulse_1us = reg_2[9:0];
-assign cfg_riscv_ctrl = reg_2[31:16];
-
-//-----------------------------------------------------------------------
-// reg-3 : Global Interrupt Mask
-//-----------------------------------------------------------------------
-
-gen_32b_reg #(32'h0) u_reg_3 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_3 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_3 )
- );
-
-//-----------------------------------------------------------------------
-// reg-4 : Global Interrupt Status
-//-----------------------------------------------------------------
-assign irq_lines = reg_3[15:0] & reg_4[15:0];
-assign soft_irq = reg_3[16] & reg_4[16];
-assign user_irq = reg_3[19:17]& reg_4[19:17];
-
-
-generic_register #(8,0 ) u_reg4_be0 (
- .we ({8{sw_wr_en_4 &
- wr_be[0] }} ),
- .data_in (sw_reg_wdata[7:0] ),
- .reset_n (h_reset_n ),
- .clk (mclk ),
-
- //List of Outs
- .data_out (reg_4[7:0] )
- );
-
-
-wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]};
-
-generic_intr_stat_reg #(.WD(8),
- .RESET_DEFAULT(0)) u_reg4_be1 (
- //inputs
- .clk (mclk ),
- .reset_n (h_reset_n ),
- .reg_we ({8{sw_wr_en_4 & reg_ack &
- wr_be[1] }} ),
- .reg_din (sw_reg_wdata[15:8] ),
- .hware_req (hware_intr_req ),
-
- //outputs
- .data_out (reg_4[15:8] )
- );
-
-
-
-generic_register #(4,0 ) u_reg4_be2 (
- .we ({4{sw_wr_en_4 &
- wr_be[2] }} ),
- .data_in (sw_reg_wdata[19:16]),
- .reset_n (h_reset_n ),
- .clk (mclk ),
-
- //List of Outs
- .data_out (reg_4[19:16] )
- );
-
-assign reg_4[31:20] = '0;
-
-
-//-----------------------------------------------------------------------
-// Logic for gpio_data_in
-//-----------------------------------------------------------------------
-logic [31:0] gpio_in_data_s;
-logic [31:0] gpio_in_data_ss;
-// Double Sync the gpio pin data for edge detection
-always @ (posedge mclk or negedge h_reset_n)
-begin
- if (h_reset_n == 1'b0) begin
- reg_5 <= 'h0 ;
- gpio_in_data_s <= 32'd0;
- gpio_in_data_ss <= 32'd0;
- end
- else begin
- gpio_in_data_s <= gpio_in_data;
- gpio_in_data_ss <= gpio_in_data_s;
- reg_5 <= gpio_in_data_ss;
- end
-end
-
-
-assign cfg_gpio_data_in = reg_5[31:0]; // to be used for edge interrupt detect
-assign gpio_prev_indata = gpio_in_data_ss;
-
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_data
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_data = reg_6[31:0]; // data to the GPIO control blk
-
-gen_32b_reg #(32'h0) u_reg_6 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_6 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_6 )
- );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_dir_sel
-//-----------------------------------------------------------------------
-assign cfg_gpio_dir_sel = reg_7[31:0]; // data to the GPIO O/P pins
-
-gen_32b_reg #(32'h0) u_reg_7 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_7 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_7 )
- );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_out_type
-//-----------------------------------------------------------------------
-assign cfg_gpio_out_type = reg_8[31:0]; // to be used for read
-
-gen_32b_reg #(32'h0) u_reg_8 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_8 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_8 )
- );
-
-
-
-//-----------------------------------------------------------------------
-// Logic for cfg_int_status
-// Always update int_status, even if no register write is occuring.
-// Interrupt posting is higher priority than int clear by host
-//-----------------------------------------------------------------------
-wire [31:0] cfg_gpio_int_status = reg_9[31:0]; // to be used for read
-
-//--------------------------------------------------------
-// Interrupt Status Generation
-// Note: Reg_9 --> Interrupt Status Register, Writting '1' will clear the
-// corresponding interrupt status bit. Writting '0' has no
-// effect
-// Reg_10 --> Writting one to this register will set the interrupt in
-// interrupt status register (reg_9), Writting '0' does not has any
-// effect.
-/// Always update int_status, even if no register write is occuring.
-// Interrupt posting is higher priority than int clear by host
-//--------------------------------------------------------
-wire [31:0] gpio_int_status = reg_9;
-
-generic_intr_stat_reg #(.WD(32),
- .RESET_DEFAULT(0)) u_reg_9 (
- //inputs
- .clk (mclk ),
- .reset_n (h_reset_n ),
- .reg_we ({
- {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
- {8{sw_wr_en_9 & reg_ack & wr_be[2]}},
- {8{sw_wr_en_9 & reg_ack & wr_be[1]}},
- {8{sw_wr_en_9 & reg_ack & wr_be[0]}}
- } ),
- .reg_din (sw_reg_wdata[31:0] ),
- .hware_req (gpio_int_event | {
- {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[31:24],
- {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[23:16],
- {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[15:8] ,
- {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[7:0]
- } ),
-
- //outputs
- .data_out (reg_9[31:0] )
- );
-//-------------------------------------------------
-// Returns same value as interrupt status register
-//------------------------------------------------
-
-assign reg_10 = reg_9;
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_int_mask : GPIO interrupt mask
-//-----------------------------------------------------------------------
-wire [31:0] cfg_gpio_int_mask = reg_11[31:0]; // to be used for read
-
-assign gpio_intr = ( | (reg_9 & reg_11) ); // interrupt pin to the RISC
-
-
-// Register-11
-gen_32b_reg #(32'h0) u_reg_11 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_11 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_11 )
- );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_posedge_int_sel : Enable posedge GPIO interrupt
-//-----------------------------------------------------------------------
-assign cfg_gpio_posedge_int_sel = reg_12[31:0]; // to be used for read
-gen_32b_reg #(32'h0) u_reg_12 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_12 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_12 )
- );
-//-----------------------------------------------------------------------
-// Logic for cfg_gpio_negedge_int_sel : Enable negedge GPIO interrupt
-//-----------------------------------------------------------------------
-assign cfg_gpio_negedge_int_sel = reg_13[31:0]; // to be used for read
-gen_32b_reg #(32'h0) u_reg_13 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_13 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_13 )
- );
-
-//-----------------------------------------------------------------------
-// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins
-//-----------------------------------------------------------------------
-assign cfg_multi_func_sel = reg_14[31:0]; // to be used for read
-
-
-gen_32b_reg #(32'h0) u_reg_14 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_14 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_14 )
- );
-
-// Reg-15
-gen_32b_reg #(32'h0) u_reg_15 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_15 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_15 )
- );
-//-----------------------------------------------------------------------
-// Logic for PWM-0 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm0_low = reg_16[15:0]; // low period of w/f
-assign cfg_pwm0_high = reg_16[31:16]; // high period of w/f
-
-gen_32b_reg #(32'h0) u_reg_16 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_16 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_16 )
- );
-
-
-//-----------------------------------------------------------------------
-// Logic for PWM-1 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm1_low = reg_17[15:0]; // low period of w/f
-assign cfg_pwm1_high = reg_17[31:16]; // high period of w/f
-gen_32b_reg #(32'h0) u_reg_17 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_17 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_17 )
- );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-2 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm2_low = reg_18[15:0]; // low period of w/f
-assign cfg_pwm2_high = reg_18[31:16]; // high period of w/f
-gen_32b_reg #(32'h0) u_reg_18 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_18 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_18 )
- );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-3 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm3_low = reg_19[15:0]; // low period of w/f
-assign cfg_pwm3_high = reg_19[31:16]; // high period of w/f
-gen_32b_reg #(32'h0) u_reg_19 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_19 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_19 )
- );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-4 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm4_low = reg_20[15:0]; // low period of w/f
-assign cfg_pwm4_high = reg_20[31:16]; // high period of w/f
-
-gen_32b_reg #(32'h0) u_reg_20 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_20 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_20 )
- );
-
-//-----------------------------------------------------------------------
-// Logic for PWM-5 Config
-//-----------------------------------------------------------------------
-assign cfg_pwm5_low = reg_21[15:0]; // low period of w/f
-assign cfg_pwm5_high = reg_21[31:16]; // high period of w/f
-
-gen_32b_reg #(32'h0) u_reg_21 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_21 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_21 )
- );
-
-
-//-----------------------------------------
-// Software Reg-1 : ASCI Representation of RISC = 32'h8273_8343
-// ----------------------------------------
-gen_32b_reg #(32'h8273_8343) u_reg_22 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_22 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_22 )
- );
-
-//-----------------------------------------
-// Software Reg-2, Release date: <DAY><MONTH><YEAR>
-// ----------------------------------------
-gen_32b_reg #(32'h2007_2022) u_reg_23 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_23 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_23 )
- );
-
-//-----------------------------------------
-// Software Reg-3: Poject Revison 4.7 = 0004800
-// ----------------------------------------
-gen_32b_reg #(32'h0004_8000) u_reg_24 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_24 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_24 )
- );
-
-//-----------------------------------------
-// Software Reg-4
-// ----------------------------------------
-gen_32b_reg #(32'h0) u_reg_25 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_25 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_25 )
- );
-
-//-----------------------------------------
-// Software Reg-5
-// ----------------------------------------
-gen_32b_reg #(32'h0) u_reg_26 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_26 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_26 )
- );
-
-//-----------------------------------------
-// Software Reg-6
-// ----------------------------------------
-gen_32b_reg #(32'h0) u_reg_27 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_27 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_27 )
- );
-
-
-//-----------------------------------------------------------------------
-// reg-28
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-// In first cycle, local register will be updated
-// In second cycle, update indication sent to timer block
-// -----------------------------------------------------------------
-assign cfg_timer0 = reg_28[18:0];
-assign cfg_timer_update[0] = sw_wr_en_28 & reg_ack;
-
-gen_32b_reg #(32'h0) u_reg_28 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_28 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_28[31:0] )
- );
-
-//-----------------------------------------------------------------------
-// reg-29
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-// In first cycle, local register will be updated
-// In second cycle, update indication sent to timer block
-// -----------------------------------------------------------------
-assign cfg_timer1 = reg_29[18:0];
-assign cfg_timer_update[1] = sw_wr_en_29 & reg_ack;
-
-gen_32b_reg #(32'h0) u_reg_29 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_29 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_29[31:0] )
- );
-
-
-//-----------------------------------------------------------------------
-// reg-30
-// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
-// In first cycle, local register will be updated
-// In second cycle, update indication sent to timer block
-// -----------------------------------------------------------------
-assign cfg_timer2 = reg_30[18:0];
-assign cfg_timer_update[2] = sw_wr_en_30 & reg_ack;
-
-gen_32b_reg #(32'h0) u_reg_30 (
- //List of Inputs
- .reset_n (h_reset_n ),
- .clk (mclk ),
- .cs (sw_wr_en_30 ),
- .we (wr_be ),
- .data_in (sw_reg_wdata ),
-
- //List of Outs
- .data_out (reg_30[31:0] )
- );
-
-//-----------------------------------------------------------------------
-// Register Read Path Multiplexer instantiation
-//-----------------------------------------------------------------------
-
-always_comb
-begin
- reg_out [31:0] = 32'h0;
-
- case (sw_addr [4:0])
- 5'b00000 : reg_out [31:0] = reg_0 [31:0];
- 5'b00001 : reg_out [31:0] = reg_1 [31:0];
- 5'b00010 : reg_out [31:0] = reg_2 [31:0];
- 5'b00011 : reg_out [31:0] = reg_3 [31:0];
- 5'b00100 : reg_out [31:0] = reg_4 [31:0];
- 5'b00101 : reg_out [31:0] = reg_5 [31:0];
- 5'b00110 : reg_out [31:0] = reg_6 [31:0];
- 5'b00111 : reg_out [31:0] = reg_7 [31:0];
- 5'b01000 : reg_out [31:0] = reg_8 [31:0];
- 5'b01001 : reg_out [31:0] = reg_9 [31:0];
- 5'b01010 : reg_out [31:0] = reg_10 [31:0];
- 5'b01011 : reg_out [31:0] = reg_11 [31:0];
- 5'b01100 : reg_out [31:0] = reg_12 [31:0];
- 5'b01101 : reg_out [31:0] = reg_13 [31:0];
- 5'b01110 : reg_out [31:0] = reg_14 [31:0];
- 5'b01111 : reg_out [31:0] = reg_15 [31:0];
- 5'b10000 : reg_out [31:0] = reg_16 [31:0];
- 5'b10001 : reg_out [31:0] = reg_17 [31:0];
- 5'b10010 : reg_out [31:0] = reg_18 [31:0];
- 5'b10011 : reg_out [31:0] = reg_19 [31:0];
- 5'b10100 : reg_out [31:0] = reg_20 [31:0];
- 5'b10101 : reg_out [31:0] = reg_21 [31:0];
- 5'b10110 : reg_out [31:0] = reg_22 [31:0];
- 5'b10111 : reg_out [31:0] = reg_23 [31:0];
- 5'b11000 : reg_out [31:0] = reg_24 [31:0];
- 5'b11001 : reg_out [31:0] = reg_25 [31:0];
- 5'b11010 : reg_out [31:0] = reg_26 [31:0];
- 5'b11011 : reg_out [31:0] = reg_27 [31:0];
- 5'b11100 : reg_out [31:0] = reg_28 [31:0];
- 5'b11101 : reg_out [31:0] = reg_29 [31:0];
- 5'b11110 : reg_out [31:0] = reg_30 [31:0];
- 5'b11111 : reg_out [31:0] = 32'h0;
- default : reg_out [31:0] = 32'h0;
- endcase
-end
-
-
-endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
new file mode 100755
index 0000000..c84c1a7
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -0,0 +1,485 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Pinmux ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// PinMux Manages all the pin multiplexing ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 16th Feb 2021, Dinesh A ////
+//// initial version ////
+//// 0.2 - 6 April 2021, Dinesh A ////
+//// 1. SSPI CS# increased from 1 to 4 ////
+// 2. UART I/F increase from 1 to 2 ////
+//// 0.3 - 8 July 2022, Dinesh A ////
+//// In ardunio, SPI chip select are control through ////
+//// GPIO, So we have moved the Auto generated SPI CS ////
+//// different config bit. I2C config position moved from////
+//// bit[14] to bit [15] ////
+//// 0.4 - 20 July 2022, Dinesh A ////
+//// On Power On, If RESET* = 0, then system will enter ////
+//// in to SPIS slave mode to support boot ////
+//////////////////////////////////////////////////////////////////////
+
+module pinmux_top (
+ `ifdef USE_POWER_PINS
+ input logic vccd1,// User area 1 1.8V supply
+ input logic vssd1,// User area 1 digital ground
+ `endif
+ // clock skew adjust
+ input logic [3:0] cfg_cska_pinmux,
+ input logic wbd_clk_int,
+ output logic wbd_clk_pinmux,
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Global Reset control
+ output logic [1:0] cpu_core_rst_n ,
+ output logic cpu_intf_rst_n ,
+ output logic qspim_rst_n ,
+ output logic sspim_rst_n ,
+ output logic [1:0] uart_rst_n ,
+ output logic i2cm_rst_n ,
+ output logic usb_rst_n ,
+
+ output logic [15:0] cfg_riscv_ctrl,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [8:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ // Risc configuration
+ output logic [15:0] irq_lines,
+ output logic soft_irq,
+ output logic [2:0] user_irq,
+ input logic usb_intr,
+ input logic i2cm_intr,
+
+ // Digital IO
+ output logic [37:0] digital_io_out,
+ output logic [37:0] digital_io_oen,
+ input logic [37:0] digital_io_in,
+
+ // SFLASH I/F
+ input logic sflash_sck,
+ input logic [3:0] sflash_ss,
+ input logic [3:0] sflash_oen,
+ input logic [3:0] sflash_do,
+ output logic [3:0] sflash_di,
+
+ // SSRAM I/F - Temp Masked
+ //input logic ssram_sck,
+ //input logic ssram_ss,
+ //input logic [3:0] ssram_oen,
+ //input logic [3:0] ssram_do,
+ //output logic [3:0] ssram_di,
+
+ // USB I/F
+ input logic usb_dp_o,
+ input logic usb_dn_o,
+ input logic usb_oen,
+ output logic usb_dp_i,
+ output logic usb_dn_i,
+
+ // UART I/F
+ input logic [1:0] uart_txd,
+ output logic [1:0] uart_rxd,
+
+ // I2CM I/F
+ input logic i2cm_clk_o,
+ output logic i2cm_clk_i,
+ input logic i2cm_clk_oen,
+ input logic i2cm_data_oen,
+ input logic i2cm_data_o,
+ output logic i2cm_data_i,
+
+ // SPI MASTER
+ input logic spim_sck,
+ input logic [3:0] spim_ssn,
+ input logic spim_miso,
+ output logic spim_mosi,
+
+ // SPI SLAVE
+ output logic spis_sck,
+ output logic spis_ssn,
+ input logic spis_miso,
+ output logic spis_mosi,
+
+ // UART MASTER I/F
+ output logic uartm_rxd ,
+ input logic uartm_txd ,
+
+ output logic pulse1m_mclk,
+ output logic [31:0] pinmux_debug,
+
+ input logic dbg_clk_mon
+
+ );
+
+
+
+logic sreset_n; // Sync Reset
+
+/* clock pulse */
+//********************************************************
+logic pulse_1ms ; // 1 Milli Second Pulse for waveform Generator
+logic [5:0] cfg_pwm_enb ;
+
+
+//---------------------------------------------------------
+// Timer Register
+// -------------------------------------------------------
+logic [2:0] timer_intr ;
+
+//---------------------------------------------------
+// 6 PWM variabled
+//---------------------------------------------------
+
+logic [5:0] pwm_wfm ;
+
+
+wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output
+wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused
+wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type
+
+
+reg [7:0] port_a_in; // PORT A Data In
+reg [7:0] port_b_in; // PORT B Data In
+reg [7:0] port_c_in; // PORT C Data In
+reg [7:0] port_d_in; // PORT D Data In
+
+wire [7:0] port_a_out; // PORT A Data Out
+wire [7:0] port_b_out; // PORT B Data Out
+wire [7:0] port_c_out; // PORT C Data Out
+wire [7:0] port_d_out; // PORT D Data Out
+wire [31:0] pad_gpio_in; // GPIO data input from PAD
+wire [31:0] pad_gpio_out; // GPIO Data out towards PAD
+wire [31:0] gpio_int_event; // GPIO Interrupt indication
+reg [1:0] ext_intr_in; // External PAD level interrupt
+
+
+assign pinmux_debug = '0; // Todo: Need to fix
+
+//------------------------------------------------------
+// Register Map Decoding
+
+`define SEL_GLBL 3'b000 // GLOBAL REGISTER
+`define SEL_GPIO 3'b001 // GPIO REGISTER
+`define SEL_PWM 3'b010 // PWM REGISTER
+`define SEL_TIMER 3'b011 // TIMER REGISTER
+`define SEL_SEMA 3'b100 // SEMAPHORE REGISTER
+
+
+//----------------------------------------
+// Register Response Path Mux
+// --------------------------------------
+logic [31:0] reg_glbl_rdata;
+logic reg_glbl_ack;
+
+logic [31:0] reg_gpio_rdata;
+logic reg_gpio_ack;
+
+logic [31:0] reg_pwm_rdata;
+logic reg_pwm_ack;
+
+logic [31:0] reg_timer_rdata;
+logic reg_timer_ack;
+
+logic [15:0] reg_sema_rdata;
+logic reg_sema_ack;
+
+
+assign reg_rdata = (reg_addr[8:6] == `SEL_GLBL) ? {reg_glbl_rdata} :
+ (reg_addr[8:6] == `SEL_GPIO) ? {reg_gpio_rdata} :
+ (reg_addr[8:6] == `SEL_PWM) ? {reg_pwm_rdata} :
+ (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_rdata :
+ (reg_addr[8:6] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : 'h0;
+
+assign reg_ack = (reg_addr[8:6] == `SEL_GLBL) ? reg_glbl_ack :
+ (reg_addr[8:6] == `SEL_GPIO) ? reg_gpio_ack :
+ (reg_addr[8:6] == `SEL_PWM) ? reg_pwm_ack :
+ (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_ack :
+ (reg_addr[8:6] == `SEL_SEMA) ? reg_sema_ack : 1'b0;
+
+wire reg_glbl_cs = (reg_addr[8:6] == `SEL_GLBL) ? reg_cs : 1'b0;
+wire reg_gpio_cs = (reg_addr[8:6] == `SEL_GPIO) ? reg_cs : 1'b0;
+wire reg_pwm_cs = (reg_addr[8:6] == `SEL_PWM) ? reg_cs : 1'b0;
+wire reg_timer_cs = (reg_addr[8:6] == `SEL_TIMER)? reg_cs : 1'b0;
+wire reg_sema_cs = (reg_addr[8:6] == `SEL_SEMA) ? reg_cs : 1'b0;
+
+//---------------------------------------------------------------------
+
+// SSRAM I/F - Temp masked
+//input logic ssram_sck,
+//input logic ssram_ss,
+//input logic [3:0] ssram_oen,
+//input logic [3:0] ssram_do,
+//output logic [3:0] ssram_di,
+
+// pinmux clock skew control
+clk_skew_adjust u_skew_pinmux
+ (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1 ),// User area 1 1.8V supply
+ .vssd1 (vssd1 ),// User area 1 digital ground
+`endif
+ .clk_in (wbd_clk_int ),
+ .sel (cfg_cska_pinmux ),
+ .clk_out (wbd_clk_pinmux )
+ );
+
+reset_sync u_rst_sync (
+ .scan_mode (1'b0 ),
+ .dclk (mclk ), // Destination clock domain
+ .arst_n (h_reset_n ), // active low async reset
+ .srst_n (sreset_n )
+ );
+
+//------------------------------------------------------------------
+// Global Register
+//------------------------------------------------------------------
+glbl_reg u_glbl_reg(
+ // System Signals
+ // Inputs
+ .mclk (mclk ),
+ .h_reset_n (sreset_n ),
+
+ .cpu_core_rst_n (cpu_core_rst_n ),
+ .cpu_intf_rst_n (cpu_intf_rst_n ),
+ .qspim_rst_n (qspim_rst_n ),
+ .sspim_rst_n (sspim_rst_n ),
+ .uart_rst_n (uart_rst_n ),
+ .i2cm_rst_n (i2cm_rst_n ),
+ .usb_rst_n (usb_rst_n ),
+
+ .cfg_riscv_ctrl (cfg_riscv_ctrl ),
+ .cfg_multi_func_sel (cfg_multi_func_sel ),
+
+
+ // Reg read/write Interface Inputs
+ .reg_cs (reg_glbl_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ .reg_rdata (reg_glbl_rdata ),
+ .reg_ack (reg_glbl_ack ),
+
+ .ext_intr_in (ext_intr_in ),
+
+ .irq_lines (irq_lines ),
+ .soft_irq (soft_irq ),
+ .user_irq (user_irq ),
+ .usb_intr (usb_intr ),
+ .i2cm_intr (i2cm_intr ),
+
+
+
+ .timer_intr (timer_intr ),
+ .gpio_intr (gpio_intr )
+
+
+ );
+
+//-----------------------------------------------------------------------
+// GPIO Top
+//-----------------------------------------------------------------------
+gpio_top u_gpio(
+ // System Signals
+ // Inputs
+ .mclk ( mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_gpio_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_gpio_rdata ),
+ .reg_ack (reg_gpio_ack ),
+
+
+ .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
+ .pad_gpio_in (pad_gpio_in ),
+ .pad_gpio_out (pad_gpio_out ),
+
+ .gpio_intr (gpio_intr )
+
+
+ );
+
+//-----------------------------------------------------------------------
+// PWM Top
+//-----------------------------------------------------------------------
+pwm_top u_pwm(
+ // System Signals
+ // Inputs
+ .mclk ( mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_pwm_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[4:2] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_pwm_rdata ),
+ .reg_ack (reg_pwm_ack ),
+
+ .pulse_1ms (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb ),
+ .pwm_wfm (pwm_wfm )
+ );
+
+//-----------------------------------------------------------------------
+// Timer Top
+//-----------------------------------------------------------------------
+timer_top u_timer(
+ // System Signals
+ // Inputs
+ .mclk ( mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_timer_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[3:2] ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_timer_rdata ),
+ .reg_ack (reg_timer_ack ),
+
+ .pulse_1ms (pulse_1ms ),
+ .timer_intr (timer_intr )
+ );
+
+//-----------------------------------------------------------------------
+// Semaphore Register
+//-----------------------------------------------------------------------
+semaphore_reg u_semaphore(
+ // System Signals
+ // Inputs
+ .mclk ( mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_sema_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr[5:2] ),
+ .reg_wdata (reg_wdata[15:0] ),
+ .reg_be (reg_be[1:0] ),
+
+ // Outputs
+ .reg_rdata (reg_sema_rdata ),
+ .reg_ack (reg_sema_ack )
+ );
+
+
+pinmux u_pinmux (
+ // Digital IO
+ .digital_io_out (digital_io_out ),
+ .digital_io_oen (digital_io_oen ),
+ .digital_io_in (digital_io_in ),
+
+ // Config
+ .cfg_gpio_dir_sel (cfg_gpio_dir_sel ),
+ .cfg_multi_func_sel (cfg_multi_func_sel ),
+
+ .cfg_pwm_enb (cfg_pwm_enb ),
+ .pwm_wfm (pwm_wfm ),
+ .ext_intr_in (ext_intr_in ), // External PAD level interrupt
+ .pad_gpio_in (pad_gpio_in ), // GPIO data input from PAD
+ .pad_gpio_out (pad_gpio_out ), // GPIO Data out towards PAD
+
+ // SFLASH I/F
+ .sflash_sck (sflash_sck ),
+ .sflash_ss (sflash_ss ),
+ .sflash_oen (sflash_oen ),
+ .sflash_do (sflash_do ),
+ .sflash_di (sflash_di ),
+
+ // USB I/F
+ .usb_dp_o (usb_dp_o ),
+ .usb_dn_o (usb_dn_o ),
+ .usb_oen (usb_oen ),
+ .usb_dp_i (usb_dp_i ),
+ .usb_dn_i (usb_dn_i ),
+
+ // UART I/F
+ .uart_txd (uart_txd ),
+ .uart_rxd (uart_rxd ),
+
+ // I2CM I/F
+ .i2cm_clk_o (i2cm_clk_o ),
+ .i2cm_clk_i (i2cm_clk_i ),
+ .i2cm_clk_oen (i2cm_clk_oen ),
+ .i2cm_data_oen (i2cm_data_oen ),
+ .i2cm_data_o (i2cm_data_o ),
+ .i2cm_data_i (i2cm_data_i ),
+
+ // SPI MASTER
+ .spim_sck (spim_sck ),
+ .spim_ssn (spim_ssn ),
+ .spim_miso (spim_miso ),
+ .spim_mosi (spim_mosi ),
+
+ // SPI SLAVE
+ .spis_sck (spis_sck ),
+ .spis_ssn (spis_ssn ),
+ .spis_miso (spis_miso ),
+ .spis_mosi (spis_mosi ),
+
+ // UART MASTER I/F
+ .uartm_rxd (uartm_rxd ),
+ .uartm_txd (uartm_txd ),
+
+ .dbg_clk_mon (dbg_clk_mon )
+
+ );
+
+endmodule
+
+
diff --git a/verilog/rtl/pinmux/src/pwm_reg.sv b/verilog/rtl/pinmux/src/pwm_reg.sv
new file mode 100644
index 0000000..702c138
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pwm_reg.sv
@@ -0,0 +1,255 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PWM Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+module pwm_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [2:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ output logic [15:0] cfg_pwm0_high ,
+ output logic [15:0] cfg_pwm0_low ,
+ output logic [15:0] cfg_pwm1_high ,
+ output logic [15:0] cfg_pwm1_low ,
+ output logic [15:0] cfg_pwm2_high ,
+ output logic [15:0] cfg_pwm2_low ,
+ output logic [15:0] cfg_pwm3_high ,
+ output logic [15:0] cfg_pwm3_low ,
+ output logic [15:0] cfg_pwm4_high ,
+ output logic [15:0] cfg_pwm4_low ,
+ output logic [15:0] cfg_pwm5_high ,
+ output logic [15:0] cfg_pwm5_low
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [2:0] sw_addr ; // addressing 16 registers
+logic [31:0] sw_reg_wdata ;
+logic [3:0] sw_be ;
+
+logic [31:0] reg_out ;
+logic [31:0] reg_0 ; // CONFIG - Unused
+logic [31:0] reg_1 ; // PWM-REG-0
+logic [31:0] reg_2 ; // PWM-REG-1
+logic [31:0] reg_3 ; // PWM-REG-2
+logic [31:0] reg_4 ; // PWM-REG-3
+logic [31:0] reg_5 ; // PWM-REG-4
+logic [31:0] reg_6 ; // PWM-REG-5
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 3'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 3'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 3'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 3'h3);
+wire sw_wr_en_4 = sw_wr_en & (sw_addr == 3'h4);
+wire sw_wr_en_5 = sw_wr_en & (sw_addr == 3'h5);
+wire sw_wr_en_6 = sw_wr_en & (sw_addr == 3'h6);
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 3'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 3'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 3'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 3'h3);
+wire sw_rd_en_4 = sw_rd_en & (sw_addr == 3'h4);
+wire sw_rd_en_5 = sw_rd_en & (sw_addr == 3'h5);
+wire sw_rd_en_6 = sw_rd_en & (sw_addr == 3'h6);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+//--------------------------------------------
+// reg-0: Reserve for pwm global config
+//---------------------------------------------
+assign reg_0 = 'h0;
+//-----------------------------------------------------------------------
+// Logic for PWM-0 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm0_low = reg_1[15:0]; // low period of w/f
+assign cfg_pwm0_high = reg_1[31:16]; // high period of w/f
+
+gen_32b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1 )
+ );
+
+
+//-----------------------------------------------------------------------
+// Logic for PWM-1 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm1_low = reg_2[15:0]; // low period of w/f
+assign cfg_pwm1_high = reg_2[31:16]; // high period of w/f
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2 )
+ );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-2 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm2_low = reg_3[15:0]; // low period of w/f
+assign cfg_pwm2_high = reg_3[31:16]; // high period of w/f
+gen_32b_reg #(32'h0) u_reg_3 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_3 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_3 )
+ );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-3 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm3_low = reg_4[15:0]; // low period of w/f
+assign cfg_pwm3_high = reg_4[31:16]; // high period of w/f
+gen_32b_reg #(32'h0) u_reg_4 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_4 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_4 )
+ );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-4 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm4_low = reg_5[15:0]; // low period of w/f
+assign cfg_pwm4_high = reg_5[31:16]; // high period of w/f
+
+gen_32b_reg #(32'h0) u_reg_5 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_5 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_5 )
+ );
+
+//-----------------------------------------------------------------------
+// Logic for PWM-5 Config
+//-----------------------------------------------------------------------
+assign cfg_pwm5_low = reg_6[15:0]; // low period of w/f
+assign cfg_pwm5_high = reg_6[31:16]; // high period of w/f
+
+gen_32b_reg #(32'h0) u_reg_6 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_6 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_6 )
+ );
+
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [2:0])
+ 3'b000 : reg_out [31:0] = reg_0 [31:0];
+ 3'b001 : reg_out [31:0] = reg_1 [31:0];
+ 3'b010 : reg_out [31:0] = reg_2 [31:0];
+ 3'b011 : reg_out [31:0] = reg_3 [31:0];
+ 3'b100 : reg_out [31:0] = reg_4 [31:0];
+ 3'b101 : reg_out [31:0] = reg_5 [31:0];
+ 3'b110 : reg_out [31:0] = reg_6 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_top.sv b/verilog/rtl/pinmux/src/pwm_top.sv
new file mode 100644
index 0000000..2b8d3a5
--- /dev/null
+++ b/verilog/rtl/pinmux/src/pwm_top.sv
@@ -0,0 +1,172 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// PWM Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+/// Includes 6 PWM ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+module pwm_top (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [2:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+
+ input logic pulse_1ms,
+ input logic [5:0] cfg_pwm_enb,
+ output logic [5:0] pwm_wfm
+
+ );
+
+//---------------------------------------------------
+// 6 PWM variabled
+//---------------------------------------------------
+
+logic [15:0] cfg_pwm0_high ;
+logic [15:0] cfg_pwm0_low ;
+logic [15:0] cfg_pwm1_high ;
+logic [15:0] cfg_pwm1_low ;
+logic [15:0] cfg_pwm2_high ;
+logic [15:0] cfg_pwm2_low ;
+logic [15:0] cfg_pwm3_high ;
+logic [15:0] cfg_pwm3_low ;
+logic [15:0] cfg_pwm4_high ;
+logic [15:0] cfg_pwm4_low ;
+logic [15:0] cfg_pwm5_high ;
+logic [15:0] cfg_pwm5_low ;
+
+
+
+pwm_reg u_reg (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_rdata ),
+ .reg_ack (reg_ack ),
+
+ .cfg_pwm0_high (cfg_pwm0_high ),
+ .cfg_pwm0_low (cfg_pwm0_low ),
+ .cfg_pwm1_high (cfg_pwm1_high ),
+ .cfg_pwm1_low (cfg_pwm1_low ),
+ .cfg_pwm2_high (cfg_pwm2_high ),
+ .cfg_pwm2_low (cfg_pwm2_low ),
+ .cfg_pwm3_high (cfg_pwm3_high ),
+ .cfg_pwm3_low (cfg_pwm3_low ),
+ .cfg_pwm4_high (cfg_pwm4_high ),
+ .cfg_pwm4_low (cfg_pwm4_low ),
+ .cfg_pwm5_high (cfg_pwm5_high ),
+ .cfg_pwm5_low (cfg_pwm5_low )
+
+ );
+
+
+// 6 PWM Waveform Generator
+pwm u_pwm_0 (
+ .waveform (pwm_wfm[0] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[0] ),
+ .cfg_pwm_high (cfg_pwm0_high ),
+ .cfg_pwm_low (cfg_pwm0_low )
+ );
+
+pwm u_pwm_1 (
+ .waveform (pwm_wfm[1] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[1] ),
+ .cfg_pwm_high (cfg_pwm1_high ),
+ .cfg_pwm_low (cfg_pwm1_low )
+ );
+
+pwm u_pwm_2 (
+ .waveform (pwm_wfm[2] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[2] ),
+ .cfg_pwm_high (cfg_pwm2_high ),
+ .cfg_pwm_low (cfg_pwm2_low )
+ );
+
+pwm u_pwm_3 (
+ .waveform (pwm_wfm[3] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[3] ),
+ .cfg_pwm_high (cfg_pwm3_high ),
+ .cfg_pwm_low (cfg_pwm3_low )
+ );
+pwm u_pwm_4 (
+ .waveform (pwm_wfm[4] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[4] ),
+ .cfg_pwm_high (cfg_pwm4_high ),
+ .cfg_pwm_low (cfg_pwm4_low )
+ );
+pwm u_pwm_5 (
+ .waveform (pwm_wfm[5] ),
+ .h_reset_n (h_reset_n ),
+ .mclk (mclk ),
+ .pulse1m_mclk (pulse_1ms ),
+ .cfg_pwm_enb (cfg_pwm_enb[5] ),
+ .cfg_pwm_high (cfg_pwm5_high ),
+ .cfg_pwm_low (cfg_pwm5_low )
+ );
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/semaphore_reg.sv b/verilog/rtl/pinmux/src/semaphore_reg.sv
new file mode 100644
index 0000000..c347178
--- /dev/null
+++ b/verilog/rtl/pinmux/src/semaphore_reg.sv
@@ -0,0 +1,165 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Semaphore Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// A semaphore is a variable or abstract data type that ////
+//// provides a simple but useful abstraction for controlling ////
+//// access by multiple processes to a common resource in a ////
+//// parallel programming or multi-user environment. ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+/***************************************************************
+ Special Semaphore Register Implementation
+ Read access from 0 to 14 will return corresponsonding bit lock status.
+ If lock is free, then it return '1' and also lock the corresponding bit
+ If lock is busy, then it return '0'
+ Write & Read access with address 15 does normal write and read access,
+ this location should used for only debug purpose
+
+*****************************************************************/
+module semaphore_reg #(parameter DW = 16, // DATA WIDTH
+ parameter AW = $clog2(DW), // ADDRESS WIDTH
+ parameter BW = $clog2(AW) // BYTE WIDTH
+ ) (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [AW-1:0] reg_addr,
+ input logic [DW-1:0] reg_wdata,
+ input logic [BW-1:0] reg_be,
+
+ // Outputs
+ output logic [DW-1:0] reg_rdata,
+ output logic reg_ack
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [AW-1:0] sw_addr ; // addressing 16 registers
+logic [DW-1:0] sw_reg_wdata ;
+logic [BW-1:0] sw_be ;
+
+logic [DW-1:0] reg_out ;
+logic [DW-1:0] reg_0 ;
+logic sw_wr_en_0 ;
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out[DW-1:0] ;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+/***************************************************************
+ Special Semaphore Register Implementation
+ Read access from 0 to 30 will return corresponsonding bit lock status.
+ If lock is free, then it return '1' and lock the corresponding bit
+ If lock is busy, then it return '0' and lock the corresponding bit
+*****************************************************************/
+
+gen_16b_reg #('h0) u_reg_0 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_0 ),
+ .we (sw_be[BW-1:0] ),
+ .data_in (sw_reg_wdata[DW-1:0] ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+
+
+//-----------------------------------------------------------------------
+// Register Write Data
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ sw_reg_wdata = 'h0;
+ sw_wr_en_0 = 'b0;
+ sw_be = 'h0;
+
+ // Address 0xF, is Simple Write Register
+ if(sw_addr == {AW {1'b1}}) begin
+ sw_reg_wdata = reg_0;
+ sw_wr_en_0 = sw_wr_en & reg_ack;
+ sw_be = reg_be[BW-1:0];
+ end else begin // 0 to 0xE is Semaphore Register
+ if(sw_rd_en) begin // Read will always lock the bit '1'
+ sw_reg_wdata = (reg_0 | ( 1 << sw_addr)) ;
+ end else begin // To release the Lock Write with '1'
+ sw_reg_wdata = (reg_0 ^ ((reg_wdata [DW-1:0] & 'h1) << sw_addr)) ;
+ end
+ sw_wr_en_0 = reg_ack;
+ sw_be = {BW{1'b1}};
+ end
+end
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ if(sw_addr == {AW {1'b1}}) begin
+ reg_out = reg_0;
+ end else begin
+ reg_out = (reg_0 >> sw_addr ) ^ 'h1;
+ end
+end
+
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/pinmux/src/timer_reg.sv
new file mode 100644
index 0000000..cd48587
--- /dev/null
+++ b/verilog/rtl/pinmux/src/timer_reg.sv
@@ -0,0 +1,213 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Timer Register ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+//
+module timer_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic h_reset_n ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [1:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+ output logic [9:0] cfg_pulse_1us ,
+ output logic [2:0] cfg_timer_update , // CPU write to timer register
+ output logic [18:0] cfg_timer0 , // Timer-0 register
+ output logic [18:0] cfg_timer1 , // Timer-1 register
+ output logic [18:0] cfg_timer2 , // Timer-2 register
+ output logic [2:0] timer_intr
+
+ );
+
+//-----------------------------------------------------------------------
+// Internal Wire Declarations
+//-----------------------------------------------------------------------
+
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic [1:0] sw_addr ; // addressing 16 registers
+logic [31:0] sw_reg_wdata ;
+logic [3:0] sw_be ;
+
+logic [31:0] reg_out ;
+logic [31:0] reg_0 ; // TIMER GLOBAL CONFIG
+logic [31:0] reg_1 ; // TIMER-0
+logic [31:0] reg_2 ; // TIMER-1
+logic [31:0] reg_3 ; // TIMER-2
+
+assign sw_addr = reg_addr;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+assign sw_be = reg_be;
+assign sw_reg_wdata = reg_wdata;
+
+//-----------------------------------------------------------------------
+// register read enable and write enable decoding logic
+//-----------------------------------------------------------------------
+wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
+wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
+wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
+wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
+
+wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
+wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
+wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
+wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);
+
+
+always @ (posedge mclk or negedge h_reset_n)
+begin : preg_out_Seq
+ if (h_reset_n == 1'b0) begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end else if (reg_cs && !reg_ack) begin
+ reg_rdata <= reg_out;
+ reg_ack <= 1'b1;
+ end else begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//----------------------------------------------
+// reg-0: GLBL_CFG
+//------------------------------------------
+
+gen_32b_reg #('h0) u_reg_0 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_0 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_0 )
+ );
+
+assign cfg_pulse_1us = reg_0[9:0];
+
+//-----------------------------------------------------------------------
+// reg-1
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+// In first cycle, local register will be updated
+// In second cycle, update indication sent to timer block
+// -----------------------------------------------------------------
+assign cfg_timer0 = reg_1[18:0];
+assign cfg_timer_update[0] = sw_wr_en_1 & reg_ack;
+
+gen_32b_reg #(32'h0) u_reg_1 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_1 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_1[31:0] )
+ );
+
+//-----------------------------------------------------------------------
+// reg-2
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+// In first cycle, local register will be updated
+// In second cycle, update indication sent to timer block
+// -----------------------------------------------------------------
+assign cfg_timer1 = reg_2[18:0];
+assign cfg_timer_update[1] = sw_wr_en_2 & reg_ack;
+
+gen_32b_reg #(32'h0) u_reg_2 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_2 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_2[31:0] )
+ );
+
+
+//-----------------------------------------------------------------------
+// reg-3
+// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle
+// In first cycle, local register will be updated
+// In second cycle, update indication sent to timer block
+// -----------------------------------------------------------------
+assign cfg_timer2 = reg_3[18:0];
+assign cfg_timer_update[2] = sw_wr_en_3 & reg_ack;
+
+gen_32b_reg #(32'h0) u_reg_3 (
+ //List of Inputs
+ .reset_n (h_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_3 ),
+ .we (sw_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_3[31:0] )
+ );
+
+//-----------------------------------------------------------------------
+// Register Read Path Multiplexer instantiation
+//-----------------------------------------------------------------------
+
+always_comb
+begin
+ reg_out [31:0] = 32'h0;
+
+ case (sw_addr [1:0])
+ 2'b00 : reg_out [31:0] = reg_0 [31:0];
+ 2'b01 : reg_out [31:0] = reg_1 [31:0];
+ 2'b10 : reg_out [31:0] = reg_2 [31:0];
+ 2'b11 : reg_out [31:0] = reg_3 [31:0];
+ default : reg_out [31:0] = 32'h0;
+ endcase
+end
+
+endmodule
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/pinmux/src/timer_top.sv
new file mode 100644
index 0000000..ae981dc
--- /dev/null
+++ b/verilog/rtl/pinmux/src/timer_top.sv
@@ -0,0 +1,191 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Timer Top ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// 0.1 - 15th Aug 2022, Dinesh A ////
+//// initial version ////
+//////////////////////////////////////////////////////////////////////
+
+module timer_top (
+ // System Signals
+ // Inputs
+ input logic mclk,
+ input logic h_reset_n,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs,
+ input logic reg_wr,
+ input logic [1:0] reg_addr,
+ input logic [31:0] reg_wdata,
+ input logic [3:0] reg_be,
+
+ // Outputs
+ output logic [31:0] reg_rdata,
+ output logic reg_ack,
+
+ output logic pulse_1ms,
+ output logic [2:0] timer_intr
+
+ );
+
+//---------------------------------------------------------
+// Timer Register
+// -------------------------------------------------------
+logic [2:0] cfg_timer_update ; // CPU write to timer register
+logic [18:0] cfg_timer0 ; // Timer-0 register
+logic [18:0] cfg_timer1 ; // Timer-1 register
+logic [18:0] cfg_timer2 ; // Timer-2 register
+
+/* clock pulse */
+//********************************************************
+logic pulse_1us ; // 1 UsSecond Pulse for waveform Generator
+logic pulse_1s ; // 1Second Pulse for waveform Generator
+logic [9:0] cfg_pulse_1us ; // 1us pulse generation config
+
+timer_reg u_reg (
+ .mclk (mclk ),
+ .h_reset_n (h_reset_n ),
+
+ // Reg Bus Interface Signal
+ .reg_cs (reg_cs ),
+ .reg_wr (reg_wr ),
+ .reg_addr (reg_addr ),
+ .reg_wdata (reg_wdata ),
+ .reg_be (reg_be ),
+
+ // Outputs
+ .reg_rdata (reg_rdata ),
+ .reg_ack (reg_ack ),
+
+ .cfg_pulse_1us (cfg_pulse_1us ),
+ .cfg_timer_update (cfg_timer_update ),
+ .cfg_timer0 (cfg_timer0 ),
+ .cfg_timer1 (cfg_timer1 ),
+ .cfg_timer2 (cfg_timer2 )
+
+ );
+
+// 1us pulse
+pulse_gen_type2 #(.WD(10)) u_pulse_1us (
+
+ .clk_pulse_o (pulse_1us ),
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .cfg_max_cnt (cfg_pulse_1us )
+
+ );
+
+// 1us/1000 to 1millisecond pulse
+pulse_gen_type1 u_pulse_1ms (
+
+ .clk_pulse_o (pulse_1ms ),
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .trigger (pulse_1us )
+
+ );
+
+// 1ms/1000 => 1 second pulse
+pulse_gen_type1 u_pulse_1s (
+
+ .clk_pulse_o (pulse_1s ),
+ .clk (mclk ),
+ .reset_n (h_reset_n ),
+ .trigger (pulse_1ms )
+
+ );
+
+// Timer
+
+wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17];
+wire cfg_timer0_enb = cfg_timer0[16];
+wire [15:0] cfg_timer0_compare = cfg_timer0[15:0];
+
+timer u_timer_0
+ (
+ .reset_n (sreset_n ),// system syn reset
+ .mclk (mclk ),// master clock
+ .pulse_1us (pulse_1us ),
+ .pulse_1ms (pulse_1ms ),
+ .pulse_1s (pulse_1s ),
+
+ .cfg_timer_update (cfg_timer_update[0] ),
+ .cfg_timer_enb (cfg_timer0_enb ),
+ .cfg_timer_compare (cfg_timer0_compare ),
+ .cfg_timer_clksel (cfg_timer0_clksel ),// to select the timer 1us/1ms reference clock
+
+ .timer_intr (timer_intr[0] )
+ );
+
+// Timer
+wire [1:0] cfg_timer1_clksel = cfg_timer1[18:17];
+wire cfg_timer1_enb = cfg_timer1[16];
+wire [15:0] cfg_timer1_compare = cfg_timer1[15:0];
+timer u_timer_1
+ (
+ .reset_n (sreset_n ),// system syn reset
+ .mclk (mclk ),// master clock
+ .pulse_1us (pulse_1us ),
+ .pulse_1ms (pulse_1ms ),
+ .pulse_1s (pulse_1s ),
+
+ .cfg_timer_update (cfg_timer_update[1] ),
+ .cfg_timer_enb (cfg_timer1_enb ),
+ .cfg_timer_compare (cfg_timer1_compare ),
+ .cfg_timer_clksel (cfg_timer1_clksel ),// to select the timer 1us/1ms reference clock
+
+ .timer_intr (timer_intr[1] )
+ );
+
+// Timer
+wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17];
+wire cfg_timer2_enb = cfg_timer2[16];
+wire [15:0] cfg_timer2_compare = cfg_timer2[15:0];
+
+timer u_timer_2
+ (
+ .reset_n (sreset_n ),// system syn reset
+ .mclk (mclk ),// master clock
+ .pulse_1us (pulse_1us ),
+ .pulse_1ms (pulse_1ms ),
+ .pulse_1s (pulse_1s ),
+
+ .cfg_timer_update (cfg_timer_update[2] ),
+ .cfg_timer_enb (cfg_timer2_enb ),
+ .cfg_timer_compare (cfg_timer2_compare ),
+ .cfg_timer_clksel (cfg_timer2_clksel ),// to select the timer 1us/1ms reference clock
+
+ .timer_intr (timer_intr[2] )
+ );
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv
index e849f81..cc81df0 100755
--- a/verilog/rtl/sspim/src/sspim_cfg.sv
+++ b/verilog/rtl/sspim/src/sspim_cfg.sv
@@ -46,17 +46,28 @@
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
+/*******************************************************************
+SPI Mode:
+ Mode 0 (the default)− Clock is normally low (CPOL = 0), and Data sampled on rising edge and shifted out on the falling edge. (CPHA = 0). - Supported
+ Mode 1 − Clock is normally low (CPOL = 0), and Data sampled on the falling edge and shifted out on the rising edge. (CPHA = 1). - Not Supported
+ Mode 2 − Clock is normally high (CPOL = 1), and Data sampled on the rising edge and shifted out on the falling edge. (CPHA = 0). - Supported
+ Mode 3 − Clock is normally high (CPOL = 1), and Data sampled on the falling edge and shifted out on the rising edge (CPHA = 1). - Not Supported
+********************************************************************/
+
module sspim_cfg (
input logic mclk ,
input logic reset_n ,
output logic [1:0] cfg_tgt_sel ,
-
+
+ output logic cfg_cpol , // spi clock idle phase
+ output logic cfg_cpha , // spi data sample and lanch phase
+ output logic cfg_bit_order , // SPI TX/RX Bit Order, 1 -> LSBFIRST or 0 -> MSBFIRST
output logic cfg_op_req , // SPI operation request
- output logic cfg_endian , // Endian selection
+ output logic cfg_endian , // Endian selection
output logic [1:0] cfg_op_type , // SPI operation type
output logic [1:0] cfg_transfer_size , // SPI transfer size
output logic [5:0] cfg_sck_period , // sck clock period
@@ -98,6 +109,7 @@
logic [31:0] reg_1; // Software-Reg_1
logic [31:0] reg_2; // Software-Reg_2
logic [31:0] reg_out;
+logic [1:0] cfg_spi_mode;
//-----------------------------------------------------------------------
// Main code starts here
@@ -168,7 +180,13 @@
//-----------------------------------------------------------------------
// Logic for Register 0 : SPI Control Register
//-----------------------------------------------------------------------
+
+assign cfg_cpha = cfg_spi_mode[0];
+assign cfg_cpol = cfg_spi_mode[1];
+
assign cfg_op_req = reg_0[31]; // cpu request
+assign cfg_bit_order = reg_0[28]; // 1 -> LSBFIRST or 0 -> MSBFIRST
+assign cfg_spi_mode = reg_0[27:26]; // spi mode
assign cfg_endian = reg_0[25]; // Endian, 0 - little, 1 - Big
assign cfg_tgt_sel = reg_0[24:23]; // target chip select
assign cfg_op_type = reg_0[22:21]; // SPI operation type
@@ -210,18 +228,17 @@
.data_out (reg_0[23:16] )
);
-generic_register #(2,0 ) u_spi_ctrl_be3 (
- .we ({2{sw_wr_en_0 &
+generic_register #(7,0 ) u_spi_ctrl_be3 (
+ .we ({7{sw_wr_en_0 &
wr_be[3] }} ),
- .data_in (reg_wdata[25:24] ),
+ .data_in (reg_wdata[30:24] ),
.reset_n (reset_n ),
.clk (mclk ),
//List of Outs
- .data_out (reg_0[25:24] )
+ .data_out (reg_0[30:24] )
);
-assign reg_0[30:26] = 5'h0;
req_register #(0 ) u_spi_ctrl_req (
.cpu_we ({sw_wr_en_0 &
diff --git a/verilog/rtl/sspim/src/sspim_clkgen.sv b/verilog/rtl/sspim/src/sspim_clkgen.sv
new file mode 100755
index 0000000..bb1a8b4
--- /dev/null
+++ b/verilog/rtl/sspim/src/sspim_clkgen.sv
@@ -0,0 +1,146 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Single SPI Master Interface Module ////
+//// ////
+//// This file is part of the riscduino cores project ////
+//// https://github.com/dineshannayya/riscduino.git ////
+//// ////
+//// Description ////
+//// SPI Clock Gen module ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// V.0 - 06 Oct 2021 ////
+//// Initial SpI Module picked from ////
+//// http://www.opencores.org/cores/turbo8051/ ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+ Design Implementation Reference
+ Reference: https://www.allaboutcircuits.com/technical-articles/spi-serial-peripheral-interface/
+*********************************************************************/
+
+
+module sspim_clkgen
+ (
+ input logic clk,
+ input logic reset_n,
+ input logic cfg_op_req,
+ input logic cfg_cpol, // CPOL : clock polarity CPOL :0- Clock Idle state low, 1 - Clock idle state high
+ input logic cfg_cpha, // CPHA : Clock Phase
+
+ input logic [5:0] cfg_sck_period,
+
+ input logic sck_active,
+
+ output logic sck_int, // SCLK
+ output logic shift, // Data Shift Phase
+ output logic sample, // Data Sample Phase
+ output logic sck_ne, // sclk negative phase
+ output logic sck_pe // sclk positive phase
+
+ );
+
+ //*************************************************************************
+
+
+ logic [5:0] clk_cnt;
+ logic [5:0] sck_half_period;
+
+
+
+ assign sck_ne = (cfg_cpha == 0) ? shift : sample;
+ assign sck_pe = (cfg_cpha == 0) ? sample : shift;
+
+ assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
+ // The first transition on the sck_toggle happens one SCK period
+ // after op_en or boot_en is asserted
+ always @(posedge clk or negedge reset_n) begin
+ if(!reset_n) begin
+ shift <= 1'b0;
+ sample <= 1'b0;
+ clk_cnt <= 6'h0;
+ sck_int <= 1'b1;
+ end // if (!reset_n)
+ else
+ begin
+ if(cfg_op_req)
+ begin
+ // clock counter
+ if(clk_cnt == cfg_sck_period) begin
+ clk_cnt <= 'h0;
+ end else begin
+ clk_cnt <= clk_cnt + 1'b1;
+ end
+
+ if(clk_cnt == sck_half_period)
+ begin
+ shift <= 1'b1;
+ sample <= 1'b0;
+ end // if (clk_cnt == sck_half_period)
+ else
+ begin
+ if(clk_cnt == cfg_sck_period)
+ begin
+ shift <= 1'b0;
+ sample <= 1'b1;
+ end // if (clk_cnt == cfg_sck_period)
+ else
+ begin
+ shift <= 1'b0;
+ sample <= 1'b0;
+ end // else: !if(clk_cnt == cfg_sck_period)
+ end // else: !if(clk_cnt == sck_half_period)
+ end // if (op_en)
+ else
+ begin
+ clk_cnt <= 6'h0;
+ shift <= 1'b0;
+ sample <= 1'b0;
+ end // else: !if(op_en)
+
+
+ if(sck_active) begin
+ if(sck_ne) sck_int <= 0;
+ else if(sck_pe) sck_int <= 1;
+ end else if (cfg_cpol == 0) begin // CPOL :0- Clock Idle state low
+ sck_int <= 0;
+ end else begin // CPOL :1- Clock Idle state High
+ sck_int <= 1;
+ end
+ end // else: !if(!reset_n)
+ end // always @ (posedge clk or negedge reset_n)
+
+
+
+endmodule
diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv
index ea6aa1f..25971e0 100755
--- a/verilog/rtl/sspim/src/sspim_ctl.sv
+++ b/verilog/rtl/sspim/src/sspim_ctl.sv
@@ -52,25 +52,24 @@
(
input logic clk,
input logic reset_n,
+ input logic cfg_cpol,
input logic cfg_op_req,
input logic cfg_endian,
input logic [1:0] cfg_op_type,
input logic [1:0] cfg_transfer_size,
+ input logic [4:0] cfg_sck_cs_period,
- input logic [5:0] cfg_sck_period,
- input logic [4:0] cfg_sck_cs_period, // cs setup & hold period
input logic [7:0] cfg_cs_byte,
input logic [31:0] cfg_datain,
output logic [31:0] cfg_dataout,
output logic [7:0] byte_out, // Byte out for Serial Shifting out
input logic [7:0] byte_in, // Serial Received Byte
- output logic sck_int,
output logic cs_int_n,
- output logic sck_pe,
- output logic sck_ne,
- output logic shift_out,
- output logic shift_in,
+ input logic shift,
+ input logic sample,
+
+ output logic sck_active,
output logic load_byte,
output logic op_done
@@ -80,74 +79,25 @@
parameter LITTLE_ENDIAN = 1'b0;
parameter BIG_ENDIAN = 1'b1;
+
+ parameter SPI_WR = 2'b00;
+ parameter SPI_RD = 2'b01;
+ parameter SPI_WR_RD = 2'b10;
- logic [5:0] clk_cnt;
logic [5:0] sck_cnt;
logic [3:0] spiif_cs;
- logic shift_enb;
- logic clr_sck_cnt ;
- logic sck_out_en;
- logic [5:0] sck_half_period;
logic [2:0] byte_cnt;
`define SPI_IDLE 4'b0000
`define SPI_CS_SU 4'b0001
- `define SPI_WRITE 4'b0010
- `define SPI_READ 4'b0011
- `define SPI_CS_HLD 4'b0100
- `define SPI_WAIT 4'b0101
+ `define SPI_DATA 4'b0010
+ `define SPI_CS_HLD 4'b0011
+ `define SPI_WAIT 4'b0100
- assign sck_half_period = {1'b0, cfg_sck_period[5:1]};
- // The first transition on the sck_toggle happens one SCK period
- // after op_en or boot_en is asserted
- always @(posedge clk or negedge reset_n) begin
- if(!reset_n) begin
- sck_ne <= 1'b0;
- clk_cnt <= 6'h1;
- sck_pe <= 1'b0;
- sck_int <= 1'b0;
- end // if (!reset_n)
- else
- begin
- if(cfg_op_req)
- begin
- if(clk_cnt == sck_half_period)
- begin
- sck_ne <= 1'b1;
- sck_pe <= 1'b0;
- if(sck_out_en) sck_int <= 0;
- clk_cnt <= clk_cnt + 1'b1;
- end // if (clk_cnt == sck_half_period)
- else
- begin
- if(clk_cnt == cfg_sck_period)
- begin
- sck_ne <= 1'b0;
- sck_pe <= 1'b1;
- if(sck_out_en) sck_int <= 1;
- clk_cnt <= 6'h1;
- end // if (clk_cnt == cfg_sck_period)
- else
- begin
- clk_cnt <= clk_cnt + 1'b1;
- sck_pe <= 1'b0;
- sck_ne <= 1'b0;
- end // else: !if(clk_cnt == cfg_sck_period)
- end // else: !if(clk_cnt == sck_half_period)
- end // if (op_en)
- else
- begin
- clk_cnt <= 6'h1;
- sck_pe <= 1'b0;
- sck_ne <= 1'b0;
- end // else: !if(op_en)
- end // else: !if(!reset_n)
- end // always @ (posedge clk or negedge reset_n)
-
wire [1:0] cs_data = (byte_cnt == 2'b00) ? cfg_cs_byte[7:6] :
(byte_cnt == 2'b01) ? cfg_cs_byte[5:4] :
@@ -162,104 +112,72 @@
(byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0]) ;
-assign shift_out = shift_enb && sck_ne;
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
spiif_cs <= `SPI_IDLE;
sck_cnt <= 6'h0;
- shift_in <= 1'b0;
- clr_sck_cnt <= 1'b1;
byte_cnt <= 2'b00;
cs_int_n <= 1'b1;
- sck_out_en <= 1'b0;
- shift_enb <= 1'b0;
cfg_dataout <= 32'h0;
load_byte <= 1'b0;
+ sck_active <= 1'b0;
end
else begin
- if(sck_ne)
- sck_cnt <= clr_sck_cnt ? 6'h0 : sck_cnt + 1 ;
-
case(spiif_cs)
`SPI_IDLE :
begin
+ sck_active <= 1'b0;
+ load_byte <= 1'b0;
op_done <= 0;
- clr_sck_cnt <= 1'b1;
- sck_out_en <= 1'b0;
- shift_enb <= 1'b0;
if(cfg_op_req)
begin
cfg_dataout <= 32'h0;
spiif_cs <= `SPI_CS_SU;
- end
- else begin
+ end else begin
spiif_cs <= `SPI_IDLE;
end
end
`SPI_CS_SU :
begin
- if(sck_ne) begin
+ if(shift) begin
cs_int_n <= cs_data[1];
if(sck_cnt == cfg_sck_cs_period) begin
- clr_sck_cnt <= 1'b1;
- if(cfg_op_type == 0) begin // Write Mode
+ sck_cnt <= 'h0;
+ if((cfg_op_type == SPI_WR) || (cfg_op_type == SPI_WR_RD )) begin // Write Mode
load_byte <= 1'b1;
- spiif_cs <= `SPI_WRITE;
- shift_enb <= 1'b0;
- end else begin
- shift_in <= 1;
- spiif_cs <= `SPI_READ;
- end
- end
- else begin
- clr_sck_cnt <= 1'b0;
- end
+ end
+ spiif_cs <= `SPI_DATA;
+ end else begin
+ sck_cnt <= sck_cnt + 1 ;
+ end
end
end
- `SPI_WRITE :
+ `SPI_DATA :
begin
load_byte <= 1'b0;
- if(sck_ne) begin
- if(sck_cnt == 3'h7 )begin
- clr_sck_cnt <= 1'b1;
- spiif_cs <= `SPI_CS_HLD;
- shift_enb <= 1'b0;
- sck_out_en <= 1'b0; // Disable clock output
- end
- else begin
- shift_enb <= 1'b1;
- sck_out_en <= 1'b1;
- clr_sck_cnt <= 1'b0;
- end
- end else begin
- shift_enb <= 1'b1;
- end
- end
-
- `SPI_READ :
- begin
- if(sck_ne) begin
- if( sck_cnt == 3'h7 ) begin
- clr_sck_cnt <= 1'b1;
- shift_in <= 0;
- spiif_cs <= `SPI_CS_HLD;
- sck_out_en <= 1'b0; // Disable clock output
- end
- else begin
- sck_out_en <= 1'b1; // Disable clock output
- clr_sck_cnt <= 1'b0;
- end
+ if((shift && (cfg_cpol == 1)) || (sample && (cfg_cpol == 0)) ) begin
+ sck_active <= 1'b1;
+ end else if((sample && (cfg_cpol == 1)) || (shift && (cfg_cpol == 0)) ) begin
+ if(sck_cnt == 4'h8 )begin
+ sck_active <= 1'b0;
+ sck_cnt <= 'h0;
+ spiif_cs <= `SPI_CS_HLD;
+ end
+ else begin
+ sck_active <= 1'b1;
+ sck_cnt <= sck_cnt + 1 ;
+ end
end
end
`SPI_CS_HLD : begin
- if(sck_ne) begin
+ if(shift) begin
cs_int_n <= cs_data[0];
if(sck_cnt == cfg_sck_cs_period) begin
- if(cfg_op_type == 1) begin // Read Mode
+ if((cfg_op_type == SPI_RD) || (cfg_op_type == SPI_WR_RD)) begin // Read Mode
cfg_dataout <= (cfg_endian == LITTLE_ENDIAN) ?
((byte_cnt[1:0] == 2'b00) ? { cfg_dataout[31:8],byte_in } :
(byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :
@@ -270,7 +188,7 @@
(byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } :
{ cfg_dataout[31:8],byte_in}) ;
end
- clr_sck_cnt <= 1'b1;
+ sck_cnt <= 'h0;
if(byte_cnt == cfg_transfer_size) begin
spiif_cs <= `SPI_WAIT;
byte_cnt <= 0;
@@ -281,7 +199,7 @@
end
end
else begin
- clr_sck_cnt <= 1'b0;
+ sck_cnt <= sck_cnt + 1 ;
end
end
end // case: `SPI_CS_HLD
diff --git a/verilog/rtl/sspim/src/sspim_if.sv b/verilog/rtl/sspim/src/sspim_if.sv
index 42b18f2..ece9ffd 100755
--- a/verilog/rtl/sspim/src/sspim_if.sv
+++ b/verilog/rtl/sspim/src/sspim_if.sv
@@ -47,24 +47,25 @@
module sspim_if
(
- input logic clk,
- input logic reset_n,
- input logic sck_pe,
- input logic sck_int,
- input logic cs_int_n,
+ input logic clk,
+ input logic reset_n,
+ input logic sck_int,
+ input logic cs_int_n,
+ input logic cfg_bit_order, // 1 -> LSBFIRST or 0 -> MSBFIRST
input logic load_byte,
input logic [1:0] cfg_tgt_sel,
input logic [7:0] byte_out,
- input logic shift_out,
- input logic shift_in,
+ input logic sck_active,
+ input logic shift,
+ input logic sample,
- output logic [7:0] byte_in,
- output logic sck,
- output logic so,
- output logic [3:0] cs_n,
- input logic si
+ output logic [7:0]byte_in,
+ output logic sck,
+ output logic so,
+ output logic [3:0]cs_n,
+ input logic si
);
@@ -73,6 +74,9 @@
logic [7:0] si_reg;
+ wire shift_out = shift & sck_active;
+ wire sample_in = sample & sck_active;
+
//Output Shift Register
always @(posedge clk or negedge reset_n) begin
@@ -86,13 +90,19 @@
if(shift_out) begin
// Handling backto back case :
// Last Transfer bit + New Trasfer Load
- so <= so_reg[7];
+ if(cfg_bit_order) so <= so_reg[0]; // LSB FIRST
+ else so <= so_reg[7]; // MSB FIRST
end
end // if (load_byte)
else begin
if(shift_out) begin
- so <= so_reg[7];
- so_reg <= {so_reg[6:0],1'b0};
+ if(cfg_bit_order) begin // LSB FIRST
+ so <= so_reg[0];
+ so_reg <= {1'b0,so_reg[7:1]};
+ end else begin
+ so <= so_reg[7];
+ so_reg <= {so_reg[6:0],1'b0};
+ end
end // if (shift_out)
end // else: !if(load_byte)
end // else: !if(!reset_n)
@@ -103,11 +113,14 @@
always @(posedge clk or negedge reset_n) begin
if(!reset_n) begin
si_reg <= 8'h0;
- end
- else begin
- if(sck_pe & shift_in) begin
- si_reg[7:0] <= {si_reg[6:0],si};
- end // if (sck_pe & shift_in)
+ end else begin
+ if(sample_in) begin
+ if(cfg_bit_order) begin // LSB FIRST
+ si_reg[7:0] <= {si,si_reg[7:1]};
+ end else begin // MSB FIRST
+ si_reg[7:0] <= {si_reg[6:0],si};
+ end
+ end // if (sample_in)
end // else: !if(!reset_n)
end // always @ (posedge clk or negedge reset_n)
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv
index 2a28d2e..6f0f17f 100755
--- a/verilog/rtl/sspim/src/sspim_top.sv
+++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -46,6 +46,9 @@
//// out is big endian, i.e bit[7],[6] ..[0] ////
//// 0.3 - April 6, 2022, Dinesh A ////
//// Four chip select are driven out ////
+//// 0.4 - Aug 5, 2022, Dinesh A ////
+//// A. SPI Mode 0 to 3 support added, ////
+//// B. SPI Duplex mode TX-RX Mode added ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -125,54 +128,81 @@
logic [31:0] cfg_datain ; // data for transfer
logic [31:0] cfg_dataout ; // data for received
logic hware_op_done ; // operation done
-
+logic cfg_bit_order ; // Bit order 1 -> LSBFIRST or 0 -> MSBFIRST
+logic cfg_cpol ; // spi clock idle phase
+logic cfg_cpha ; // spi data sample and lanch phase
sspim_if u_spi_if
(
. clk (clk ),
. reset_n (reset_n ),
- // towards ctrl i/f
- . sck_pe (sck_pe ),
+ // cfg
+ . cfg_bit_order (cfg_bit_order ),
+ . cfg_tgt_sel (cfg_tgt_sel ),
+
+ // clkgen
+ . shift (shift ),
+ . sample (sample ),
. sck_int (sck_int ),
+
+ // towards ctrl i/f
+ . sck_active (sck_active ),
. cs_int_n (cs_int_n ),
. byte_in (byte_in ),
. load_byte (load_byte ),
. byte_out (byte_out ),
- . shift_out (shift_out ),
- . shift_in (shift_in ),
- . cfg_tgt_sel (cfg_tgt_sel ),
-
+ // External I/F
. sck (sck ),
. so (so ),
. si (si ),
. cs_n (ssn )
);
+sspim_clkgen u_clkgen
+ (
+ . clk (clk ),
+ . reset_n (reset_n ),
+
+ // cfg
+ . cfg_cpol (cfg_cpol ),
+ . cfg_cpha (cfg_cpha ),
+ . cfg_sck_period (cfg_sck_period ),
+ . cfg_op_req (cfg_op_req ),
+
+ // ctrl
+ . sck_active (sck_active ),
+
+ . sck_int (sck_int ),
+ . shift (shift ),
+ . sample (sample ),
+ . sck_ne (),
+ . sck_pe ()
+
+ );
sspim_ctl u_spi_ctrl
(
. clk (clk ),
. reset_n (reset_n ),
+ // cfg
+ . cfg_cpol (cfg_cpol ),
. cfg_op_req (cfg_op_req ),
. cfg_endian (cfg_endian ),
. cfg_op_type (cfg_op_type ),
. cfg_transfer_size (cfg_transfer_size ),
- . cfg_sck_period (cfg_sck_period ),
. cfg_sck_cs_period (cfg_sck_cs_period ),
. cfg_cs_byte (cfg_cs_byte ),
. cfg_datain (cfg_datain ),
. cfg_dataout (cfg_dataout ),
. op_done (hware_op_done ),
- . sck_int (sck_int ),
+ . sck_active (sck_active ),
. cs_int_n (cs_int_n ),
- . sck_pe (sck_pe ),
- . sck_ne (sck_ne ),
- . shift_out (shift_out ),
- . shift_in (shift_in ),
+ . shift (shift ),
+ . sample (sample ),
. load_byte (load_byte ),
. byte_out (byte_out ),
. byte_in (byte_in )
@@ -200,6 +230,9 @@
// configuration signal
+ . cfg_cpol (cfg_cpol ),
+ . cfg_cpha (cfg_cpha ),
+ . cfg_bit_order (cfg_bit_order ),
. cfg_tgt_sel (cfg_tgt_sel ),
. cfg_op_req (cfg_op_req ), // SPI operation request
. cfg_endian (cfg_endian ),
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv
index 948cd35..653e285 100644
--- a/verilog/rtl/uart/src/uart_core.sv
+++ b/verilog/rtl/uart/src/uart_core.sv
@@ -185,8 +185,9 @@
//##############################################################
// 16x Baud clock generation
+// Baud Rate config = (F_CPU / (BAUD * 16)) - 2
// Example: to generate 19200 Baud clock from 50Mhz Link clock
-// 50 * 1000 * 1000 / (2 + cfg_baud_16x) = 19200 * 16
+// cfg_baud_16x = ((50 * 1000 * 1000) / (19200 * 16)) - 2
// cfg_baud_16x = 0xA0 (160)
//###############################################################
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 34c8794..3429628 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -35,6 +35,7 @@
//// 8. 2KB icache and 2KB dcache ////
//// 8. 6 Channel ADC ////
//// 9. Pinmux with GPIO and 6 PWM ////
+////
//// ////
//// To Do: ////
//// nothing ////
@@ -216,6 +217,20 @@
//// SPI ISP boot option added in wb_host, spi slave uses ////
//// same spi master interface, but will be active only ////
//// when internal SPI config disabled + RESET PIN = 0 ////
+//// 4.9 Aug 5 2022, Dinesh A ////
+//// changes in sspim ////
+//// A. SPI Mode 0 to 3 support added, ////
+//// B. SPI Duplex mode TX-RX Mode added ////
+//// 5.0 Aug 15 2022, Dinesh A ////
+//// A. 15 Hardware Semahore added ////
+//// B. Pinmux Address Space are Split as ////
+//// `define ADDR_SPACE_PINMUX 32'h1002_0000 ////
+//// `define ADDR_SPACE_GLBL 32'h1002_0000 ////
+//// `define ADDR_SPACE_GPIO 32'h1002_0040 ////
+//// `define ADDR_SPACE_PWM 32'h1002_0080 ////
+//// `define ADDR_SPACE_TIMER 32'h1002_00C0 ////
+//// `define ADDR_SPACE_SEMA 32'h1002_0100 ////
+//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -243,6 +258,32 @@
//// ////
//////////////////////////////////////////////////////////////////////
+/*********************************************************************
+ Memory Map: ////
+ ////
+ SOC Memory Map ////
+ 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY ////
+ 0x1000_0000 to 0x1000_00FF - QSPIM REG
+ 0x1001_0000 to 0x1001_003F - UART0
+ 0x1001_0040 to 0x1001_007F - I2
+ 0x1001_0080 to 0x1001_00BF - USB
+ 0x1001_00C0 to 0x1001_00FF - SSPIM
+ 0x1001_0100 to 0x1001_013F - UART1
+ 0x1002_0000 to 0x1002_00FF - PINMUX
+
+ Caravel Memory Map:
+-----------------------------------------------------------------------
+ caravel user space is 0x3000_0000 to 0x300F_FFFF
+ So we have allocated
+ 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
+ Since We need more than 16MB Address space to access SDRAM/SPI we have
+ added indirect MSB 13 bit address select option
+ So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]}
+ ---------------------------------------------------------------------
+ 0x3080_0000 to 0x3080_00FF - WB HOST
+ 0x3000_0000 to 0x307F_FFFF - Indirect Address
+ {Bank_Sel[15:3],WB ADDR[18:0]}
+***********************************************************************/
module user_project_wrapper (
`ifdef USE_POWER_PINS
@@ -418,7 +459,7 @@
// Global Register Wishbone Interface
//---------------------------------------------------------------------
wire wbd_glbl_stb_o ; // strobe/request
-wire [7:0] wbd_glbl_adr_o ; // address
+wire [8:0] wbd_glbl_adr_o ; // address
wire wbd_glbl_we_o ; // write
wire [WB_WIDTH-1:0] wbd_glbl_dat_o ; // data output
wire [3:0] wbd_glbl_sel_o ; // byte enable
@@ -1214,7 +1255,7 @@
);
-pinmux u_pinmux(
+pinmux_top u_pinmux(
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ),// User area 1 1.8V supply
.vssd1 (vssd1 ),// User area 1 digital ground
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 42f9e73..53d8331 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -9,6 +9,11 @@
`define ADDR_SPACE_SSPI 32'h3001_00C0
`define ADDR_SPACE_UART1 32'h3001_0100
`define ADDR_SPACE_PINMUX 32'h3002_0000
+`define ADDR_SPACE_GLBL 32'h3002_0000
+`define ADDR_SPACE_GPIO 32'h3002_0040
+`define ADDR_SPACE_PWM 32'h3002_0080
+`define ADDR_SPACE_TIMER 32'h3002_00C0
+`define ADDR_SPACE_SEMA 32'h3002_0100
`define ADDR_SPACE_WBHOST 32'h3008_0000
//--------------------------------------------------
@@ -21,41 +26,74 @@
`define WBHOST_PLL_CTRL 8'h10 // reg_4 - PLL Control
//--------------------------------------------------
-// Pinmux Register
+// GLOBAL Register
// -------------------------------------------------
+`define GLBL_CFG_CHIP_ID 8'h00 // reg_0 - Chip ID
+`define GLBL_CFG_CFG0 8'h04 // reg_1 - Global Config-0
+`define GLBL_CFG_CFG1 8'h08 // reg_2 - Global Config-1
+`define GLBL_CFG_INTR_MSK 8'h0C // reg_3 - Global Interrupt Mask
+`define GLBL_CFG_INTR_STAT 8'h10 // reg_4 - Global Interrupt
+`define GLBL_CFG_MUTI_FUNC 8'h14 // reg_5 - Multi functional sel
+`define GLBL_CFG_SOFT_REG_0 8'h18 // reg_6 - Sof Register
+`define GLBL_CFG_SOFT_REG_1 8'h1C // reg_7 - Sof Register
+`define GLBL_CFG_SOFT_REG_2 8'h20 // reg_8 - Sof Register
+`define GLBL_CFG_SOFT_REG_3 8'h24 // reg_9 - Sof Register
+`define GLBL_CFG_SOFT_REG_4 8'h28 // reg_10 - Sof Register
+`define GLBL_CFG_SOFT_REG_5 8'h2C // reg_11 - Sof Register
-`define PINMUX_CHIP_ID 8'h00 // reg_0 - Chip ID
-`define PINMUX_GBL_CFG0 8'h04 // reg_1 - Global Config-2
-`define PINMUX_GBL_CFG1 8'h08 // reg_2 - Global Config-1
-`define PINMUX_GBL_INTR_MSK 8'h0C // reg_3 - Global Interrupt Mask
-`define PINMUX_GBL_INTR 8'h10 // reg_4 - Global Interrupt
-`define PINMUX_GPIO_IDATA 8'h14 // reg_5 - GPIO Data In
-`define PINMUX_GPIO_ODATA 8'h18 // reg_6 - GPIO Data Out
-`define PINMUX_GPIO_DSEL 8'h1C // reg_7 - GPIO Direction Select
-`define PINMUX_GPIO_TYPE 8'h20 // reg_8 - GPIO TYPE - Static/Waveform
-`define PINMUX_GPIO_INTR_STAT 8'h24 // reg_9 - GPIO Interrupt status
-`define PINMUX_GPIO_INTR_CLR 8'h24 // reg_9 - GPIO Interrupt Clear
-`define PINMUX_GPIO_INTR_SET 8'h28 // reg_10 - GPIO Interrupt Set
-`define PINMUX_GPIO_INTR_MASK 8'h2C // reg_11 - GPIO Interrupt Mask
-`define PINMUX_GPIO_POS_INTR 8'h30 // reg_12 - GPIO Posedge Interrupt
-`define PINMUX_GPIO_NEG_INTR 8'h34 // reg_13 - GPIO Neg Interrupt
-`define PINMUX_GPIO_MULTI_FUNC 8'h38 // reg_14 - GPIO Multi Function
-`define PINMUX_SOFT_REG_0 8'h3C // reg_15 - Soft Register
-`define PINMUX_CFG_PWM0 8'h40 // reg_16 - PWM Reg-0
-`define PINMUX_CFG_PWM1 8'h44 // reg_17 - PWM Reg-1
-`define PINMUX_CFG_PWM2 8'h48 // reg_18 - PWM Reg-2
-`define PINMUX_CFG_PWM3 8'h4C // reg_19 - PWM Reg-3
-`define PINMUX_CFG_PWM4 8'h50 // reg_20 - PWM Reg-4
-`define PINMUX_CFG_PWM5 8'h54 // reg_21 - PWM Reg-5
-`define PINMUX_SOFT_REG_1 8'h58 // reg_22 - Sof Register
-`define PINMUX_SOFT_REG_2 8'h5C // reg_23 - Sof Register
-`define PINMUX_SOFT_REG_3 8'h60 // reg_24 - Sof Register
-`define PINMUX_SOFT_REG_4 8'h64 // reg_25 - Sof Register
-`define PINMUX_SOFT_REG_5 8'h68 // reg_26 - Sof Register
-`define PINMUX_SOFT_REG_6 8'h6C // reg_27 - Sof Register
-`define PINMUX_CFG_TIMER0 8'h70 // reg_28 - Timer-0
-`define PINMUX_CFG_TIMER1 8'h74 // reg_28 - Timer-1
-`define PINMUX_CFG_TIMER2 8'h78 // reg_28 - Timer-2
+//--------------------------------------------------
+// GPIO Register
+// -------------------------------------------------
+`define GPIO_CFG_DSEL 8'h00 // reg_0 - GPIO Direction Select
+`define GPIO_CFG_TYPE 8'h04 // reg_1 - GPIO TYPE - Static/Waveform
+`define GPIO_CFG_IDATA 8'h08 // reg_2 - GPIO Data In
+`define GPIO_CFG_ODATA 8'h0C // reg_3 - GPIO Data Out
+`define GPIO_CFG_INTR_STAT 8'h10 // reg_4 - GPIO Interrupt status
+`define GPIO_CFG_INTR_CLR 8'h10 // reg_4 - GPIO Interrupt Clear
+`define GPIO_CFG_INTR_SET 8'h14 // reg_5 - GPIO Interrupt Set
+`define GPIO_CFG_INTR_MASK 8'h18 // reg_6 - GPIO Interrupt Mask
+`define GPIO_CFG_POS_INTR_SEL 8'h1C // reg_7 - GPIO Posedge Interrupt
+`define GPIO_CFG_NEG_INTR_SEL 8'h20 // reg_8 - GPIO Neg Interrupt
+
+
+//--------------------------------------------------
+// PWM Register
+// -------------------------------------------------
+`define PWM_GLBL_CFG 8'h00 // reg_0 - PWM Global Config
+`define PWM_CFG_PWM_0 8'h04 // reg_1 - PWM Reg-0
+`define PWM_CFG_PWM_1 8'h08 // reg_2 - PWM Reg-1
+`define PWM_CFG_PWM_2 8'h0C // reg_3 - PWM Reg-2
+`define PWM_CFG_PWM_3 8'h10 // reg_4 - PWM Reg-3
+`define PWM_CFG_PWM_4 8'h14 // reg_5 - PWM Reg-4
+`define PWM_CFG_PWM_5 8'h18 // reg_6 - PWM Reg-5
+
+//--------------------------------------------------
+// TIMER Register
+// -------------------------------------------------
+`define TIMER_CFG_GLBL 8'h00 // reg_0 - Global Config
+`define TIMER_CFG_TIMER_0 8'h04 // reg_1 - Timer-0
+`define TIMER_CFG_TIMER_1 8'h08 // reg_2 - Timer-1
+`define TIMER_CFG_TIMER_2 8'h0C // reg_3 - Timer-2
+
+//--------------------------------------------------
+// SEMAPHORE Register
+// -------------------------------------------------
+`define SEMA_CFG_LOCK_0 8'h00 // reg_0 - Semaphore Lock Bit-0
+`define SEMA_CFG_LOCK_1 8'h04 // reg_1 - Semaphore Lock Bit-1
+`define SEMA_CFG_LOCK_2 8'h08 // reg_2 - Semaphore Lock Bit-2
+`define SEMA_CFG_LOCK_3 8'h0C // reg_3 - Semaphore Lock Bit-3
+`define SEMA_CFG_LOCK_4 8'h10 // reg_4 - Semaphore Lock Bit-4
+`define SEMA_CFG_LOCK_5 8'h14 // reg_5 - Semaphore Lock Bit-5
+`define SEMA_CFG_LOCK_6 8'h18 // reg_6 - Semaphore Lock Bit-6
+`define SEMA_CFG_LOCK_7 8'h1C // reg_7 - Semaphore Lock Bit-7
+`define SEMA_CFG_LOCK_8 8'h20 // reg_8 - Semaphore Lock Bit-8
+`define SEMA_CFG_LOCK_9 8'h24 // reg_9 - Semaphore Lock Bit-9
+`define SEMA_CFG_LOCK_10 8'h28 // reg_10 - Semaphore Lock Bit-10
+`define SEMA_CFG_LOCK_11 8'h2C // reg_11 - Semaphore Lock Bit-11
+`define SEMA_CFG_LOCK_12 8'h30 // reg_12 - Semaphore Lock Bit-12
+`define SEMA_CFG_LOCK_13 8'h34 // reg_13 - Semaphore Lock Bit-13
+`define SEMA_CFG_LOCK_14 8'h38 // reg_14 - Semaphore Lock Bit-14
+`define SEMA_CFG_STATUS 8'h3C // reg_15 - Semaphore Lock Status
//----------------------------------------------------------
// QSPI Register Map
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index 26029c2..d3d85cc 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -411,11 +411,11 @@
// Locally there register are define to control the reset and clock for user
// area
//-----------------------------------------------------------------------
-// caravel user space is 0x3000_0000 to 0x3007_FFFF
+// caravel user space is 0x3000_0000 to 0x300F_FFFF
// So we have allocated
// 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space
// Since We need more than 16MB Address space to access SDRAM/SPI we have
-// added indirect MSB 8 bit address select option
+// added indirect MSB 13 bit address select option
// So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]}
// ---------------------------------------------------------------------
assign reg_sel = wb_req & (wb_adr_i[19] == 1'b1);
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index 9fb6344..7e348fc 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,8 +203,8 @@
input logic s2_wbd_ack_i,
// input logic s2_wbd_err_i, - unused
output logic [31:0] s2_wbd_dat_o,
- output logic [7:0] s2_wbd_adr_o, // glbl reg need only 8 bits
- output logic [3:0] s2_wbd_sel_o,
+ output logic [8:0] s2_wbd_adr_o, // glbl reg need only 9 bits
+ output logic [3:0] s2_wbd_sel_o,
output logic s2_wbd_we_o,
output logic s2_wbd_cyc_o,
output logic s2_wbd_stb_o
@@ -677,7 +677,7 @@
assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ;
assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ;
- assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit
+ assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[8:0] ; // Global Reg Need 8 bit
assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ;
assign s2_wbd_we_o = s2_wb_wr.wbd_we ;
assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;
