commit 9be297281fd2bdb4fbc5558270387e5267cee235
author dineshannayya <dinesh.annayya@gmail.com> Sun May 29 19:09:57 2022 +0530
committer dineshannayya <dinesh.annayya@gmail.com> Sun May 29 19:09:57 2022 +0530
tree a1374682c1ff1b5fe25224fa6303baaabef4c047
parent 75cebb146d29f4d263f490568a0cb7d78dee270f

digital pll integrated

verilog/dv/user_timer/Makefile

diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index 0cc574f..077652a 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile
@@ -55,10 +55,12 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else