digital pll integrated
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile
index b7d0ec4..15194cc 100644
--- a/verilog/dv/riscv_regress/Makefile
+++ b/verilog/dv/riscv_regress/Makefile
@@ -278,6 +278,7 @@
iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(UPRJ_TESTS_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$(sv_list) \
-o $(top_module).vvp; \
printf "" > $(test_results); \
@@ -295,6 +296,7 @@
iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-I $(UPRJ_TESTS_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$(sv_list) \
-o $(top_module).vvp; \
printf "" > $(test_results); \
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index 115c577..c1ad8ae 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -50,10 +50,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 9dd1e05..8438fa6 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -150,12 +150,13 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_basic_tb);
- $dumpvars(1, user_basic_tb.u_top);
- $dumpvars(1, user_basic_tb.u_top.u_wb_host);
- $dumpvars(1, user_basic_tb.u_top.u_intercon);
- $dumpvars(1, user_basic_tb.u_top.u_intercon);
- $dumpvars(1, user_basic_tb.u_top.u_pinmux);
+ $dumpvars(0, user_basic_tb);
+ //$dumpvars(1, user_basic_tb.u_top);
+ //$dumpvars(0, user_basic_tb.u_top.u_pll);
+ //$dumpvars(1, user_basic_tb.u_top.u_wb_host);
+ //$dumpvars(1, user_basic_tb.u_top.u_intercon);
+ //$dumpvars(1, user_basic_tb.u_top.u_intercon);
+ //$dumpvars(1, user_basic_tb.u_top.u_pinmux);
end
`endif
@@ -164,6 +165,12 @@
#100;
wb_rst_i <= 1'b0; // Release reset
end
+
+
+// Hook to pll clock
+wire pll_clock = u_top.u_wb_host.u_clkbuf_pll.X;
+
+
initial
begin
@@ -177,81 +184,111 @@
fork
begin
// Default Value Check
- // cfg_glb_ctrl = reg_0[6:0];
- // uart_i2c_usb_sel = reg_0[8:7];
- // cfg_wb_clk_ctrl = reg_0[11:9];
- // cfg_rtc_clk_ctrl = reg_0[19:12];
- // cfg_cpu_clk_ctrl = reg_0[23:20];
- // cfg_usb_clk_ctrl = reg_0[31:24];
+ // cfg_wb_clk_ctrl = cfg_clk_ctrl2[7:0];
+ // cfg_rtc_clk_ctrl = cfg_clk_ctrl2[15:8];
+ // cfg_cpu_clk_ctrl = cfg_clk_ctrl2[23:16];
+ // cfg_usb_clk_ctrl = cfg_clk_ctrl2[31:24];
- $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1");
+
+ $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1");
test_step = 1;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00});
- clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0});
+ clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD);
- $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2");
+ $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2");
test_step = 2;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h80,4'h8,8'h1,4'h8,8'h00});
- clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40});
+ clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD);
- $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2");
+ $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2");
test_step = 3;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h81,4'h4,8'h2,4'h4,8'h00});
- clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20});
+ clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD);
- $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3");
+ $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3");
test_step = 4;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h5,8'h3,4'h5,8'h00});
- clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21});
+ clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD);
- $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4");
+ $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4");
test_step = 5;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h83,4'h6,8'h4,4'h6,8'h00});
- clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22});
+ clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD);
- $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)");
+ $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
test_step = 6;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h84,4'h7,8'h5,4'h7,8'h00});
- clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23});
+ clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);
- $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)");
+ $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)");
test_step = 7;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h85,4'hC,8'h6,4'hC,8'h00});
- clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60});
+ clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD);
- $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3");
+ $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3");
test_step = 8;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h86,4'hD,8'h7,4'hD,8'h00});
- clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61});
+ clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD);
- $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4");
+ $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4");
test_step = 9;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h87,4'hE,8'h8,4'hE,8'h00});
- clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62});
+ clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD);
- $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+8), WBS:CLOCK1/(2+3)");
+ $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)");
test_step = 10;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h88,4'hF,8'h80,4'hF,8'h00});
- clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,10*CLK2_PERIOD,5*CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63});
+ clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD);
- $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+9), WBS:CLOCK2/(2+3)");
+ $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
test_step = 10;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00});
- clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+ clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
$display("###################################################");
+ $display("Monitor: Checking the PLL:");
+ $display("###################################################");
+ test_step = 11;
+ // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
+ repeat (100) @(posedge clock);
+ pll_clock_monitor(5);
+
+ test_step = 12;
+ // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+ repeat (100) @(posedge clock);
+ pll_clock_monitor(4);
+
+ $display("###################################################");
+ $display("Monitor: Monitor Clock output:");
+ $display("###################################################");
+ $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
+ test_step = 13;
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+
+ // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+ dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
+
+ $display("###################################################");
$display("Monitor: Checking the chip signature :");
+ $display("###################################################");
+ test_step = 14;
// Remove Wb/PinMux Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2305_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_3000);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2905_2022);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_4000);
end
begin
- repeat (20000) @(posedge clock);
+ repeat (30000) @(posedge clock);
// $display("+1000 cycles");
test_fail = 1;
end
@@ -329,28 +366,71 @@
task clock_monitor;
input [15:0] exp_cpu_period;
-input [15:0] exp_rtc_period;
input [15:0] exp_usb_period;
+input [15:0] exp_rtc_period;
input [15:0] exp_wbs_period;
begin
force clock_mon = u_top.u_wb_host.cpu_clk;
check_clock_period("CPU CLock",exp_cpu_period);
release clock_mon;
- force clock_mon = u_top.u_wb_host.rtc_clk;
- check_clock_period("RTC Clock",exp_rtc_period);
- release clock_mon;
-
force clock_mon = u_top.u_wb_host.usb_clk;
check_clock_period("USB Clock",exp_usb_period);
release clock_mon;
+ force clock_mon = u_top.u_wb_host.rtc_clk;
+ check_clock_period("RTC Clock",exp_rtc_period);
+ release clock_mon;
+
force clock_mon = u_top.u_wb_host.wbs_clk_out;
check_clock_period("WBS Clock",exp_wbs_period);
release clock_mon;
end
endtask
+task pll_clock_monitor;
+input [15:0] exp_period;
+begin
+ force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+ check_clock_period("PLL CLock",exp_period);
+ release clock_mon;
+end
+endtask
+
+
+wire dbg_clk_mon = io_out[33];
+
+task dbg_clk_monitor;
+input [15:0] exp_pll_div16_period;
+input [15:0] exp_pll_ref_period;
+input [15:0] exp_cpu_period;
+input [15:0] exp_usb_period;
+input [15:0] exp_rtc_period;
+input [15:0] exp_wbs_period;
+begin
+ force clock_mon = dbg_clk_mon;
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+ check_clock_period("PLL CLock",exp_pll_div16_period);
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2});
+ check_clock_period("PLL REF Clock",exp_pll_ref_period);
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2});
+ check_clock_period("WBS Clock",exp_wbs_period);
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2});
+ check_clock_period("CPU CLock",exp_cpu_period);
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2});
+ check_clock_period("RTC Clock",exp_rtc_period);
+
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2});
+ check_clock_period("USB Clock",exp_usb_period);
+ release clock_mon;
+end
+endtask
+
//----------------------------------
// Check the clock period
//----------------------------------
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index 3e01197..f01c09d 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -54,10 +54,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_mcore/Makefile b/verilog/dv/user_mcore/Makefile
index a3eb6d3..a0795af 100644
--- a/verilog/dv/user_mcore/Makefile
+++ b/verilog/dv/user_mcore/Makefile
@@ -62,10 +62,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile
index 36a8452..c521c74 100644
--- a/verilog/dv/user_pwm/Makefile
+++ b/verilog/dv/user_pwm/Makefile
@@ -55,10 +55,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile
index da8c07b..6b87fce 100644
--- a/verilog/dv/user_qspi/Makefile
+++ b/verilog/dv/user_qspi/Makefile
@@ -55,10 +55,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index b4f71fd..da70cab 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -61,10 +61,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_sram_exec/Makefile b/verilog/dv/user_sram_exec/Makefile
index 628804e..44f56ab 100644
--- a/verilog/dv/user_sram_exec/Makefile
+++ b/verilog/dv/user_sram_exec/Makefile
@@ -61,10 +61,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
index 8ef867e..f16f2a7 100644
--- a/verilog/dv/user_sspi/Makefile
+++ b/verilog/dv/user_sspi/Makefile
@@ -55,10 +55,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index 0cc574f..077652a 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile
@@ -55,10 +55,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index d463172..0c74848 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -61,10 +61,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile
index 8ef2e69..7f299a1 100644
--- a/verilog/dv/user_uart1/Makefile
+++ b/verilog/dv/user_uart1/Makefile
@@ -61,10 +61,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index 5bae64b..800f73a 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -53,10 +53,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index 73ce5e7..d8eee80 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile
@@ -55,10 +55,12 @@
ifeq ($(DUMP),OFF)
iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index b6b4892..5974990 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -53,7 +53,7 @@
module user_usb_tb;
parameter USB_HPER = 10.4167; // 48Mhz Half cycle
-parameter USER2_HPER = 2.6042; // 192Mhz Half cycle
+parameter USER2_HPER = 2.7777; // 180Mhz Half cycle
reg clock;
reg user_clock2;
@@ -135,10 +135,10 @@
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_usb_tb);
- $dumpvars(1, user_usb_tb.u_top);
- $dumpvars(1, user_usb_tb.u_top.u_uart_i2c_usb_spi);
- $dumpvars(0, user_usb_tb.u_top.u_uart_i2c_usb_spi.u_usb_host);
+ $dumpvars(0, user_usb_tb);
+ //$dumpvars(1, user_usb_tb.u_top);
+ //$dumpvars(1, user_usb_tb.u_top.u_uart_i2c_usb_spi);
+ //$dumpvars(0, user_usb_tb.u_top.u_uart_i2c_usb_spi.u_usb_host);
//$dumpvars(0, user_usb_tb.u_top.u_intercon);
//$dumpvars(0, user_usb_tb.u_top.u_wb_host);
end
@@ -171,8 +171,9 @@
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
- // Remove Wb Reset
- wb_user_core_write('h3080_0000,'h1);
+
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable SPI Multi Functional Ports
wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
@@ -180,8 +181,10 @@
repeat (2) @(posedge clock);
#1;
- // Set USB clock : 192/4 = 48Mhz
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h0,8'h0,4'h0,8'h01});
+ // Remove Wb/PinMux Reset
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ // Set USB clock : 180/3 = 60Mhz
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0});
// Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
