gate level sim clean-up
diff --git a/Makefile b/Makefile index b89e69f..4cd69b5 100644 --- a/Makefile +++ b/Makefile
@@ -86,15 +86,12 @@ $(blocks): % : export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $* -dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d) -dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) -dv-targets-gl=$(dv_patterns:%=verify-%-gl) -dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) +PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d) +DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) TARGET_PATH=$(shell pwd) verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make" -dv_base_dependencies= ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo -docker_run_verify=\ +$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ @@ -107,40 +104,13 @@ -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:latest \ sh -c $(verify_command) -.PHONY: harden -harden: $(blocks) .PHONY: verify -verify: $(dv-targets) +verify: + cd ./verilog/dv/ && \ + export SIM=${SIM} DUMP=${DUMP} && \ + $(MAKE) -j$(THREADS) -$(dv-targets-rtl): SIM=RTL -$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies) - $(docker_run_verify) - -$(dv-targets-gl): SIM=GL -$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies) - $(docker_run_verify) - -$(dv-targets-gl-sdf): SIM=GL_SDF -$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies) - $(docker_run_verify) - -clean-targets=$(blocks:%=clean-%) -.PHONY: $(clean-targets) -$(clean-targets): clean-% : - rm -f ./verilog/gl/$*.v - rm -f ./spef/$*.spef - rm -f ./sdc/$*.sdc - rm -f ./sdf/$*.sdf - rm -f ./gds/$*.gds - rm -f ./mag/$*.mag - rm -f ./lef/$*.lef - rm -f ./maglef/*.maglef - -make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets) -.PHONY: what -what: - # $(make_what) # Install Openlane .PHONY: openlane
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 4422d7d..8d46511 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile @@ -139,7 +140,7 @@ %.lst: %.elf ${GCC_PREFIX}-objdump -d -S $< > $@ -%.hex: %.elf +%.hex: %.elf %.lst ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ @@ -163,26 +164,26 @@ ## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -endif +endif -## GL +##GL ifeq ($(SIM),GL) - ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + ifeq ($(DUMP),OFF) + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ - -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif endif
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 7de5444..00d308d 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -141,7 +141,7 @@ reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; - reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; + //reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP; @@ -150,6 +150,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); + reg_la0_data = 0x001; // Remove Soft Reset reg_la0_data = 0x000; reg_la0_data = 0x001; // Remove Soft Reset
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index e879f99..e9865d9 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -121,6 +121,9 @@ clock = 0; end +pullup(mprj_io[3]); + + `ifdef WFDUMP initial begin @@ -130,7 +133,6 @@ //$dumpvars(2,risc_boot_tb.uut); $dumpvars(1,risc_boot_tb.uut.mprj); $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host); - $dumpvars(1,risc_boot_tb.uut.mprj.u_riscv_top); //$dumpvars(0,risc_boot_tb.tb_uart); //$dumpvars(0,risc_boot_tb.u_user_spiflash); $display("Waveform Dump started");
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 0746413..3a63981 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index e8d50fd..115c577 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -60,10 +60,12 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 5c9addd..6714457 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -20,7 +20,6 @@ //// //// //// This file is part of the YIFive cores project //// //// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// //// //// //// Description //// //// This is a standalone test bench to validate the ////
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index a801f55..3e01197 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -24,8 +24,12 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -60,10 +64,12 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 0607308..e0f8219 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -444,13 +444,11 @@ wbd_ext_we_i ='h0; // write wbd_ext_dat_i ='h0; // data output wbd_ext_sel_i ='h0; // byte enable - if(data === cmp_data) begin - $display("STATUS: DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; end else begin - $display("ERROR: DEBUG WB USER ACCESS READ Address : %x, Exp Data : %x Rxd Data: ",address,cmp_data,data); - test_fail= 1; - #100 - $finish; + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); end repeat (2) @(posedge clock); end @@ -458,29 +456,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c.u_uart_core.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c.u_uart_core.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c.u_uart_core.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c.u_uart_core.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c.u_uart_core.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c.u_uart_core.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c.u_uart_core.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile index 96815e2..36a8452 100644 --- a/verilog/dv/user_pwm/Makefile +++ b/verilog/dv/user_pwm/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -61,9 +62,17 @@ $< -o $@ endif else - iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif endif %.vcd: %.vvp
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 43ba01f..e5222cc 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -20,7 +20,6 @@ //// //// //// This file is part of the YIFive cores project //// //// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// //// //// //// Description //// //// This is a standalone test bench to validate the //// @@ -413,21 +412,21 @@ `ifdef GL -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; `endif
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index ca06f65..c2b9689 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -24,13 +24,18 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 85751d6..b4f71fd 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -70,10 +71,12 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index 8968de7..a161b2e 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -24,13 +24,18 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 ### To Enable IVERILOG FST DUMP export IVERILOG_DUMPER = fst
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile index 6520c31..6d04ada 100644 --- a/verilog/dv/user_timer/Makefile +++ b/verilog/dv/user_timer/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index a97fa0f..d463172 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE @@ -70,10 +71,12 @@ ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ $< -o $@ endif endif
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index ffb5584..b5a6da1 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -184,7 +184,7 @@ if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); - end else begin + end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243); end else if(d_risc_id == 2) begin
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile index 04737d0..928d873 100644 --- a/verilog/dv/user_uart1/Makefile +++ b/verilog/dv/user_uart1/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index 1684a0d..0d9eaf4 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -24,6 +24,7 @@ ####################################################################### DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index b7dd1b4..0a94555 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -23,6 +23,7 @@ DESIGNS?=../../.. CONFIG = caravel_user_project +TOOLS?=/opt/riscv64i/ ######################################################## #include $(MCW_ROOT)/verilog/dv/make/env.makefile @@ -50,7 +51,8 @@ ## Compiler Information ####################################################################### -export GCC_PATH?= $(TOOLS)/bin +export TOOLS ?= /opt/riscv64i +export GCC_PATH ?= $(TOOLS)/bin export GCC_PREFIX?= riscv64-unknown-linux-gnu @@ -160,18 +162,18 @@ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -endif +endif -## GL +##GL ifeq ($(SIM),GL) - ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + ifeq ($(DUMP),OFF) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ - -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif endif
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index d3d63fe..03a5799 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -57,7 +57,7 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spi_enable = 1; + reg_spi_enable = 0; reg_wb_enable = 1; // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, // connect to housekeeping SPI
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index fdbbf92..ba2cae8 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -24,7 +24,7 @@ reg power1, power2; reg power3, power4; - wire gpio; + tri gpio; wire [37:0] mprj_io; wire [7:0] mprj_io_0; wire [15:0] checkbits; @@ -43,14 +43,21 @@ clock = 0; end +pullup(mprj_io[3]); + `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); $dumpvars(1, wb_port_tb); - //$dumpvars(0, wb_port_tb.uut.soc); - //$dumpvars(1, wb_port_tb.uut.mprj); + $dumpvars(1, wb_port_tb.uut); + $dumpvars(1, wb_port_tb.uut.mgmt_buffers); + $dumpvars(1, wb_port_tb.uut.housekeeping); + $dumpvars(1, wb_port_tb.uut.pll); + $dumpvars(1, wb_port_tb.uut.soc); + $dumpvars(1, wb_port_tb.uut.soc.core); + $dumpvars(1, wb_port_tb.uut.mprj); $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host); - $dumpvars(2, wb_port_tb.uut.mprj.u_pinmux); + //$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux); end `endif
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project index fbeb490..5ac85e4 100644 --- a/verilog/includes/includes.gl.caravel_user_project +++ b/verilog/includes/includes.gl.caravel_user_project
@@ -17,13 +17,4 @@ $(USER_PROJECT_VERILOG)/gl/pinmux.v $(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v $(USER_PROJECT_VERILOG)/gl/wb_interconnect.v -########################################################### -# STD CELLS - they need to be below the defines.v files -########################################################### --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v --v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 7966d8b..3d9a0b5 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -266,8 +266,8 @@ // 3 - Riscdunio (MPW-5) wire [15:0] manu_id = 16'h8268; // Asci value of RD -wire [3:0] total_core = 4'h02; -wire [3:0] chip_id = 4'h03; +wire [3:0] total_core = 4'h2; +wire [3:0] chip_id = 4'h3; wire [7:0] chip_rev = 8'h01; assign reg_0 = {manu_id,total_core,chip_id,chip_rev};