sdc/wb_interconnect.sdc

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# Created by write_sdc
# Sat Dec 10 08:54:13 2022
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current_design wb_interconnect
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# Timing Constraints
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create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
set_clock_transition 0.1500 [get_clocks {clk_i}]
set_clock_uncertainty -setup 0.5000 clk_i
set_clock_uncertainty -hold 0.2500 clk_i
set_propagated_clock [get_clocks {clk_i}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -max -add_delay [get_ports {rst_n}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -max -add_delay [get_ports {rst_n}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_ack_i}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_ack_i}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_ack_i}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_ack_i}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[9]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_ack_i}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_ack_i}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[0]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[10]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[11]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[12]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[13]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[14]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[15]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[16]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[17]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[18]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[19]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[1]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[20]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[21]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[22]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[23]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[24]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[25]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[26]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[27]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[28]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[29]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[2]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[30]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[31]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[3]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[4]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[5]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[6]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[7]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[8]}]
set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_ack_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_ack_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_err_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_err_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_ack_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_ack_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_err_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_err_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_ack_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_ack_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_err_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_err_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_cyc_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_cyc_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_stb_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_stb_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_we_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_we_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_cyc_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_cyc_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_stb_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_stb_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_we_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_cyc_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_cyc_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[10]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[10]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[11]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[11]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[12]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[12]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[13]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[13]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[14]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[14]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[15]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[15]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[16]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[16]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[17]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[17]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[18]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[18]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[19]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[19]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[20]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[20]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[21]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[21]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[22]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[22]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[23]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[23]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[24]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[24]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[25]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[25]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[26]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[26]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[27]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[27]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[28]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[28]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[29]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[29]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[30]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[30]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[31]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[31]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[4]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[4]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[5]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[5]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[6]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[6]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[7]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[7]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[8]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[8]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[9]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[9]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[0]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[0]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[1]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[1]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[2]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[2]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[3]}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[3]}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_stb_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_stb_o}]
set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_we_o}]
set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_we_o}]
set_max_delay\
    -from [get_ports {wbd_clk_int}] 4.0000
set_max_delay\
    -from [get_ports {wbd_clk_int}]\
    -to [get_ports {wbd_clk_wi}] 4.0000
set_max_delay\
    -to [get_ports {wbd_clk_wi}] 2.0000
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m0_wbd_lack_o}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m1_wbd_lack_o}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m2_wbd_lack_o}]
set_load -pin_load 0.0334 [get_ports {m3_wbd_ack_o}]
set_load -pin_load 0.0334 [get_ports {m3_wbd_err_o}]
set_load -pin_load 0.0334 [get_ports {m3_wbd_lack_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_bry_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[7]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[6]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[5]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[4]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[3]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[157]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[156]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[155]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[154]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[153]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[152]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[151]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[150]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[149]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[148]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[147]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[146]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[145]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[144]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[143]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[142]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[141]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[140]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[139]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[138]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[137]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[136]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[135]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[134]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[133]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[132]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[131]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[130]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[129]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[128]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[127]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[126]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[125]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[124]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[123]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[122]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[121]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[120]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[119]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[118]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[117]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[116]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[115]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[114]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[113]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[112]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[111]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[110]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[109]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[108]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[107]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[106]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[105]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[104]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[103]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[102]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[101]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[100]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[99]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[98]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[97]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[96]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[95]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[94]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[93]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[92]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[91]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[90]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[89]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[88]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[87]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[86]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[85]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[84]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[83]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[82]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[81]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[80]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[79]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[78]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[77]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[76]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[75]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[74]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[73]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[72]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[71]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[70]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[69]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[68]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[67]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[66]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[65]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[64]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[63]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[62]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[61]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[60]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[59]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[58]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[57]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[56]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[55]}]
set_load -pin_load 0.0334 [get_ports {ch_data_out[54]}]
set_load -<