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foss-eda-tools/third_party/shuttle/sky130/mpw-008/slot-004/75cebb146d29f4d263f490568a0cb7d78dee270f^!/.
commit
75cebb146d29f4d263f490568a0cb7d78dee270f
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Thu May 26 18:36:42 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Thu May 26 18:36:42 2022 +0530
tree
86349ea934bfd1d43a76c9171b17d6c05413f21f
parent
c18df79f328fe588d7871115a4532494327a5b78 [diff]
Timing clean up

diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index 9e9c32a..8854979 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl

@@ -55,6 +55,8 @@
 	$script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv           \
 	$script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv           \
 	$script_dir/../../verilog/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv               \
+        $script_dir/../../verilog/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv               \
+        $script_dir/../../verilog/rtl/yifive/ycr2c/src/lib/sync_fifo2.sv                     \
 	"
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr2c/src/includes ]
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -72,10 +74,10 @@
 ## Floorplan
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 560 950 "
+set ::env(DIE_AREA) "0 0 540 950 "
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.40
+set ::env(PL_TARGET_DENSITY) 0.43
 set ::env(CELL_PAD) "4"
 
 #set ::env(GLB_RT_MAXLAYER) 5

diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 5ac85e4..2876d64 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project

@@ -8,13 +8,171 @@
 +incdir+$(USER_PROJECT_VERILOG)/dv/model
 +incdir+$(USER_PROJECT_VERILOG)/dv/agents
 $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
-$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
-$(USER_PROJECT_VERILOG)/gl/ycr_intf.v
-$(USER_PROJECT_VERILOG)/gl/qspim_top.v
-$(USER_PROJECT_VERILOG)/gl/wb_host.v
-$(USER_PROJECT_VERILOG)/gl/ycr2_iconnect.v
-$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v
-$(USER_PROJECT_VERILOG)/gl/pinmux.v
-$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
-$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
 
+##################################################
+### USER PROJECT RTL
+##################################################
+#ifdef USER_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_top_wb.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+#endif
+
+##################################################
+### YCR INTERFACE
+##################################################
+#ifdef YCR_INTF_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/dcache_tag_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_async_wbb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_intf.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr_intf.v
+#endif
+##################################################
+### YCR INTER CONNECT
+##################################################
+#ifdef YCR_ICONNECT_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_iconnect.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_cross_bar.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr2_router.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_dmem_router.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_tcm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_timer.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/lib/ycr_arb.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr2_iconnect.v
+#endif
+
+
+##################################################
+### YCR CORE
+##################################################
+#ifdef YCR_CORE_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_core_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_synchronizer.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_clk_ctrl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_scu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_tapc_shift_reg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/ycr_dmi.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ifu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_idu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_exu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mprf.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_csr.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_ialu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_mul.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_div.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_lsu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v
+#endif
+##################################################
+### QSPIM
+##################################################
+#ifdef QSPIM_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/qspim_top.v
+#endif
+
+
+##################################################
+### WB_HOST
+##################################################
+#ifdef WB_HOST_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v
+#else
+$(USER_PROJECT_VERILOG)/gl/wb_host.v
+#endif
+
+##################################################
+### PINMUX
+##################################################
+#ifdef PINMUX_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/pinmux.v
+#endif
+
+##################################################
+### UART
+##################################################
+#ifdef UART_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv 
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
+#endif
+
+##################################################
+### WISHBONE INTERCONNECT
+##################################################
+#ifdef WB_INTER_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
+#endif
+
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv

diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index f28fced..ebbd617 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv

@@ -8,7 +8,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
@@ -22,7 +32,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
@@ -36,7 +56,17 @@
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin : bit_
+          sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule

diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c
index c548af0..922b82e 160000
--- a/verilog/rtl/yifive/ycr2c
+++ b/verilog/rtl/yifive/ycr2c

@@ -1 +1 @@
-Subproject commit c548af0aca4999d81d3a0168eee6a187b9fb060c
+Subproject commit 922b82e5227d3b9adcd41ca823f7c4011a1aa11e