icache and dcache bypass added
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 1534993..fe3302c 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -210,6 +210,10 @@ m1_wbd_sel_i\[2\] m1_wbd_sel_i\[1\] m1_wbd_sel_i\[0\] +m1_wbd_bl_i\[2\] +m1_wbd_bl_i\[1\] +m1_wbd_bl_i\[0\] +m1_wbd_bry_i m1_wbd_dat_i\[31\] m1_wbd_dat_i\[30\] m1_wbd_dat_i\[29\]
diff --git a/openlane/ycr2_iconnect/config.tcl b/openlane/ycr2_iconnect/config.tcl index 9484296..389847d 100644 --- a/openlane/ycr2_iconnect/config.tcl +++ b/openlane/ycr2_iconnect/config.tcl
@@ -60,7 +60,7 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 380 1100" +set ::env(DIE_AREA) "0 0 390 1100" #set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl #set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg index 178edb5..5cb4104 100644 --- a/openlane/ycr2_iconnect/pin_order.cfg +++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -938,7 +938,10 @@ core_dmem_req_ack 0200 0 2 core_dmem_req -core_dmem_cmd +core_dmem_cmd +core_dmem_bl\[2\] +core_dmem_bl\[1\] +core_dmem_bl\[0\] core_dmem_width\[1\] core_dmem_width\[0\] core_dmem_addr\[31\] @@ -1134,3 +1137,5 @@ rtc_clk pwrup_rst_n cpu_intf_rst_n +cfg_bypass_icache +cfg_bypass_dcache
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc index 0a05d50..32fd5d0 100644 --- a/openlane/ycr_core_top/base.sdc +++ b/openlane/ycr_core_top/base.sdc
@@ -14,18 +14,17 @@ #IMEM Constraints set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] -set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}] set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] @@ -34,8 +33,8 @@ #DMEM Constraints set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] -set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] -set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] @@ -44,9 +43,8 @@ set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}] set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}] set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 8854979..161152f 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -74,7 +74,7 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 540 950 " +set ::env(DIE_AREA) "0 0 550 950 " set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.43 @@ -92,5 +92,5 @@ set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" #Need to cross-check why global timing opimization creating setup vio with hugh hold fix -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1" +set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
diff --git a/openlane/ycr_intf/pin_order.cfg b/openlane/ycr_intf/pin_order.cfg index 6b93ea3..fb87e40 100644 --- a/openlane/ycr_intf/pin_order.cfg +++ b/openlane/ycr_intf/pin_order.cfg
@@ -186,6 +186,9 @@ core_dmem_req_ack 0200 0 2 core_dmem_req core_dmem_cmd +core_dmem_bl\[2\] +core_dmem_bl\[1\] +core_dmem_bl\[0\] core_dmem_width\[1\] core_dmem_width\[0\] core_dmem_addr\[31\] @@ -288,6 +291,8 @@ core_dmem_resp\[0\] cfg_dcache_force_flush +cfg_bypass_icache +cfg_bypass_dcache #S icache_mem_clk0 @@ -569,6 +574,10 @@ wbd_dmem_sel_o\[2\] wbd_dmem_sel_o\[1\] wbd_dmem_sel_o\[0\] +wbd_dmem_bl_o\[2\] +wbd_dmem_bl_o\[1\] +wbd_dmem_bl_o\[0\] +wbd_dmem_bry_o wbd_dmem_dat_o\[31\] wbd_dmem_dat_o\[30\] wbd_dmem_dat_o\[29\] @@ -633,6 +642,7 @@ wbd_dmem_dat_i\[2\] wbd_dmem_dat_i\[1\] wbd_dmem_dat_i\[0\] +wbd_dmem_lack_i wbd_dmem_ack_i wbd_dmem_err_i
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION index cf40e34..078e9d2 100644 --- a/signoff/wb_interconnect/OPENLANE_VERSION +++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 8120faaedf752714e65fb7ff91993a8e6630a664 +openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/sta/sdc/ycr_core_top.sdc b/sta/sdc/ycr_core_top.sdc index f0ec289..e7fcf77 100644 --- a/sta/sdc/ycr_core_top.sdc +++ b/sta/sdc/ycr_core_top.sdc
@@ -1,7 +1,7 @@ ############################################################################### # Timing Constraints ############################################################################### -create_clock -name core_clk -period 20.0000 [get_ports {clk}] +create_clock -name core_clk -period 10.0000 [get_ports {clk}] set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks] @@ -13,10 +13,10 @@ set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] #IMEM Constraints -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}] @@ -30,11 +30,11 @@ set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}] #DMEM Constraints -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] -set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}] +set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}] set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 17cd90d..71d260d 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_mcore user_sram_exec user_cache_bypass all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/firmware/link.ld index 222363d..b2a0030 100644 --- a/verilog/dv/firmware/link.ld +++ b/verilog/dv/firmware/link.ld
@@ -25,7 +25,7 @@ ENTRY(_start) MEMORY { - ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K + ROM (rxx) : ORIGIN = 0x0, LENGTH = 128K RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 64K TCM (rwx) : ORIGIN = 0x0C480000, LENGTH = 2K }
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 8d892af..ceaec71 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -71,7 +71,7 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "is62wvs1288.v"
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 8438fa6..b1e5ba9 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -282,8 +282,8 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2905_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_4000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1306_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_6000); end
diff --git a/verilog/dv/user_cache_bypass/Makefile b/verilog/dv/user_cache_bypass/Makefile new file mode 100644 index 0000000..eb7f108 --- /dev/null +++ b/verilog/dv/user_cache_bypass/Makefile
@@ -0,0 +1,95 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. +TOOLS?=/opt/riscv64i/ + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_cache_bypass + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_cache_bypass.c -o user_cache_bypass.o + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC64_PREFIX}-gcc -o user_cache_bypass.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_cache_bypass.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC64_PREFIX}-objcopy -O verilog user_cache_bypass.elf user_cache_bypass.hex + ${GCC64_PREFIX}-objdump -D user_cache_bypass.elf > user_cache_bypass.dump + rm crt.o user_cache_bypass.o +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< +risc_core_id=$(RISC_CORE) + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_cache_bypass/run_iverilog b/verilog/dv/user_cache_bypass/run_iverilog new file mode 100755 index 0000000..f083d6d --- /dev/null +++ b/verilog/dv/user_cache_bypass/run_iverilog
@@ -0,0 +1,42 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o + +riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 + +riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex + +riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump + +rm crt_tcm.o user_risc_boot.o + +#iverilog with waveform dump +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp + + +#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp + +# GLS +#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp + +vvp user_risc_boot_tb.vvp | tee test.log + +\rm -rf user_risc_boot_tb.vvp
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c new file mode 100644 index 0000000..9c99cd9 --- /dev/null +++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -0,0 +1,87 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// +#define SC_SIM_OUTPORT (0xf0000000) +#define uint32_t long +#define uint16_t int + +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) +#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) +#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) +#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) +#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) +#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) +#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) +#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) +#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) +#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) +#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) +#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) +#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) +#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) +#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) +#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) +#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) +#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) +#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) +#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) +#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) +#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) +#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +// ------------------------------------------------------------------------- +// Test copying code into SRAM and running it from there. +// ------------------------------------------------------------------------- + +void test_function() +{ + reg_mprj_globl_reg24 = 0x33445566; // Sig-3 + reg_mprj_globl_reg25 = 0x44556677; // Sig-4 + + return; +} + +void main() +{ + uint16_t func[&main - &test_function]; + uint16_t *src_ptr; + uint16_t *dst_ptr; + + + src_ptr = &test_function; + dst_ptr = func; + + reg_mprj_globl_reg22 = 0x11223344; // Sig-1 + while (src_ptr < &main) { + *(dst_ptr++) = *(src_ptr++); + } + + // Call the routine in SRAM + reg_mprj_globl_reg23 = 0x22334455; // Sig-2 + + ((void(*)())func)(); + + reg_mprj_globl_reg26 = 0x55667788; + reg_mprj_globl_reg27 = 0x66778899; + + // Signal end of test +} +
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v new file mode 100644 index 0000000..c5d1478 --- /dev/null +++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -0,0 +1,418 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the Riscduino cores project //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core with Risc core executing code from TCM/SRAM. //// +//// with icache and dcache bypass mode //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ns + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +module user_cache_bypass_tb; + reg clock; + reg wb_rst_i; + reg power1, power2; + reg power3, power4; + + reg wbd_ext_cyc_i; // strobe/request + reg wbd_ext_stb_i; // strobe/request + reg [31:0] wbd_ext_adr_i; // address + reg wbd_ext_we_i; // write + reg [31:0] wbd_ext_dat_i; // data output + reg [3:0] wbd_ext_sel_i; // byte enable + + wire [31:0] wbd_ext_dat_o; // data input + wire wbd_ext_ack_o; // acknowlegement + wire wbd_ext_err_o; // error + + // User I/O + wire [37:0] io_oeb; + wire [37:0] io_out; + wire [37:0] io_in; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + reg test_fail; + reg [31:0] read_data; + integer d_risc_id; + + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(2, user_cache_bypass_tb); + $dumpvars(0, user_cache_bypass_tb.u_top.u_riscv_top); + end + `endif + + initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Risc Boot Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + // Set the icahce and dcache bypass + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0}); + + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + end else begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + end + + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (30) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + + + $display("Monitor: Reading Back the expected value"); + // User RISC core expect to write these value in global + // register, read back and decide on pass fail + // 0x30000018 = 0x11223344; + // 0x3000001C = 0x22334455; + // 0x30000020 = 0x33445566; + // 0x30000024 = 0x44556677; + // 0x30000028 = 0x55667788; + // 0x3000002C = 0x66778899; + + test_fail = 0; + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + + + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Standalone User Risc Boot (GL) Passed"); + `else + $display("Monitor: Standalone User Risc Boot (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone User Risc Boot (GL) Failed"); + `else + $display("Monitor: Standalone User Risc Boot (RTL) Failed"); + `endif + end + $display("###################################################"); + $finish; + end + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + end +`endif + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + + wire flash_clk = io_out[24]; + wire flash_csb = io_out[25]; + // Creating Pad Delay + wire #1 io_oeb_29 = io_oeb[29]; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; + + // Quard flash + s25fl256s #(.mem_file_name("user_cache_bypass.hex"), + .otp_file_name("none"), + .TimingModel("S25FL512SAGMFI010_F_30pF")) + u_spi_flash_256mb ( + // Data Inputs/Outputs + .SI (flash_io0), + .SO (flash_io1), + // Controls + .SCK (flash_clk), + .CSNeg (flash_csb), + .WPNeg (flash_io2), + .HOLDNeg (flash_io3), + .RSTNeg (!wb_rst_i) + + ); + + + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`include "s25fl256s.sv" +`default_nettype wire
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 067ac1c..4efed12 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -59,7 +59,6 @@ -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv - -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_hdu.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_pipe_tdu.sv -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/pipeline/ycr_ipic.sv
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index a9460e4..d4e056c 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -716,7 +716,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h2905_2022) u_reg_23 ( +gen_32b_reg #(32'h1306_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -729,9 +729,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 4.4 = 0004400 +// Software Reg-3: Poject Revison 4.6 = 0004600 // ---------------------------------------- -gen_32b_reg #(32'h0004_4000) u_reg_24 ( +gen_32b_reg #(32'h0004_6000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index 8cff517..a49490e 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -138,12 +138,13 @@ `include "yifive/ycr2c/src/top/ycr_timer.sv" `include "yifive/ycr2c/src/top/ycr_dmem_wb.sv" `include "yifive/ycr2c/src/top/ycr_imem_wb.sv" - `include "yifive/ycr2c/src/top/ycr2_mcore_router.sv" `include "yifive/ycr2c/src/top/ycr2_intf.sv" - `include "yifive/ycr2c/src/top/ycr2_mintf.sv" + `include "yifive/ycr2c/src/top/ycr_sram_mux.sv" + `include "yifive/ycr2c/src/top/ycr_router.sv" + `include "yifive/ycr2c/src/top/ycr2_iconnect.sv" + `include "yifive/ycr2c/src/top/ycr2_cross_bar.sv" `include "yifive/ycr2c/src/top/ycr2_top_wb.sv" - `include "yifive/ycr2c/src/top/ycr_icache_router.sv" - `include "yifive/ycr2c/src/top/ycr_dcache_router.sv" + `include "yifive/ycr2c/src/top/ycr_req_retiming.sv" `include "yifive/ycr2c/src/cache/src/core/icache_top.sv" `include "yifive/ycr2c/src/cache/src/core/icache_app_fsm.sv" `include "yifive/ycr2c/src/cache/src/core/icache_tag_fifo.sv" @@ -165,4 +166,8 @@ // standard cell + power pin `include "lib/clk_skew_adjust.gv" `include "lib/ctech_cells.sv" + + `include "digital_pll/src/digital_pll_controller.v" + `include "digital_pll/src/digital_pll.v" + `include "digital_pll/src/ring_osc2x13.v" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index a862533..bf93048 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -207,6 +207,8 @@ //// 4.4 May 29 2022, Dinesh A //// //// 1. Digital PLL integrated and clock debug signal add //// //// @digitial io [33] port +//// 4.6 June 13 2022, Dinesh A //// +//// 1. icache and dcache bypass config addded //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -357,8 +359,11 @@ wire wbd_riscv_dmem_we_i ; // write wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i ; // data output wire [3:0] wbd_riscv_dmem_sel_i ; // byte enable +wire [2:0] wbd_riscv_dmem_bl_i ; // byte enable +wire wbd_riscv_dmem_bry_i ; // burst access ready wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o ; // data input wire wbd_riscv_dmem_ack_o ; // acknowlegement +wire wbd_riscv_dmem_lack_o ; // acknowlegement wire wbd_riscv_dmem_err_o ; // error //--------------------------------------------------------------------- @@ -609,6 +614,8 @@ wire [3:0] cfg_riscv_sram_lphase = cfg_riscv_ctrl[3:0]; wire [2:0] cfg_riscv_cache_ctrl = cfg_riscv_ctrl[6:4]; wire [1:0] cfg_riscv_debug_sel = cfg_riscv_ctrl[9:8]; +wire cfg_bypass_icache = cfg_riscv_ctrl[10]; +wire cfg_bypass_dcache = cfg_riscv_ctrl[11]; ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -730,6 +737,8 @@ .core_debug_sel (cfg_riscv_debug_sel ), .cfg_sram_lphase (cfg_riscv_sram_lphase ), .cfg_cache_ctrl (cfg_riscv_cache_ctrl ), + .cfg_bypass_icache (cfg_bypass_icache ), + .cfg_bypass_dcache (cfg_bypass_dcache ), // Clock .core_clk (cpu_clk ), @@ -839,8 +848,11 @@ .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), + .wbd_dmem_bl_o (wbd_riscv_dmem_bl_i ), + .wbd_dmem_bry_o (wbd_riscv_dmem_bry_i ), .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), + .wbd_dmem_lack_i (wbd_riscv_dmem_lack_o ), .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) ); @@ -1047,11 +1059,14 @@ .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), + .m1_wbd_bl_i (wbd_riscv_dmem_bl_i ), + .m1_wbd_bry_i (wbd_riscv_dmem_bry_i ), .m1_wbd_we_i (wbd_riscv_dmem_we_i ), .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), + .m1_wbd_lack_o (wbd_riscv_dmem_lack_o ), .m1_wbd_err_o (wbd_riscv_dmem_err_o ), // Master 2 Interface
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 8ab9487..9fb6344 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -136,6 +136,8 @@ input logic [31:0] m1_wbd_dat_i, input logic [31:0] m1_wbd_adr_i, input logic [3:0] m1_wbd_sel_i, + input logic [2:0] m1_wbd_bl_i, + input logic m1_wbd_bry_i, input logic m1_wbd_we_i, input logic m1_wbd_cyc_i, input logic m1_wbd_stb_i, @@ -363,6 +365,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ), @@ -441,6 +445,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ), @@ -519,6 +525,8 @@ .m1_wbd_dat_i (m1_wbd_dat_i ), .m1_wbd_adr_i (m1_wbd_adr_i ), .m1_wbd_sel_i (m1_wbd_sel_i ), + .m1_wbd_bl_i (m1_wbd_bl_i ), + .m1_wbd_bry_i (m1_wbd_bry_i ), .m1_wbd_we_i (m1_wbd_we_i ), .m1_wbd_cyc_i (m1_wbd_cyc_i ), .m1_wbd_stb_i (m1_wbd_stb_i ),
diff --git a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv index 87f0d4a..bc70ea2 100644 --- a/verilog/rtl/wb_interconnect/src/wb_slave_port.sv +++ b/verilog/rtl/wb_interconnect/src/wb_slave_port.sv
@@ -61,6 +61,8 @@ input logic [31:0] m1_wbd_dat_i, input logic [31:0] m1_wbd_adr_i, input logic [3:0] m1_wbd_sel_i, + input logic [2:0] m1_wbd_bl_i, + input logic m1_wbd_bry_i, input logic m1_wbd_we_i, input logic m1_wbd_cyc_i, input logic m1_wbd_stb_i, @@ -172,8 +174,8 @@ assign m1_wb_wr.wbd_dat = m1_wbd_dat_i; assign m1_wb_wr.wbd_adr = {m1_wbd_adr_i[31:2],2'b00}; assign m1_wb_wr.wbd_sel = m1_wbd_sel_i; -assign m1_wb_wr.wbd_bl = 'h1; -assign m1_wb_wr.wbd_bry = 'b1; +assign m1_wb_wr.wbd_bl = {7'b0,m1_wbd_bl_i}; +assign m1_wb_wr.wbd_bry = m1_wbd_bry_i; assign m1_wb_wr.wbd_we = m1_wbd_we_i; assign m1_wb_wr.wbd_cyc = m1_wbd_cyc_i; assign m1_wb_wr.wbd_stb = m1_stb_i;
diff --git a/verilog/rtl/yifive/ycr2c b/verilog/rtl/yifive/ycr2c index 922b82e..1c7c248 160000 --- a/verilog/rtl/yifive/ycr2c +++ b/verilog/rtl/yifive/ycr2c
@@ -1 +1 @@ -Subproject commit 922b82e5227d3b9adcd41ca823f7c4011a1aa11e +Subproject commit 1c7c248e0fbf41b2db64a746a61651742c9120c7