commit c0f115c4c0dc44da8a2dabeae75c139f8d2a9594
author jeffdi <jeffdi@efabless.com> Tue Oct 18 15:02:03 2022 -0700
committer jeffdi <jeffdi@efabless.com> Tue Oct 18 15:02:03 2022 -0700
tree 2ad14af0898528105ea5f40dd5d4f72ec83220f4
parent b8e5cd65b0462fbbf0fc7d131d05e87670fea972

update config.json

openlane/user_project_wrapper/config.json

diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index d0e9cfc..99ac12b 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -6,9 +6,9 @@
     "CLOCK_NET": "mprj.clk",
     "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
     "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
-    "VERILOG_FILES_BLACKBOX": ["dir::project_root/verilog/rtl/defines.v", "dir::project_root/verilog/rtl/user_proj_example.v"],
-    "EXTRA_LEFS": "dir::project_root/lef/user_proj_example.lef",
-    "EXTRA_GDS_FILES": "dir::project_root/gds/user_proj_example.gds",
+    "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"],
+    "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
+    "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
     "FP_PDN_CHECK_NODES": 0,
     "SYNTH_ELABORATE_ONLY": 1,
     "PL_RANDOM_GLB_PLACEMENT": 1,