update vdd and vss
Signed-off-by: Sean Cross <sean@xobs.io>
diff --git a/.gitignore b/.gitignore
index 04edfb0..5b0a9df 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,14 @@
*.lst
*.vcd
*.gtkw
+
+# These all seem to be generated by the build, and can probably be ignored
+# unless a release is generated
+/verilog/gl/*.v
+/spef/*.spef
+/sdc/*.sdc
+/sdf/*.sdf
+/gds/*.gds
+/mag/*.mag
+/lef/*.lef
+/maglef/*.maglef
diff --git a/openlane/wb_pio/config.json b/openlane/wb_pio/config.json
index 73595bd..5e4e44a 100644
--- a/openlane/wb_pio/config.json
+++ b/openlane/wb_pio/config.json
@@ -4,17 +4,17 @@
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/wb_pio_top.v", "dir::../../verilog/rtl/fpga_pio/src/*.v"],
"CLOCK_PERIOD": 10,
"CLOCK_PORT": "wb_clk_i",
- "CLOCK_NET": "counter.clk",
+ "CLOCK_NET": "pio1.clk",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 1900 1600",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
- "PL_BASIC_PLACEMENT": 1,
+ "PL_BASIC_PLACEMENT": 0,
"PL_TARGET_DENSITY": 0.50,
"SYNTH_NO_FLAT": 0,
- "VDD_NETS": ["vccd1"],
- "GND_NETS": ["vssd1"],
+ "VDD_NETS": ["vdd"],
+ "GND_NETS": ["vss"],
"DIODE_INSERTION_STRATEGY": 4,
- "RUN_CVC": 1,
+ "RUN_CVC": 0,
"SYNTH_STRATEGY": "DELAY 4",
"pdk::sky130*": {
"FP_CORE_UTIL": 75,
@@ -41,7 +41,6 @@
"CLOCK_PERIOD": 24.0,
"FP_CORE_UTIL": 20,
"RT_MAX_LAYER": "Metal4",
- "SYNTH_MAX_FANOUT": 4,
- "PL_TARGET_DENSITY": 0.85
+ "SYNTH_MAX_FANOUT": 4
}
}
diff --git a/verilog/rtl/wb_pio_top.v b/verilog/rtl/wb_pio_top.v
index ce5deb7..d8fc045 100644
--- a/verilog/rtl/wb_pio_top.v
+++ b/verilog/rtl/wb_pio_top.v
@@ -39,8 +39,8 @@
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
- inout vccd1, // User area 1 1.8V supply
- inout vssd1, // User area 1 digital ground
+ inout vdd, // User area 1 1.8V supply
+ inout vss, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
