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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-040 / a194d0e9b5e7ba770762009efa68d6a57a594aaf
commita194d0e9b5e7ba770762009efa68d6a57a594aaf[log] [tgz]
authorAng Li <angl@princeton.edu>Fri May 20 17:01:41 2022 -0400
committerAng Li <angl@princeton.edu>Fri May 20 17:01:41 2022 -0400
treed7b1dff6950735d70fc1a48b562a674478234d4c
parente20bfbc621a920ef56036eb4123f2f6415e0936f [diff]
[RTL] PRGA fullsim
3 files changed
tree: d7b1dff6950735d70fc1a48b562a674478234d4c
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build

Design

We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile