Test PRGA
diff --git a/Makefile b/Makefile
index f5f7d06..7b7c19e 100644
--- a/Makefile
+++ b/Makefile
@@ -186,7 +186,7 @@
-e PDK_ROOT=$(PDK_ROOT) \
-e PDKPATH=$(PDKPATH) \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
- efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
+ efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)"
.PHONY: custom-precheck
custom-precheck: check-pdk check-precheck
diff --git a/README.md b/README.md
index ccb8e55..499d9eb 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,8 @@
This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.
-
+The project is a test project, forked from the MPW5 PRGA project.
+
A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)
- An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
- 24-track routing channel with L1 tracks
diff --git a/gds/tile_clb.gds b/gds/tile_clb.gds
deleted file mode 100644
index 3ebb99c..0000000
--- a/gds/tile_clb.gds
+++ /dev/null
Binary files differ
diff --git a/gds/tile_clb.gds.gz b/gds/tile_clb.gds.gz
new file mode 100644
index 0000000..9a3d75a
--- /dev/null
+++ b/gds/tile_clb.gds.gz
Binary files differ
diff --git a/gds/top.gds.gz b/gds/top.gds.gz
index 7b27454..21e1526 100644
--- a/gds/top.gds.gz
+++ b/gds/top.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index a6d4087..11cff61 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
