commit: 0a0912598a9cd202f07815b9366b5d02bcfda949
[log] [tgz]
author: Ang Li <angl@princeton.edu>
Fri May 20 22:28:49 2022 -0400
committer: Ang Li <angl@princeton.edu>
Fri May 20 22:28:49 2022 -0400
tree: b94665af9015271cacd8051edc8d0225aa95ad1a
parent: a194d0e9b5e7ba770762009efa68d6a57a594aaf [diff]

[C] Use NOPULL for inputs

verilog/dv/prga/prga.c[diff]

1 file changed

tree: b94665af9015271cacd8051edc8d0225aa95ad1a

README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
24-track routing channel with L1 tracks
Capable of implementing 16 out of 30 ISCAS'89 circuits

Design

We used a three level hierarchical design:

1x Caravel user project wrapper
- 1x PRGA top
  - 64x CLB tile