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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-039 / c4a2ba678ac2001236cfc75c90c8893326eaf265
commitc4a2ba678ac2001236cfc75c90c8893326eaf265[log] [tgz]
authorvijayank88 <paruthi143@gmail.com>Mon Nov 28 14:04:34 2022 +0000
committervijayank88 <paruthi143@gmail.com>Mon Nov 28 14:04:34 2022 +0000
tree0a282010ad61611ac2cb614b94436995b4de20c7
parent4395c10e1643c83b75c1ff3a839bc71ad77f02c6 [diff]
user_define update

Signed-off-by: vijayank88 <paruthi143@gmail.com>
2 files changed
tree: 0a282010ad61611ac2cb614b94436995b4de20c7
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. spi/
  14. verilog/
  15. .gitignore
  16. gfx430_architecture.png
  17. LICENSE
  18. Makefile
  19. README.md
README.md

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Graphics Controller

Description

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog. It is compatible with Texas Instruments' MSP430 microcontroller family and can execute the code generated by any MSP430 toolchain in a near cycle accurate way.

The core comes with some peripherals (16x16 Hardware Multiplier, Watchdog, GPIO, TimerA, generic templates), with a DMA interface, and most notably with a two-wire Serial Debug Interface supporting the MSPGCC GNU Debugger (GDB) for in-system software debugging.

While being fully FPGA friendly, this design is also particularly suited for ASIC implementations (typically mixed signal ICs with strong area and low-power requirements). In a nutshell, the openMSP430 brings with it:

  • Low area (8k-Gates), without hidden extra infrastructure overhead (memory backbone, IRQ controller and watchdog timer are already included).
  • Excellent code density.
  • Good performances.
  • Build-in power and clock managment options.
  • Multiple times Silicon Proven.

GFX430_Architecture

Features

Support following graphic modes:

  • 16bpp
  • 8bpp
  • 4bpp
  • 2bpp
  • 1bpp
  • Smart address generation unit for fast indirect memory access.
  • GPU allowing hardware FILL, COPY and COPY_TRANSPARENT operations.
  • Supports the LT24 Terasic daughter card.