Adding a dummy mos in tx_line to fix the module mismatch problem. The only thing left is the vssa1 problem
2 files changed
tree: a218f10d4915fe1ba84f2aaaa3d2240521ce8793
  1. .github/
  2. bypass_lvs_mag/
  3. configs/
  4. docs/
  5. drc/
  6. gds/
  7. mag/
  8. netgen/
  9. openlane/
  10. sandbox/
  11. verilog/
  12. xml_results/
  13. xschem/
  14. .gitattributes
  15. .gitignore
  16. .swp
  17. LICENSE
  18. Makefile
  19. README.md
  20. sourceme_precheck
  21. test_push
README.md

Caravel Analog User

License CI Caravan Build


:exclamation: Important Note

Please fill in your project documentation in this README.md file

This is a lab-on-a-chip research project targeted to bring instrumentation near the magnetic new materials. It contains a voltage controlled oscillator(VCO), a bandgap reference(BGR), and a variable gain amplifier (VGA).

VCO specs
    Frequency range: 1.71 ~ 9.73GHz
    Amplitude: 0.2 ~ 0.5V differential
    2nd harmonic < -60dB
    3rd harmonic < 60dB
    settling time < 6ns
    Startup time < 48 ns
BGA specs
    Output Vbg = 1.1974V+/-0.6mV (0.05% error) from -20 ~ 100C
        TC =  -5+/-45ppm V/C
    Output current reference = 39.95uA+/-0.11uA (0.27% error) from -20 ~ 100C
        TC = -0.001+/-0.007ppm A/C

Refer to README for this sample project documentation.