)]}'
{
  "commit": "0f37f4a7d8d122a7be1ebcfbaa2f279c0c516062",
  "tree": "a218f10d4915fe1ba84f2aaaa3d2240521ce8793",
  "parents": [
    "d77260190c7a26b2111c0c33bfed345cd62e1824"
  ],
  "author": {
    "name": "NohealthyBBQ",
    "email": "zexil@andrew.cmu.edu",
    "time": "Thu Dec 01 17:08:46 2022 -0500"
  },
  "committer": {
    "name": "NohealthyBBQ",
    "email": "zexil@andrew.cmu.edu",
    "time": "Thu Dec 01 17:08:46 2022 -0500"
  },
  "message": "Adding a dummy mos in tx_line to fix the module mismatch problem. The only thing left is the vssa1 problem\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ea4b8d8476638081fea5766b2ecf2d0e3aa4c5e3",
      "new_mode": 33188,
      "new_path": "mag/lvs/user_analog_project_wrapper.spice"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1c7cc10256e6f0702162b3421c167209b57baacd",
      "new_mode": 33188,
      "new_path": "mag/sky130_fd_pr__nfet_01v8_lvt_M9466H.mag"
    }
  ]
}