commit: 5ec6d70dea1ec1b3288778649be316a77d2ef9b4
[log] [tgz]
author: Ruige <295054118@whut.edu.cn>
Wed Nov 23 20:46:49 2022 +0800
committer: Ruige <295054118@whut.edu.cn>
Wed Nov 23 21:23:51 2022 +0800
tree: 0747451800e5a0c46ea44a7da22b9e34d928ae30
parent: 3f2d7c3ed02a001d422a868cac7f187b4566a7f4 [diff]

signoff design files

Signed-off-by: Ruige <295054118@whut.edu.cn>

Makefile[diff]
def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[Deleted - diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[Deleted - diff]
openlane/user_proj_example/config.json[diff]
openlane/user_proj_example/pin_order.cfg[diff]
openlane/user_proj_example/timing.sdc[Added - diff]
openlane/user_project_wrapper/config.json[diff]
openlane/user_project_wrapper/macro.cfg[diff]
verilog/dv/riscv/Makefile[Added - diff]
verilog/dv/riscv/Rift2Chip.v[Added - diff]
verilog/dv/riscv/axi_full_slv_sram.v[Added - diff]
verilog/dv/riscv/ci/.keep[Added - diff]
verilog/dv/riscv/ci/rv64ui-p-simple.dump[Added - diff]
verilog/dv/riscv/ci/rv64ui-p-simple.verilog[Added - diff]
verilog/dv/riscv/ci/rv64ui-v-simple.dump[Added - diff]
verilog/dv/riscv/ci/rv64ui-v-simple.verilog[Added - diff]
verilog/dv/riscv/gen_dffr.v[Added - diff]
verilog/dv/riscv/gen_dffren.v[Added - diff]
verilog/dv/riscv/gen_dpdffren.v[Added - diff]
verilog/dv/riscv/gen_rsffr.v[Added - diff]
verilog/dv/riscv/gen_sram.v[Added - diff]
verilog/dv/riscv/plusarg_reader.v[Added - diff]
verilog/dv/riscv/riscv.c[Added - diff]
verilog/dv/riscv/riscv_tb.v[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/TapeMain/Rift2LinkA.anno.json[Added - diff]
verilog/rtl/TapeMain/Rift2LinkA.fir[Added - diff]
verilog/rtl/TapeMain/Rift2LinkA.v[Added - diff]
verilog/rtl/TapeMain/firrtl_black_box_resource_files.f[Added - diff]
verilog/rtl/TapeMain/plusarg_reader.v[Added - diff]
verilog/rtl/rift2Wrap.v[Added - diff]
verilog/rtl/user_defines.v[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]

40 files changed

tree: 0747451800e5a0c46ea44a7da22b9e34d928ae30

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.