| # Caravel User Project: Rift2Chip 2330 |
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| ## Attention |
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| A Fake Code "LFSR16" and "Multiplier"is Uploaded. |
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| ### LFSR |
| A LFSR16 is instance, it will output four ramdom code in HEX to io. It will be connected to 7-segment seconds and display 4 numbers. |
| A IO can lock the LFSR, it will be connect to a switch. |
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| ### Multiplier |
| A Multiplier in Rift2Core is instance in 32-bits Mode. All ports are connected to la. |
| It's Boot4-WallceTree Multiplier. |
| -------------------------------------------- |
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| Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode. |
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| [RiftCore](https://github.com/whutddk/RiftCore) is the previous version of Rift2Core in Verilog. |
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| ---------------- |
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| ## Rift To Go |
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| Download Pre-compile Version [Here](https://github.com/whutddk/Rift2Core/releases), the newest status is as follows: |
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| |Version|Test|Dhrystone|CoreMark| |
| |:----: |:--:|:-------:|:------:| |
| |Rift-2300|N/A|N/A|N/A| |
| |Rift-2310|N/A|N/A|N/A| |
| |Rift-2320|N/A|N/A|N/A| |
| |Rift-2330|||| |
| |Rift-2340|||| |
| |Rift-2350|||| |
| |Rift-2360|||| |
| |Rift-2370|||| |
| |Rift-2380|||| |
| |Rift-2390|||| |
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| ## API |
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| Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules. |
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| Search the provided API in the Scala Doc. |
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| [API Here](https://whutddk.github.io/Rift2Core/ScalaDoc/api/index.html) |
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| ## Wiki |
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| [Wiki in Chinese](https://bitbucket.org/whutddk/rift2core/wiki/browse/) |
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| [Wiki in English(Comming Soon!)](https://bitbucket.org/whutddk/rift2core/wiki/browse/) |
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| --------------------------------------- |
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| ## Micro-Architecture |
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| ### FrontEnd |
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|  |
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| ### BackEnd |
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| ----------------------------------------------- |