update Makefile

openlane/user_proj_example/config.json

diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json
index de0ba2e..14b9bb4 100644
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -1,6 +1,8 @@
 {
     "DESIGN_NAME": "user_proj_example",
-    "VERILOG_FILES": "::env(CARAVEL_ROOT)/verilog/rtl/defines.v \\\n\t$script_dir/../../verilog/rtl/user_proj_example.v",
+    "VERILOG_FILES": "dir::verilog/rtl/defines.v dir::verilog/rtl/user_proj_example.v",
+
+
 
     "CLOCK_PERIOD": 10,
     "CLOCK_PORT": "wb_clk_i",