| /root/waveform_generator/lib/merge_memory.lib |
| /root/waveform_generator/lib/user_project_wrapper.lib |
| /root/waveform_generator/lib/wb_memory.lib |
| /root/waveform_generator/lib/wb_mux.lib |
| /root/waveform_generator/lib/wfg_top.lib |
| /root/waveform_generator/openlane/merge_memory/config.json |
| /root/waveform_generator/openlane/user_project_wrapper/config.json |
| /root/waveform_generator/openlane/wb_memory/config.json |
| /root/waveform_generator/openlane/wb_mux/config.json |
| /root/waveform_generator/openlane/wfg_top/config.json |
| /root/waveform_generator/sdc/merge_memory.sdc |
| /root/waveform_generator/sdc/user_project_wrapper.sdc |
| /root/waveform_generator/sdc/wb_memory.sdc |
| /root/waveform_generator/sdc/wb_mux.sdc |
| /root/waveform_generator/sdc/wfg_top.sdc |
| /root/waveform_generator/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/waveform_generator/verilog/includes/includes.gl.caravel_user_project |
| /root/waveform_generator/verilog/includes/includes.rtl.caravel_user_project |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_core/data/wfg_core_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_core/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_pat/data/wfg_drive_pat_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat.sv |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_channel.sv |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_pat/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_pat/testbench/test_wfg_drive_pat.py |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_spi/data/wfg_drive_spi_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_drive_spi/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_interconnect/data/wfg_interconnect_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_pkg.svh |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_interconnect/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_stim_mem/data/wfg_stim_mem_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_stim_mem/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_stim_sine/data/wfg_stim_sine_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_stim_sine/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_subcore/data/wfg_subcore_reg.json |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_subcore/sim/Makefile |
| /root/waveform_generator/verilog/rtl/waveform-generator/design/wfg_top/sim/Makefile |
