| # source files | |
| SRC := $(wildcard ../rtl/*.sv) | |
| SRC += $(wildcard ../testbench/*.sv) | |
| # defaults | |
| SIM ?= icarus | |
| TOPLEVEL_LANG ?= verilog | |
| VERILOG_SOURCES += $(SRC) | |
| # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file | |
| TOPLEVEL = wfg_drive_pat_tb | |
| # MODULE is the basename of the Python test file | |
| export PYTHONPATH := $(PYTHONPATH):../testbench/ | |
| MODULE = test_wfg_drive_pat | |
| # include cocotb's make rules to take care of the simulator setup | |
| include $(shell cocotb-config --makefiles)/Makefile.sim |