openlane/wfg_top/config.json

{
    "DESIGN_NAME": "wfg_top",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/dsp_scale_sn_us.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_channel.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_top.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv",
        "dir::../../verilog/rtl/waveform-generator/design/wfg_top/rtl/wfg_top.sv"
        ],
    "CLOCK_PERIOD": 20,
    "CLOCK_PORT": "io_wbs_clk",
    "FP_SIZING": "absolute",
    "DIE_AREA": "0 0 750 550",
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "PL_BASIC_PLACEMENT": 0,
    "ROUTING_CORES": 6,
    "PL_TARGET_DENSITY": 0.3,
    "VDD_NETS": ["vccd1"],
    "GND_NETS": ["vssd1"],
    "DIODE_INSERTION_STRATEGY": 4,
    "RUN_CVC": 1,
    "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "RT_MAX_LAYER": "met4"
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 50.0,
        "FP_CORE_UTIL": 40,
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4,
        "PL_TARGET_DENSITY": 0.50
    }
}