| { |
| "DESIGN_NAME": "merge_memory", |
| "DESIGN_IS_CORE": 0, |
| "VERILOG_FILES": [ |
| "dir::../../verilog/rtl/defines.v", |
| "dir::../../verilog/rtl/merge_memory.sv" |
| ], |
| "CLOCK_TREE_SYNTH": 0, |
| "CLOCK_PORT": "", |
| "FP_SIZING": "absolute", |
| "DIE_AREA": "0 0 750 200", |
| "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", |
| "PL_BASIC_PLACEMENT": 0, |
| "ROUTING_CORES": 6, |
| "PL_TARGET_DENSITY": 0.7, |
| "VDD_NETS": ["vccd1"], |
| "GND_NETS": ["vssd1"], |
| "DIODE_INSERTION_STRATEGY": 4, |
| "RUN_CVC": 1, |
| "pdk::sky130*": { |
| "FP_CORE_UTIL": 45, |
| "RT_MAX_LAYER": "met4" |
| }, |
| "pdk::gf180mcuC": { |
| "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", |
| "CLOCK_PERIOD": 50.0, |
| "FP_CORE_UTIL": 40, |
| "RT_MAX_LAYER": "Metal4", |
| "SYNTH_MAX_FANOUT": 4, |
| "PL_TARGET_DENSITY": 0.50 |
| } |
| } |
