Add config files
diff --git a/openlane/merge_memory/config.json b/openlane/merge_memory/config.json new file mode 100644 index 0000000..3c23ef8 --- /dev/null +++ b/openlane/merge_memory/config.json
@@ -0,0 +1,32 @@ +{ + "DESIGN_NAME": "merge_memory", + "DESIGN_IS_CORE": 0, + "VERILOG_FILES": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/rtl/merge_memory.sv" + ], + "CLOCK_TREE_SYNTH": 0, + "CLOCK_PORT": "", + "FP_SIZING": "absolute", + "DIE_AREA": "0 0 750 200", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "PL_BASIC_PLACEMENT": 0, + "ROUTING_CORES": 6, + "PL_TARGET_DENSITY": 0.7, + "VDD_NETS": ["vccd1"], + "GND_NETS": ["vssd1"], + "DIODE_INSERTION_STRATEGY": 4, + "RUN_CVC": 1, + "pdk::sky130*": { + "FP_CORE_UTIL": 45, + "RT_MAX_LAYER": "met4" + }, + "pdk::gf180mcuC": { + "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", + "CLOCK_PERIOD": 50.0, + "FP_CORE_UTIL": 40, + "RT_MAX_LAYER": "Metal4", + "SYNTH_MAX_FANOUT": 4, + "PL_TARGET_DENSITY": 0.50 + } +}
diff --git a/openlane/merge_memory/pin_order.cfg b/openlane/merge_memory/pin_order.cfg new file mode 100644 index 0000000..9ce9913 --- /dev/null +++ b/openlane/merge_memory/pin_order.cfg
@@ -0,0 +1,16 @@ +#BUS_SORT + +#E +csb +addr\[.*\] +dout\[.*\] + +#S + +csb_mem0 +addr_mem0\[.*\] +dout_mem0\[.*\] + +csb_mem1 +addr_mem1\[.*\] +dout_mem1\[.*\]
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json deleted file mode 100644 index 370d74c..0000000 --- a/openlane/user_proj_example/config.json +++ /dev/null
@@ -1,45 +0,0 @@ -{ - "DESIGN_NAME": "user_proj_example", - "DESIGN_IS_CORE": 0, - "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"], - "CLOCK_PERIOD": 10, - "CLOCK_PORT": "wb_clk_i", - "CLOCK_NET": "counter.clk", - "FP_SIZING": "absolute", - "DIE_AREA": "0 0 900 600", - "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", - "PL_BASIC_PLACEMENT": 0, - "PL_TARGET_DENSITY": 0.55, - "VDD_NETS": ["vccd1"], - "GND_NETS": ["vssd1"], - "DIODE_INSERTION_STRATEGY": 4, - "RUN_CVC": 1, - "pdk::sky130*": { - "FP_CORE_UTIL": 45, - "RT_MAX_LAYER": "met4", - "scl::sky130_fd_sc_hd": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hdll": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hs": { - "CLOCK_PERIOD": 8 - }, - "scl::sky130_fd_sc_ls": { - "CLOCK_PERIOD": 10, - "SYNTH_MAX_FANOUT": 5 - }, - "scl::sky130_fd_sc_ms": { - "CLOCK_PERIOD": 10 - } - }, - "pdk::gf180mcuC": { - "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", - "CLOCK_PERIOD": 24.0, - "FP_CORE_UTIL": 40, - "RT_MAX_LAYER": "Metal4", - "SYNTH_MAX_FANOUT": 4, - "PL_TARGET_DENSITY": 0.45 - } -} \ No newline at end of file
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg deleted file mode 100644 index 2fda806..0000000 --- a/openlane/user_proj_example/pin_order.cfg +++ /dev/null
@@ -1,10 +0,0 @@ -#BUS_SORT - -#S -wb_.* -wbs_.* -la_.* -irq.* - -#N -io_.*
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json index 22a00ee..dbbea9e 100644 --- a/openlane/user_project_wrapper/config.json +++ b/openlane/user_project_wrapper/config.json
@@ -1,14 +1,39 @@ { "DESIGN_NAME": "user_project_wrapper", "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_project_wrapper.v"], - "CLOCK_PERIOD": 10, + "CLOCK_PERIOD": 20, "CLOCK_PORT": "user_clock2", - "CLOCK_NET": "mprj.clk", - "FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1", + "FP_PDN_MACRO_HOOKS": [ + "wfg_top_inst vccd1 vssd1 vccd1 vssd1", + "merge_memory_inst vccd1 vssd1 vccd1 vssd1", + "wb_mux_inst vccd1 vssd1 vccd1 vssd1", + "wb_memory_inst vccd1 vssd1 vccd1 vssd1", + "sky130_sram_2kbyte_1rw1r_32x512_8_inst0 vccd1 vssd1 vccd1 vssd1", + "sky130_sram_2kbyte_1rw1r_32x512_8_inst1 vccd1 vssd1 vccd1 vssd1" + ], "MACRO_PLACEMENT_CFG": "dir::macro.cfg", - "VERILOG_FILES_BLACKBOX": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"], - "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef", - "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds", + "VERILOG_FILES_BLACKBOX": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/gl/wfg_top.v", + "dir::../../verilog/gl/merge_memory.v", + "dir::../../verilog/gl/wb_mux.v", + "dir::../../verilog/gl/wb_memory.v", + "dir::../../../dependencies/pdks/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v" + ], + "EXTRA_LEFS": [ + "dir::../../lef/wfg_top.lef", + "dir::../../lef/merge_memory.lef", + "dir::../../lef/wb_mux.lef", + "dir::../../lef/wb_memory.lef", + "dir::../../../dependencies/pdks/sky130B/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef" + ], + "EXTRA_GDS_FILES": [ + "dir::../../gds/wfg_top.gds", + "dir::../../gds/merge_memory.gds", + "dir::../../gds/wb_mux.gds", + "dir::../../gds/wb_memory.gds", + "dir::../../../dependencies/pdks/sky130B/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds" + ], "FP_PDN_CHECK_NODES": 0, "SYNTH_ELABORATE_ONLY": 1, "PL_RANDOM_GLB_PLACEMENT": 1, @@ -51,23 +76,7 @@ "pdk::sky130*": { "RT_MAX_LAYER": "met4", "DIE_AREA": "0 0 2920 3520", - "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def", - "scl::sky130_fd_sc_hd": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hdll": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hs": { - "CLOCK_PERIOD": 8 - }, - "scl::sky130_fd_sc_ls": { - "CLOCK_PERIOD": 10, - "SYNTH_MAX_FANOUT": 5 - }, - "scl::sky130_fd_sc_ms": { - "CLOCK_PERIOD": 10 - } + "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def" }, "pdk::gf180mcuC": { "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", @@ -81,5 +90,9 @@ "FP_PDN_CHECK_NODES": 0, "MAGIC_WRITE_FULL_LEF": 0, "FP_PDN_ENABLE_RAILS": 0 - } + }, + "MAGIC_DRC_USE_GDS": 0, + "RUN_MAGIC_DRC": 0, + "QUIT_ON_MAGIC_DRC": 0, + "RUN_KLAYOUT_XOR": 0 }
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index a7365ab..8578df7 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1 +1,6 @@ -mprj 1175 1690 N +wfg_top_inst 1900 2200 N +sky130_sram_2kbyte_1rw1r_32x512_8_inst0 100 1500 N +sky130_sram_2kbyte_1rw1r_32x512_8_inst1 900 1500 N +merge_memory_inst 500 2375 N +wb_mux_inst 1250 200 N +wb_memory_inst 500 850 N
diff --git a/openlane/wb_memory/config.json b/openlane/wb_memory/config.json new file mode 100644 index 0000000..9efebdc --- /dev/null +++ b/openlane/wb_memory/config.json
@@ -0,0 +1,32 @@ +{ + "DESIGN_NAME": "wb_memory", + "DESIGN_IS_CORE": 0, + "VERILOG_FILES": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/rtl/wb_memory.sv" + ], + "CLOCK_PERIOD": 20, + "CLOCK_PORT": "io_wbs_clk", + "FP_SIZING": "absolute", + "DIE_AREA": "0 0 750 200", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "PL_BASIC_PLACEMENT": 0, + "ROUTING_CORES": 6, + "PL_TARGET_DENSITY": 0.7, + "VDD_NETS": ["vccd1"], + "GND_NETS": ["vssd1"], + "DIODE_INSERTION_STRATEGY": 4, + "RUN_CVC": 1, + "pdk::sky130*": { + "FP_CORE_UTIL": 45, + "RT_MAX_LAYER": "met4" + }, + "pdk::gf180mcuC": { + "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", + "CLOCK_PERIOD": 50.0, + "FP_CORE_UTIL": 40, + "RT_MAX_LAYER": "Metal4", + "SYNTH_MAX_FANOUT": 4, + "PL_TARGET_DENSITY": 0.50 + } +}
diff --git a/openlane/wb_memory/pin_order.cfg b/openlane/wb_memory/pin_order.cfg new file mode 100644 index 0000000..7f345ce --- /dev/null +++ b/openlane/wb_memory/pin_order.cfg
@@ -0,0 +1,8 @@ +#BUS_SORT + +#S +io_wbs_.* + +#N +.*mem0.* +.*mem1.*
diff --git a/openlane/wb_mux/config.json b/openlane/wb_mux/config.json new file mode 100644 index 0000000..d6ab448 --- /dev/null +++ b/openlane/wb_mux/config.json
@@ -0,0 +1,32 @@ +{ + "DESIGN_NAME": "wb_mux", + "DESIGN_IS_CORE": 0, + "VERILOG_FILES": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/rtl/wb_mux.sv" + ], + "CLOCK_TREE_SYNTH": 0, + "CLOCK_PORT": "", + "FP_SIZING": "absolute", + "DIE_AREA": "0 0 400 400", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "PL_BASIC_PLACEMENT": 0, + "ROUTING_CORES": 6, + "PL_TARGET_DENSITY": 0.7, + "VDD_NETS": ["vccd1"], + "GND_NETS": ["vssd1"], + "DIODE_INSERTION_STRATEGY": 4, + "RUN_CVC": 1, + "pdk::sky130*": { + "FP_CORE_UTIL": 45, + "RT_MAX_LAYER": "met4" + }, + "pdk::gf180mcuC": { + "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", + "CLOCK_PERIOD": 50.0, + "FP_CORE_UTIL": 40, + "RT_MAX_LAYER": "Metal4", + "SYNTH_MAX_FANOUT": 4, + "PL_TARGET_DENSITY": 0.50 + } +}
diff --git a/openlane/wb_mux/pin_order.cfg b/openlane/wb_mux/pin_order.cfg new file mode 100644 index 0000000..348a243 --- /dev/null +++ b/openlane/wb_mux/pin_order.cfg
@@ -0,0 +1,31 @@ +#BUS_SORT + +#E +io_wbs_adr_0\[.*\] +io_wbs_datwr_0\[.*\] +io_wbs_datrd_0\[.*\] +io_wbs_we_0 +io_wbs_sel_0\[.*\] +io_wbs_stb_0 +io_wbs_ack_0 +io_wbs_cyc_0 + +#W +io_wbs_adr_1\[.*\] +io_wbs_datwr_1\[.*\] +io_wbs_datrd_1\[.*\] +io_wbs_we_1 +io_wbs_sel_1\[.*\] +io_wbs_stb_1 +io_wbs_ack_1 +io_wbs_cyc_1 + +#S +io_wbs_adr\[.*\] +io_wbs_datwr\[.*\] +io_wbs_datrd\[.*\] +io_wbs_we +io_wbs_sel\[.*\] +io_wbs_stb +io_wbs_ack +io_wbs_cyc
diff --git a/openlane/wfg_top/config.json b/openlane/wfg_top/config.json new file mode 100644 index 0000000..f437e9a --- /dev/null +++ b/openlane/wfg_top/config.json
@@ -0,0 +1,55 @@ +{ + "DESIGN_NAME": "wfg_top", + "DESIGN_IS_CORE": 0, + "VERILOG_FILES": [ + "dir::../../verilog/rtl/defines.v", + "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/dsp_scale_sn_us.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_channel.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_top.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv", + "dir::../../verilog/rtl/waveform-generator/design/wfg_top/rtl/wfg_top.sv" + ], + "CLOCK_PERIOD": 20, + "CLOCK_PORT": "io_wbs_clk", + "FP_SIZING": "absolute", + "DIE_AREA": "0 0 600 600", + "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", + "PL_BASIC_PLACEMENT": 0, + "ROUTING_CORES": 6, + "PL_TARGET_DENSITY": 0.4, + "VDD_NETS": ["vccd1"], + "GND_NETS": ["vssd1"], + "DIODE_INSERTION_STRATEGY": 4, + "RUN_CVC": 1, + "pdk::sky130*": { + "FP_CORE_UTIL": 45, + "RT_MAX_LAYER": "met4" + }, + "pdk::gf180mcuC": { + "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", + "CLOCK_PERIOD": 50.0, + "FP_CORE_UTIL": 40, + "RT_MAX_LAYER": "Metal4", + "SYNTH_MAX_FANOUT": 4, + "PL_TARGET_DENSITY": 0.50 + } +}
diff --git a/openlane/wfg_top/pin_order.cfg b/openlane/wfg_top/pin_order.cfg new file mode 100644 index 0000000..05e6ff8 --- /dev/null +++ b/openlane/wfg_top/pin_order.cfg
@@ -0,0 +1,13 @@ +#BUS_SORT + +#S +io_wbs_.* + +#N +wfg_drive_.* +io_oeb.* + +#W +csb1 +addr1.* +dout1.*