verilog/includes/includes.rtl.caravel_user_project

# Caravel user project includes
-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
-v $(USER_PROJECT_VERILOG)/rtl/merge_memory.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_memory.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_mux.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_core/rtl/wfg_core.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_core/rtl/wfg_core_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_subcore/rtl/wfg_subcore_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_interconnect/rtl/wfg_interconnect_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_mem/rtl/dsp_scale_sn_us.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_mem/rtl/wfg_stim_mem_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_stim_sine/rtl/wfg_stim_sine_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_spi/rtl/wfg_drive_spi_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_channel.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/waveform-generator/design/wfg_top/rtl/wfg_top.sv