| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| /work/stu/yzhu/ai-chip/rioschip2/rioschip/openlane/top,top,22_11_24_22_08,flow completed,1h52m51s0ms,0h41m20s0ms,-2.0,3.8025,-1,14.88,17332.84,-1,0,0,0,0,0,0,0,167,0,-1,-1,3913213,465999,-1.34,-14.67,0.0,0.0,-1,-31.01,-13316.42,0.0,0.0,-1,2504384848.0,0.0,25.74,28.35,10.13,15.03,-1,38593,62723,1809,25776,0,0,0,47255,3062,316,334,739,3470,1072,206,19504,9115,9199,43,1416,53250,0,54666,3738780.2304,0.0468,0.0179,0.00038,0.0588,0.0232,5.43e-07,0.0675,0.0275,8.05e-07,29.77,13.5,74.07407407407408,12.5,AREA 0,20,50,1,153.6,153.18,0.34,0.3,sky130_fd_sc_hd,4,3 |
