fixed connections in ADC module
diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index c91ca9f..70e049d 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/4bit_dram.ext b/mag/4bit_dram.ext
index e03c6e2..583fd1e 100644
--- a/mag/4bit_dram.ext
+++ b/mag/4bit_dram.ext
@@ -8,97 +8,97 @@
use dram_array dram_array_0 1 0 30 0 1 520
node "li_370_440#" 35 65.1189 370 440 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4400 300 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_0/storage" 4.43108
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_1/RBL" 1.26319
-cap "dram_array_1/dram_cell_1/storage" "dram_array_1/dram_cell_1/WBL" -0.0312673
-cap "dram_array_0/dram_cell_1/WBL" "dram_array_0/dram_cell_1/storage" -2.78045
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_0/WBL" 18.6551
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RWL" 2.43793
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_0/storage" 2.62663
-cap "dram_array_0/dram_cell_1/storage" "dram_array_1/dram_cell_1/WBL" 4.78253
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/RBL" 1.08186
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_1/WBL" -1.5626
-cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_1/WBL" 5.60188
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/WBL" 103.739
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_0/WBL" 1.63195
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_0/dram_cell_1/RBL" -0.137974
-cap "dram_array_1/dram_cell_1/RWL" "dram_array_0/dram_cell_1/storage" 0.398074
-cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_1/WBL" -0.467034
-cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_0/WBL" 19.2726
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_1/WBL" 2.55547
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_1/WBL" -5.25471
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_0/storage" -0.519257
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_1/storage" 0.938398
-cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_0/RWL" 0.114594
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/WBL" -2.08074
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/WBL" 11.8825
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/RWL" 0.275028
-cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_1/RBL" -0.0540698
-cap "dram_array_1/dram_cell_1/storage" "dram_array_1/dram_cell_0/WBL" -0.0750067
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_0/RBL" 5.13798
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/storage" 1.40336
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/storage" 0.12309
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_1/dram_cell_1/RBL" -1.01813
-cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_1/RBL" 1.29475
-cap "dram_array_0/dram_cell_1/storage" "dram_array_1/dram_cell_0/WBL" 1.42982
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/RWL" 0.0720466
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_0/dram_cell_1/WBL" -0.175542
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/RWL" 1.19074
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_1/storage" -0.1572
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/RBL" 1.66109
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_1/RBL" 3.5021
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/WBL" 3.98393
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_0/WBL" 145.991
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_0/RWL" 2.1812
-cap "dram_array_0/dram_cell_1/WBL" "dram_array_1/dram_cell_1/WBL" 48.2109
-cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_0/WBL" -0.160807
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/RBL" 4.04032
-cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_0/WBL" 2.63089
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/RWL" 0.264623
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/WBL" 14.0255
-cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_1/WBL" 0.954346
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_0/WBL" 104.516
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/WWL" 1.97293
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_1/RBL" -5.63239
-cap "dram_array_1/dram_cell_1/RWL" "dram_array_0/dram_cell_1/WBL" 2.284
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RBL" 4.03162
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_0/storage" 1.56996
-cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_1/WBL" -0.0670397
-cap "dram_array_1/dram_cell_1/storage" "dram_array_0/dram_cell_1/storage" 3.90423
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_1/WBL" 3.44757
cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_0/storage" 1.00506
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_1/dram_cell_1/WBL" -1.23666
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/storage" 0.574382
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_0/WBL" 8.76976
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_0/storage" -1.79613
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_0/storage" 6.04535
-cap "dram_array_1/dram_cell_1/storage" "dram_array_1/dram_cell_1/RBL" -0.346486
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_0/WBL" -0.170606
-cap "dram_array_0/dram_cell_1/WBL" "dram_array_1/dram_cell_0/WBL" 5.04076
-cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_0/RBL" -1.29851
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_1/storage" 0.169062
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_1/WBL" -1.48826
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/storage" 1.53342
-cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_0/WBL" -11.5862
-cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_1/storage" 1.8317
-cap "dram_array_1/dram_cell_1/storage" "dram_array_0/dram_cell_1/RBL" 2.15495
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/WBL" 251.074
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_0/dram_cell_0/storage" -2.2775
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_1/storage" 20.7873
-cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_1/storage" -1.5633
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/RBL" 4.01738
-cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_0/WBL" -0.446088
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_0/storage" 3.09709
-cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/RWL" 0.603255
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_1/WWL" -2.08074
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_0/storage" 1.29475
cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/RWL" -3.11008
-cap "dram_array_1/dram_cell_0/RBL" "dram_array_1/dram_cell_0/WBL" -2.48551
-cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_1/RBL" 1.85263
-cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/storage" 0.770791
-cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_1/WBL" 1.44363
+cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_0/RBL" 3.09709
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_0/dram_cell_1/storage" 1.42982
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_1/storage" -0.346486
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_1/WBL" 5.60188
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_0/WBL" 104.516
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_1/RBL" -0.467034
+cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_0/storage" 4.43108
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_0/dram_cell_0/RBL" 18.6551
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_0/RWL" 4.01738
+cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_1/storage" 0.938398
+cap "dram_array_1/dram_cell_1/RWL" "dram_array_0/dram_cell_1/WBL" 2.284
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_0/RBL" 3.5021
cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_0/RBL" 35.6298
-cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/RBL" 1.46047
-cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_1/RBL" 7.43198
+cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/RWL" 0.275028
+cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_1/WBL" 0.954346
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_0/dram_cell_0/storage" 19.2726
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_1/WWL" 1.46047
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_0/storage" -0.0670397
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_0/WBL" -0.137974
+cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_0/RWL" 0.114594
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_0/dram_cell_0/RBL" -0.170606
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/RWL" 0.0720466
+cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_0/RBL" 2.62663
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_1/dram_cell_1/storage" -0.0750067
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_0/dram_cell_1/WBL" 5.04076
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_0/WBL" -11.5862
+cap "dram_array_0/dram_cell_0/storage" "dram_array_0/dram_cell_0/WBL" -2.2775
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/storage" 0.12309
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RWL" 145.991
+cap "dram_array_1/dram_cell_0/RBL" "dram_array_0/dram_cell_1/WBL" 3.44757
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_1/storage" -1.5633
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_0/RBL" -1.23666
+cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_1/storage" -0.1572
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/storage" 0.770791
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_0/dram_cell_1/WBL" -0.175542
+cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_0/RBL" 5.13798
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_1/dram_cell_1/WWL" 14.0255
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_0/storage" -0.0540698
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_0/dram_cell_0/WBL" 3.98393
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_0/RBL" -5.63239
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RWL" 2.43793
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_0/RBL" 1.66109
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_0/storage" -1.79613
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_0/WBL" -0.160807
+cap "dram_array_0/dram_cell_0/storage" "dram_array_0/dram_cell_0/RBL" -0.519257
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_0/WBL" 1.63195
+cap "dram_array_0/dram_cell_1/storage" "dram_array_0/dram_cell_1/WBL" -2.78045
+cap "dram_array_0/dram_cell_1/storage" "dram_array_1/dram_cell_1/storage" 3.90423
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_0/dram_cell_1/storage" 4.78253
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/storage" 2.15495
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_1/dram_cell_0/RBL" -1.01813
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_0/dram_cell_1/WBL" -5.25471
+cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_1/storage" 0.169062
+cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/storage" 1.40336
+cap "dram_array_0/dram_cell_0/RBL" "dram_array_0/dram_cell_1/WBL" -1.48826
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/WBL" 11.8825
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_1/dram_cell_0/storage" -0.446088
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_0/WBL" 1.08186
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_0/dram_cell_0/RBL" 251.074
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_0/RWL" 1.85263
+cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_0/RWL" 2.1812
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_1/RWL" 0.264623
+cap "dram_array_1/dram_cell_0/storage" "dram_array_1/dram_cell_0/RBL" -1.29851
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_1/storage" 20.7873
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_0/dram_cell_0/storage" 1.44363
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/WWL" 1.26319
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_0/RBL" 1.97293
+cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_0/RWL" 1.56996
+cap "dram_array_1/dram_cell_0/storage" "dram_array_0/dram_cell_0/WBL" 2.63089
cap "dram_array_1/dram_cell_1/storage" "dram_array_0/dram_cell_1/WBL" 4.01725
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_1/storage" 1.8317
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_1/storage" -0.0312673
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RBL" -2.48551
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_0/dram_cell_1/WBL" 48.2109
+cap "dram_array_1/dram_cell_0/RWL" "dram_array_1/dram_cell_1/storage" 0.574382
+cap "dram_array_1/dram_cell_0/RWL" "dram_array_0/dram_cell_1/WBL" -1.5626
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/RBL" 7.43198
+cap "dram_array_0/dram_cell_0/storage" "dram_array_1/dram_cell_1/WWL" 6.04535
+cap "dram_array_1/dram_cell_0/WBL" "dram_array_0/dram_cell_0/WBL" 8.76976
+cap "dram_array_1/dram_cell_1/RBL" "dram_array_0/dram_cell_0/RBL" 4.04032
+cap "dram_array_1/dram_cell_1/WBL" "dram_array_1/dram_cell_0/RWL" 103.739
+cap "dram_array_1/dram_cell_1/RWL" "dram_array_0/dram_cell_1/storage" 0.398074
+cap "dram_array_0/dram_cell_1/RBL" "dram_array_1/dram_cell_1/RWL" 1.19074
+cap "dram_array_0/dram_cell_0/RBL" "dram_array_1/dram_cell_1/RWL" 0.603255
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_0/dram_cell_1/WBL" 2.55547
+cap "dram_array_1/dram_cell_1/WWL" "dram_array_1/dram_cell_1/storage" 1.53342
+cap "dram_array_0/dram_cell_0/WBL" "dram_array_1/dram_cell_0/RBL" 4.03162
merge "dram_array_0/VSUBS" "dram_array_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "dram_array_1/VSUBS" "VSUBS"
merge "dram_array_0/dram_cell_1/RWL" "dram_array_1/dram_cell_0/RWL" -172.622 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -160 0 0 0 0 -2700 -210 0 0 0 0 0 0
diff --git a/mag/8bit_dram.ext b/mag/8bit_dram.ext
index efc0c0b..97634e6 100644
--- a/mag/8bit_dram.ext
+++ b/mag/8bit_dram.ext
@@ -10,321 +10,321 @@
node "li_790_290#" 67 97.1038 790 290 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8320 496 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cap "li_790_290#" "li_1660_290#" 7.01687
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.14214
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.895458
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.02273
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.62703
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.29475
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 3.20098
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.49211
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 8.27494
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 3.33668
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 2.92916
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.39922
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.599686
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.50198
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.428145
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 4.04019
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 3.8719
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -11.5862
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.02571
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.276897
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.462736
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.170606
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.74082
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.42982
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.639264
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.00506
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.2775
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.446088
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 5.78903
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.105583
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.10264
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 1.11844
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.43754
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.65225
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.488613
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.16956
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.940947
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.10429
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.18288
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 7.43076
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 3.8719
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 4.01725
-cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.654306
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 5.144
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -2.48533
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.137974
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 4.78253
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.48836
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.30807
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.44414
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.410131
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0533245
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.270571
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.92916
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.0670397
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.79197
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 4.10545
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.7076
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 1.8116
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.880825
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 9.2665
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.67971
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.196152
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.418966
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.0805
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -1.23651
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.58055
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.160626
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.40336
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.624513
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 8.76976
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.938398
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.75042
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.661855
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.666265
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.51272
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.00647
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 6.17545
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" -1.29851
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.831003
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.734378
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" -2.2105
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 2.49974
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 5.86929
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.6507
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 6.33367
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.466881
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.18939
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" -1.48826
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.58081
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.15371
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 3.57988
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.98393
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.935436
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.8321
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.19546
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.105148
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.300223
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.31055
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.0540698
-cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.83359
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 2.84373
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.79143
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.63089
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.22354
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.77891
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" -5.25471
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 6.4929
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 3.71485
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.43142
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.89443
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.19162
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -1.01799
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.01248
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0750067
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0822097
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.103147
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 4.03177
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.15146
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0249404
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.3493
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.520149
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.939589
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.556618
cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.2779
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.439437
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.78073
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 7.07867
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 5.14492
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.229625
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.212935
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.85953
-cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.65711
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 3.76366
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.12492
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 2.49068
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.41701
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" -5.63264
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 2.00754
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 5.04076
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0312673
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.872503
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.10363
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.08201
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 3.90423
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.76406
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -1.79613
-cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 21.4621
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 4.99559
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 4.27688
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.37715
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.209878
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.110142
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.402441
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.41954
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.01576
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 48.2109
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.07761
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.36119
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.78549
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 18.6539
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" -2.78045
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.91088
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.79143
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.0732133
-cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.36578
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 19.2726
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.954346
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.309103
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.678465
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0388327
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0556588
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" -1.82431e-05
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 148.288
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 6.73702
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" -1.82431e-05
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.49068
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.488613
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.831003
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.3493
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 2.92916
cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.39057
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.3453
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.4477
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.291453
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 251.074
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.952641
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 104.516
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.19352
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.346486
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.56292
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.272103
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.07074
-cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.3204
-cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.770791
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.1572
-cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.69454
-cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.44363
-cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.15146
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.57013
-cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.0474576
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 3.09544
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 98.2721
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 3.12656
-cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.819409
-cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 4.43108
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.731891
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.796488
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 2.88615
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.1927
-cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 11.8816
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 5.60201
-cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.61703
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 3.57988
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" -5.63264
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 251.074
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.17545
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.309103
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 4.04019
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.36578
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.0805
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" -5.25471
cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0251167
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 35.6281
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.175542
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.196152
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 5.60201
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 48.2109
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.666265
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 4.99559
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.22354
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.79143
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.83359
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 98.2721
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 5.78903
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 5.14492
+cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.57013
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.939589
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.77891
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.16956
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" -1.48826
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.79143
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 6.73702
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.61703
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.212935
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.00647
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.209878
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 7.07867
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.14214
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 3.8719
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.37715
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.42982
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.6507
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.624513
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0533245
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.3204
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.74082
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.0474576
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.84373
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.938398
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.18939
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.272103
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 19.2726
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.428145
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.796488
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -2.48533
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.01248
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.229625
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 6.4929
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.07761
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.58055
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.62703
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.19546
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 2.41954
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.270571
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.654306
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0822097
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.51272
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.15146
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.76406
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.65711
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 8.76976
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.10264
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.69454
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.410131
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.639264
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.49211
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -2.2775
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.556618
+cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 4.03177
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.661855
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 5.144
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 2.92916
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.10363
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.56292
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 2.88615
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.276897
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.446088
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.105148
+cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.36119
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 3.90423
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.75042
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 2.78549
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 3.8719
+cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.8116
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 4.43108
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.79197
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.7076
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0750067
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.462736
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0388327
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.48836
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -1.29851
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.940947
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.300223
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.103147
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 4.27688
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.105583
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 4.10545
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.12656
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.78073
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.678465
cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" -1.56405
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.2105
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.291453
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.0732133
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 104.516
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 4.78253
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.8321
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.63089
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 3.71485
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 9.2665
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.872503
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.02571
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.935436
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -11.5862
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -1.79613
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.160626
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.770791
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.31055
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.50198
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.18288
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.19352
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.44363
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.12492
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -1.23651
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0556588
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.00506
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.880825
+cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.418966
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" -1.01799
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.1572
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 6.33367
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.952641
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 18.6539
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" -2.78045
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.67971
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.0249404
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.137974
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.895458
cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.58714
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.520149
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 35.6281
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 5.04076
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.30807
cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 3.74794
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 8.95512
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 1.21503
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.157422
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 13.6207
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.279345
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.0859045
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.233012
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 1.10881
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.28567
-cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.443827
-cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0562754
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0965689
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.75502
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.201977
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.030388
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.178753
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.84521
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.16762
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.667912
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.64913
-cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.153685
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.185055
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.165241
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.292951
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.660722
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 5.7162
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 3.39722
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.0587642
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.48464
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.4727
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.98393
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.20098
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.08201
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.731891
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.02273
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.89443
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.10429
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.110142
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.4477
+cap "4bit_dram_1/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 148.288
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.29475
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" -1.82431e-05
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.11844
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 2.49974
+cap "4bit_dram_1/dram_array_0/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.734378
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.599686
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.76366
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.85953
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0540698
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0670397
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 8.27494
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.170606
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.15371
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0312673
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.439437
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.44414
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.346486
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.3453
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.175542
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" -1.82431e-05
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.33668
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.09544
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.402441
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.43142
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.19162
+cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.43754
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.819409
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 4.65225
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.40336
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.954346
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.39922
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 11.8816
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 7.43076
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 5.86929
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.58081
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.15146
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.01576
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/WBL" 2.00754
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.07074
+cap "4bit_dram_1/dram_array_0/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 4.01725
+cap "4bit_dram_1/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.466881
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.1927
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 21.4621
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.91088
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.41701
+cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.178753
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.950407
cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.560458
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.03566
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.3542
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.89993
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.566051
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.326642
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.528576
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0472348
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0250806
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.644521
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.270803
-cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00881938
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.709403
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.950407
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0208523
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.102897
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 8.95512
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.48726
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.030388
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.401477
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.102897
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.46946
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.313359
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 1.10881
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.23181
+cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.233012
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.4727
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.3542
cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.45639
-cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.792606
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.22514
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.536694
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.137953
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.652168
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0320946
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.5878
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.18502
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.446647
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.50073
-cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.168525
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.11243
-cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.46946
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.363898
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.165964
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.295921
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.09681
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.158886
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0320946
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0250806
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.227874
cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.246331
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 2.72846
-cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0652651
-cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.314005
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0177814
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.062169
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0562754
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.270803
+cap "4bit_dram_1/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.279345
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.165241
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.584545
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0208523
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.0731444
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0177814
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0868822
+cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.292951
+cap "4bit_dram_1/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.04892
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.0474576
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.5878
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.792606
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.667912
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.0718539
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.446647
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.21503
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.644521
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.443827
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.165964
+cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.363898
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.64913
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.0153
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.89993
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.00237866
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.157422
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.189959
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.18502
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0859045
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.28567
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0965689
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.137953
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.16762
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0652651
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.29481
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.709403
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0472348
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.50073
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0507256
+cap "4bit_dram_0/dram_array_1/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.72846
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.185055
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 5.7162
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.566051
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.11243
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.75502
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.528576
+cap "4bit_dram_0/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.84521
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0537236
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.200361
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0804447
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.326642
+cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00881938
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.22514
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.48464
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 13.6207
+cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0997144
cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.486705
cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0876837
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0537236
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0731444
+cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.4816
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.153685
cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.957468
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.0153
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00237866
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.04892
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.775442
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0804447
-cap "4bit_dram_0/dram_array_0/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0659876
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.0718539
-cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.062169
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.52892
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.401477
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0868822
-cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.227874
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0198963
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.0474576
-cap "4bit_dram_0/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.4816
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.23181
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0997144
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RBL" "4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.445293
-cap "4bit_dram_1/dram_array_1/dram_cell_1/WBL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 1.48726
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.313359
-cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.200361
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.0587642
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.168525
cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.15382
-cap "4bit_dram_0/dram_array_0/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.189959
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.584545
-cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0507256
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.775442
cap "4bit_dram_1/dram_array_1/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.0877782
-cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.29481
+cap "4bit_dram_0/dram_array_1/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.652168
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.295921
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0659876
+cap "4bit_dram_1/dram_array_1/dram_cell_0/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.201977
+cap "4bit_dram_0/dram_array_0/dram_cell_0/storage" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.536694
+cap "4bit_dram_0/dram_array_1/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.03566
+cap "4bit_dram_1/dram_array_1/dram_cell_0/storage" "4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.314005
+cap "4bit_dram_1/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.660722
+cap "4bit_dram_0/dram_array_0/dram_cell_1/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.52892
+cap "4bit_dram_1/dram_array_1/dram_cell_1/storage" "4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0198963
+cap "4bit_dram_0/dram_array_1/dram_cell_1/WBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.39722
+cap "4bit_dram_0/dram_array_0/dram_cell_1/storage" "4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.445293
+cap "4bit_dram_0/dram_array_0/dram_cell_0/RBL" "4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.09681
+cap "4bit_dram_1/dram_array_1/dram_cell_1/RWL" "4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.158886
merge "4bit_dram_0/dram_array_1/dram_cell_1/WWL" "4bit_dram_1/dram_array_1/dram_cell_1/WWL" -157.777 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4500 -270 0 0 0 0 0 0
merge "4bit_dram_0/VSUBS" "4bit_dram_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "4bit_dram_1/VSUBS" "VSUBS"
diff --git a/mag/8bit_sens.ext b/mag/8bit_sens.ext
index 9c064ba..36660aa 100644
--- a/mag/8bit_sens.ext
+++ b/mag/8bit_sens.ext
@@ -54,2898 +54,2898 @@
node "VDD" 0 98.5381 -110 2930 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000 700 0 0 0 0 0 0 0 0 0 0
node "w_n100_2890#" 7899 3055.5 -100 2890 nw 0 0 0 0 1018500 6520 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "INx6x" "w_n100_2890#" 2.19653
-cap "INx6x" "INx5x" 6.51667
-cap "w_n100_2890#" "VDD" 62.7919
-cap "w_n100_2890#" "INx7x" 2.19653
-cap "INx1x" "w_n100_2890#" 2.19653
-cap "INx4x" "w_n100_2890#" 2.19653
-cap "INx4x" "INx5x" 6.51667
-cap "INx5x" "w_n100_2890#" 2.19653
-cap "SA_IREF" "OUTx7x" 1.83962
-cap "INx1x" "INx0x" 6.51667
-cap "SA_IREF" "GND" 2.34677
-cap "OUTx1x" "OUTx0x" 12.6429
-cap "INx2x" "INx3x" 6.51667
-cap "w_n100_2890#" "INx0x" 2.19653
-cap "OUTx6x" "OUTx5x" 12.6429
-cap "OUTx4x" "OUTx5x" 12.6429
-cap "OUTx4x" "OUTx3x" 12.6429
-cap "OUTx7x" "VREF" 1.2399
-cap "OUTx3x" "OUTx2x" 12.6429
-cap "GND" "VREF" 0.683333
cap "w_n100_2890#" "INx3x" 2.19653
-cap "INx4x" "INx3x" 6.51667
-cap "SA_IREF" "VREF" 79.804
-cap "OUTx6x" "OUTx7x" 12.6429
-cap "OUTx2x" "OUTx1x" 12.6429
+cap "OUTx4x" "OUTx3x" 12.6429
+cap "INx0x" "w_n100_2890#" 2.19653
+cap "INx2x" "INx3x" 6.51667
+cap "INx1x" "w_n100_2890#" 2.19653
+cap "OUTx0x" "OUTx1x" 12.6429
+cap "OUTx7x" "SA_IREF" 1.83962
+cap "INx6x" "INx5x" 6.51667
+cap "INx4x" "INx5x" 6.51667
cap "INx1x" "INx2x" 6.51667
+cap "GND" "SA_IREF" 2.34677
+cap "OUTx4x" "OUTx5x" 12.6429
+cap "INx2x" "w_n100_2890#" 2.19653
cap "INx6x" "INx7x" 6.51667
-cap "w_n100_2890#" "INx2x" 2.19653
-cap "sens_amp_0/net1" "sens_amp_1/OUT" 4.77555
-cap "sens_amp_2/net2" "sens_amp_3/OUT" 3.76509
-cap "sens_amp_4/net1" "sens_amp_3/net2" 0.712332
-cap "sens_amp_3/V_IN" "sens_amp_7/OUT" 0.00571773
-cap "sens_amp_6/OUT" "sens_amp_3/V_IN" 0.0115777
-cap "sens_amp_0/OUT" "sens_amp_2/GN" 4.70387
-cap "sens_amp_4/V_IN" "sens_amp_2/OUT" 2.13316
-cap "sens_amp_2/OUT" "sens_amp_1/net1" 4.77555
-cap "sens_amp_2/V_IN" "sens_amp_6/net1" 0.776685
-cap "sens_amp_2/net2" "sens_amp_1/net2" 17.0389
-cap "sens_amp_7/V_IN" "sens_amp_7/GND" 0.0653325
-cap "sens_amp_3/GN" "sens_amp_7/GN" 0.918583
-cap "sens_amp_4/GN" "sens_amp_7/GND" 3.64613
-cap "sens_amp_5/net2" "sens_amp_1/net1" 0.470415
-cap "sens_amp_6/V_IN" "sens_amp_3/net2" 0.348864
-cap "sens_amp_2/net2" "sens_amp_0/GN" 2.58596
-cap "sens_amp_2/net1" "sens_amp_4/net1" 1.30777
-cap "sens_amp_4/net2" "sens_amp_1/net1" 0.845903
-cap "sens_amp_2/OUT" "sens_amp_3/net2" 3.7884
-cap "sens_amp_1/net2" "sens_amp_0/OUT" 3.7884
-cap "sens_amp_6/GN" "sens_amp_1/net1" 0.248779
-cap "sens_amp_3/OUT" "sens_amp_2/GN" 5.12214
-cap "sens_amp_4/V_IN" "sens_amp_1/V_IN" 0.62569
-cap "sens_amp_1/V_IN" "sens_amp_1/net1" -2.0641
-cap "sens_amp_5/net2" "sens_amp_3/net2" 0.630883
-cap "sens_amp_2/net1" "sens_amp_6/V_IN" 0.173139
-cap "sens_amp_1/net2" "sens_amp_2/GN" 2.10269
-cap "sens_amp_0/V_IN" "sens_amp_3/GN" 2.85299
-cap "sens_amp_3/net1" "sens_amp_1/OUT" 3.72776
-cap "sens_amp_2/net2" "sens_amp_6/net1" 0.119523
-cap "sens_amp_4/V_IN" "sens_amp_2/V_IN" 0.877673
-cap "sens_amp_4/net2" "sens_amp_3/net2" 8.51946
-cap "sens_amp_7/OUT" "sens_amp_7/REF" 0.019367
-cap "sens_amp_6/OUT" "sens_amp_7/REF" 0.0785085
-cap "sens_amp_1/net1" "sens_amp_2/V_IN" 1.67233
-cap "sens_amp_5/V_IN" "sens_amp_2/OUT" 1.40414
-cap "sens_amp_3/V_IN" "sens_amp_1/OUT" 2.16013
-cap "sens_amp_0/GN" "sens_amp_2/GN" 4.23878
-cap "sens_amp_1/GN" "sens_amp_3/GN" 4.23878
-cap "sens_amp_6/GN" "sens_amp_3/net2" 0.532835
-cap "sens_amp_0/V_IN" "sens_amp_1/OUT" 3.53914
-cap "sens_amp_7/net2" "sens_amp_3/V_IN" 0.0173158
-cap "sens_amp_1/net2" "sens_amp_3/OUT" 3.15609
-cap "sens_amp_5/GN" "sens_amp_3/GN" 2.81242
-cap "sens_amp_2/net1" "sens_amp_2/OUT" -12.5567
-cap "sens_amp_1/V_IN" "sens_amp_3/net2" 2.47648
-cap "sens_amp_2/OUT" "sens_amp_5/net1" 2.27108
-cap "sens_amp_4/net1" "sens_amp_7/GND" 2.62879
-cap "sens_amp_1/GN" "sens_amp_1/OUT" -13.9502
-cap "sens_amp_0/GN" "sens_amp_3/OUT" 2.59192
-cap "sens_amp_7/SA_IREF" "sens_amp_2/OUT" 13.0647
-cap "sens_amp_2/net1" "sens_amp_5/net2" 0.845903
-cap "sens_amp_6/net2" "sens_amp_1/net1" 0.0433164
-cap "sens_amp_5/GN" "sens_amp_1/OUT" 1.95854
-cap "sens_amp_2/V_IN" "sens_amp_3/net2" 2.83815
-cap "sens_amp_1/V_IN" "sens_amp_4/OUT" 0.502023
-cap "sens_amp_2/net1" "sens_amp_4/net2" 1.12801
-cap "sens_amp_1/net2" "sens_amp_0/GN" 3.22983
-cap "sens_amp_5/V_IN" "sens_amp_1/V_IN" 0.304638
-cap "sens_amp_2/net1" "sens_amp_6/GN" 0.807013
-cap "sens_amp_3/net1" "sens_amp_0/net1" 2.31094
-cap "sens_amp_2/GN" "sens_amp_6/net1" 0.169074
-cap "sens_amp_6/V_IN" "sens_amp_7/GND" 0.242269
-cap "sens_amp_0/net2" "sens_amp_3/GN" 1.39501
-cap "sens_amp_3/V_IN" "sens_amp_0/net1" 0.34921
-cap "sens_amp_4/V_IN" "sens_amp_2/net2" 0.532494
-cap "sens_amp_2/net1" "sens_amp_1/V_IN" 3.97969
-cap "sens_amp_2/net2" "sens_amp_1/net1" 2.0465
-cap "sens_amp_1/V_IN" "sens_amp_5/net1" 0.776685
-cap "sens_amp_6/net2" "sens_amp_3/net2" 0.442664
-cap "sens_amp_0/V_IN" "sens_amp_0/net1" -2.0641
-cap "sens_amp_2/V_IN" "sens_amp_4/OUT" 0.676275
-cap "sens_amp_3/OUT" "sens_amp_6/net1" 2.27108
-cap "sens_amp_0/net2" "sens_amp_1/OUT" 3.76509
-cap "sens_amp_5/V_IN" "sens_amp_2/V_IN" 0.62569
-cap "sens_amp_2/OUT" "sens_amp_7/GND" 27.1477
-cap "sens_amp_3/GN" "sens_amp_7/REF" 2.83067
-cap "sens_amp_1/GN" "sens_amp_0/net1" 477.18
-cap "sens_amp_1/V_IN" "sens_amp_5/OUT" 0.272354
-cap "sens_amp_2/net1" "sens_amp_2/V_IN" -2.0641
-cap "sens_amp_5/GN" "sens_amp_0/net1" 0.248779
-cap "sens_amp_2/V_IN" "sens_amp_5/net1" 1.70182
-cap "sens_amp_5/net2" "sens_amp_7/GND" 2.3744
-cap "sens_amp_7/REF" "sens_amp_1/OUT" 5.47741
-cap "sens_amp_4/V_IN" "sens_amp_0/OUT" 0.520122
-cap "sens_amp_7/net2" "sens_amp_7/REF" 0.0357377
-cap "sens_amp_0/OUT" "sens_amp_1/net1" 4.69194
-cap "sens_amp_2/net2" "sens_amp_3/net2" 17.0389
-cap "sens_amp_2/V_IN" "sens_amp_5/OUT" 0.502023
-cap "sens_amp_4/net2" "sens_amp_7/GND" 3.78103
-cap "sens_amp_3/GN" "sens_amp_7/V_IN" 0.0965559
-cap "sens_amp_6/net2" "sens_amp_2/net1" 0.470415
-cap "sens_amp_6/GN" "sens_amp_7/GND" 1.32514
-cap "sens_amp_3/GN" "sens_amp_4/GN" 3.3399
-cap "sens_amp_4/V_IN" "sens_amp_2/GN" 0.775991
-cap "sens_amp_1/net1" "sens_amp_2/GN" 477.18
-cap "sens_amp_1/V_IN" "sens_amp_7/GND" 122.234
-cap "sens_amp_2/net2" "sens_amp_4/OUT" 0.162313
-cap "sens_amp_3/OUT" "sens_amp_7/net1" 0.801829
-cap "sens_amp_4/GN" "sens_amp_1/OUT" 3.43556
-cap "sens_amp_0/OUT" "sens_amp_3/net2" 2.26292
-cap "sens_amp_2/net2" "sens_amp_5/V_IN" 0.348864
-cap "sens_amp_4/V_IN" "sens_amp_3/OUT" 2.6267
-cap "sens_amp_3/OUT" "sens_amp_1/net1" 4.17653
-cap "sens_amp_7/GND" "sens_amp_2/V_IN" 122.017
-cap "sens_amp_0/net1" "sens_amp_7/REF" 1.24035
-cap "sens_amp_3/net1" "sens_amp_0/V_IN" 2.14603
-cap "sens_amp_2/net2" "sens_amp_5/net1" 0.364963
-cap "sens_amp_0/V_IN" "sens_amp_3/V_IN" 0.713437
-cap "sens_amp_2/GN" "sens_amp_3/net2" 3.22983
-cap "sens_amp_3/net1" "sens_amp_1/GN" 3.89829
-cap "sens_amp_4/V_IN" "sens_amp_1/net2" 0.348864
-cap "sens_amp_2/net2" "sens_amp_5/OUT" 0.112649
-cap "sens_amp_1/GN" "sens_amp_3/V_IN" 0.775991
-cap "sens_amp_6/net2" "sens_amp_7/GND" 1.19514
-cap "sens_amp_4/V_IN" "sens_amp_0/GN" 0.0965559
-cap "sens_amp_0/V_IN" "sens_amp_1/GN" 3.95137
-cap "sens_amp_0/GN" "sens_amp_1/net1" 5.85267
-cap "sens_amp_3/OUT" "sens_amp_3/net2" -1.96857
-cap "sens_amp_2/net1" "sens_amp_0/OUT" 3.78788
-cap "sens_amp_5/GN" "sens_amp_0/V_IN" 0.458631
-cap "sens_amp_0/net1" "sens_amp_4/GN" 0.807013
-cap "sens_amp_2/GN" "sens_amp_4/OUT" 0.290838
-cap "sens_amp_4/net1" "sens_amp_3/GN" 2.80353
-cap "sens_amp_5/V_IN" "sens_amp_2/GN" 0.46176
-cap "sens_amp_7/SA_IREF" "sens_amp_0/OUT" 10.3498
-cap "sens_amp_5/GN" "sens_amp_1/GN" 0.918583
-cap "sens_amp_1/net2" "sens_amp_3/net2" 1.26177
-cap "sens_amp_3/OUT" "sens_amp_4/OUT" 141.179
-cap "sens_amp_4/net1" "sens_amp_1/OUT" 2.27108
-cap "sens_amp_2/GN" "sens_amp_5/net1" 1.21488
-cap "sens_amp_2/net2" "sens_amp_7/GND" 5.73798
-cap "sens_amp_5/V_IN" "sens_amp_3/OUT" 2.13316
-cap "sens_amp_3/net1" "sens_amp_0/net2" 1.40467
-cap "sens_amp_0/GN" "sens_amp_3/net2" 1.65663
-cap "sens_amp_1/V_IN" "sens_amp_6/OUT" 0.0144184
-cap "sens_amp_0/net2" "sens_amp_3/V_IN" 0.384082
-cap "sens_amp_2/net1" "sens_amp_3/OUT" 4.77555
-cap "sens_amp_0/V_IN" "sens_amp_0/net2" -0.518908
-cap "sens_amp_2/GN" "sens_amp_5/OUT" 0.184951
-cap "sens_amp_3/OUT" "sens_amp_5/net1" 3.48963
-cap "sens_amp_6/V_IN" "sens_amp_3/GN" 0.46176
-cap "sens_amp_1/net2" "sens_amp_4/OUT" 0.112649
-cap "sens_amp_3/net1" "sens_amp_7/REF" 1.06743
-cap "sens_amp_1/GN" "sens_amp_0/net2" 2.10269
-cap "sens_amp_5/V_IN" "sens_amp_1/net2" 0.126724
-cap "sens_amp_7/SA_IREF" "sens_amp_3/OUT" 15.3664
-cap "sens_amp_0/OUT" "sens_amp_7/GND" 23.0773
-cap "sens_amp_6/OUT" "sens_amp_2/V_IN" 0.272354
-cap "sens_amp_3/V_IN" "sens_amp_7/REF" 4.91647
-cap "sens_amp_7/OUT" "sens_amp_2/V_IN" 0.0144184
-cap "sens_amp_0/GN" "sens_amp_4/OUT" 0.0586484
-cap "sens_amp_5/GN" "sens_amp_0/net2" 0.0242901
-cap "sens_amp_2/net1" "sens_amp_1/net2" 3.19269
-cap "sens_amp_0/V_IN" "sens_amp_7/REF" 138.326
-cap "sens_amp_2/OUT" "sens_amp_3/GN" 5.32309
-cap "sens_amp_1/net2" "sens_amp_5/net1" 0.119523
-cap "sens_amp_1/GN" "sens_amp_7/REF" 2.24078
-cap "sens_amp_2/net1" "sens_amp_0/GN" 4.44428
-cap "sens_amp_3/GN" "sens_amp_5/net2" 1.98124
-cap "sens_amp_4/net1" "sens_amp_0/net1" 0.42426
-cap "sens_amp_2/OUT" "sens_amp_1/OUT" 282.357
-cap "sens_amp_6/net1" "sens_amp_3/net2" 0.364963
-cap "sens_amp_1/net2" "sens_amp_5/OUT" 0.0505492
-cap "sens_amp_2/GN" "sens_amp_7/GND" -6.14748
-cap "sens_amp_3/V_IN" "sens_amp_7/V_IN" 0.00355617
-cap "sens_amp_5/net2" "sens_amp_1/OUT" 1.01919
-cap "sens_amp_3/GN" "sens_amp_4/net2" 2.47193
-cap "sens_amp_0/V_IN" "sens_amp_4/GN" 1.53033
-cap "sens_amp_3/OUT" "sens_amp_7/GND" 30.8501
-cap "sens_amp_3/GN" "sens_amp_6/GN" 1.97448
-cap "sens_amp_4/V_IN" "sens_amp_1/net1" 0.34921
-cap "sens_amp_4/net2" "sens_amp_1/OUT" 2.14694
-cap "sens_amp_1/GN" "sens_amp_4/GN" 1.97448
-cap "sens_amp_1/V_IN" "sens_amp_3/GN" 3.60093
-cap "sens_amp_6/GN" "sens_amp_1/OUT" 0.265309
-cap "sens_amp_2/net2" "sens_amp_6/OUT" 0.0505492
-cap "sens_amp_0/net2" "sens_amp_7/REF" 2.36378
-cap "sens_amp_2/net1" "sens_amp_6/net1" 0.42426
-cap "sens_amp_1/net2" "sens_amp_7/GND" 6.53982
-cap "sens_amp_1/V_IN" "sens_amp_1/OUT" -7.59529
-cap "sens_amp_2/OUT" "sens_amp_0/net1" 4.17653
-cap "sens_amp_3/GN" "sens_amp_2/V_IN" 3.95137
-cap "sens_amp_0/GN" "sens_amp_7/GND" 9.59743
-cap "sens_amp_7/net1" "sens_amp_3/net2" 0.119523
-cap "sens_amp_4/V_IN" "sens_amp_3/net2" 0.657343
-cap "sens_amp_1/net1" "sens_amp_3/net2" 1.79298
-cap "sens_amp_0/net1" "sens_amp_5/net2" 0.0433164
-cap "sens_amp_2/V_IN" "sens_amp_1/OUT" 2.96463
-cap "sens_amp_7/net2" "sens_amp_2/V_IN" 0.0589222
-cap "sens_amp_6/net2" "sens_amp_3/GN" 1.27185
-cap "sens_amp_0/net2" "sens_amp_4/GN" 0.294663
-cap "sens_amp_0/net1" "sens_amp_4/net2" 0.470415
-cap "sens_amp_1/net1" "sens_amp_4/OUT" 0.124499
-cap "sens_amp_2/OUT" "sens_amp_7/GN" 0.265309
-cap "sens_amp_0/V_IN" "sens_amp_4/net1" 0.776685
-cap "sens_amp_7/REF" "sens_amp_7/V_IN" 0.0479845
-cap "sens_amp_6/OUT" "sens_amp_2/GN" 0.0586484
-cap "sens_amp_5/V_IN" "sens_amp_1/net1" 0.173139
-cap "sens_amp_1/V_IN" "sens_amp_0/net1" 1.67233
-cap "sens_amp_7/GND" "sens_amp_6/net1" 0.718183
-cap "sens_amp_1/GN" "sens_amp_4/net1" 1.21488
-cap "sens_amp_4/V_IN" "sens_amp_2/net1" 0.486732
-cap "sens_amp_2/net1" "sens_amp_1/net1" 4.63518
-cap "sens_amp_1/net1" "sens_amp_5/net1" 0.42426
-cap "sens_amp_2/net2" "sens_amp_3/GN" 2.10269
-cap "sens_amp_0/net1" "sens_amp_2/V_IN" 1.40735
-cap "sens_amp_6/V_IN" "sens_amp_3/V_IN" 0.0092174
-cap "sens_amp_7/SA_IREF" "sens_amp_0/VDD" 3.46945e-18
-cap "sens_amp_1/net1" "sens_amp_5/OUT" 0.0682677
-cap "sens_amp_3/net2" "sens_amp_4/OUT" 0.19406
-cap "sens_amp_2/net2" "sens_amp_1/OUT" 3.7884
-cap "sens_amp_5/V_IN" "sens_amp_3/net2" 0.532494
-cap "sens_amp_3/net1" "sens_amp_2/OUT" 4.61729
-cap "sens_amp_2/net1" "sens_amp_3/net2" 2.0465
-cap "sens_amp_0/OUT" "sens_amp_3/GN" 3.56539
-cap "sens_amp_2/OUT" "sens_amp_3/V_IN" 2.65988
-cap "sens_amp_5/net1" "sens_amp_3/net2" 0.570114
-cap "sens_amp_0/V_IN" "sens_amp_2/OUT" 3.08091
-cap "sens_amp_4/net1" "sens_amp_0/net2" 0.119523
-cap "sens_amp_3/V_IN" "sens_amp_5/net2" 0.0477285
-cap "sens_amp_7/net1" "sens_amp_7/GND" 0.175876
-cap "sens_amp_1/GN" "sens_amp_2/OUT" 5.12214
-cap "sens_amp_0/OUT" "sens_amp_1/OUT" 282.357
-cap "sens_amp_2/V_IN" "sens_amp_7/GN" 0.458631
-cap "sens_amp_0/V_IN" "sens_amp_5/net2" 0.0589222
-cap "sens_amp_5/OUT" "sens_amp_3/net2" 0.162313
-cap "sens_amp_4/V_IN" "sens_amp_7/GND" 0.842664
-cap "sens_amp_5/GN" "sens_amp_2/OUT" 3.43556
-cap "sens_amp_1/net1" "sens_amp_7/GND" 14.0018
-cap "sens_amp_3/GN" "sens_amp_2/GN" 5.02725
-cap "sens_amp_7/GND" "sens_amp_0/VDD" 6.93889e-18
-cap "sens_amp_2/net1" "sens_amp_4/OUT" 0.166987
-cap "sens_amp_1/GN" "sens_amp_5/net2" 0.422061
-cap "sens_amp_3/V_IN" "sens_amp_4/net2" 0.0557662
-cap "sens_amp_2/net1" "sens_amp_5/V_IN" 0.34921
-cap "sens_amp_0/V_IN" "sens_amp_4/net2" 0.771952
-cap "sens_amp_2/net2" "sens_amp_0/net1" 1.79298
-cap "sens_amp_3/net1" "sens_amp_1/V_IN" 3.08384
-cap "sens_amp_7/SA_IREF" "sens_amp_4/OUT" 1.46146
-cap "sens_amp_2/GN" "sens_amp_1/OUT" 5.32309
-cap "sens_amp_3/OUT" "sens_amp_3/GN" -13.9502
-cap "sens_amp_1/GN" "sens_amp_4/net2" 1.27185
-cap "sens_amp_1/V_IN" "sens_amp_3/V_IN" 1.00173
-cap "sens_amp_2/net1" "sens_amp_5/net1" 0.916606
-cap "sens_amp_0/V_IN" "sens_amp_1/V_IN" 1.95014
-cap "sens_amp_3/net1" "sens_amp_2/V_IN" 3.68123
-cap "sens_amp_7/GND" "sens_amp_3/net2" 2.37038
-cap "sens_amp_2/net1" "sens_amp_5/OUT" 0.124499
-cap "sens_amp_7/net2" "sens_amp_3/OUT" 1.01919
-cap "sens_amp_6/V_IN" "sens_amp_7/REF" 0.353823
-cap "sens_amp_0/net2" "sens_amp_2/OUT" 3.15609
-cap "sens_amp_1/net2" "sens_amp_3/GN" 1.85101
-cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 1.17944
-cap "sens_amp_5/GN" "sens_amp_1/V_IN" 1.53033
-cap "sens_amp_0/OUT" "sens_amp_0/net1" -12.5567
-cap "sens_amp_0/V_IN" "sens_amp_2/V_IN" 1.64184
-cap "sens_amp_7/SA_IREF" "sens_amp_5/OUT" 0.883626
-cap "sens_amp_0/GN" "sens_amp_3/GN" 2.98241
-cap "sens_amp_2/net2" "sens_amp_7/GN" 0.0242901
-cap "sens_amp_1/net2" "sens_amp_1/OUT" -1.96857
-cap "sens_amp_2/OUT" "sens_amp_7/REF" 8.56704
-cap "sens_amp_1/GN" "sens_amp_2/V_IN" 2.11007
-cap "sens_amp_7/GND" "sens_amp_4/OUT" 2.76784
-cap "sens_amp_5/GN" "sens_amp_2/V_IN" 2.43309
-cap "sens_amp_5/V_IN" "sens_amp_7/GND" 0.511278
-cap "sens_amp_0/net2" "sens_amp_4/net2" 0.205581
-cap "sens_amp_0/net1" "sens_amp_2/GN" 3.09552
-cap "sens_amp_6/net2" "sens_amp_3/V_IN" 0.034422
-cap "sens_amp_0/GN" "sens_amp_1/OUT" 5.12214
-cap "sens_amp_5/net2" "sens_amp_7/REF" 0.299576
-cap "sens_amp_2/net1" "sens_amp_7/GND" 12.5671
-cap "sens_amp_7/GND" "sens_amp_5/net1" 1.56706
-cap "sens_amp_0/net2" "sens_amp_1/V_IN" 1.54964
-cap "sens_amp_0/net1" "sens_amp_3/OUT" 3.11647
-cap "sens_amp_7/REF" "sens_amp_4/net2" 0.498551
-cap "sens_amp_7/SA_IREF" "sens_amp_7/GND" 73.0618
-cap "sens_amp_6/OUT" "sens_amp_1/net1" 0.00460497
-cap "sens_amp_2/net2" "sens_amp_3/net1" 2.70515
-cap "sens_amp_2/OUT" "sens_amp_4/GN" 4.53334
-cap "sens_amp_7/GND" "sens_amp_5/OUT" 1.69595
-cap "sens_amp_3/GN" "sens_amp_6/net1" 1.21488
-cap "sens_amp_2/net2" "sens_amp_3/V_IN" 0.723142
+cap "VDD" "w_n100_2890#" 62.7919
+cap "OUTx2x" "OUTx1x" 12.6429
+cap "INx4x" "INx3x" 6.51667
+cap "OUTx2x" "OUTx3x" 12.6429
+cap "w_n100_2890#" "INx5x" 2.19653
+cap "OUTx6x" "OUTx7x" 12.6429
+cap "VREF" "OUTx7x" 1.2399
+cap "VREF" "GND" 0.683333
+cap "VREF" "SA_IREF" 79.804
+cap "INx7x" "w_n100_2890#" 2.19653
+cap "OUTx5x" "OUTx6x" 12.6429
+cap "INx6x" "w_n100_2890#" 2.19653
+cap "INx4x" "w_n100_2890#" 2.19653
+cap "INx1x" "INx0x" 6.51667
cap "sens_amp_1/V_IN" "sens_amp_7/REF" 140.2
-cap "sens_amp_0/net2" "sens_amp_2/V_IN" 1.24464
-cap "sens_amp_2/net2" "sens_amp_0/V_IN" 2.47648
-cap "sens_amp_1/net2" "sens_amp_0/net1" 2.0465
-cap "sens_amp_2/net2" "sens_amp_1/GN" 3.22983
-cap "sens_amp_2/net2" "sens_amp_5/GN" 0.532835
-cap "sens_amp_3/OUT" "sens_amp_7/GN" 1.95854
-cap "sens_amp_3/net1" "sens_amp_0/OUT" 2.42674
-cap "sens_amp_7/OUT" "sens_amp_3/net2" 0.0505492
-cap "sens_amp_7/REF" "sens_amp_2/V_IN" 141.419
-cap "sens_amp_6/OUT" "sens_amp_3/net2" 0.112649
-cap "sens_amp_0/OUT" "sens_amp_3/V_IN" 1.42193
-cap "sens_amp_0/V_IN" "sens_amp_0/OUT" -7.59529
-cap "sens_amp_1/V_IN" "sens_amp_4/GN" 2.43309
-cap "sens_amp_1/GN" "sens_amp_0/OUT" 5.32309
-cap "sens_amp_3/net1" "sens_amp_2/GN" 5.13174
-cap "sens_amp_6/net2" "sens_amp_7/REF" 0.139411
-cap "sens_amp_7/V_IN" "sens_amp_2/V_IN" 8.10171e-07
-cap "sens_amp_5/GN" "sens_amp_0/OUT" 0.265309
-cap "sens_amp_3/GN" "sens_amp_7/net1" 0.169074
-cap "sens_amp_3/V_IN" "sens_amp_2/GN" 1.00456
-cap "sens_amp_4/V_IN" "sens_amp_3/GN" 1.00456
-cap "sens_amp_0/V_IN" "sens_amp_2/GN" 3.60093
-cap "sens_amp_4/GN" "sens_amp_2/V_IN" 3.06727
-cap "sens_amp_3/GN" "sens_amp_1/net1" 3.09552
-cap "sens_amp_2/net2" "sens_amp_0/net2" 1.26177
-cap "sens_amp_4/net1" "sens_amp_2/OUT" 3.48963
-cap "sens_amp_3/net1" "sens_amp_3/OUT" -12.5567
-cap "sens_amp_2/net1" "sens_amp_7/OUT" 0.00460497
-cap "sens_amp_2/net1" "sens_amp_6/OUT" 0.0682677
-cap "sens_amp_1/GN" "sens_amp_2/GN" 5.02725
-cap "sens_amp_4/V_IN" "sens_amp_1/OUT" 1.40414
-cap "sens_amp_3/V_IN" "sens_amp_3/OUT" -7.59529
-cap "sens_amp_1/net1" "sens_amp_1/OUT" -12.5567
-cap "sens_amp_0/V_IN" "sens_amp_3/OUT" 2.28258
-cap "sens_amp_5/GN" "sens_amp_2/GN" 1.97448
-cap "sens_amp_7/SA_IREF" "sens_amp_6/OUT" 0.416286
-cap "sens_amp_7/SA_IREF" "sens_amp_7/OUT" 0.111026
-cap "sens_amp_2/net2" "sens_amp_7/REF" 3.212
-cap "sens_amp_3/net1" "sens_amp_1/net2" 2.17496
-cap "sens_amp_1/GN" "sens_amp_3/OUT" 4.08235
-cap "sens_amp_1/net2" "sens_amp_3/V_IN" 0.585954
-cap "sens_amp_0/net2" "sens_amp_0/OUT" -0.218363
-cap "sens_amp_5/GN" "sens_amp_3/OUT" 4.53334
-cap "sens_amp_6/V_IN" "sens_amp_2/OUT" 0.520122
-cap "sens_amp_0/V_IN" "sens_amp_1/net2" 2.83815
-cap "sens_amp_3/net1" "sens_amp_0/GN" 2.23452
-cap "sens_amp_0/GN" "sens_amp_3/V_IN" 0.46176
-cap "sens_amp_4/net1" "sens_amp_1/V_IN" 1.70182
-cap "sens_amp_3/net2" "sens_amp_1/OUT" 3.20242
-cap "sens_amp_0/OUT" "sens_amp_7/REF" 8.5825
-cap "sens_amp_0/net2" "sens_amp_2/GN" 1.85101
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-cap "sens_amp_1/GN" "sens_amp_0/GN" 5.02725
-cap "sens_amp_7/OUT" "sens_amp_7/GND" 0.23097
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-cap "sens_amp_7/GND" "sens_amp_1/OUT" 19.9434
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cap "sens_amp_6/net2" "sens_amp_2/GN" 0.422061
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cap "sens_amp_6/net2" "sens_amp_3/OUT" 2.14694
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+cap "sens_amp_2/GN" "sens_amp_2/OUT" -13.9502
+cap "sens_amp_2/net1" "sens_amp_4/V_IN" 0.486732
+cap "sens_amp_6/V_IN" "sens_amp_7/REF" 0.353823
+cap "sens_amp_0/net2" "sens_amp_1/V_IN" 1.54964
+cap "sens_amp_4/net1" "sens_amp_0/net2" 0.119523
+cap "sens_amp_2/V_IN" "sens_amp_6/net1" 0.776685
+cap "sens_amp_0/net1" "sens_amp_7/REF" 1.24035
+cap "sens_amp_4/V_IN" "sens_amp_0/net1" 0.173139
+cap "sens_amp_1/net2" "sens_amp_7/REF" 2.6472
+cap "sens_amp_1/net2" "sens_amp_4/V_IN" 0.348864
+cap "sens_amp_3/net1" "sens_amp_2/GN" 5.13174
+cap "sens_amp_7/GND" "sens_amp_3/net2" 2.37038
+cap "sens_amp_4/net1" "sens_amp_2/GN" 2.12658
+cap "sens_amp_3/V_IN" "sens_amp_7/REF" 4.91647
+cap "sens_amp_2/GN" "sens_amp_1/V_IN" 3.95137
cap "sens_amp_6/net2" "sens_amp_3/net2" 0.442664
-cap "sens_amp_3/net2" "sens_amp_7/net1" 0.443046
-cap "sens_amp_4/net2" "sens_amp_7/OUT" 2.1987
-cap "sens_amp_2/GN" "sens_amp_5/OUT" 2.40696
-cap "sens_amp_3/OUT" "sens_amp_7/GN" 0.0747927
-cap "sens_amp_7/REF" "sens_amp_7/V_IN" 5.37209
-cap "sens_amp_7/REF" "sens_amp_5/V_IN" 140.39
-cap "sens_amp_4/net1" "sens_amp_5/V_IN" 1.67233
-cap "sens_amp_4/net1" "sens_amp_7/V_IN" 0.98702
-cap "sens_amp_6/OUT" "sens_amp_5/net1" 4.77555
-cap "sens_amp_5/GN" "sens_amp_0/net2" 0.0643981
-cap "sens_amp_6/OUT" "sens_amp_3/net2" 2.08605
-cap "sens_amp_6/GN" "sens_amp_5/GN" 5.02725
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-cap "sens_amp_7/REF" "sens_amp_3/V_IN" 138.646
-cap "sens_amp_4/net1" "sens_amp_3/V_IN" 3.97969
-cap "sens_amp_4/OUT" "sens_amp_2/GN" 3.79151
-cap "sens_amp_4/GN" "sens_amp_5/V_IN" 2.11007
-cap "sens_amp_4/GN" "sens_amp_7/V_IN" 0.924572
-cap "sens_amp_4/net2" "sens_amp_5/GN" 2.10269
-cap "sens_amp_4/net2" "sens_amp_0/net1" 0.271593
-cap "sens_amp_7/GND" "sens_amp_5/V_IN" 122.281
-cap "sens_amp_7/GND" "sens_amp_7/V_IN" 0.963293
-cap "sens_amp_1/V_IN" "sens_amp_3/V_IN" 0.640114
-cap "sens_amp_6/net2" "sens_amp_5/OUT" 3.7884
-cap "sens_amp_5/OUT" "sens_amp_7/net1" 3.78788
-cap "sens_amp_6/OUT" "sens_amp_7/SA_IREF" 8.05999
-cap "sens_amp_5/net2" "sens_amp_3/OUT" 0.164721
-cap "sens_amp_4/V_IN" "sens_amp_2/GN" 0.829972
-cap "sens_amp_2/net2" "sens_amp_4/GN" 1.13882
-cap "sens_amp_4/V_IN" "sens_amp_2/OUT" 0.271018
-cap "sens_amp_7/GND" "sens_amp_2/net2" 4.39589
-cap "sens_amp_4/GN" "sens_amp_3/V_IN" 3.95137
-cap "sens_amp_2/GN" "sens_amp_6/net1" 0.196254
-cap "sens_amp_5/V_IN" "sens_amp_7/OUT" 3.08091
-cap "sens_amp_2/OUT" "sens_amp_6/net1" 0.0694815
-cap "sens_amp_7/GND" "sens_amp_3/V_IN" 120.936
-cap "sens_amp_5/net2" "sens_amp_2/V_IN" 0.438605
-cap "sens_amp_5/net1" "sens_amp_6/GN" 477.18
-cap "sens_amp_6/GN" "sens_amp_3/net2" 0.862175
-cap "sens_amp_6/OUT" "sens_amp_5/OUT" 282.357
-cap "sens_amp_4/net1" "sens_amp_0/GN" 0.196254
-cap "sens_amp_7/OUT" "sens_amp_3/V_IN" 1.22657
-cap "sens_amp_6/V_IN" "sens_amp_3/net1" 0.98702
-cap "sens_amp_6/net2" "sens_amp_4/OUT" 3.20242
-cap "sens_amp_4/OUT" "sens_amp_7/net1" 2.46569
-cap "sens_amp_5/net2" "sens_amp_7/GN" 1.85101
-cap "sens_amp_5/net1" "sens_amp_4/net2" 3.19269
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-cap "sens_amp_4/net2" "sens_amp_3/net2" 8.51946
-cap "sens_amp_6/net2" "sens_amp_4/V_IN" 2.47648
-cap "sens_amp_0/VDD" "sens_amp_7/REF" 1.21781
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-cap "sens_amp_4/GN" "sens_amp_0/GN" 0.478221
-cap "sens_amp_5/GN" "sens_amp_7/V_IN" 1.60596
-cap "sens_amp_7/GND" "sens_amp_0/GN" 0.490422
-cap "sens_amp_7/net1" "sens_amp_6/net1" 4.63518
-cap "sens_amp_6/net2" "sens_amp_1/net1" 0.0181502
-cap "sens_amp_5/net2" "sens_amp_1/OUT" 0.0544281
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-cap "sens_amp_2/net2" "sens_amp_5/GN" 0.862175
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-cap "sens_amp_6/OUT" "sens_amp_4/V_IN" 3.08091
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-cap "sens_amp_6/net2" "sens_amp_7/net2" 17.0389
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-cap "sens_amp_6/OUT" "sens_amp_1/net1" 0.11725
-cap "sens_amp_6/OUT" "sens_amp_6/net1" -12.5567
-cap "sens_amp_0/VDD" "sens_amp_7/GND" 6.93889e-18
-cap "sens_amp_6/OUT" "sens_amp_2/net1" 1.64412
-cap "sens_amp_3/net1" "sens_amp_7/REF" 1.20465
-cap "sens_amp_4/net1" "sens_amp_3/net1" 4.63518
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-cap "sens_amp_5/net1" "sens_amp_5/V_IN" -2.0641
-cap "sens_amp_5/net1" "sens_amp_7/V_IN" 1.40735
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-cap "sens_amp_5/V_IN" "sens_amp_3/net2" 0.712142
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-cap "sens_amp_3/net1" "sens_amp_4/GN" 477.18
-cap "sens_amp_5/net1" "sens_amp_2/net2" 1.29055
-cap "sens_amp_4/net1" "sens_amp_3/GN" 3.04914
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-cap "sens_amp_3/net1" "sens_amp_7/GND" 14.681
-cap "sens_amp_5/net1" "sens_amp_3/V_IN" 3.33078
-cap "sens_amp_6/GN" "sens_amp_4/V_IN" 3.60093
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-cap "sens_amp_4/GN" "sens_amp_1/GN" 1.00792
-cap "sens_amp_4/OUT" "sens_amp_4/net2" -1.96857
-cap "sens_amp_7/GND" "sens_amp_1/GN" 2.04931
-cap "sens_amp_6/GN" "sens_amp_1/net1" 0.248457
-cap "sens_amp_3/net1" "sens_amp_7/OUT" 1.71238
-cap "sens_amp_2/net1" "sens_amp_6/GN" 0.762681
-cap "sens_amp_6/V_IN" "sens_amp_7/REF" 138.912
-cap "sens_amp_6/V_IN" "sens_amp_4/net1" 1.40735
-cap "sens_amp_6/GN" "sens_amp_7/net2" 3.22983
-cap "sens_amp_4/GN" "sens_amp_3/GN" 1.68735
-cap "sens_amp_4/net2" "sens_amp_4/V_IN" -0.518908
-cap "sens_amp_7/GND" "sens_amp_3/GN" 7.58519
-cap "sens_amp_6/V_IN" "sens_amp_1/V_IN" 3.6556e-07
-cap "sens_amp_4/net2" "sens_amp_1/net1" 0.495638
-cap "sens_amp_4/net2" "sens_amp_6/net1" 2.56571
-cap "sens_amp_5/V_IN" "sens_amp_5/OUT" -7.59529
-cap "sens_amp_7/V_IN" "sens_amp_5/OUT" 2.40417
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-cap "sens_amp_2/OUT" "sens_amp_7/GN" 0.0115053
-cap "sens_amp_2/net1" "sens_amp_4/net2" 0.66497
-cap "sens_amp_3/GN" "sens_amp_7/OUT" 0.756718
-cap "sens_amp_6/V_IN" "sens_amp_4/GN" 1.60596
-cap "sens_amp_6/V_IN" "sens_amp_7/GND" 121.95
-cap "sens_amp_4/net2" "sens_amp_7/net2" 0.885329
-cap "sens_amp_2/net2" "sens_amp_5/OUT" 2.08605
-cap "sens_amp_3/OUT" "sens_amp_6/net2" 0.115976
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-cap "sens_amp_5/OUT" "sens_amp_3/V_IN" 3.06475
-cap "sens_amp_3/net1" "sens_amp_5/GN" 3.09552
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-cap "sens_amp_6/V_IN" "sens_amp_7/OUT" 3.53914
-cap "sens_amp_5/GN" "sens_amp_1/GN" 0.478221
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-cap "sens_amp_4/net1" "sens_amp_7/REF" 2.65978
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-cap "sens_amp_5/GN" "sens_amp_3/GN" 1.42636
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-cap "sens_amp_7/REF" "sens_amp_4/GN" 2.80267
-cap "sens_amp_6/OUT" "sens_amp_7/GN" 5.32309
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-cap "sens_amp_0/VDD" "sens_amp_7/SA_IREF" 3.46945e-18
-cap "sens_amp_3/net1" "sens_amp_5/net1" 3.90585
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-cap "sens_amp_4/net1" "sens_amp_7/GND" 15.4182
-cap "sens_amp_6/V_IN" "sens_amp_5/GN" 2.11007
-cap "sens_amp_2/net2" "sens_amp_6/net1" 0.443046
-cap "sens_amp_5/V_IN" "sens_amp_7/net2" 2.47648
-cap "sens_amp_3/V_IN" "sens_amp_6/net1" 2.31419
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-cap "sens_amp_0/OUT" "sens_amp_3/V_IN" 0.156397
-cap "sens_amp_5/net1" "sens_amp_1/GN" 0.196254
-cap "sens_amp_2/net1" "sens_amp_3/V_IN" 1.10181
-cap "sens_amp_1/V_IN" "sens_amp_4/GN" 0.419899
-cap "sens_amp_4/net1" "sens_amp_7/OUT" 3.11647
-cap "sens_amp_7/REF" "sens_amp_7/OUT" 3.18091
-cap "sens_amp_1/V_IN" "sens_amp_7/GND" 0.602371
-cap "sens_amp_3/OUT" "sens_amp_6/GN" 0.129824
-cap "sens_amp_4/OUT" "sens_amp_0/GN" 0.756718
-cap "sens_amp_7/net2" "sens_amp_3/V_IN" 0.985793
-cap "sens_amp_5/net2" "sens_amp_6/net2" 17.0389
-cap "sens_amp_5/net2" "sens_amp_7/net1" 2.56571
-cap "sens_amp_6/GN" "sens_amp_2/V_IN" 0.259789
-cap "sens_amp_7/GND" "sens_amp_4/GN" -4.33548
-cap "sens_amp_5/net1" "sens_amp_3/GN" 2.31769
-cap "sens_amp_4/V_IN" "sens_amp_0/GN" 0.0446191
-cap "sens_amp_4/GN" "sens_amp_7/OUT" 2.59192
-cap "sens_amp_3/OUT" "sens_amp_4/net2" 0.195283
-cap "sens_amp_5/net2" "sens_amp_6/OUT" 3.76509
-cap "sens_amp_7/GND" "sens_amp_7/OUT" 13.8566
-cap "sens_amp_6/V_IN" "sens_amp_5/net1" 1.67233
-cap "sens_amp_6/GN" "sens_amp_7/GN" 5.02725
-cap "sens_amp_6/V_IN" "sens_amp_3/net2" 0.453377
-cap "sens_amp_4/net2" "sens_amp_2/V_IN" 0.597636
-cap "sens_amp_3/net1" "sens_amp_5/OUT" 4.17653
-cap "sens_amp_7/REF" "sens_amp_5/GN" 2.41006
-cap "sens_amp_4/net1" "sens_amp_0/net1" 0.857537
-cap "sens_amp_4/net1" "sens_amp_5/GN" 477.18
-cap "sens_amp_1/GN" "sens_amp_5/OUT" 0.756718
-cap "sens_amp_6/GN" "sens_amp_1/OUT" 0.0115053
-cap "sens_amp_1/V_IN" "sens_amp_5/GN" 0.259789
-cap "sens_amp_4/net2" "sens_amp_7/GN" 1.39501
-cap "sens_amp_4/OUT" "sens_amp_3/net1" 4.77555
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-cap "sens_amp_4/GN" "sens_amp_5/GN" 5.02725
-cap "sens_amp_3/GN" "sens_amp_5/OUT" 3.79151
-cap "sens_amp_6/GN" "sens_amp_1/net2" 0.0643981
-cap "sens_amp_7/GND" "sens_amp_0/net1" 1.14886
-cap "sens_amp_7/GND" "sens_amp_5/GN" -4.83529
-cap "sens_amp_5/net2" "sens_amp_6/GN" 2.10269
-cap "sens_amp_4/OUT" "sens_amp_1/GN" 2.40696
-cap "sens_amp_4/net2" "sens_amp_1/OUT" 0.115976
-cap "sens_amp_3/OUT" "sens_amp_5/V_IN" 0.271018
-cap "sens_amp_3/OUT" "sens_amp_7/V_IN" 0.0581218
-cap "sens_amp_3/net1" "sens_amp_4/V_IN" 1.67233
-cap "sens_amp_5/GN" "sens_amp_7/OUT" 4.08235
-cap "sens_amp_6/V_IN" "sens_amp_5/OUT" 2.96463
-cap "sens_amp_4/net1" "sens_amp_5/net1" 4.63518
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-cap "sens_amp_7/REF" "sens_amp_0/V_IN" 0.35067
-cap "sens_amp_7/REF" "sens_amp_3/net2" 0.492165
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-cap "sens_amp_4/net1" "sens_amp_3/net2" 2.48035
-cap "sens_amp_3/net1" "sens_amp_6/net1" 2.74535
-cap "sens_amp_5/V_IN" "sens_amp_2/V_IN" 0.526615
-cap "sens_amp_7/V_IN" "sens_amp_2/V_IN" 3.6556e-07
-cap "sens_amp_4/net2" "sens_amp_1/net2" 0.442664
-cap "sens_amp_4/V_IN" "sens_amp_1/GN" 0.462812
-cap "sens_amp_4/OUT" "sens_amp_3/GN" 4.75752
-cap "sens_amp_5/net2" "sens_amp_4/net2" 17.0389
-cap "sens_amp_1/V_IN" "sens_amp_5/net1" 0.265454
-cap "sens_amp_3/net1" "sens_amp_7/net2" 0.742008
-cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 0.770699
-cap "sens_amp_6/V_IN" "sens_amp_4/OUT" 2.40417
-cap "sens_amp_5/net1" "sens_amp_4/GN" 5.85267
-cap "sens_amp_4/V_IN" "sens_amp_3/GN" 1.10551
-cap "sens_amp_5/V_IN" "sens_amp_7/GN" 3.60093
-cap "sens_amp_4/GN" "sens_amp_0/V_IN" 0.259789
-cap "sens_amp_4/GN" "sens_amp_3/net2" 1.28976
-cap "sens_amp_5/net1" "sens_amp_7/GND" 14.3869
-cap "sens_amp_7/GND" "sens_amp_0/V_IN" 0.205912
-cap "sens_amp_7/GND" "sens_amp_3/net2" 7.0001
-cap "sens_amp_7/REF" "sens_amp_7/SA_IREF" 35.968
-cap "sens_amp_3/GN" "sens_amp_6/net1" 1.3304
-cap "sens_amp_6/net2" "sens_amp_2/GN" 0.122363
-cap "sens_amp_6/net2" "sens_amp_2/OUT" 0.0544281
-cap "sens_amp_5/GN" "sens_amp_0/net1" 0.248457
-cap "sens_amp_2/net2" "sens_amp_7/GN" 0.0643981
-cap "sens_amp_5/net1" "sens_amp_7/OUT" 4.17653
-cap "sens_amp_3/V_IN" "sens_amp_7/GN" 1.79012
-cap "sens_amp_6/V_IN" "sens_amp_4/V_IN" 1.64184
-cap "sens_amp_3/net2" "sens_amp_7/OUT" 0.948045
-cap "sens_amp_5/V_IN" "sens_amp_1/OUT" 0.0581218
-cap "sens_amp_3/GN" "sens_amp_7/net2" 0.122363
-cap "sens_amp_6/V_IN" "sens_amp_6/net1" -2.0641
-cap "sens_amp_4/net1" "sens_amp_5/OUT" 4.77555
-cap "sens_amp_7/REF" "sens_amp_5/OUT" 7.77446
-cap "sens_amp_6/OUT" "sens_amp_2/GN" 0.756718
-cap "sens_amp_6/V_IN" "sens_amp_2/net1" 0.284592
-cap "sens_amp_5/V_IN" "sens_amp_1/net2" 0.144565
-cap "sens_amp_7/GND" "sens_amp_7/SA_IREF" 76.0595
-cap "sens_amp_3/V_IN" "sens_amp_1/OUT" 0.244044
-cap "sens_amp_6/V_IN" "sens_amp_7/net2" 2.83815
-cap "sens_amp_1/V_IN" "sens_amp_5/OUT" 0.959933
-cap "sens_amp_5/net2" "sens_amp_7/V_IN" 1.24464
-cap "sens_amp_5/net2" "sens_amp_5/V_IN" -0.518908
-cap "sens_amp_1/net2" "sens_amp_3/V_IN" 0.658683
-cap "sens_amp_6/net2" "sens_amp_7/net1" 3.19269
-cap "sens_amp_7/SA_IREF" "sens_amp_7/OUT" 6.21729
-cap "sens_amp_4/GN" "sens_amp_5/OUT" 5.12214
-cap "sens_amp_4/net1" "sens_amp_4/OUT" -12.5567
-cap "sens_amp_4/OUT" "sens_amp_7/REF" 10.1332
-cap "sens_amp_5/net2" "sens_amp_2/net2" 0.442664
-cap "sens_amp_7/GND" "sens_amp_5/OUT" 26.3889
-cap "sens_amp_5/net2" "sens_amp_3/V_IN" 2.42875
-cap "sens_amp_5/GN" "sens_amp_0/V_IN" 0.0710006
-cap "sens_amp_5/GN" "sens_amp_3/net2" 1.13882
-cap "sens_amp_1/V_IN" "sens_amp_4/OUT" 1.78056
-cap "sens_amp_6/OUT" "sens_amp_7/net1" 4.69194
-cap "sens_amp_6/net2" "sens_amp_6/OUT" -1.96857
-cap "sens_amp_4/net1" "sens_amp_4/V_IN" -2.0641
-cap "sens_amp_7/REF" "sens_amp_4/V_IN" 141.247
-cap "sens_amp_7/REF" "sens_amp_6/net1" 2.02227
-cap "sens_amp_6/GN" "sens_amp_2/GN" 0.478221
-cap "sens_amp_4/net1" "sens_amp_6/net1" 3.90585
-cap "sens_amp_6/GN" "sens_amp_2/OUT" 0.0747927
-cap "sens_amp_4/net1" "sens_amp_1/net1" 1.82874
-cap "sens_amp_7/REF" "sens_amp_0/OUT" 0.0483046
-cap "sens_amp_4/OUT" "sens_amp_4/GN" -13.9502
-cap "sens_amp_4/net1" "sens_amp_0/OUT" 0.0694815
-cap "sens_amp_4/net1" "sens_amp_2/net1" 2.59808
-cap "sens_amp_4/OUT" "sens_amp_7/GND" 31.8198
-cap "sens_amp_1/V_IN" "sens_amp_4/V_IN" 0.526615
-cap "sens_amp_7/REF" "sens_amp_7/net2" 1.73377
-cap "sens_amp_4/net1" "sens_amp_7/net2" 1.34154
-cap "sens_amp_7/GND" "sens_amp_4/V_IN" 122.387
-cap "sens_amp_4/net2" "sens_amp_2/GN" 0.604713
-cap "sens_amp_4/net2" "sens_amp_2/OUT" 0.164721
-cap "sens_amp_4/GN" "sens_amp_6/net1" 4.44428
-cap "sens_amp_5/net1" "sens_amp_3/net2" 1.9956
-cap "sens_amp_4/GN" "sens_amp_1/net1" 1.19272
-cap "sens_amp_7/GND" "sens_amp_6/net1" 12.4321
-cap "sens_amp_4/GN" "sens_amp_0/OUT" 0.0747927
-cap "sens_amp_5/GN" "sens_amp_5/OUT" -13.9502
-cap "sens_amp_5/OUT" "sens_amp_0/net1" 0.11725
-cap "sens_amp_7/GND" "sens_amp_1/net1" 3.09883
-cap "sens_amp_2/net1" "sens_amp_4/GN" 1.49109
-cap "sens_amp_7/GND" "sens_amp_0/OUT" 0.52098
-cap "sens_amp_2/net1" "sens_amp_7/GND" 5.71165
-cap "sens_amp_4/V_IN" "sens_amp_7/OUT" 2.28258
-cap "sens_amp_3/net1" "sens_amp_7/GN" 1.56969
-cap "sens_amp_6/GN" "sens_amp_7/net1" 5.85267
-cap "sens_amp_4/GN" "sens_amp_7/net2" 1.65663
-cap "sens_amp_7/OUT" "sens_amp_6/net1" 4.77555
-cap "sens_amp_7/GND" "sens_amp_7/net2" 2.21792
-cap "sens_amp_2/net1" "sens_amp_7/OUT" 0.11725
-cap "sens_amp_6/V_IN" "sens_amp_3/OUT" 0.174184
-cap "sens_amp_7/net2" "sens_amp_7/OUT" -1.75021
-cap "sens_amp_4/OUT" "sens_amp_0/net1" 1.64412
-cap "sens_amp_6/OUT" "sens_amp_6/GN" -13.9502
-cap "sens_amp_4/OUT" "sens_amp_5/GN" 5.32309
-cap "sens_amp_6/V_IN" "sens_amp_2/V_IN" 0.23093
-cap "sens_amp_6/net2" "sens_amp_4/net2" 1.26177
-cap "sens_amp_4/net2" "sens_amp_7/net1" 1.65552
-cap "sens_amp_3/GN" "sens_amp_7/GN" 0.478221
-cap "sens_amp_4/V_IN" "sens_amp_5/GN" 3.95137
-cap "sens_amp_5/net1" "sens_amp_5/OUT" -12.5567
-cap "sens_amp_4/V_IN" "sens_amp_0/net1" 0.284592
-cap "sens_amp_5/net2" "sens_amp_3/net1" 1.79298
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-cap "sens_amp_3/net2" "sens_amp_5/OUT" 2.99378
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-cap "sens_amp_5/V_IN" "sens_amp_2/OUT" 0.174184
-cap "sens_amp_6/OUT" "sens_amp_4/net2" 3.15609
-cap "sens_amp_5/GN" "sens_amp_6/net1" 5.85267
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-cap "sens_amp_5/GN" "sens_amp_0/OUT" 0.0115053
-cap "sens_amp_2/net1" "sens_amp_5/GN" 1.19272
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-cap "sens_amp_5/GN" "sens_amp_7/net2" 2.58596
-cap "sens_amp_4/OUT" "sens_amp_5/net1" 4.69194
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-cap "sens_amp_3/OUT" "sens_amp_7/REF" 0.336831
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-cap "sens_amp_5/net2" "sens_amp_3/GN" 0.604713
-cap "sens_amp_5/OUT" "sens_amp_7/SA_IREF" 12.1352
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-cap "sens_amp_7/REF" "sens_amp_2/V_IN" 1.33179
-cap "sens_amp_6/net2" "sens_amp_5/V_IN" 2.83815
-cap "sens_amp_6/net2" "sens_amp_7/V_IN" 1.54964
-cap "sens_amp_5/V_IN" "sens_amp_7/net1" 3.33078
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-cap "sens_amp_5/net1" "sens_amp_6/net1" 4.63518
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cap "sens_amp_6/net2" "sens_amp_2/net2" 0.205581
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-cap "sens_amp_4/net1" "sens_amp_7/GN" 2.46888
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-cap "sens_amp_6/OUT" "sens_amp_7/V_IN" 2.96463
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-cap "sens_amp_6/OUT" "sens_amp_3/V_IN" 2.271
-cap "sens_amp_4/OUT" "sens_amp_5/OUT" 282.357
-cap "sens_amp_7/REF" "sens_amp_1/OUT" 0.124903
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-cap "sens_amp_4/GN" "sens_amp_7/GN" 2.98241
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-cap "sens_amp_7/OUT" "sens_amp_7/GN" -13.9502
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-cap "sens_amp_6/GN" "sens_amp_7/V_IN" 2.11007
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-cap "sens_amp_2/net1" "sens_amp_5/OUT" 2.99197
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-cap "sens_amp_2/net2" "sens_amp_6/GN" 0.490351
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-cap "sens_amp_7/GND" "sens_amp_1/net2" 2.21265
-cap "sens_amp_6/GN" "sens_amp_3/V_IN" 2.85299
-cap "sens_amp_4/OUT" "sens_amp_4/V_IN" -7.59529
-cap "sens_amp_5/net2" "sens_amp_4/GN" 3.22983
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-cap "sens_amp_4/OUT" "sens_amp_6/net1" 3.78788
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cap "sens_amp_5/net1" "sens_amp_1/net2" 0.443046
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cap "sens_amp_5/net2" "sens_amp_0/V_IN" 0.00837147
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cap "sens_amp_6/V_IN" "sens_amp_3/net1" 0.04315
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cap "sens_amp_7/GND" "sens_amp_6/GN" 0.920097
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+cap "sens_amp_1/net2" "sens_amp_3/net1" 1.24643
+cap "sens_amp_0/GN" "sens_amp_4/V_IN" 0.0704639
+cap "sens_amp_5/GN" "sens_amp_1/net1" 0.542318
+cap "sens_amp_7/REF" "sens_amp_1/net1" 1.38329
+cap "sens_amp_2/net2" "sens_amp_1/OUT" 1.58576
+cap "sens_amp_7/REF" "sens_amp_6/net2" 0.00814231
+cap "sens_amp_3/GN" "sens_amp_5/OUT" 3.08586
+cap "sens_amp_6/net1" "sens_amp_2/OUT" 1.77892
+cap "sens_amp_2/GN" "sens_amp_4/net2" 1.10438
+cap "sens_amp_0/OUT" "sens_amp_1/V_IN" 7.85568
+cap "sens_amp_0/net2" "sens_amp_2/net1" 1.45683
+cap "sens_amp_0/net2" "sens_amp_0/V_IN" -0.258739
+cap "sens_amp_6/OUT" "sens_amp_3/net1" 0.352632
+cap "sens_amp_2/GN" "sens_amp_5/V_IN" 0.496482
+cap "sens_amp_1/GN" "sens_amp_5/net2" 0.235264
cap "sens_amp_2/GN" "sens_amp_5/net1" 1.72636
cap "sens_amp_7/GND" "sens_amp_0/net1" 7.54777
-cap "sens_amp_0/net2" "sens_amp_2/net2" 0.456915
-cap "sens_amp_1/net2" "sens_amp_5/GN" 0.199538
-cap "sens_amp_2/OUT" "sens_amp_5/GN" 3.58135
-cap "sens_amp_7/GND" "sens_amp_7/net1" 0.166612
-cap "sens_amp_6/net1" "sens_amp_2/V_IN" 1.8501
-cap "sens_amp_2/V_IN" "sens_amp_6/net2" 0.432424
-cap "sens_amp_2/V_IN" "sens_amp_6/V_IN" 0.0982191
-cap "sens_amp_7/V_IN" "sens_amp_3/net2" 0.0413478
-cap "sens_amp_7/GND" "sens_amp_2/net1" 7.27621
-cap "sens_amp_0/GN" "sens_amp_1/net1" 5.62731
-cap "sens_amp_5/GN" "sens_amp_1/OUT" 2.08802
-cap "sens_amp_0/net1" "sens_amp_0/net2" -0.254835
-cap "sens_amp_4/GN" "sens_amp_2/V_IN" 3.96516
-cap "sens_amp_0/OUT" "sens_amp_2/net2" 1.34047
-cap "sens_amp_5/net1" "sens_amp_3/OUT" 3.32114
-cap "sens_amp_2/GN" "sens_amp_5/net2" 0.708951
-cap "sens_amp_0/OUT" "sens_amp_5/OUT" 0.00046923
-cap "sens_amp_2/GN" "sens_amp_2/V_IN" -4.01438
-cap "sens_amp_0/net2" "sens_amp_2/net1" 1.45683
-cap "sens_amp_7/GND" "sens_amp_7/VDD" 3.19744e-14
-cap "sens_amp_0/net1" "sens_amp_0/OUT" -14.653
-cap "sens_amp_2/OUT" "sens_amp_6/OUT" 1.70375
-cap "sens_amp_3/GN" "sens_amp_6/V_IN" 0.496482
-cap "sens_amp_3/GN" "sens_amp_6/net1" 1.72636
-cap "sens_amp_7/net2" "sens_amp_3/OUT" 0.436714
-cap "sens_amp_3/GN" "sens_amp_6/net2" 0.708951
-cap "sens_amp_5/net2" "sens_amp_3/OUT" 1.30162
-cap "sens_amp_3/GN" "sens_amp_4/GN" 2.58416
-cap "sens_amp_0/GN" "sens_amp_2/net2" 1.45914
-cap "sens_amp_6/GN" "sens_amp_3/V_IN" 0.289055
-cap "sens_amp_6/OUT" "sens_amp_1/OUT" 0.00046923
-cap "sens_amp_0/OUT" "sens_amp_2/net1" 10.1381
-cap "sens_amp_2/V_IN" "sens_amp_3/OUT" 26.048
-cap "sens_amp_1/net1" "sens_amp_3/V_IN" 0.56616
-cap "sens_amp_2/GN" "sens_amp_3/GN" 4.24571
-cap "sens_amp_0/net1" "sens_amp_0/GN" -0.0742372
-cap "sens_amp_0/V_IN" "sens_amp_4/V_IN" 0.0982191
-cap "sens_amp_7/VDD" "sens_amp_0/OUT" 132.165
-cap "sens_amp_7/GND" "sens_amp_4/net2" 1.06978
-cap "sens_amp_6/net1" "sens_amp_3/net2" 0.220528
-cap "sens_amp_3/net2" "sens_amp_6/V_IN" 0.110638
-cap "sens_amp_3/net2" "sens_amp_6/net2" 0.159188
-cap "sens_amp_0/GN" "sens_amp_2/net1" 4.35496
-cap "sens_amp_5/V_IN" "sens_amp_3/net1" 0.0678538
-cap "sens_amp_7/GND" "sens_amp_7/OUT" 0.198131
-cap "sens_amp_7/REF" "sens_amp_5/V_IN" 0.00424749
-cap "sens_amp_4/GN" "sens_amp_3/net2" 3.01959
-cap "sens_amp_0/V_IN" "sens_amp_4/OUT" 2.04267
-cap "sens_amp_3/GN" "sens_amp_3/OUT" -12.7773
-cap "sens_amp_1/net1" "sens_amp_1/GN" -0.592745
-cap "sens_amp_0/V_IN" "sens_amp_4/net1" 1.8501
-cap "sens_amp_3/net1" "sens_amp_4/V_IN" 0.0850674
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-cap "sens_amp_2/net2" "sens_amp_3/V_IN" 0.217097
-cap "sens_amp_7/GND" "sens_amp_1/net2" 1.80123
-cap "sens_amp_0/net2" "sens_amp_4/net2" 0.072346
-cap "sens_amp_3/V_IN" "sens_amp_5/OUT" 0.0414103
-cap "sens_amp_7/GND" "sens_amp_2/OUT" 46.1467
-cap "sens_amp_2/GN" "sens_amp_3/net2" 1.82263
-cap "sens_amp_7/VDD" "sens_amp_0/GN" 13.9034
-cap "sens_amp_6/net1" "sens_amp_1/V_IN" 0.107086
-cap "sens_amp_6/net2" "sens_amp_1/V_IN" 0.0298972
-cap "sens_amp_7/GND" "sens_amp_1/OUT" 43.8385
-cap "sens_amp_0/net1" "sens_amp_3/V_IN" 0.395735
-cap "sens_amp_4/OUT" "sens_amp_3/net1" 0.625328
-cap "sens_amp_4/net1" "sens_amp_3/net1" 6.69717
-cap "sens_amp_7/REF" "sens_amp_4/OUT" 0.00936409
-cap "sens_amp_7/REF" "sens_amp_4/net1" 0.024306
-cap "sens_amp_0/OUT" "sens_amp_4/net2" 0.436714
-cap "sens_amp_0/V_IN" "sens_amp_5/net1" 0.107086
-cap "sens_amp_1/net2" "sens_amp_0/net2" 0.545016
-cap "sens_amp_2/OUT" "sens_amp_0/net2" 1.32783
-cap "sens_amp_4/GN" "sens_amp_1/V_IN" 3.14984
-cap "sens_amp_7/net1" "sens_amp_3/V_IN" 0.0301834
-cap "sens_amp_2/net2" "sens_amp_1/GN" 1.82263
-cap "sens_amp_2/net1" "sens_amp_3/V_IN" 0.674088
-cap "sens_amp_3/net2" "sens_amp_3/OUT" -0.720943
-cap "sens_amp_1/GN" "sens_amp_5/OUT" 0.353243
-cap "sens_amp_0/net2" "sens_amp_1/OUT" 1.58409
-cap "sens_amp_2/GN" "sens_amp_1/V_IN" 5.00189
-cap "sens_amp_1/net2" "sens_amp_0/OUT" 1.58576
-cap "sens_amp_5/net1" "sens_amp_3/net1" 0.109148
-cap "sens_amp_7/REF" "sens_amp_5/net1" 0.013997
-cap "sens_amp_2/OUT" "sens_amp_0/OUT" 10.533
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-cap "sens_amp_0/net1" "sens_amp_1/GN" 966.389
-cap "sens_amp_0/GN" "sens_amp_4/net2" 0.235264
-cap "sens_amp_7/VDD" "sens_amp_3/V_IN" 0.321955
-cap "sens_amp_0/OUT" "sens_amp_1/OUT" 213.708
-cap "sens_amp_2/V_IN" "sens_amp_0/V_IN" 0.368428
-cap "sens_amp_7/GND" "sens_amp_7/GN" 0.345556
-cap "sens_amp_1/V_IN" "sens_amp_3/OUT" 7.72902
-cap "sens_amp_7/net2" "sens_amp_7/REF" 0.00226682
-cap "sens_amp_2/net1" "sens_amp_1/GN" 5.62731
-cap "sens_amp_1/net2" "sens_amp_0/GN" 1.82263
-cap "sens_amp_7/REF" "sens_amp_5/net2" 0.0169779
-cap "sens_amp_2/OUT" "sens_amp_0/GN" 6.78529
-cap "sens_amp_2/V_IN" "sens_amp_3/net1" 6.48493
-cap "sens_amp_2/V_IN" "sens_amp_7/REF" 3.67664
-cap "sens_amp_0/GN" "sens_amp_1/OUT" 8.68828
-cap "sens_amp_7/VDD" "sens_amp_1/GN" 9.92543
-cap "sens_amp_3/GN" "sens_amp_0/V_IN" 3.62635
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-cap "sens_amp_3/V_IN" "sens_amp_7/OUT" 0.0146522
-cap "sens_amp_3/GN" "sens_amp_3/net1" -0.592745
-cap "sens_amp_3/GN" "sens_amp_7/REF" 1.83217
-cap "sens_amp_1/net2" "sens_amp_3/V_IN" 0.17655
-cap "sens_amp_2/OUT" "sens_amp_3/V_IN" 2.53057
-cap "sens_amp_6/net1" "sens_amp_1/net1" 0.0306036
-cap "sens_amp_1/net1" "sens_amp_6/net2" 0.0239283
-cap "sens_amp_3/net2" "sens_amp_0/V_IN" 0.907777
-cap "sens_amp_1/OUT" "sens_amp_3/V_IN" 2.05557
-cap "sens_amp_1/GN" "sens_amp_4/net2" 0.708951
-cap "sens_amp_4/GN" "sens_amp_1/net1" 0.870768
-cap "sens_amp_2/GN" "sens_amp_6/GN" 0.569218
-cap "sens_amp_3/net2" "sens_amp_3/net1" -0.254835
-cap "sens_amp_2/GN" "sens_amp_1/net1" 966.389
-cap "sens_amp_3/net2" "sens_amp_7/REF" 0.775488
-cap "sens_amp_2/OUT" "sens_amp_1/GN" 8.68828
-cap "sens_amp_7/VDD" "sens_amp_7/V_IN" 0.00987411
-cap "sens_amp_7/GND" "sens_amp_5/GN" 1.68743
-cap "sens_amp_1/V_IN" "sens_amp_0/V_IN" 118.504
-cap "sens_amp_6/net2" "sens_amp_2/net2" 0.072346
-cap "sens_amp_6/net1" "sens_amp_2/net2" 0.0723262
-cap "sens_amp_2/net2" "sens_amp_6/V_IN" 0.0413478
-cap "sens_amp_1/OUT" "sens_amp_1/GN" -12.7773
-cap "sens_amp_6/GN" "sens_amp_3/OUT" 2.80917
-cap "sens_amp_4/GN" "sens_amp_2/net2" 0.481184
-cap "sens_amp_0/net2" "sens_amp_5/GN" 0.0169805
-cap "sens_amp_2/V_IN" "sens_amp_5/V_IN" 0.200001
-cap "sens_amp_1/net1" "sens_amp_3/OUT" 7.96676
-cap "sens_amp_7/GN" "sens_amp_3/V_IN" 0.171655
-cap "sens_amp_1/V_IN" "sens_amp_3/net1" 5.54802
-cap "sens_amp_1/V_IN" "sens_amp_7/REF" 3.63711
-cap "sens_amp_2/V_IN" "sens_amp_4/V_IN" 0.279706
-cap "sens_amp_7/GND" "sens_amp_6/OUT" 0.724428
-cap "sens_amp_2/GN" "sens_amp_5/OUT" 1.82001
-cap "sens_amp_0/net1" "sens_amp_4/GN" 0.542318
-cap "sens_amp_0/OUT" "sens_amp_5/GN" 0.364193
-cap "sens_amp_2/net1" "sens_amp_6/V_IN" 0.178266
-cap "sens_amp_6/net1" "sens_amp_2/net1" 0.555411
-cap "sens_amp_2/net1" "sens_amp_6/net2" 0.260591
-cap "sens_amp_2/GN" "sens_amp_0/net1" 2.70338
-cap "sens_amp_2/V_IN" "sens_amp_4/OUT" 5.48398
-cap "sens_amp_3/GN" "sens_amp_5/V_IN" 0.867695
-cap "sens_amp_2/V_IN" "sens_amp_4/net1" 5.0605
-cap "sens_amp_4/GN" "sens_amp_2/net1" 1.10309
-cap "sens_amp_2/net2" "sens_amp_3/OUT" 1.58409
-cap "sens_amp_5/OUT" "sens_amp_3/OUT" 3.37601
-cap "sens_amp_3/GN" "sens_amp_4/V_IN" 1.14312
-cap "sens_amp_7/VDD" "sens_amp_6/net1" 0.875791
-cap "sens_amp_2/GN" "sens_amp_2/net1" -0.592745
-cap "sens_amp_7/VDD" "sens_amp_6/V_IN" 0.0740631
-cap "sens_amp_7/VDD" "sens_amp_4/GN" 1.11389
-cap "sens_amp_0/net1" "sens_amp_3/OUT" 5.70067
-cap "sens_amp_2/V_IN" "sens_amp_5/net1" 3.65716
-cap "sens_amp_3/GN" "sens_amp_4/OUT" 4.01108
-cap "sens_amp_3/GN" "sens_amp_4/net1" 3.64731
-cap "sens_amp_7/net1" "sens_amp_3/OUT" 0.846673
-cap "sens_amp_2/GN" "sens_amp_7/VDD" 12.2625
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-cap "sens_amp_7/net2" "sens_amp_2/V_IN" 0.0298972
-cap "sens_amp_2/net1" "sens_amp_3/OUT" 9.35341
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-cap "sens_amp_2/V_IN" "sens_amp_5/net2" 0.792306
-cap "sens_amp_3/GN" "sens_amp_5/net1" 2.8438
-cap "sens_amp_7/VDD" "sens_amp_3/OUT" 8.1348
-cap "sens_amp_5/GN" "sens_amp_3/V_IN" 0.374548
-cap "sens_amp_7/GND" "sens_amp_0/net2" 2.71556
-cap "sens_amp_3/net2" "sens_amp_4/OUT" 0.0539388
-cap "sens_amp_1/V_IN" "sens_amp_5/V_IN" 0.0982191
-cap "sens_amp_3/net2" "sens_amp_4/net1" 0.430227
-cap "sens_amp_1/net1" "sens_amp_0/V_IN" 7.26132
-cap "sens_amp_7/net2" "sens_amp_3/GN" 0.235264
-cap "sens_amp_2/OUT" "sens_amp_6/net1" 1.77892
-cap "sens_amp_2/OUT" "sens_amp_6/V_IN" 0.501527
-cap "sens_amp_2/OUT" "sens_amp_6/net2" 0.436714
-cap "sens_amp_2/GN" "sens_amp_4/net2" 1.10438
-cap "sens_amp_6/GN" "sens_amp_3/net1" 0.131378
-cap "sens_amp_1/V_IN" "sens_amp_4/V_IN" 0.200001
-cap "sens_amp_6/GN" "sens_amp_7/REF" 0.0300706
-cap "sens_amp_3/GN" "sens_amp_5/net2" 1.10438
-cap "sens_amp_7/GND" "sens_amp_0/OUT" 45.411
-cap "sens_amp_1/net2" "sens_amp_4/GN" 0.360244
-cap "sens_amp_6/net1" "sens_amp_1/OUT" 0.0185122
-cap "sens_amp_2/OUT" "sens_amp_4/GN" 4.67934
-cap "sens_amp_1/net1" "sens_amp_3/net1" 2.73284
-cap "sens_amp_1/net1" "sens_amp_7/REF" 1.38329
-cap "sens_amp_3/GN" "sens_amp_2/V_IN" 5.00189
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-cap "sens_amp_5/GN" "sens_amp_1/GN" 0.569218
-cap "sens_amp_1/V_IN" "sens_amp_4/OUT" 3.98317
-cap "sens_amp_1/net2" "sens_amp_2/GN" 6.20483
-cap "sens_amp_1/V_IN" "sens_amp_4/net1" 3.65716
-cap "sens_amp_6/OUT" "sens_amp_3/V_IN" 0.0296688
-cap "sens_amp_1/OUT" "sens_amp_4/GN" 3.58135
-cap "sens_amp_2/GN" "sens_amp_2/OUT" -12.7773
-cap "sens_amp_2/net2" "sens_amp_0/V_IN" 1.22285
-cap "sens_amp_4/net2" "sens_amp_3/OUT" 1.53961
-cap "sens_amp_0/OUT" "sens_amp_0/net2" -0.0226666
-cap "sens_amp_0/V_IN" "sens_amp_5/OUT" 0.0337971
-cap "sens_amp_2/GN" "sens_amp_1/OUT" 7.17932
-cap "sens_amp_7/OUT" "sens_amp_3/OUT" 1.07806
-cap "sens_amp_7/net2" "sens_amp_3/net2" 0.072346
-cap "sens_amp_7/GND" "sens_amp_0/GN" 6.28756
-cap "sens_amp_0/net1" "sens_amp_0/V_IN" -1.60807
-cap "sens_amp_3/net2" "sens_amp_5/net2" 0.228458
-cap "sens_amp_2/net2" "sens_amp_3/net1" 1.55034
-cap "sens_amp_1/net2" "sens_amp_3/OUT" 1.32783
-cap "sens_amp_1/V_IN" "sens_amp_5/net1" 1.8501
-cap "sens_amp_2/net2" "sens_amp_7/REF" 0.84146
-cap "sens_amp_2/OUT" "sens_amp_3/OUT" 213.708
-cap "sens_amp_5/OUT" "sens_amp_3/net1" 0.517546
-cap "sens_amp_2/V_IN" "sens_amp_3/net2" 1.40293
-cap "sens_amp_7/REF" "sens_amp_5/OUT" 0.00569009
-cap "sens_amp_2/net1" "sens_amp_0/V_IN" 6.19604
-cap "sens_amp_1/OUT" "sens_amp_3/OUT" 10.533
-cap "sens_amp_0/net1" "sens_amp_3/net1" 1.95696
-cap "sens_amp_0/net1" "sens_amp_7/REF" 1.07863
-cap "sens_amp_7/net1" "sens_amp_3/net1" 0.02201
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-cap "sens_amp_7/net1" "sens_amp_7/REF" 0.00113403
-cap "sens_amp_0/OUT" "sens_amp_0/GN" -0.0194813
-cap "sens_amp_2/net1" "sens_amp_3/net1" 16.3277
-cap "sens_amp_7/VDD" "sens_amp_0/V_IN" 16.9097
-cap "sens_amp_7/GND" "sens_amp_3/V_IN" 0.691311
-cap "sens_amp_2/net1" "sens_amp_7/REF" 1.56987
-cap "sens_amp_2/V_IN" "sens_amp_1/V_IN" 118.504
-cap "sens_amp_0/net2" "sens_amp_3/V_IN" 0.116513
-cap "sens_amp_1/net1" "sens_amp_5/V_IN" 0.178266
-cap "sens_amp_7/VDD" "sens_amp_3/net1" 10.0944
-cap "sens_amp_7/VDD" "sens_amp_7/REF" 1.06581e-14
-cap "sens_amp_7/GN" "sens_amp_3/OUT" 1.61428
-cap "sens_amp_1/net1" "sens_amp_4/V_IN" 0.388934
-cap "sens_amp_3/GN" "sens_amp_1/V_IN" 4.56615
-cap "sens_amp_7/GND" "sens_amp_1/GN" -3.6739
-cap "sens_amp_0/OUT" "sens_amp_3/V_IN" 1.35367
-cap "sens_amp_0/V_IN" "sens_amp_4/net2" 0.432424
-cap "sens_amp_1/net1" "sens_amp_4/OUT" 1.50355
-cap "sens_amp_0/net2" "sens_amp_1/GN" 6.20483
-cap "sens_amp_1/net1" "sens_amp_4/net1" 1.1086
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-cap "sens_amp_1/net2" "sens_amp_0/V_IN" 1.40293
-cap "sens_amp_2/OUT" "sens_amp_0/V_IN" 7.72902
-cap "sens_amp_2/net2" "sens_amp_4/V_IN" 0.167714
-cap "sens_amp_7/REF" "sens_amp_4/net2" 0.0277982
-cap "sens_amp_0/GN" "sens_amp_3/V_IN" 0.509952
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-cap "sens_amp_0/OUT" "sens_amp_1/GN" 7.17932
-cap "sens_amp_1/OUT" "sens_amp_0/V_IN" 26.048
-cap "sens_amp_7/REF" "sens_amp_7/OUT" 0.000734526
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-cap "sens_amp_1/OUT" "sens_amp_3/net1" 6.63329
-cap "sens_amp_1/OUT" "sens_amp_7/REF" 0.530916
-cap "sens_amp_0/GN" "sens_amp_1/GN" 4.24571
-cap "sens_amp_2/net1" "sens_amp_4/V_IN" 0.556668
-cap "sens_amp_0/net1" "sens_amp_4/OUT" 0.73397
-cap "sens_amp_2/V_IN" "sens_amp_6/GN" 1.98682
-cap "sens_amp_1/net1" "sens_amp_5/net2" 0.260591
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-cap "sens_amp_7/VDD" "sens_amp_5/V_IN" 0.185481
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-cap "sens_amp_5/GN" "sens_amp_3/OUT" 3.69397
-cap "sens_amp_1/net1" "sens_amp_2/V_IN" 5.02073
-cap "sens_amp_2/net1" "sens_amp_4/OUT" 2.10716
-cap "sens_amp_2/GN" "sens_amp_6/OUT" 0.353243
-cap "sens_amp_2/net1" "sens_amp_4/net1" 1.53942
-cap "sens_amp_7/VDD" "sens_amp_4/V_IN" 0.331829
-cap "sens_amp_0/net1" "sens_amp_5/net1" 0.0306036
-cap "sens_amp_3/GN" "sens_amp_6/GN" 1.22197
-cap "sens_amp_2/net2" "sens_amp_5/net2" 0.159188
-cap "sens_amp_7/VDD" "sens_amp_4/OUT" 2.00528
-cap "sens_amp_7/GN" "sens_amp_3/net1" 0.0747197
-cap "sens_amp_7/VDD" "sens_amp_4/net1" 3.1932
-cap "sens_amp_3/GN" "sens_amp_1/net1" 2.70338
-cap "sens_amp_7/GN" "sens_amp_7/REF" 0.0101396
-cap "sens_amp_2/net1" "sens_amp_5/net1" 1.1086
-cap "sens_amp_1/GN" "sens_amp_3/V_IN" 0.890377
-cap "sens_amp_6/OUT" "sens_amp_3/OUT" 2.35713
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-cap "sens_amp_2/V_IN" "sens_amp_5/OUT" 3.98317
-cap "sens_amp_0/net1" "sens_amp_5/net2" 0.0239283
-cap "sens_amp_7/GND" "sens_amp_6/net2" 0.338144
-cap "sens_amp_7/GND" "sens_amp_6/V_IN" 0.158675
-cap "sens_amp_7/GND" "sens_amp_6/net1" 0.649527
-cap "sens_amp_7/net2" "sens_amp_2/net1" 0.0239283
-cap "sens_amp_0/net1" "sens_amp_2/V_IN" 4.09312
-cap "sens_amp_7/VDD" "sens_amp_5/net1" 1.90604
-cap "sens_amp_7/GND" "sens_amp_4/GN" 2.53562
-cap "sens_amp_3/net2" "sens_amp_6/GN" 0.360244
-cap "sens_amp_2/net1" "sens_amp_5/net2" 0.468659
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-cap "sens_amp_2/OUT" "sens_amp_5/V_IN" 1.35163
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-cap "sens_amp_3/GN" "sens_amp_2/net2" 6.20483
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-cap "sens_amp_2/net1" "sens_amp_2/V_IN" -7.91599
-cap "sens_amp_7/GND" "sens_amp_2/GN" -4.12821
-cap "sens_amp_3/GN" "sens_amp_5/OUT" 3.08586
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-cap "sens_amp_1/OUT" "sens_amp_5/V_IN" 0.501527
-cap "sens_amp_2/OUT" "sens_amp_4/V_IN" 2.05254
-cap "sens_amp_0/net2" "sens_amp_4/GN" 0.199538
-cap "sens_amp_3/GN" "sens_amp_0/net1" 2.11581
-cap "sens_amp_1/OUT" "sens_amp_4/V_IN" 1.35163
-cap "sens_amp_1/net2" "sens_amp_4/OUT" 0.0311452
-cap "sens_amp_2/GN" "sens_amp_0/net2" 1.1122
-cap "sens_amp_6/GN" "sens_amp_1/V_IN" 0.604472
-cap "sens_amp_7/VDD" "sens_amp_2/V_IN" 2.7025
-cap "sens_amp_2/OUT" "sens_amp_4/OUT" 5.22882
-cap "sens_amp_3/GN" "sens_amp_7/net1" 0.418359
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-cap "sens_amp_2/OUT" "sens_amp_4/net1" 5.92247
-cap "sens_amp_7/GND" "sens_amp_3/OUT" 13.4747
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-cap "sens_amp_7/V_IN" "sens_amp_3/V_IN" 0.00891935
-cap "sens_amp_0/OUT" "sens_amp_4/GN" 2.08802
-cap "sens_amp_3/GN" "sens_amp_2/net1" 966.389
-cap "sens_amp_1/net1" "sens_amp_1/V_IN" -7.91599
-cap "sens_amp_1/OUT" "sens_amp_4/OUT" 3.66878
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-cap "sens_amp_3/net2" "sens_amp_5/OUT" 0.0450273
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-cap "sens_amp_0/net2" "sens_amp_3/OUT" 0.924995
-cap "sens_amp_7/GND" "sens_amp_7/SA_IREF" -1.77636e-15
-cap "sens_amp_5/GN" "sens_amp_3/net1" 0.173534
-cap "sens_amp_5/GN" "sens_amp_7/REF" 0.0576166
-cap "sens_amp_2/OUT" "sens_amp_5/net1" 4.07564
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-cap "sens_amp_7/VDD" "sens_amp_3/GN" 13.1656
-cap "sens_amp_0/GN" "sens_amp_4/GN" 0.569218
-cap "sens_amp_1/OUT" "sens_amp_5/net1" 1.77892
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-cap "sens_amp_2/net2" "sens_amp_1/V_IN" 1.40293
-cap "sens_amp_2/V_IN" "sens_amp_4/net2" 1.06473
-cap "sens_amp_0/OUT" "sens_amp_3/OUT" 7.42466
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-cap "sens_amp_2/GN" "sens_amp_0/GN" 2.70568
-cap "sens_amp_1/V_IN" "sens_amp_5/OUT" 2.04267
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-cap "sens_amp_0/net1" "sens_amp_1/V_IN" 5.02073
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-cap "sens_amp_6/OUT" "sens_amp_7/REF" 0.00270368
-cap "sens_amp_2/OUT" "sens_amp_2/V_IN" -21.2517
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-cap "sens_amp_6/V_IN" "sens_amp_3/V_IN" 0.0231185
-cap "sens_amp_6/net2" "sens_amp_3/V_IN" 0.0882095
-cap "sens_amp_3/GN" "sens_amp_4/net2" 1.3779
-cap "sens_amp_1/OUT" "sens_amp_2/V_IN" 7.85568
-cap "sens_amp_0/GN" "sens_amp_3/OUT" 4.13327
-cap "sens_amp_2/net1" "sens_amp_1/V_IN" 7.26132
-cap "sens_amp_4/GN" "sens_amp_3/V_IN" 0.418694
-cap "sens_amp_3/GN" "sens_amp_7/OUT" 0.353243
-cap "sens_amp_1/net2" "sens_amp_3/GN" 1.1122
-cap "sens_amp_2/GN" "sens_amp_3/V_IN" 1.17251
-cap "sens_amp_3/GN" "sens_amp_2/OUT" 7.17932
-cap "sens_amp_7/VDD" "sens_amp_1/V_IN" -0.554857
-cap "sens_amp_7/GND" "sens_amp_0/V_IN" 89.5866
-cap "sens_amp_3/GN" "sens_amp_1/OUT" 6.40448
-cap "sens_amp_1/net1" "sens_amp_6/GN" 0.154003
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-cap "sens_amp_4/GN" "sens_amp_1/GN" 1.22197
-cap "sens_amp_3/net2" "sens_amp_7/OUT" 0.0138251
-cap "sens_amp_3/V_IN" "sens_amp_3/OUT" -6.29296
-cap "sens_amp_7/GND" "sens_amp_3/net1" 2.77471
-cap "sens_amp_0/net2" "sens_amp_0/V_IN" -0.258739
-cap "sens_amp_7/GN" "sens_amp_2/V_IN" 0.604472
-cap "sens_amp_2/GN" "sens_amp_1/GN" 4.24571
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-cap "sens_amp_2/OUT" "sens_amp_3/net2" 1.58576
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-cap "sens_amp_0/OUT" "sens_amp_0/V_IN" -8.473
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-cap "sens_amp_1/OUT" "sens_amp_3/net2" 1.34047
-cap "sens_amp_6/GN" "sens_amp_2/net2" 0.199538
-cap "sens_amp_0/net2" "sens_amp_7/REF" 0.795885
-cap "sens_amp_3/GN" "sens_amp_7/GN" 0.569218
-cap "sens_amp_1/GN" "sens_amp_3/OUT" 6.78529
-cap "sens_amp_1/net1" "sens_amp_2/net2" 1.13968
-cap "sens_amp_1/net1" "sens_amp_5/OUT" 0.73397
-cap "sens_amp_1/net2" "sens_amp_1/V_IN" -0.258739
-cap "sens_amp_0/OUT" "sens_amp_3/net1" 4.57559
-cap "sens_amp_2/OUT" "sens_amp_1/V_IN" 26.048
-cap "sens_amp_0/OUT" "sens_amp_7/REF" 1.3198
-cap "sens_amp_0/GN" "sens_amp_0/V_IN" -0.0197463
-cap "sens_amp_0/net1" "sens_amp_1/net1" 18.8714
-cap "sens_amp_1/OUT" "sens_amp_1/V_IN" -21.2517
-cap "sens_amp_2/net1" "sens_amp_6/GN" 0.542318
-cap "sens_amp_7/GN" "sens_amp_3/net2" 0.199538
-cap "sens_amp_0/GN" "sens_amp_3/net1" 2.43454
-cap "sens_amp_1/net1" "sens_amp_2/net1" 18.8714
-cap "sens_amp_0/GN" "sens_amp_7/REF" 2.02791
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-cap "sens_amp_7/VDD" "sens_amp_6/GN" 0.367568
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-cap "sens_amp_7/VDD" "sens_amp_1/net1" 19.7151
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-cap "sens_amp_7/GND" "sens_amp_5/V_IN" 0.344905
-cap "sens_amp_7/V_IN" "sens_amp_3/OUT" 0.409617
-cap "sens_amp_0/V_IN" "sens_amp_3/V_IN" 0.202138
-cap "sens_amp_7/GND" "sens_amp_4/V_IN" 0.577447
-cap "sens_amp_2/net1" "sens_amp_2/net2" -0.254835
-cap "sens_amp_2/net1" "sens_amp_5/OUT" 1.50355
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-cap "sens_amp_7/REF" "sens_amp_3/V_IN" 1.28211
-cap "sens_amp_3/GN" "sens_amp_5/GN" 1.73983
-cap "sens_amp_7/GND" "sens_amp_4/OUT" 2.49932
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-cap "sens_amp_0/net1" "sens_amp_2/net1" 4.76332
-cap "sens_amp_7/GND" "sens_amp_4/net1" 2.322
-cap "sens_amp_6/OUT" "sens_amp_2/V_IN" 2.04267
-cap "sens_amp_1/GN" "sens_amp_0/V_IN" 5.00189
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-cap "sens_amp_2/GN" "sens_amp_6/net2" 0.235264
-cap "sens_amp_2/GN" "sens_amp_6/V_IN" 0.0704639
-cap "sens_amp_1/net1" "sens_amp_4/net2" 0.468659
-cap "sens_amp_1/net2" "sens_amp_6/GN" 0.0169805
-cap "sens_amp_0/net2" "sens_amp_4/OUT" 0.0138251
-cap "sens_amp_7/VDD" "sens_amp_0/net1" 11.971
-cap "sens_amp_2/GN" "sens_amp_4/GN" 1.73983
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-cap "sens_amp_0/OUT" "sens_amp_4/V_IN" 0.501527
-cap "sens_amp_2/OUT" "sens_amp_6/GN" 2.08802
-cap "sens_amp_1/GN" "sens_amp_3/net1" 4.06097
-cap "sens_amp_7/GND" "sens_amp_5/net1" 1.39544
-cap "sens_amp_1/GN" "sens_amp_7/REF" 2.10845
-cap "sens_amp_3/GN" "sens_amp_6/OUT" 1.82001
-cap "sens_amp_2/OUT" "sens_amp_1/net1" 9.35341
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-cap "sens_amp_1/OUT" "sens_amp_6/GN" 0.364193
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-cap "sens_amp_6/net1" "sens_amp_3/OUT" 2.20565
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-cap "sens_amp_7/VDD" "sens_amp_2/net1" 25.7616
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-cap "sens_amp_6/V_IN" "sens_amp_3/OUT" 1.12381
-cap "sens_amp_0/OUT" "sens_amp_4/OUT" 1.70375
-cap "sens_amp_0/OUT" "sens_amp_4/net1" 1.77892
-cap "sens_amp_1/OUT" "sens_amp_1/net1" -16.8555
-cap "sens_amp_7/GND" "sens_amp_7/net2" 0.105658
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-cap "sens_amp_0/GN" "sens_amp_4/V_IN" 0.0704639
-cap "sens_amp_7/GND" "sens_amp_5/net2" 0.671795
-cap "sens_amp_2/GN" "sens_amp_3/OUT" 8.68828
-cap "sens_amp_7/GND" "sens_amp_2/V_IN" 87.9176
-cap "sens_amp_1/net2" "sens_amp_2/net2" 0.545016
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-cap "sens_amp_0/GN" "sens_amp_4/OUT" 0.353243
-cap "sens_amp_5/GN" "sens_amp_1/V_IN" 1.98682
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-cap "sens_amp_2/OUT" "sens_amp_2/net2" -0.720943
-cap "sens_amp_6/OUT" "sens_amp_3/net2" 0.0311452
-cap "sens_amp_1/net2" "sens_amp_5/OUT" 0.0138251
-cap "sens_amp_0/GN" "sens_amp_4/net1" 0.418359
-cap "sens_amp_2/OUT" "sens_amp_5/OUT" 3.66878
-cap "sens_amp_1/OUT" "sens_amp_2/net2" 1.58576
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-cap "sens_amp_0/net2" "sens_amp_2/V_IN" 0.480188
-cap "sens_amp_1/OUT" "sens_amp_5/OUT" 1.70375
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-cap "sens_amp_0/net1" "sens_amp_2/OUT" 7.96676
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-cap "sens_amp_2/net1" "sens_amp_7/OUT" 0.00758052
-cap "sens_amp_7/V_IN" "sens_amp_3/net1" 0.0136829
-cap "sens_amp_7/V_IN" "sens_amp_7/REF" 0.000316566
-cap "sens_amp_0/net1" "sens_amp_1/OUT" 9.35341
-cap "sens_amp_2/OUT" "sens_amp_7/net1" 0.0185122
-cap "sens_amp_7/GND" "sens_amp_3/GN" -5.34158
-cap "sens_amp_3/V_IN" "sens_amp_4/V_IN" 0.0425749
-cap "sens_amp_6/OUT" "sens_amp_1/V_IN" 0.0337971
-cap "sens_amp_1/net2" "sens_amp_2/net1" 1.81286
-cap "sens_amp_2/OUT" "sens_amp_2/net1" -16.8555
-cap "sens_amp_0/OUT" "sens_amp_2/V_IN" 6.3986
-cap "sens_amp_7/VDD" "sens_amp_7/OUT" 0.105277
-cap "sens_amp_3/GN" "sens_amp_0/net2" 0.837971
-cap "sens_amp_1/OUT" "sens_amp_2/net1" 12.2505
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-cap "sens_amp_4/net1" "sens_amp_3/V_IN" 0.137826
-cap "sens_amp_1/GN" "sens_amp_5/V_IN" 0.0704639
-cap "sens_amp_7/VDD" "sens_amp_2/OUT" 136.414
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-cap "sens_amp_1/GN" "sens_amp_4/V_IN" 0.496482
-cap "sens_amp_7/GND" "sens_amp_3/net2" 0.52377
-cap "sens_amp_0/GN" "sens_amp_2/V_IN" 2.51632
-cap "sens_amp_7/VDD" "sens_amp_1/OUT" 133.138
-cap "sens_amp_3/GN" "sens_amp_0/OUT" 4.92266
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-cap "sens_amp_3/V_IN" "sens_amp_7/net1" 2.17648
-cap "sens_amp_6/GN" "sens_amp_4/GN" 2.70568
-cap "sens_amp_4/net1" "sens_amp_7/V_IN" 2.71367
-cap "sens_amp_3/V_IN" "sens_amp_6/net2" 0.819568
-cap "sens_amp_7/REF" "sens_amp_7/GND" -1.07395
-cap "sens_amp_6/OUT" "sens_amp_3/OUT" 4.36043
-cap "sens_amp_1/net2" "sens_amp_5/OUT" 0.406227
-cap "sens_amp_3/net2" "sens_amp_7/net1" 0.247059
-cap "sens_amp_2/OUT" "sens_amp_6/net1" 1.13371
-cap "sens_amp_5/V_IN" "sens_amp_5/GN" -4.01438
-cap "sens_amp_3/V_IN" "sens_amp_1/net1" 3.52696
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-cap "sens_amp_6/net1" "sens_amp_7/GN" 966.389
-cap "sens_amp_3/net2" "sens_amp_6/net2" 0.159188
-cap "sens_amp_1/GN" "sens_amp_7/GND" 1.45416
-cap "sens_amp_2/net2" "sens_amp_4/GN" 0.631017
-cap "sens_amp_2/OUT" "sens_amp_5/net1" 2.83091
-cap "sens_amp_7/net2" "sens_amp_6/net1" 1.13968
-cap "sens_amp_3/V_IN" "sens_amp_6/OUT" 5.62011
-cap "sens_amp_6/GN" "sens_amp_6/V_IN" -4.01438
-cap "sens_amp_7/GN" "sens_amp_5/net1" 2.70338
-cap "sens_amp_3/GN" "sens_amp_5/net1" 1.51117
-cap "sens_amp_5/OUT" "sens_amp_6/net1" 12.2505
-cap "sens_amp_3/net1" "sens_amp_4/OUT" 8.72808
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-cap "sens_amp_7/net2" "sens_amp_5/net1" 0.998443
-cap "sens_amp_5/V_IN" "sens_amp_4/GN" 3.35462
-cap "sens_amp_4/net1" "sens_amp_4/V_IN" -7.91599
-cap "sens_amp_2/net2" "sens_amp_6/V_IN" 0.0624477
-cap "sens_amp_1/OUT" "sens_amp_7/GND" 1.30914
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-cap "sens_amp_7/REF" "sens_amp_5/GN" 2.25708
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-cap "sens_amp_2/OUT" "sens_amp_7/GN" 0.188179
-cap "sens_amp_7/V_IN" "sens_amp_7/OUT" -12.7787
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-cap "sens_amp_3/GN" "sens_amp_7/GN" 0.322947
-cap "sens_amp_1/GN" "sens_amp_5/GN" 0.322947
-cap "sens_amp_6/GN" "sens_amp_7/VDD" 8.39615
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-cap "sens_amp_4/net2" "sens_amp_4/OUT" -0.720943
-cap "sens_amp_5/net2" "sens_amp_4/OUT" 1.58576
-cap "sens_amp_0/V_IN" "sens_amp_4/net2" 0.0600723
-cap "sens_amp_3/OUT" "sens_amp_6/net1" 3.79473
-cap "sens_amp_5/V_IN" "sens_amp_6/V_IN" 118.504
-cap "sens_amp_7/net2" "sens_amp_3/GN" 0.0715974
-cap "sens_amp_5/OUT" "sens_amp_2/OUT" 3.75587
-cap "sens_amp_0/V_IN" "sens_amp_5/net2" 0.00146339
-cap "sens_amp_5/OUT" "sens_amp_7/GN" 6.40448
-cap "sens_amp_2/net1" "sens_amp_7/GND" 4.37348
-cap "sens_amp_7/REF" "sens_amp_4/GN" 2.67137
-cap "sens_amp_5/OUT" "sens_amp_3/GN" 3.69942
-cap "sens_amp_4/V_IN" "sens_amp_2/V_IN" 0.0887224
-cap "sens_amp_3/OUT" "sens_amp_5/net1" 5.5458
-cap "sens_amp_7/V_IN" "sens_amp_7/GND" 0.144552
-cap "sens_amp_7/net2" "sens_amp_5/OUT" 1.34047
-cap "sens_amp_1/GN" "sens_amp_4/GN" 0.682041
-cap "sens_amp_3/V_IN" "sens_amp_6/net1" 4.37099
-cap "sens_amp_1/OUT" "sens_amp_5/GN" 0.809423
-cap "sens_amp_7/net1" "sens_amp_4/OUT" 6.90655
-cap "sens_amp_4/V_IN" "sens_amp_7/OUT" 5.64978
-cap "sens_amp_3/net2" "sens_amp_6/net1" 0.719464
-cap "sens_amp_7/VDD" "sens_amp_5/V_IN" -1.17811
-cap "sens_amp_6/net2" "sens_amp_4/OUT" 1.34047
-cap "sens_amp_3/V_IN" "sens_amp_5/net1" 6.08298
-cap "sens_amp_7/REF" "sens_amp_6/V_IN" 3.12719
-cap "sens_amp_3/OUT" "sens_amp_7/GN" 1.01759
-cap "sens_amp_1/net1" "sens_amp_4/OUT" 4.19711
-cap "sens_amp_3/net2" "sens_amp_5/net1" 1.11245
-cap "sens_amp_7/net2" "sens_amp_3/OUT" 0.012672
-cap "sens_amp_2/net1" "sens_amp_5/GN" 1.24505
-cap "sens_amp_1/OUT" "sens_amp_4/GN" 1.34132
-cap "sens_amp_7/V_IN" "sens_amp_5/GN" 2.51632
-cap "sens_amp_6/OUT" "sens_amp_4/OUT" 10.533
-cap "sens_amp_3/V_IN" "sens_amp_2/OUT" 5.32511
-cap "sens_amp_4/V_IN" "sens_amp_7/GND" 88.2507
-cap "sens_amp_7/REF" "sens_amp_0/OUT" 0.0156401
-cap "sens_amp_3/OUT" "sens_amp_5/OUT" 6.16253
-cap "sens_amp_3/V_IN" "sens_amp_3/GN" -3.99463
-cap "sens_amp_3/V_IN" "sens_amp_7/GN" 2.11459
+cap "sens_amp_7/VDD" "sens_amp_5/GN" 0.710998
cap "sens_amp_7/REF" "sens_amp_7/VDD" 1.06581e-14
-cap "sens_amp_7/net2" "sens_amp_3/V_IN" 0.448123
-cap "sens_amp_3/net2" "sens_amp_7/GN" 0.271701
-cap "sens_amp_2/net1" "sens_amp_4/GN" 1.60029
-cap "sens_amp_1/GN" "sens_amp_7/VDD" 0.374094
-cap "sens_amp_3/V_IN" "sens_amp_5/OUT" 7.68761
-cap "sens_amp_7/net2" "sens_amp_3/net2" 0.072346
-cap "sens_amp_7/V_IN" "sens_amp_4/GN" 1.40025
-cap "sens_amp_0/GN" "sens_amp_4/OUT" 0.671754
-cap "sens_amp_3/net2" "sens_amp_5/OUT" 1.2828
-cap "sens_amp_1/net2" "sens_amp_4/OUT" 0.89385
-cap "sens_amp_4/net1" "sens_amp_2/GN" 1.51117
-cap "sens_amp_4/V_IN" "sens_amp_5/GN" 5.00189
-cap "sens_amp_6/GN" "sens_amp_3/net1" 1.98444
-cap "sens_amp_0/net2" "sens_amp_3/V_IN" 0.192536
-cap "sens_amp_2/net1" "sens_amp_6/V_IN" 0.856403
-cap "sens_amp_7/V_IN" "sens_amp_6/V_IN" 118.504
-cap "sens_amp_7/VDD" "sens_amp_1/OUT" 1.26693
-cap "sens_amp_4/OUT" "sens_amp_6/net1" 10.1381
-cap "sens_amp_3/V_IN" "sens_amp_3/OUT" -14.0887
-cap "sens_amp_4/net1" "sens_amp_1/V_IN" 0.789632
-cap "sens_amp_4/V_IN" "sens_amp_4/GN" -4.01438
-cap "sens_amp_6/GN" "sens_amp_4/net2" 1.1122
-cap "sens_amp_4/OUT" "sens_amp_5/net1" 12.2505
-cap "sens_amp_0/V_IN" "sens_amp_5/net1" 0.00387258
-cap "sens_amp_4/net1" "sens_amp_0/net1" 0.822676
-cap "sens_amp_7/VDD" "sens_amp_2/net1" 3.16167
-cap "sens_amp_6/GN" "sens_amp_5/net2" 6.20483
-cap "sens_amp_7/VDD" "sens_amp_7/V_IN" -19.3501
-cap "sens_amp_3/net1" "sens_amp_5/V_IN" 4.02526
-cap "sens_amp_2/net2" "sens_amp_4/net2" 0.228458
-cap "sens_amp_4/V_IN" "sens_amp_6/V_IN" 0.368428
-cap "sens_amp_4/OUT" "sens_amp_2/OUT" 5.30415
-cap "sens_amp_2/net2" "sens_amp_5/net2" 0.159188
-cap "sens_amp_4/OUT" "sens_amp_3/GN" 4.6772
-cap "sens_amp_4/OUT" "sens_amp_7/GN" 4.92266
-cap "sens_amp_6/GN" "sens_amp_7/net1" 5.62731
-cap "sens_amp_7/net2" "sens_amp_4/OUT" 0.947209
-cap "sens_amp_4/net2" "sens_amp_5/V_IN" 0.598319
-cap "sens_amp_7/GND" "sens_amp_2/GN" 3.182
-cap "sens_amp_7/REF" "sens_amp_3/net1" 1.11616
-cap "sens_amp_5/net2" "sens_amp_5/V_IN" -0.258739
-cap "sens_amp_4/OUT" "sens_amp_5/OUT" 213.708
-cap "sens_amp_6/GN" "sens_amp_1/net1" 0.176633
-cap "sens_amp_4/V_IN" "sens_amp_0/OUT" 1.10273
+cap "sens_amp_4/GN" "sens_amp_3/net2" 3.01959
+cap "sens_amp_6/net1" "sens_amp_3/net1" 0.0694101
+cap "sens_amp_2/net1" "sens_amp_3/OUT" 9.35341
+cap "sens_amp_1/GN" "sens_amp_1/V_IN" -4.01438
+cap "sens_amp_3/GN" "sens_amp_0/GN" 1.90401
+cap "sens_amp_3/OUT" "sens_amp_0/V_IN" 5.64978
+cap "sens_amp_4/net1" "sens_amp_2/net1" 1.53942
+cap "sens_amp_4/GN" "sens_amp_1/net1" 0.870768
+cap "sens_amp_0/net2" "sens_amp_3/net2" 0.318376
+cap "sens_amp_4/net1" "sens_amp_0/V_IN" 1.8501
+cap "sens_amp_5/GN" "sens_amp_1/OUT" 2.08802
+cap "sens_amp_7/REF" "sens_amp_1/OUT" 0.530916
+cap "sens_amp_3/GN" "sens_amp_4/net2" 1.3779
+cap "sens_amp_7/GND" "sens_amp_7/V_IN" 0.0393146
+cap "sens_amp_7/GND" "sens_amp_0/OUT" 45.411
+cap "sens_amp_3/OUT" "sens_amp_7/OUT" 1.07806
+cap "sens_amp_0/net2" "sens_amp_1/net1" 1.81286
+cap "sens_amp_7/GND" "sens_amp_7/GN" 0.345556
+cap "sens_amp_3/GN" "sens_amp_5/V_IN" 0.867695
+cap "sens_amp_7/VDD" "sens_amp_4/GN" 1.11389
+cap "sens_amp_3/GN" "sens_amp_5/net1" 2.8438
+cap "sens_amp_4/OUT" "sens_amp_3/V_IN" 0.0485806
+cap "sens_amp_5/OUT" "sens_amp_2/net1" 1.50355
+cap "sens_amp_6/V_IN" "sens_amp_3/V_IN" 0.0231185
+cap "sens_amp_3/net2" "sens_amp_3/OUT" -0.720943
+cap "sens_amp_5/OUT" "sens_amp_0/V_IN" 0.0337971
+cap "sens_amp_2/GN" "sens_amp_5/net2" 0.708951
+cap "sens_amp_4/OUT" "sens_amp_2/V_IN" 5.48398
+cap "sens_amp_4/net1" "sens_amp_3/net2" 0.430227
+cap "sens_amp_2/net2" "sens_amp_3/V_IN" 0.217097
+cap "sens_amp_6/V_IN" "sens_amp_2/V_IN" 0.0982191
+cap "sens_amp_7/GND" "sens_amp_1/GN" -3.6739
+cap "sens_amp_3/OUT" "sens_amp_1/net1" 7.96676
+cap "sens_amp_6/net2" "sens_amp_3/OUT" 0.919942
+cap "sens_amp_2/net2" "sens_amp_2/V_IN" -0.258739
+cap "sens_amp_7/net2" "sens_amp_3/V_IN" 0.0443733
cap "sens_amp_7/VDD" "sens_amp_4/V_IN" 1.55154
-cap "sens_amp_0/V_IN" "sens_amp_5/OUT" 0.0620459
-cap "sens_amp_2/net2" "sens_amp_6/net2" 0.072346
-cap "sens_amp_6/GN" "sens_amp_6/OUT" -12.7773
-cap "sens_amp_1/V_IN" "sens_amp_7/GND" 0.444062
-cap "sens_amp_0/net2" "sens_amp_4/OUT" 0.406227
-cap "sens_amp_7/net1" "sens_amp_5/V_IN" 6.19604
-cap "sens_amp_7/REF" "sens_amp_4/net2" 1.08135
-cap "sens_amp_2/net2" "sens_amp_6/OUT" 0.406227
-cap "sens_amp_7/REF" "sens_amp_5/net2" 0.905659
-cap "sens_amp_6/net2" "sens_amp_5/V_IN" 1.40293
-cap "sens_amp_3/OUT" "sens_amp_4/OUT" 107.899
-cap "sens_amp_5/GN" "sens_amp_2/GN" 0.682041
-cap "sens_amp_0/net1" "sens_amp_7/GND" 0.882169
-cap "sens_amp_1/GN" "sens_amp_4/net2" 0.225634
-cap "sens_amp_3/net1" "sens_amp_1/OUT" 3.47241
-cap "sens_amp_1/net1" "sens_amp_5/V_IN" 0.856403
-cap "sens_amp_1/GN" "sens_amp_5/net2" 0.0715974
-cap "sens_amp_1/net2" "sens_amp_6/GN" 0.0356827
-cap "sens_amp_6/OUT" "sens_amp_5/V_IN" 26.048
-cap "sens_amp_3/V_IN" "sens_amp_4/OUT" 25.9994
-cap "sens_amp_0/V_IN" "sens_amp_3/V_IN" 0.0571235
-cap "sens_amp_7/REF" "sens_amp_7/net1" 0.961118
-cap "sens_amp_1/V_IN" "sens_amp_5/GN" 0.299423
-cap "sens_amp_4/GN" "sens_amp_2/GN" 0.965846
-cap "sens_amp_3/net2" "sens_amp_4/OUT" 1.53015
-cap "sens_amp_2/net1" "sens_amp_3/net1" 2.14465
-cap "sens_amp_4/net2" "sens_amp_1/OUT" 0.0272668
-cap "sens_amp_7/REF" "sens_amp_6/net2" 0.656331
-cap "sens_amp_6/GN" "sens_amp_6/net1" -0.592745
-cap "sens_amp_7/V_IN" "sens_amp_3/net1" 1.02099
-cap "sens_amp_5/net2" "sens_amp_1/OUT" 0.012672
-cap "sens_amp_7/REF" "sens_amp_1/net1" 0.166904
-cap "sens_amp_0/net1" "sens_amp_5/GN" 0.176633
-cap "sens_amp_7/REF" "sens_amp_6/OUT" 0.358582
-cap "sens_amp_6/GN" "sens_amp_5/net1" 966.389
-cap "sens_amp_2/net2" "sens_amp_6/net1" 0.247059
-cap "sens_amp_1/V_IN" "sens_amp_4/GN" 0.476504
-cap "sens_amp_1/net2" "sens_amp_5/V_IN" 0.0624477
-cap "sens_amp_6/V_IN" "sens_amp_2/GN" 0.0593834
-cap "sens_amp_4/net1" "sens_amp_2/V_IN" 1.13554
-cap "sens_amp_4/net2" "sens_amp_2/net1" 0.373451
-cap "sens_amp_4/net2" "sens_amp_7/V_IN" 0.309049
-cap "sens_amp_5/net2" "sens_amp_2/net1" 0.278332
-cap "sens_amp_2/net2" "sens_amp_5/net1" 0.719464
-cap "sens_amp_0/net1" "sens_amp_4/GN" 0.752366
-cap "sens_amp_7/V_IN" "sens_amp_5/net2" 0.480188
-cap "sens_amp_4/net1" "sens_amp_7/OUT" 5.70067
-cap "sens_amp_6/GN" "sens_amp_2/OUT" 0.809423
-cap "sens_amp_5/V_IN" "sens_amp_6/net1" 7.26132
-cap "sens_amp_7/REF" "sens_amp_0/GN" 0.0805964
-cap "sens_amp_4/V_IN" "sens_amp_3/net1" 4.93566
-cap "sens_amp_6/GN" "sens_amp_7/GN" 4.24571
-cap "sens_amp_6/GN" "sens_amp_3/GN" 0.682041
-cap "sens_amp_7/REF" "sens_amp_1/net2" 0.132583
-cap "sens_amp_7/VDD" "sens_amp_2/GN" 0.760318
-cap "sens_amp_6/OUT" "sens_amp_1/OUT" 0.0016529
-cap "sens_amp_7/net2" "sens_amp_6/GN" 1.82263
-cap "sens_amp_5/V_IN" "sens_amp_5/net1" -7.91599
-cap "sens_amp_7/net1" "sens_amp_2/net1" 0.00622933
-cap "sens_amp_2/net2" "sens_amp_7/GN" 0.0356827
-cap "sens_amp_7/V_IN" "sens_amp_7/net1" -6.30791
-cap "sens_amp_6/GN" "sens_amp_5/OUT" 7.17932
-cap "sens_amp_6/net2" "sens_amp_2/net1" 0.15249
-cap "sens_amp_4/net1" "sens_amp_7/GND" 9.38829
-cap "sens_amp_4/net2" "sens_amp_4/V_IN" -0.258739
-cap "sens_amp_7/V_IN" "sens_amp_6/net2" 0.598319
-cap "sens_amp_2/V_IN" "sens_amp_7/OUT" 0.0620459
-cap "sens_amp_7/REF" "sens_amp_6/net1" 1.32965
-cap "sens_amp_5/net2" "sens_amp_4/V_IN" 1.40293
-cap "sens_amp_7/VDD" "sens_amp_1/V_IN" 0.255515
-cap "sens_amp_2/net2" "sens_amp_5/OUT" 0.89385
-cap "sens_amp_5/V_IN" "sens_amp_2/OUT" 2.88355
-cap "sens_amp_0/V_IN" "sens_amp_4/OUT" 0.90419
-cap "sens_amp_2/net1" "sens_amp_6/OUT" 2.07132
-cap "sens_amp_5/V_IN" "sens_amp_7/GN" 4.56615
-cap "sens_amp_5/V_IN" "sens_amp_3/GN" 1.64863
-cap "sens_amp_7/V_IN" "sens_amp_6/OUT" 7.85568
-cap "sens_amp_7/REF" "sens_amp_5/net1" 1.65526
-cap "sens_amp_7/VDD" "sens_amp_0/net1" 0.657967
-cap "sens_amp_7/net2" "sens_amp_5/V_IN" 1.22285
-cap "sens_amp_6/GN" "sens_amp_3/OUT" 1.6786
-cap "sens_amp_2/V_IN" "sens_amp_7/GND" 0.823359
-cap "sens_amp_1/GN" "sens_amp_5/net1" 0.143218
-cap "sens_amp_5/OUT" "sens_amp_5/V_IN" -21.2517
-cap "sens_amp_4/V_IN" "sens_amp_7/net1" 4.44679
-cap "sens_amp_4/net1" "sens_amp_5/GN" 966.389
-cap "sens_amp_4/V_IN" "sens_amp_6/net2" 1.22285
-cap "sens_amp_7/OUT" "sens_amp_7/GND" 5.8195
-cap "sens_amp_7/REF" "sens_amp_2/OUT" 0.0880739
-cap "sens_amp_6/GN" "sens_amp_3/V_IN" 3.33729
-cap "sens_amp_1/OUT" "sens_amp_6/net1" 0.00188699
-cap "sens_amp_7/REF" "sens_amp_3/GN" 1.00742
-cap "sens_amp_7/REF" "sens_amp_7/GN" 0.818262
-cap "sens_amp_4/V_IN" "sens_amp_1/net1" 2.32474
-cap "sens_amp_6/GN" "sens_amp_3/net2" 0.477727
-cap "sens_amp_7/REF" "sens_amp_7/net2" 0.360885
-cap "sens_amp_4/V_IN" "sens_amp_6/OUT" 7.72902
-cap "sens_amp_1/OUT" "sens_amp_5/net1" 1.13371
-cap "sens_amp_2/net2" "sens_amp_3/V_IN" 0.381221
-cap "sens_amp_4/net1" "sens_amp_4/GN" -0.592745
-cap "sens_amp_7/REF" "sens_amp_5/OUT" 0.763385
-cap "sens_amp_3/OUT" "sens_amp_5/V_IN" 4.49381
-cap "sens_amp_2/V_IN" "sens_amp_5/GN" 0.476504
-cap "sens_amp_2/net1" "sens_amp_6/net1" 0.822676
-cap "sens_amp_1/GN" "sens_amp_5/OUT" 0.671754
-cap "sens_amp_7/V_IN" "sens_amp_6/net1" 5.02073
-cap "sens_amp_3/V_IN" "sens_amp_5/V_IN" 0.333662
-cap "sens_amp_7/OUT" "sens_amp_5/GN" 6.78529
-cap "sens_amp_2/net1" "sens_amp_5/net1" 2.14149
-cap "sens_amp_4/net1" "sens_amp_6/V_IN" 4.09312
-cap "sens_amp_0/net2" "sens_amp_7/REF" 0.0443733
-cap "sens_amp_0/GN" "sens_amp_4/V_IN" 0.0593834
-cap "sens_amp_7/V_IN" "sens_amp_5/net1" 4.09312
-cap "sens_amp_2/V_IN" "sens_amp_4/GN" 0.600984
-cap "sens_amp_1/net2" "sens_amp_4/V_IN" 0.198412
-cap "sens_amp_3/net2" "sens_amp_5/V_IN" 0.312473
-cap "sens_amp_7/REF" "sens_amp_3/OUT" 0.136872
-cap "sens_amp_5/OUT" "sens_amp_1/OUT" 1.79299
-cap "sens_amp_5/GN" "sens_amp_7/GND" -2.94253
-cap "sens_amp_3/net1" "sens_amp_1/V_IN" 0.515057
-cap "sens_amp_7/OUT" "sens_amp_4/GN" 4.13327
-cap "sens_amp_2/net1" "sens_amp_7/GN" 0.176633
-cap "sens_amp_4/net2" "sens_amp_2/GN" 0.354763
-cap "sens_amp_4/net1" "sens_amp_0/OUT" 1.13371
-cap "sens_amp_7/VDD" "sens_amp_4/net1" 25.8252
-cap "sens_amp_7/REF" "sens_amp_3/V_IN" 2.5082
-cap "sens_amp_5/net2" "sens_amp_2/GN" 0.225634
-cap "sens_amp_4/V_IN" "sens_amp_6/net1" 6.19604
-cap "sens_amp_7/V_IN" "sens_amp_7/GN" -3.99463
-cap "sens_amp_2/V_IN" "sens_amp_6/V_IN" 0.0232572
-cap "sens_amp_7/V_IN" "sens_amp_3/GN" 0.0593834
-cap "sens_amp_7/net2" "sens_amp_2/net1" 0.0101423
-cap "sens_amp_3/net1" "sens_amp_0/net1" 1.05921
-cap "sens_amp_1/GN" "sens_amp_3/V_IN" 1.62595
-cap "sens_amp_7/REF" "sens_amp_3/net2" 0.397797
-cap "sens_amp_4/V_IN" "sens_amp_5/net1" 7.26132
-cap "sens_amp_2/net1" "sens_amp_5/OUT" 4.19711
-cap "sens_amp_7/OUT" "sens_amp_6/V_IN" 26.048
-cap "sens_amp_7/V_IN" "sens_amp_5/OUT" 6.3986
-cap "sens_amp_7/GND" "sens_amp_4/GN" -2.45542
-cap "sens_amp_6/GN" "sens_amp_4/OUT" 6.40448
-cap "sens_amp_4/net2" "sens_amp_1/V_IN" 0.115471
-cap "sens_amp_5/net2" "sens_amp_1/V_IN" 0.0600723
-cap "sens_amp_6/net2" "sens_amp_2/GN" 0.0715974
-cap "sens_amp_4/net2" "sens_amp_0/net1" 0.15249
-cap "sens_amp_7/VDD" "sens_amp_2/V_IN" 0.435057
-cap "sens_amp_2/net2" "sens_amp_4/OUT" 1.2828
-cap "sens_amp_4/V_IN" "sens_amp_2/OUT" 4.34606
-cap "sens_amp_3/V_IN" "sens_amp_1/OUT" 4.34302
-cap "sens_amp_5/net2" "sens_amp_0/net1" 0.0101423
-cap "sens_amp_4/V_IN" "sens_amp_7/GN" 3.62635
-cap "sens_amp_4/V_IN" "sens_amp_3/GN" 2.21149
-cap "sens_amp_6/V_IN" "sens_amp_7/GND" 84.8169
-cap "sens_amp_7/VDD" "sens_amp_7/OUT" 6.10446
-cap "sens_amp_7/net2" "sens_amp_4/V_IN" 0.907777
-cap "sens_amp_7/V_IN" "sens_amp_3/OUT" 1.14369
-cap "sens_amp_6/OUT" "sens_amp_2/GN" 0.671754
-cap "sens_amp_4/V_IN" "sens_amp_5/OUT" 26.048
-cap "sens_amp_4/OUT" "sens_amp_5/V_IN" 7.85568
-cap "sens_amp_6/net2" "sens_amp_1/V_IN" 0.00146339
-cap "sens_amp_5/GN" "sens_amp_4/GN" 4.24571
-cap "sens_amp_3/V_IN" "sens_amp_2/net1" 4.34664
-cap "sens_amp_0/OUT" "sens_amp_7/GND" 0.465385
-cap "sens_amp_7/V_IN" "sens_amp_3/V_IN" 0.112557
-cap "sens_amp_7/VDD" "sens_amp_7/GND" 3.19744e-14
-cap "sens_amp_6/OUT" "sens_amp_1/V_IN" 0.0620459
-cap "sens_amp_3/net2" "sens_amp_7/V_IN" 0.0624477
-cap "sens_amp_0/net2" "sens_amp_4/V_IN" 0.0624477
-cap "sens_amp_6/V_IN" "sens_amp_5/GN" 3.35462
-cap "sens_amp_7/REF" "sens_amp_4/OUT" 1.05825
-cap "sens_amp_4/V_IN" "sens_amp_3/OUT" 5.50813
-cap "sens_amp_0/V_IN" "sens_amp_7/REF" 0.021909
-cap "sens_amp_1/GN" "sens_amp_4/OUT" 2.31327
-cap "sens_amp_4/net1" "sens_amp_3/net1" 12.1742
-cap "sens_amp_0/OUT" "sens_amp_5/GN" 0.188179
-cap "sens_amp_4/V_IN" "sens_amp_3/V_IN" 118.461
-cap "sens_amp_6/net1" "sens_amp_2/GN" 0.143218
-cap "sens_amp_6/V_IN" "sens_amp_4/GN" 2.51632
-cap "sens_amp_7/VDD" "sens_amp_5/GN" 13.355
-cap "sens_amp_3/net2" "sens_amp_4/V_IN" 0.392042
-cap "sens_amp_5/net1" "sens_amp_2/GN" 0.875516
-cap "sens_amp_4/net1" "sens_amp_4/net2" -0.254835
-cap "sens_amp_4/OUT" "sens_amp_1/OUT" 3.75587
-cap "sens_amp_3/net1" "sens_amp_2/V_IN" 0.615676
-cap "sens_amp_4/net1" "sens_amp_5/net2" 1.13968
-cap "sens_amp_0/OUT" "sens_amp_4/GN" 0.809423
-cap "sens_amp_1/V_IN" "sens_amp_6/net1" 0.00387258
-cap "sens_amp_7/VDD" "sens_amp_4/GN" 15.1233
-cap "sens_amp_1/V_IN" "sens_amp_5/net1" 0.356562
-cap "sens_amp_3/net1" "sens_amp_7/OUT" 2.65649
-cap "sens_amp_2/net1" "sens_amp_4/OUT" 5.8596
-cap "sens_amp_7/V_IN" "sens_amp_4/OUT" 4.23519
-cap "sens_amp_0/net1" "sens_amp_5/net1" 0.00622933
-cap "sens_amp_4/net1" "sens_amp_7/net1" 3.25009
-cap "sens_amp_2/net2" "sens_amp_6/GN" 0.271701
-cap "sens_amp_4/net2" "sens_amp_2/V_IN" 0.158122
-cap "sens_amp_7/VDD" "sens_amp_6/V_IN" -8.8348
-cap "sens_amp_5/net2" "sens_amp_2/V_IN" 0.115471
-cap "sens_amp_4/net1" "sens_amp_6/net2" 0.998443
-cap "sens_amp_5/OUT" "sens_amp_2/GN" 2.31327
-cap "sens_amp_3/net1" "sens_amp_7/GND" 9.58144
-cap "sens_amp_4/net2" "sens_amp_7/OUT" 0.924995
-cap "sens_amp_4/net1" "sens_amp_1/net1" 2.14149
-cap "sens_amp_5/net2" "sens_amp_7/OUT" 1.32783
-cap "sens_amp_4/net1" "sens_amp_6/OUT" 7.96676
-cap "sens_amp_6/GN" "sens_amp_5/V_IN" 5.00189
-cap "sens_amp_7/VDD" "sens_amp_0/OUT" 0.519839
-cap "sens_amp_1/V_IN" "sens_amp_5/OUT" 0.90419
-cap "sens_amp_7/net1" "sens_amp_2/V_IN" 0.00387258
-cap "sens_amp_4/V_IN" "sens_amp_4/OUT" -21.2517
-cap "sens_amp_6/net2" "sens_amp_2/V_IN" 0.0600723
-cap "sens_amp_4/net2" "sens_amp_7/GND" 2.09291
-cap "sens_amp_2/net2" "sens_amp_5/V_IN" 0.198412
-cap "sens_amp_0/V_IN" "sens_amp_4/V_IN" 0.0232572
-cap "sens_amp_5/OUT" "sens_amp_0/net1" 0.0967716
-cap "sens_amp_7/net1" "sens_amp_7/OUT" -2.20244
-cap "sens_amp_5/net2" "sens_amp_7/GND" 1.84035
-cap "sens_amp_3/net1" "sens_amp_5/GN" 2.52985
-cap "sens_amp_0/GN" "sens_amp_4/net1" 0.143218
-cap "sens_amp_6/net2" "sens_amp_7/OUT" 1.58409
-cap "sens_amp_7/REF" "sens_amp_6/GN" 1.61563
-cap "sens_amp_6/OUT" "sens_amp_2/V_IN" 0.90419
-cap "sens_amp_3/V_IN" "sens_amp_2/GN" 2.1821
-cap "sens_amp_1/net2" "sens_amp_4/net1" 0.719464
-cap "sens_amp_7/REF" "sens_amp_2/net2" 0.254891
-cap "sens_amp_6/OUT" "sens_amp_7/OUT" 213.708
-cap "sens_amp_7/net1" "sens_amp_7/GND" 4.25782
-cap "sens_amp_4/net2" "sens_amp_5/GN" 6.20483
-cap "sens_amp_3/net1" "sens_amp_4/GN" 966.192
-cap "sens_amp_6/net2" "sens_amp_7/GND" 1.24037
-cap "sens_amp_3/V_IN" "sens_amp_1/V_IN" 0.0857591
-cap "sens_amp_4/net1" "sens_amp_6/net1" 4.76332
-cap "sens_amp_1/net1" "sens_amp_7/GND" 2.37386
-cap "sens_amp_7/REF" "sens_amp_5/V_IN" 3.42651
-cap "sens_amp_3/V_IN" "sens_amp_0/net1" 2.31794
-cap "sens_amp_4/net1" "sens_amp_5/net1" 18.8714
-cap "sens_amp_6/GN" "sens_amp_1/OUT" 0.188179
-cap "sens_amp_6/OUT" "sens_amp_7/GND" 41.6426
-cap "sens_amp_1/GN" "sens_amp_5/V_IN" 0.0593834
-cap "sens_amp_3/net1" "sens_amp_6/V_IN" 2.67052
-cap "sens_amp_7/net1" "sens_amp_5/GN" 4.35496
-cap "sens_amp_5/net2" "sens_amp_4/GN" 1.82263
-cap "sens_amp_2/V_IN" "sens_amp_6/net1" 0.356562
-cap "sens_amp_4/net1" "sens_amp_2/OUT" 4.2156
-cap "sens_amp_6/net2" "sens_amp_5/GN" 1.82263
-cap "sens_amp_6/GN" "sens_amp_2/net1" 0.752366
-cap "sens_amp_4/net1" "sens_amp_7/GN" 2.11581
-cap "sens_amp_0/GN" "sens_amp_7/GND" 0.352975
-cap "sens_amp_4/net1" "sens_amp_3/GN" 1.98
-cap "sens_amp_1/net1" "sens_amp_5/GN" 0.752366
-cap "sens_amp_6/GN" "sens_amp_7/V_IN" 3.35462
-cap "sens_amp_3/net1" "sens_amp_0/OUT" 2.30998
-cap "sens_amp_2/V_IN" "sens_amp_5/net1" 0.789632
-cap "sens_amp_7/OUT" "sens_amp_6/net1" 9.35341
-cap "sens_amp_7/net2" "sens_amp_4/net1" 0.746991
-cap "sens_amp_4/net2" "sens_amp_6/V_IN" 0.480188
-cap "sens_amp_1/net2" "sens_amp_7/GND" 0.889417
cap "sens_amp_1/OUT" "sens_amp_5/V_IN" 1.10273
-cap "sens_amp_7/VDD" "sens_amp_3/net1" 21.976
-cap "sens_amp_1/GN" "sens_amp_7/REF" 0.29299
-cap "sens_amp_6/OUT" "sens_amp_5/GN" 8.68828
-cap "sens_amp_4/net1" "sens_amp_5/OUT" 9.35341
-cap "sens_amp_7/net1" "sens_amp_4/GN" 2.60188
-cap "sens_amp_5/net2" "sens_amp_6/V_IN" 0.598319
-cap "sens_amp_7/OUT" "sens_amp_5/net1" 7.96676
-cap "sens_amp_6/net2" "sens_amp_4/GN" 1.45914
-cap "sens_amp_4/OUT" "sens_amp_2/GN" 3.69942
-cap "sens_amp_1/net1" "sens_amp_4/GN" 1.24505
-cap "sens_amp_7/GND" "sens_amp_6/net1" 6.6513
-cap "sens_amp_2/V_IN" "sens_amp_7/GN" 0.0892897
-cap "sens_amp_4/net2" "sens_amp_0/OUT" 0.012672
-cap "sens_amp_2/net1" "sens_amp_5/V_IN" 2.32474
-cap "sens_amp_7/net1" "sens_amp_6/V_IN" 7.26132
-cap "sens_amp_6/OUT" "sens_amp_4/GN" 6.78529
-cap "sens_amp_7/net2" "sens_amp_2/V_IN" 0.00146339
-cap "sens_amp_0/net2" "sens_amp_4/net1" 0.247059
-cap "sens_amp_7/REF" "sens_amp_1/OUT" 0.0461049
-cap "sens_amp_7/V_IN" "sens_amp_5/V_IN" 0.368428
-cap "sens_amp_7/OUT" "sens_amp_2/OUT" 0.0016529
-cap "sens_amp_6/GN" "sens_amp_4/V_IN" 4.56615
-cap "sens_amp_7/GND" "sens_amp_5/net1" 8.42679
-cap "sens_amp_1/net2" "sens_amp_5/GN" 0.271701
-cap "sens_amp_4/net1" "sens_amp_3/OUT" 6.68468
-cap "sens_amp_6/net2" "sens_amp_6/V_IN" -0.258739
-cap "sens_amp_7/OUT" "sens_amp_3/GN" 0.671754
-cap "sens_amp_7/OUT" "sens_amp_7/GN" -12.7578
-cap "sens_amp_4/OUT" "sens_amp_1/V_IN" 1.66661
-cap "sens_amp_2/V_IN" "sens_amp_5/OUT" 1.66661
-cap "sens_amp_7/net2" "sens_amp_7/OUT" -0.698277
-cap "sens_amp_2/net2" "sens_amp_4/V_IN" 0.312473
-cap "sens_amp_4/OUT" "sens_amp_0/net1" 2.07132
-cap "sens_amp_6/OUT" "sens_amp_6/V_IN" -21.2517
-cap "sens_amp_7/OUT" "sens_amp_5/OUT" 10.533
-cap "sens_amp_4/net1" "sens_amp_3/V_IN" 7.12349
-cap "sens_amp_0/GN" "sens_amp_4/GN" 0.322947
-cap "sens_amp_2/OUT" "sens_amp_7/GND" 2.46243
-cap "sens_amp_7/VDD" "sens_amp_7/net1" 17.2238
+cap "sens_amp_4/net1" "sens_amp_7/GND" 9.38829
+cap "sens_amp_6/net2" "sens_amp_4/net1" 0.998443
+cap "sens_amp_4/net1" "sens_amp_3/net1" 12.1742
+cap "sens_amp_1/V_IN" "sens_amp_7/REF" 0.0529436
+cap "sens_amp_7/net2" "sens_amp_5/net1" 0.998443
cap "sens_amp_7/REF" "sens_amp_2/net1" 0.296252
-cap "sens_amp_5/GN" "sens_amp_6/net1" 5.62731
-cap "sens_amp_7/REF" "sens_amp_7/V_IN" 0.240912
-cap "sens_amp_7/GND" "sens_amp_7/GN" -6.41985
-cap "sens_amp_3/GN" "sens_amp_7/GND" 5.34576
-cap "sens_amp_1/net2" "sens_amp_4/GN" 0.477727
-cap "sens_amp_4/net1" "sens_amp_3/net2" 1.38263
-cap "sens_amp_4/V_IN" "sens_amp_5/V_IN" 118.504
-cap "sens_amp_7/net2" "sens_amp_7/GND" 0.35921
-cap "sens_amp_5/GN" "sens_amp_5/net1" -0.592745
-cap "sens_amp_7/VDD" "sens_amp_1/net1" 1.73071
-cap "sens_amp_5/OUT" "sens_amp_7/GND" 45.3541
-cap "sens_amp_7/VDD" "sens_amp_6/OUT" 129.325
-cap "sens_amp_3/OUT" "sens_amp_7/OUT" 2.07698
-cap "sens_amp_4/GN" "sens_amp_6/net1" 4.35496
-cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 59.1383
-cap "sens_amp_2/OUT" "sens_amp_5/GN" 1.34132
-cap "sens_amp_0/net2" "sens_amp_7/GND" 0.277911
-cap "sens_amp_5/GN" "sens_amp_7/GN" 2.70568
-cap "sens_amp_3/GN" "sens_amp_5/GN" 0.965846
-cap "sens_amp_4/GN" "sens_amp_5/net1" 5.62731
-cap "sens_amp_7/REF" "sens_amp_4/V_IN" 3.65582
-cap "sens_amp_3/V_IN" "sens_amp_7/OUT" 2.93221
-cap "sens_amp_7/net2" "sens_amp_5/GN" 1.45914
-cap "sens_amp_3/OUT" "sens_amp_7/GND" 19.3292
-cap "sens_amp_6/V_IN" "sens_amp_6/net1" -7.91599
-cap "sens_amp_1/GN" "sens_amp_4/V_IN" 0.903772
-cap "sens_amp_7/VDD" "sens_amp_0/GN" 0.110972
-cap "sens_amp_3/net2" "sens_amp_7/OUT" 0.406227
-cap "sens_amp_5/OUT" "sens_amp_5/GN" -12.7773
-cap "sens_amp_2/OUT" "sens_amp_4/GN" 1.72514
-cap "sens_amp_6/V_IN" "sens_amp_5/net1" 5.02073
-cap "sens_amp_4/GN" "sens_amp_7/GN" 1.90401
-cap "sens_amp_3/GN" "sens_amp_4/GN" 1.66155
-cap "sens_amp_4/net2" "sens_amp_3/net1" 1.13968
-cap "sens_amp_3/V_IN" "sens_amp_7/GND" 88.8521
-cap "sens_amp_7/net2" "sens_amp_4/GN" 0.934585
-cap "sens_amp_5/net2" "sens_amp_3/net1" 0.998443
-cap "sens_amp_3/net2" "sens_amp_7/GND" 2.81383
-cap "sens_amp_6/GN" "sens_amp_2/GN" 0.322947
-cap "sens_amp_0/net2" "sens_amp_5/GN" 0.0356827
-cap "sens_amp_7/VDD" "sens_amp_6/net1" 18.2509
-cap "sens_amp_4/V_IN" "sens_amp_1/OUT" 2.88355
-cap "sens_amp_5/OUT" "sens_amp_4/GN" 8.68828
-cap "sens_amp_4/net1" "sens_amp_4/OUT" -16.8555
-cap "sens_amp_2/OUT" "sens_amp_6/V_IN" 1.10273
-cap "sens_amp_0/OUT" "sens_amp_5/net1" 0.00188699
-cap "sens_amp_0/V_IN" "sens_amp_4/net1" 0.356562
-cap "sens_amp_3/OUT" "sens_amp_5/GN" 2.15432
-cap "sens_amp_3/GN" "sens_amp_6/V_IN" 0.903772
-cap "sens_amp_6/V_IN" "sens_amp_7/GN" 5.00189
-cap "sens_amp_7/VDD" "sens_amp_5/net1" 23.2854
-cap "sens_amp_4/net2" "sens_amp_5/net2" 0.545016
-cap "sens_amp_7/net1" "sens_amp_3/net1" 1.35608
-cap "sens_amp_7/net2" "sens_amp_6/V_IN" 1.40293
-cap "sens_amp_6/GN" "sens_amp_1/V_IN" 0.0892897
-cap "sens_amp_4/V_IN" "sens_amp_2/net1" 3.53645
-cap "sens_amp_3/V_IN" "sens_amp_5/GN" 4.1916
-cap "sens_amp_0/net2" "sens_amp_4/GN" 0.271701
-cap "sens_amp_6/net2" "sens_amp_3/net1" 0.746991
-cap "sens_amp_5/OUT" "sens_amp_6/V_IN" 7.85568
-cap "sens_amp_7/V_IN" "sens_amp_4/V_IN" 0.259262
-cap "sens_amp_1/net1" "sens_amp_3/net1" 1.69551
-cap "sens_amp_5/V_IN" "sens_amp_2/GN" 0.903772
-cap "sens_amp_3/OUT" "sens_amp_4/GN" 2.39223
-cap "sens_amp_7/VDD" "sens_amp_2/OUT" 2.2402
-cap "sens_amp_3/net2" "sens_amp_5/GN" 0.631017
-cap "sens_amp_2/V_IN" "sens_amp_4/OUT" 2.24505
-cap "sens_amp_7/VDD" "sens_amp_3/GN" 1.22701
-cap "sens_amp_7/VDD" "sens_amp_7/GN" -0.357829
-cap "sens_amp_3/net1" "sens_amp_6/OUT" 5.34803
-cap "sens_amp_4/net2" "sens_amp_7/net1" 0.939992
-cap "sens_amp_0/OUT" "sens_amp_5/OUT" 0.0016529
-cap "sens_amp_5/net2" "sens_amp_7/net1" 1.45683
-cap "sens_amp_4/net2" "sens_amp_6/net2" 0.456915
-cap "sens_amp_4/OUT" "sens_amp_7/OUT" 7.42466
-cap "sens_amp_3/V_IN" "sens_amp_4/GN" 4.5832
-cap "sens_amp_7/VDD" "sens_amp_5/OUT" 134.984
-cap "sens_amp_5/net2" "sens_amp_6/net2" 0.545016
-cap "sens_amp_3/OUT" "sens_amp_6/V_IN" 2.98342
-cap "sens_amp_4/net2" "sens_amp_1/net1" 0.278332
-cap "sens_amp_1/V_IN" "sens_amp_5/V_IN" 0.0232572
-cap "sens_amp_3/net2" "sens_amp_4/GN" 3.18524
-cap "sens_amp_5/net2" "sens_amp_1/net1" 0.15249
-cap "sens_amp_7/REF" "sens_amp_2/GN" 0.613735
-cap "sens_amp_4/net2" "sens_amp_6/OUT" 1.32783
-cap "sens_amp_5/net2" "sens_amp_6/OUT" 1.58409
-cap "sens_amp_3/V_IN" "sens_amp_6/V_IN" 0.236143
-cap "sens_amp_4/OUT" "sens_amp_7/GND" 47.6555
-cap "sens_amp_0/V_IN" "sens_amp_7/GND" 0.163339
-cap "sens_amp_6/net2" "sens_amp_7/net1" 1.81286
-cap "sens_amp_3/net2" "sens_amp_6/V_IN" 0.198412
-cap "sens_amp_7/VDD" "sens_amp_3/OUT" 126.914
-cap "sens_amp_7/REF" "sens_amp_1/V_IN" 0.0529436
-cap "sens_amp_7/SA_IREF" "sens_amp_7/GND" -1.77636e-15
-cap "sens_amp_0/GN" "sens_amp_4/net2" 0.0715974
-cap "sens_amp_6/net2" "sens_amp_1/net1" 0.0101423
-cap "sens_amp_3/net1" "sens_amp_6/net1" 3.18068
-cap "sens_amp_7/net1" "sens_amp_6/OUT" 12.2505
-cap "sens_amp_3/V_IN" "sens_amp_0/OUT" 2.88152
-cap "sens_amp_1/net2" "sens_amp_4/net2" 0.159188
-cap "sens_amp_7/REF" "sens_amp_0/net1" 0.0678844
-cap "sens_amp_7/VDD" "sens_amp_3/V_IN" 4.4742
-cap "sens_amp_6/net2" "sens_amp_6/OUT" -0.720943
-cap "sens_amp_1/net2" "sens_amp_5/net2" 0.072346
-cap "sens_amp_3/net1" "sens_amp_5/net1" 4.65417
-cap "sens_amp_4/OUT" "sens_amp_5/GN" 7.17932
-cap "sens_amp_1/net1" "sens_amp_6/OUT" 0.0967716
-cap "sens_amp_0/V_IN" "sens_amp_5/GN" 0.0892897
-cap "sens_amp_4/net2" "sens_amp_6/net1" 1.45683
-cap "sens_amp_6/GN" "sens_amp_4/net1" 2.70338
-cap "sens_amp_5/net2" "sens_amp_6/net1" 1.81286
-cap "sens_amp_3/net1" "sens_amp_2/OUT" 4.25153
-cap "sens_amp_4/net2" "sens_amp_5/net1" 1.81286
-cap "sens_amp_3/net1" "sens_amp_7/GN" 1.21996
-cap "sens_amp_4/OUT" "sens_amp_4/GN" -12.7773
-cap "sens_amp_5/net2" "sens_amp_5/net1" -0.254835
-cap "sens_amp_2/net2" "sens_amp_4/net1" 1.11245
-cap "sens_amp_0/V_IN" "sens_amp_4/GN" 0.299423
-cap "sens_amp_7/net2" "sens_amp_3/net1" 0.413081
-cap "sens_amp_7/net1" "sens_amp_6/net1" 18.8714
-cap "sens_amp_3/net1" "sens_amp_5/OUT" 7.44921
-cap "sens_amp_6/GN" "sens_amp_2/V_IN" 0.299423
-cap "sens_amp_4/net2" "sens_amp_2/OUT" 0.0388518
-cap "sens_amp_6/net2" "sens_amp_6/net1" -0.254835
-cap "sens_amp_4/OUT" "sens_amp_6/V_IN" 6.3986
-cap "sens_amp_5/net2" "sens_amp_2/OUT" 0.0272668
-cap "sens_amp_4/net2" "sens_amp_7/GN" 0.837971
-cap "sens_amp_4/net2" "sens_amp_3/GN" 0.444731
-cap "sens_amp_4/net1" "sens_amp_5/V_IN" 5.02073
-cap "sens_amp_7/net1" "sens_amp_5/net1" 4.76332
-cap "sens_amp_5/net2" "sens_amp_7/GN" 1.1122
-cap "sens_amp_1/net1" "sens_amp_6/net1" 0.00622933
-cap "sens_amp_5/net2" "sens_amp_3/GN" 0.354763
-cap "sens_amp_7/net2" "sens_amp_4/net2" 0.318376
-cap "sens_amp_4/V_IN" "sens_amp_2/GN" 1.64863
-cap "sens_amp_6/net2" "sens_amp_5/net1" 1.13968
-cap "sens_amp_6/GN" "sens_amp_7/OUT" 8.68828
-cap "sens_amp_7/net2" "sens_amp_5/net2" 0.456915
-cap "sens_amp_6/OUT" "sens_amp_6/net1" -16.8555
-cap "sens_amp_4/net2" "sens_amp_5/OUT" 1.58409
-cap "sens_amp_1/net1" "sens_amp_5/net1" 0.822676
-cap "sens_amp_3/net1" "sens_amp_3/OUT" -2.45217
-cap "sens_amp_5/net2" "sens_amp_5/OUT" -0.720943
-cap "sens_amp_0/OUT" "sens_amp_4/OUT" 1.79299
-cap "sens_amp_7/net1" "sens_amp_2/OUT" 0.00188699
-cap "sens_amp_6/OUT" "sens_amp_5/net1" 9.35341
-cap "sens_amp_7/VDD" "sens_amp_4/OUT" 137.403
-cap "sens_amp_7/REF" "sens_amp_4/net1" 1.902
-cap "sens_amp_7/net1" "sens_amp_7/GN" -0.518508
-cap "sens_amp_6/net2" "sens_amp_2/OUT" 0.012672
-cap "sens_amp_7/net1" "sens_amp_3/GN" 0.143218
-cap "sens_amp_4/V_IN" "sens_amp_1/V_IN" 0.0592606
-cap "sens_amp_2/V_IN" "sens_amp_5/V_IN" 0.0592606
-cap "sens_amp_0/V_IN" "sens_amp_7/VDD" 0.113704
-cap "sens_amp_6/GN" "sens_amp_7/GND" -4.32715
-cap "sens_amp_6/net2" "sens_amp_7/GN" 6.20483
-cap "sens_amp_6/net2" "sens_amp_3/GN" 0.225634
-cap "sens_amp_0/net2" "sens_amp_4/net2" 0.072346
-cap "sens_amp_3/V_IN" "sens_amp_3/net1" -7.67405
-cap "sens_amp_1/GN" "sens_amp_4/net1" 0.875516
-cap "sens_amp_7/net2" "sens_amp_6/net2" 0.545016
-cap "sens_amp_7/net1" "sens_amp_5/OUT" 10.1381
-cap "sens_amp_4/V_IN" "sens_amp_0/net1" 0.856403
-cap "sens_amp_7/OUT" "sens_amp_5/V_IN" 7.72902
-cap "sens_amp_4/net2" "sens_amp_3/OUT" 0.0461479
-cap "sens_amp_6/OUT" "sens_amp_2/OUT" 1.79299
-cap "sens_amp_2/net2" "sens_amp_7/GND" 1.76702
-cap "sens_amp_6/net2" "sens_amp_5/OUT" 1.58576
-cap "sens_amp_5/net2" "sens_amp_3/OUT" 0.0388518
-cap "sens_amp_6/OUT" "sens_amp_7/GN" 7.17932
-cap "sens_amp_6/OUT" "sens_amp_3/GN" 2.31327
+cap "sens_amp_7/OUT" "sens_amp_6/net1" 9.35341
+cap "sens_amp_5/net2" "sens_amp_7/V_IN" 0.480188
cap "sens_amp_7/net2" "sens_amp_6/OUT" 1.58576
-cap "sens_amp_1/net2" "sens_amp_5/net1" 0.247059
-cap "sens_amp_1/net1" "sens_amp_5/OUT" 2.07132
-cap "sens_amp_7/REF" "sens_amp_2/V_IN" 0.0932648
-cap "sens_amp_4/net2" "sens_amp_3/V_IN" 1.26003
-cap "sens_amp_6/OUT" "sens_amp_5/OUT" 213.708
+cap "sens_amp_1/net1" "sens_amp_4/GN" 1.24505
+cap "sens_amp_0/OUT" "sens_amp_7/GND" 0.465385
+cap "sens_amp_3/V_IN" "sens_amp_7/REF" 2.5082
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+cap "sens_amp_0/OUT" "sens_amp_3/net1" 2.30998
+cap "sens_amp_4/net1" "sens_amp_2/V_IN" 1.13554
+cap "sens_amp_7/GN" "sens_amp_7/GND" -6.41985
+cap "sens_amp_7/GN" "sens_amp_6/net2" 6.20483
+cap "sens_amp_7/net2" "sens_amp_6/V_IN" 1.40293
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+cap "sens_amp_7/VDD" "sens_amp_5/OUT" 134.984
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+cap "sens_amp_7/VDD" "sens_amp_5/GN" 13.355
+cap "sens_amp_7/VDD" "sens_amp_7/net1" 17.2238
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cap "sens_amp_5/net2" "sens_amp_3/V_IN" 1.10054
-cap "sens_amp_4/net1" "sens_amp_1/OUT" 2.83091
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cap "sens_amp_6/GN" "sens_amp_5/GN" 4.24571
-cap "sens_amp_5/V_IN" "sens_amp_7/GND" 86.8194
-cap "sens_amp_4/net2" "sens_amp_3/net2" 0.272508
-cap "sens_amp_7/net1" "sens_amp_3/OUT" 1.62476
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cap "sens_amp_7/REF" "sens_amp_7/OUT" -0.111475
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+cap "sens_amp_7/VDD" "sens_amp_3/OUT" 126.914
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+cap "sens_amp_5/GN" "sens_amp_3/V_IN" 4.1916
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+cap "sens_amp_7/net1" "sens_amp_3/V_IN" 2.17648
+cap "sens_amp_3/GN" "sens_amp_7/GN" 0.322947
cap "sens_amp_3/net2" "sens_amp_5/net2" 0.228458
-cap "sens_amp_6/net2" "sens_amp_3/OUT" 0.0272668
-cap "sens_amp_6/net1" "sens_amp_5/net1" 18.8714
-cap "sens_amp_2/net2" "sens_amp_5/GN" 0.477727
-cap "sens_amp_2/V_IN" "sens_amp_3/OUT" 0.180419
-cap "sens_amp_0/V_IN" "sens_amp_1/GN" 6.00624
-cap "sens_amp_2/GN" "sens_amp_5/net1" 0.492096
-cap "sens_amp_2/GN" "sens_amp_5/V_IN" 0.156212
-cap "sens_amp_3/net1" "sens_amp_1/GN" 5.80095
-cap "sens_amp_4/GN" "sens_amp_1/GN" 1.28221
-cap "sens_amp_2/V_IN" "sens_amp_6/net1" 1.07733
-cap "sens_amp_0/V_IN" "sens_amp_1/V_IN" 158.444
-cap "sens_amp_5/GN" "sens_amp_3/GN" 0.637462
-cap "sens_amp_4/GN" "sens_amp_1/V_IN" 3.68128
-cap "sens_amp_0/V_IN" "sens_amp_5/OUT" 3.55618e-05
-cap "sens_amp_5/GN" "sens_amp_1/OUT" 0.0113544
-cap "sens_amp_0/OUT" "sens_amp_1/GN" 0.0809214
-cap "sens_amp_5/GN" "sens_amp_7/VDD" 4.73535
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-cap "sens_amp_2/V_IN" "sens_amp_7/net1" 0.0334798
-cap "sens_amp_2/OUT" "sens_amp_6/OUT" 0.0154908
-cap "sens_amp_2/GN" "sens_amp_7/VDD" 121.62
-cap "sens_amp_2/GN" "sens_amp_3/GN" 23.1843
-cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 79.2222
-cap "sens_amp_2/GN" "sens_amp_1/OUT" 0.0809214
-cap "sens_amp_0/V_IN" "sens_amp_5/GN" 0.205511
-cap "sens_amp_2/net1" "sens_amp_7/OUT" 4.96025e-06
-cap "sens_amp_3/net1" "sens_amp_5/GN" 0.159571
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-cap "sens_amp_7/V_IN" "sens_amp_3/GN" 0.020208
-cap "sens_amp_6/GN" "sens_amp_1/GN" 0.0446209
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-cap "sens_amp_2/OUT" "sens_amp_2/V_IN" -0.49522
-cap "sens_amp_6/GN" "sens_amp_1/V_IN" 0.205511
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-cap "sens_amp_0/V_IN" "sens_amp_2/GN" 5.24439
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-cap "sens_amp_0/GN" "sens_amp_1/GN" 23.1843
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-cap "sens_amp_3/net1" "sens_amp_7/V_IN" 0.0090059
-cap "sens_amp_1/GN" "sens_amp_0/net1" 73.589
-cap "sens_amp_0/GN" "sens_amp_1/V_IN" 5.61566
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-cap "sens_amp_2/GN" "sens_amp_0/net1" 6.18725
-cap "sens_amp_2/GN" "sens_amp_0/GN" 3.8567
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cap "sens_amp_2/net1" "sens_amp_5/GN" 3.96754
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cap "sens_amp_2/OUT" "sens_amp_3/GN" 0.0809214
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cap "sens_amp_4/GN" "sens_amp_3/GN" 10.0862
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cap "sens_amp_5/OUT" "sens_amp_1/V_IN" 0.0530216
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-cap "sens_amp_0/GN" "sens_amp_7/VDD" 114.351
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cap "sens_amp_2/GN" "sens_amp_1/GN" 23.1843
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cap "sens_amp_4/net1" "sens_amp_1/OUT" 0.0525719
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-cap "sens_amp_2/net1" "sens_amp_7/VDD" 71.2959
-cap "sens_amp_2/net1" "sens_amp_3/GN" 73.589
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cap "sens_amp_4/net1" "sens_amp_0/net1" 0.706897
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cap "sens_amp_2/GN" "sens_amp_6/V_IN" 0.0496114
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cap "sens_amp_7/VDD" "sens_amp_1/V_IN" 8.41444
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cap "sens_amp_2/GN" "sens_amp_3/V_IN" 0.307818
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cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 79.2222
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cap "sens_amp_1/GN" "sens_amp_4/OUT" 0.00863073
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cap "sens_amp_6/GN" "sens_amp_2/V_IN" 0.125242
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cap "sens_amp_7/VDD" "sens_amp_2/GN" 5.77095
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cap "sens_amp_7/VDD" "sens_amp_1/V_IN" 0.539597
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cap "sens_amp_7/VDD" "sens_amp_4/net1" 73.0179
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+cap "sens_amp_4/net1" "sens_amp_2/V_IN" 0.678645
+cap "sens_amp_5/V_IN" "sens_amp_7/GN" 5.24439
+cap "sens_amp_5/net1" "sens_amp_7/GN" 6.18725
+cap "sens_amp_7/VDD" "sens_amp_1/OUT" 0.0665022
+cap "sens_amp_4/net1" "sens_amp_0/net1" 0.691701
+cap "sens_amp_4/V_IN" "sens_amp_7/VDD" 18.8812
+cap "sens_amp_4/V_IN" "sens_amp_1/OUT" 0.0910755
+cap "sens_amp_2/OUT" "sens_amp_7/VDD" 0.11759
+cap "sens_amp_3/OUT" "sens_amp_5/OUT" 0.085889
+cap "sens_amp_7/VDD" "sens_amp_3/net1" 62.7109
+cap "sens_amp_7/VDD" "sens_amp_2/V_IN" 0.916176
+cap "sens_amp_6/net1" "sens_amp_2/GN" 1.36082
+cap "sens_amp_3/net1" "sens_amp_1/OUT" 0.132932
+cap "sens_amp_5/OUT" "sens_amp_6/GN" 0.0809214
+cap "sens_amp_5/net1" "sens_amp_4/OUT" 0.246955
+cap "sens_amp_1/GN" "sens_amp_3/V_IN" 4.2432
+cap "sens_amp_4/GN" "sens_amp_5/OUT" 0.172045
+cap "sens_amp_5/V_IN" "sens_amp_4/OUT" 0.176152
+cap "sens_amp_7/VDD" "sens_amp_0/net1" 0.787297
+cap "sens_amp_5/GN" "sens_amp_1/V_IN" 0.125242
+cap "sens_amp_6/V_IN" "sens_amp_2/GN" 0.877981
+cap "sens_amp_2/OUT" "sens_amp_4/V_IN" 0.136243
+cap "sens_amp_7/net1" "sens_amp_5/OUT" 0.205488
+cap "sens_amp_4/V_IN" "sens_amp_3/net1" 3.5653
+cap "sens_amp_4/GN" "sens_amp_0/V_IN" 0.125242
+cap "sens_amp_0/OUT" "sens_amp_5/GN" 0.00598632
+cap "sens_amp_7/V_IN" "sens_amp_7/OUT" -0.423762
+cap "sens_amp_7/V_IN" "sens_amp_4/net1" 2.20854
+cap "sens_amp_7/GN" "sens_amp_2/GN" 0.0511255
+cap "sens_amp_2/OUT" "sens_amp_3/net1" 0.162424
+cap "sens_amp_7/OUT" "sens_amp_5/GN" 0.131704
+cap "sens_amp_6/OUT" "sens_amp_7/OUT" 0.102198
+cap "sens_amp_6/OUT" "sens_amp_4/net1" 0.102612
+cap "sens_amp_4/V_IN" "sens_amp_0/net1" 0.688107
+cap "sens_amp_3/net1" "sens_amp_2/V_IN" 0.021889
+cap "sens_amp_3/GN" "sens_amp_7/OUT" 0.00151284
+cap "sens_amp_4/net1" "sens_amp_5/GN" 73.589
+cap "sens_amp_3/GN" "sens_amp_4/net1" 6.60126
+cap "sens_amp_3/net1" "sens_amp_0/net1" 0.0428603
+cap "sens_amp_7/V_IN" "sens_amp_7/VDD" -30.0581
+cap "sens_amp_5/V_IN" "sens_amp_5/OUT" -0.49522
+cap "sens_amp_4/OUT" "sens_amp_2/GN" 0.0147959
+cap "sens_amp_6/OUT" "sens_amp_7/VDD" 6.77573
+cap "sens_amp_6/V_IN" "sens_amp_6/net1" -9.38634
+cap "sens_amp_5/net1" "sens_amp_5/OUT" -0.133755
+cap "sens_amp_6/net1" "sens_amp_7/GN" 73.589
+cap "sens_amp_5/net1" "sens_amp_0/V_IN" 0.00376241
+cap "sens_amp_7/VDD" "sens_amp_5/GN" 121.393
+cap "sens_amp_1/GN" "sens_amp_6/GN" 0.0511255
+cap "sens_amp_3/GN" "sens_amp_7/VDD" 104.978
+cap "sens_amp_1/OUT" "sens_amp_5/GN" 0.023745
+cap "sens_amp_4/GN" "sens_amp_1/GN" 1.43151
+cap "sens_amp_3/V_IN" "sens_amp_1/net1" 2.69126
+cap "sens_amp_4/V_IN" "sens_amp_6/OUT" 0.154277
+cap "sens_amp_6/V_IN" "sens_amp_7/GN" 6.00624
+cap "sens_amp_7/V_IN" "sens_amp_3/net1" 0.754076
+cap "sens_amp_4/V_IN" "sens_amp_5/GN" 6.00624
+cap "sens_amp_2/OUT" "sens_amp_5/GN" 0.0388825
+cap "sens_amp_6/OUT" "sens_amp_3/net1" 0.0710991
+cap "sens_amp_2/OUT" "sens_amp_6/OUT" 0.0121845
+cap "sens_amp_3/GN" "sens_amp_4/V_IN" 5.42685
+cap "sens_amp_3/net1" "sens_amp_5/GN" 2.19856
+cap "sens_amp_6/OUT" "sens_amp_2/V_IN" 0.00264547
+cap "sens_amp_6/net1" "sens_amp_4/OUT" 0.205488
+cap "sens_amp_5/GN" "sens_amp_2/V_IN" 0.222346
+cap "sens_amp_5/OUT" "sens_amp_2/GN" 0.00863073
+cap "sens_amp_5/GN" "sens_amp_0/net1" 0.0160443
+cap "sens_amp_6/V_IN" "sens_amp_4/OUT" 0.144302
+cap "sens_amp_1/GN" "sens_amp_5/net1" 1.36082
+cap "sens_amp_0/GN" "sens_amp_4/net1" 1.36082
+cap "sens_amp_1/GN" "sens_amp_5/V_IN" 0.877981
+cap "sens_amp_4/OUT" "sens_amp_7/GN" 0.05728
+cap "sens_amp_2/net1" "sens_amp_4/net1" 2.15847
+cap "sens_amp_6/GN" "sens_amp_1/net1" 0.0160443
+cap "sens_amp_3/V_IN" "sens_amp_0/OUT" 0.0910755
+cap "sens_amp_4/GN" "sens_amp_1/net1" 0.48629
+cap "sens_amp_3/V_IN" "sens_amp_7/OUT" 0.0556671
+cap "sens_amp_6/net1" "sens_amp_5/OUT" 0.246955
+cap "sens_amp_0/GN" "sens_amp_7/VDD" 1.14414
+cap "sens_amp_7/V_IN" "sens_amp_6/OUT" 0.176152
+cap "sens_amp_2/net1" "sens_amp_7/VDD" 3.42659
+cap "sens_amp_3/V_IN" "sens_amp_4/net1" 4.21657
+cap "sens_amp_7/V_IN" "sens_amp_5/GN" 4.48877
+cap "sens_amp_6/OUT" "sens_amp_5/GN" 0.172045
+cap "sens_amp_3/GN" "sens_amp_7/V_IN" 0.907384
+cap "sens_amp_3/GN" "sens_amp_6/OUT" 0.00863073
+cap "sens_amp_2/net1" "sens_amp_4/V_IN" 2.69126
+cap "sens_amp_0/GN" "sens_amp_4/V_IN" 0.877981
+cap "sens_amp_6/V_IN" "sens_amp_5/OUT" 0.176152
+cap "sens_amp_5/OUT" "sens_amp_7/GN" 0.0731374
+cap "sens_amp_3/GN" "sens_amp_5/GN" 3.21924
+cap "sens_amp_6/GN" "sens_amp_1/V_IN" 0.0211219
+cap "sens_amp_2/net1" "sens_amp_3/net1" 0.087025
+cap "sens_amp_3/V_IN" "sens_amp_7/VDD" 25.4379
+cap "sens_amp_5/V_IN" "sens_amp_1/net1" 0.688107
+cap "sens_amp_3/V_IN" "sens_amp_1/OUT" 0.136243
+cap "sens_amp_7/OUT" "sens_amp_3/OUT" 0.0276753
+cap "sens_amp_5/net1" "sens_amp_1/net1" 0.691701
+cap "sens_amp_4/GN" "sens_amp_1/V_IN" 0.222346
+cap "sens_amp_4/net1" "sens_amp_3/OUT" 0.246955
+cap "sens_amp_3/V_IN" "sens_amp_4/V_IN" 158.444
+cap "sens_amp_4/GN" "sens_amp_0/OUT" 0.023745
+cap "sens_amp_7/OUT" "sens_amp_6/GN" 0.172045
+cap "sens_amp_4/GN" "sens_amp_7/OUT" 0.0768244
+cap "sens_amp_4/net1" "sens_amp_6/GN" 6.18725
+cap "sens_amp_3/V_IN" "sens_amp_2/OUT" 0.166371
+cap "sens_amp_4/OUT" "sens_amp_5/OUT" 0.102198
+cap "sens_amp_3/V_IN" "sens_amp_3/net1" -7.67655
+cap "sens_amp_1/GN" "sens_amp_6/net1" 0.00362768
+cap "sens_amp_4/GN" "sens_amp_4/net1" -13.5459
+cap "sens_amp_3/V_IN" "sens_amp_2/V_IN" 79.2222
+cap "sens_amp_4/OUT" "sens_amp_0/V_IN" 0.00264547
+cap "sens_amp_7/net1" "sens_amp_4/net1" 3.01905
+cap "sens_amp_7/VDD" "sens_amp_3/OUT" 6.80692
+cap "sens_amp_3/V_IN" "sens_amp_0/net1" 1.78839
+cap "sens_amp_5/net1" "sens_amp_1/V_IN" 0.243837
+cap "sens_amp_7/VDD" "sens_amp_6/GN" 112.857
+cap "sens_amp_1/OUT" "sens_amp_6/GN" 0.00598632
+cap "sens_amp_4/GN" "sens_amp_7/VDD" 125.612
+cap "sens_amp_2/net1" "sens_amp_6/OUT" 0.0153565
+cap "sens_amp_4/V_IN" "sens_amp_3/OUT" 0.176152
+cap "sens_amp_7/net1" "sens_amp_7/VDD" -1.51851
+cap "sens_amp_0/GN" "sens_amp_5/GN" 0.0511255
+cap "sens_amp_4/GN" "sens_amp_1/OUT" 0.0388825
+cap "sens_amp_5/V_IN" "sens_amp_7/OUT" 0.154277
+cap "sens_amp_5/net1" "sens_amp_7/OUT" 0.102612
+cap "sens_amp_3/OUT" "sens_amp_3/net1" -0.133755
+cap "sens_amp_4/V_IN" "sens_amp_6/GN" 5.24439
+cap "sens_amp_2/net1" "sens_amp_5/GN" 0.48629
+cap "sens_amp_5/V_IN" "sens_amp_4/net1" 4.05548
+cap "sens_amp_5/net1" "sens_amp_4/net1" 77.1975
cap "sens_amp_7/net1" "sens_amp_7/V_IN" 0.00192884
+cap "sens_amp_7/net1" "sens_amp_7/VDD" -0.00045064
+cap "sens_amp_7/VDD" "sens_amp_7/V_IN" 1.39555
merge "sens_amp_1/OUT" "OUTx6x" -882.653 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "sens_amp_0/GND" "GND" -3412.93 0 0 0 0 0 0 0 0 0 0 0 -1120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1120 -6000 -3260 0 0 0 0 0 0 0 0 0 0
merge "GND" "sens_amp_1/GND"
diff --git a/mag/adc.ext b/mag/adc.ext
index d4171fb..6af68e1 100644
--- a/mag/adc.ext
+++ b/mag/adc.ext
@@ -62,331 +62,331 @@
node "a_1000_n1450#" 1641 491.836 1000 -1450 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123000 2580 0 0 32662 1466 0 0 0 0 0 0 0 0 0 0 0 0
node "VDD" 7379 2707.25 810 -770 m1 0 0 0 0 612750 3710 0 0 20000 600 58000 2180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158400 4360 165600 3680 0 0 0 0 0 0 0 0 0 0
substrate "GND" 0 0 730 -1660 m1 0 0 0 0 0 0 0 0 34800 1420 43200 860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92800 2820 220775 5250 0 0 0 0 0 0 0 0 0 0
-cap "GRAY_INx2x" "VDD" 26.2571
-cap "BIAS1" "OUTx6x" 11.7322
-cap "OUTx1x" "VDD" 31.2837
-cap "READ" "VDD" 36.7718
-cap "GRAY_INx0x" "VDD" 18.0743
-cap "BIAS2" "a_1000_n1450#" 33.71
-cap "a_2260_n1450#" "OUTx5x" 5.16631
+cap "OUTx3x" "a_1100_n1450#" 2.75922
+cap "V_IN" "VDD" 23.2781
+cap "BIAS2" "V_RAMP" 43.0991
+cap "OUTx5x" "GRAY_INx7x" 2.35117
+cap "OUTx7x" "V_RAMP" 10.7191
+cap "OUTx1x" "a_1870_n1400#" 10.9296
+cap "OUTx4x" "GRAY_INx6x" 2.87958
+cap "BIAS1" "GRAY_INx2x" 17.4273
+cap "GRAY_INx3x" "GRAY_INx0x" 2.31575
+cap "GRAY_INx5x" "OUTx1x" 2.00008
+cap "a_1870_n1400#" "a_2260_n1450#" 29.2813
+cap "GRAY_INx4x" "V_RAMP" 439.035
+cap "GRAY_INx7x" "BIAS2" 6.95009
+cap "GRAY_INx5x" "a_2260_n1450#" 8.56734
cap "OUTx7x" "GRAY_INx7x" 2.22841
-cap "a_2260_n1450#" "OUTx4x" 5.58034
-cap "OUTx2x" "a_2260_n1450#" 9.14974
-cap "a_2260_n1450#" "GRAY_INx5x" 8.56734
-cap "OUTx7x" "OUTx1x" 0.766667
-cap "a_2260_n1450#" "GRAY_INx3x" 11.9736
-cap "a_1720_n1450#" "OUTx6x" 1.45785
-cap "OUTx7x" "READ" 5.09842
-cap "a_2260_n1450#" "OUTx0x" 11.074
-cap "OUTx4x" "OUTx5x" 2.09868
-cap "OUTx2x" "OUTx5x" 2.04766
-cap "OUTx5x" "GRAY_INx5x" 1.76895
+cap "OUTx6x" "V_IN" 9.39569
+cap "OUTx3x" "a_2260_n1450#" 7.54687
+cap "GRAY_INx1x" "V_RAMP" 20.4094
+cap "GRAY_INx7x" "GRAY_INx4x" 2.2334
+cap "OUTx5x" "BIAS1" 46.2606
+cap "a_1000_n1450#" "GRAY_INx6x" 14.3784
+cap "BIAS1" "BIAS2" 249.145
+cap "V_IN" "a_1870_n1400#" 0.649421
+cap "OUTx0x" "GRAY_INx0x" 2.07348
+cap "OUTx7x" "BIAS1" 19.3486
+cap "GRAY_INx5x" "V_IN" 1.57629
+cap "GRAY_INx3x" "GRAY_INx2x" 2.60018
+cap "OUTx3x" "V_IN" 1.65111
+cap "BIAS1" "GRAY_INx4x" 17.4398
+cap "OUTx2x" "V_RAMP" 22.5584
+cap "VDD" "GRAY_INx0x" 18.0743
+cap "OUTx4x" "a_1000_n1450#" 7.0591
+cap "READ" "GRAY_INx6x" 7.46657
cap "OUTx5x" "GRAY_INx3x" 1.56864
-cap "a_2260_n1450#" "GRAY_INx1x" 72.3185
-cap "OUTx4x" "GRAY_INx5x" 462.923
-cap "BIAS2" "a_1100_n1450#" 94.6849
-cap "a_2260_n1450#" "a_1870_n1400#" 29.2813
-cap "OUTx2x" "GRAY_INx3x" 462.923
-cap "OUTx2x" "GRAY_INx5x" 325.297
-cap "OUTx5x" "OUTx0x" 1.60549
-cap "GRAY_INx3x" "OUTx0x" 325.297
-cap "OUTx5x" "GRAY_INx1x" 1.07973
+cap "GRAY_INx1x" "BIAS1" 22.5419
+cap "BIAS2" "GRAY_INx3x" 10.5669
+cap "OUTx6x" "GRAY_INx0x" 0.0653327
+cap "OUTx0x" "GRAY_INx2x" 3.02989
+cap "OUTx7x" "GRAY_INx3x" 1.19038
+cap "OUTx4x" "READ" 6.90673
+cap "a_1720_n1450#" "GRAY_INx6x" 2.81697
+cap "VDD" "GRAY_INx2x" 26.2571
+cap "GRAY_INx4x" "GRAY_INx3x" 2.11839
+cap "OUTx2x" "BIAS1" 23.6154
+cap "GRAY_INx7x" "V_RAMP" 17.7634
+cap "a_1870_n1400#" "GRAY_INx0x" 2.90887
+cap "OUTx0x" "OUTx5x" 1.60549
+cap "GRAY_INx5x" "GRAY_INx0x" 1.58022
+cap "OUTx5x" "VDD" 29.2456
+cap "OUTx0x" "BIAS2" 8.38834
+cap "OUTx4x" "a_1720_n1450#" 2.14051
+cap "READ" "a_1000_n1450#" 15.1134
+cap "OUTx6x" "GRAY_INx2x" 0.95202
+cap "OUTx0x" "OUTx7x" 0.943415
+cap "BIAS1" "V_RAMP" 951.073
cap "BIAS2" "VDD" 209.153
-cap "li_1640_n2140#" "READ" 1.31957
-cap "OUTx5x" "a_1870_n1400#" 1.95799
-cap "a_2260_n1450#" "V_RAMP" 16.315
-cap "OUTx4x" "a_1870_n1400#" 1.79508
-cap "GRAY_INx3x" "a_1870_n1400#" 4.75807
-cap "OUTx2x" "a_1870_n1400#" 2.33939
-cap "GRAY_INx5x" "a_1870_n1400#" 2.83315
+cap "OUTx0x" "GRAY_INx4x" 2.31071
+cap "OUTx7x" "VDD" 21.8656
+cap "a_1100_n1450#" "GRAY_INx6x" 6.84082
+cap "a_1870_n1400#" "GRAY_INx2x" 5.87446
+cap "OUTx2x" "GRAY_INx3x" 462.923
+cap "OUTx6x" "OUTx5x" 1.8448
+cap "GRAY_INx4x" "VDD" 26.0297
+cap "a_1000_n1450#" "a_1720_n1450#" 23.7038
+cap "GRAY_INx5x" "GRAY_INx2x" 2.29934
+cap "BIAS1" "GRAY_INx7x" 28.581
cap "OUTx0x" "GRAY_INx1x" 462.923
-cap "OUTx6x" "GRAY_INx7x" 481.077
+cap "OUTx3x" "GRAY_INx2x" 291.078
+cap "OUTx6x" "BIAS2" 6.97704
+cap "GRAY_INx1x" "VDD" 15.8419
+cap "OUTx5x" "a_1870_n1400#" 1.95799
+cap "OUTx6x" "OUTx7x" 7.82061
+cap "OUTx4x" "a_1100_n1450#" 3.09895
+cap "GRAY_INx5x" "OUTx5x" 1.76895
+cap "GRAY_INx6x" "a_2260_n1450#" 4.61361
+cap "GRAY_INx3x" "V_RAMP" 17.5737
cap "OUTx6x" "GRAY_INx4x" 1.5944
-cap "BIAS2" "OUTx7x" 9.94506
+cap "BIAS2" "a_1870_n1400#" 46.5525
+cap "li_1640_n2140#" "BIAS2" 0.645755
+cap "READ" "a_1720_n1450#" 7.66535
+cap "GRAY_INx5x" "BIAS2" 8.06454
+cap "OUTx7x" "a_1870_n1400#" 1.41969
+cap "GRAY_INx5x" "OUTx7x" 1.71934
+cap "OUTx3x" "BIAS2" 15.4895
+cap "OUTx4x" "OUTx1x" 1.38352
+cap "OUTx2x" "VDD" 23.3622
+cap "GRAY_INx4x" "a_1870_n1400#" 2.20436
+cap "a_1000_n1450#" "a_1100_n1450#" 106.971
+cap "GRAY_INx5x" "GRAY_INx4x" 2.52547
+cap "OUTx4x" "a_2260_n1450#" 5.58034
+cap "VDD" "li_764_n2030#" 0.526083
+cap "V_IN" "GRAY_INx6x" 52.7923
+cap "OUTx3x" "GRAY_INx4x" 113.22
+cap "OUTx0x" "V_RAMP" 18.0102
+cap "GRAY_INx1x" "a_1870_n1400#" 2.57237
+cap "BIAS1" "GRAY_INx3x" 21.7231
+cap "OUTx3x" "GRAY_INx1x" 1.53177
+cap "a_1000_n1450#" "OUTx1x" 3.63416
+cap "VDD" "V_RAMP" 172.457
+cap "a_1000_n1450#" "a_2260_n1450#" 4.33884
+cap "READ" "a_1100_n1450#" 9.26602
+cap "OUTx4x" "V_IN" 2.29638
+cap "GRAY_INx7x" "VDD" 17.3693
+cap "OUTx2x" "a_1870_n1400#" 2.33939
+cap "OUTx2x" "GRAY_INx5x" 325.297
+cap "OUTx6x" "V_RAMP" 5.03727
+cap "li_1640_n2140#" "li_764_n2030#" 5.40359
+cap "READ" "OUTx1x" 5.72333
+cap "OUTx2x" "OUTx3x" 2.10059
+cap "a_1720_n1450#" "a_1100_n1450#" 76.4086
+cap "OUTx0x" "BIAS1" 21.2679
+cap "a_1000_n1450#" "V_IN" 137.415
+cap "READ" "a_2260_n1450#" 25.7735
+cap "a_1870_n1400#" "V_RAMP" 15.4114
+cap "OUTx6x" "GRAY_INx7x" 481.077
+cap "BIAS1" "VDD" 65.9299
+cap "li_1640_n2140#" "V_RAMP" 2.9373
+cap "GRAY_INx5x" "V_RAMP" 18.4046
+cap "OUTx3x" "V_RAMP" 68.8925
+cap "a_1720_n1450#" "OUTx1x" 3.14372
+cap "a_1720_n1450#" "a_2260_n1450#" 7.93385
+cap "GRAY_INx7x" "a_1870_n1400#" 1.82615
+cap "READ" "V_IN" 9.32086
+cap "OUTx4x" "GRAY_INx0x" 0.938394
+cap "OUTx6x" "BIAS1" 11.7322
+cap "OUTx0x" "GRAY_INx3x" 325.297
+cap "OUTx3x" "GRAY_INx7x" 1.80441
+cap "VDD" "GRAY_INx3x" 22.4013
+cap "BIAS1" "a_1870_n1400#" 16.0471
+cap "li_1640_n2140#" "BIAS1" 0.336809
+cap "GRAY_INx5x" "BIAS1" 24.1926
+cap "a_1720_n1450#" "V_IN" 0.626756
+cap "a_1000_n1450#" "GRAY_INx0x" 2.39003
+cap "OUTx5x" "GRAY_INx6x" 178.794
+cap "OUTx3x" "BIAS1" 15.5267
+cap "OUTx1x" "a_1100_n1450#" 1.86307
+cap "OUTx4x" "GRAY_INx2x" 1.64187
+cap "a_1100_n1450#" "a_2260_n1450#" 9.60873
+cap "BIAS2" "GRAY_INx6x" 10.0223
+cap "OUTx0x" "VDD" 21.5291
+cap "OUTx7x" "GRAY_INx6x" 222.445
+cap "READ" "GRAY_INx0x" 7.15514
+cap "OUTx4x" "OUTx5x" 2.09868
+cap "a_1870_n1400#" "GRAY_INx3x" 4.75807
+cap "OUTx1x" "a_2260_n1450#" 65.0779
+cap "a_1000_n1450#" "GRAY_INx2x" 3.48582
+cap "V_IN" "a_1100_n1450#" 2.02691
+cap "OUTx4x" "BIAS2" 6.50189
+cap "OUTx3x" "GRAY_INx3x" 1.73851
+cap "GRAY_INx1x" "GRAY_INx6x" 1.00188
+cap "OUTx4x" "OUTx7x" 2.20559
+cap "a_1000_n1450#" "OUTx5x" 6.77171
+cap "OUTx4x" "GRAY_INx4x" 1.973
+cap "a_1720_n1450#" "GRAY_INx0x" 2.76708
+cap "OUTx6x" "VDD" 12.5851
+cap "V_IN" "OUTx1x" 0.756156
cap "OUTx0x" "a_1870_n1400#" 3.57482
+cap "a_1000_n1450#" "BIAS2" 33.71
+cap "READ" "GRAY_INx2x" 6.8245
+cap "V_IN" "a_2260_n1450#" 3.49524
+cap "OUTx2x" "GRAY_INx6x" 2.5129
+cap "a_1000_n1450#" "OUTx7x" 5.79683
+cap "VDD" "a_1870_n1400#" 255.829
+cap "OUTx0x" "OUTx3x" 2.01523
+cap "li_1640_n2140#" "VDD" 2.22381
+cap "GRAY_INx5x" "VDD" 25.1198
+cap "a_1000_n1450#" "GRAY_INx4x" 11.5747
+cap "READ" "OUTx5x" 5.07725
+cap "OUTx3x" "VDD" 28.2014
+cap "a_1720_n1450#" "GRAY_INx2x" 10.8868
+cap "a_1000_n1450#" "GRAY_INx1x" 2.09814
+cap "READ" "BIAS2" 29.5835
+cap "a_1100_n1450#" "GRAY_INx0x" 1.09107
+cap "GRAY_INx6x" "V_RAMP" 13.3188
+cap "OUTx6x" "a_1870_n1400#" 0.931511
+cap "READ" "OUTx7x" 5.09842
+cap "READ" "GRAY_INx4x" 6.71497
+cap "OUTx5x" "a_1720_n1450#" 2.26137
cap "OUTx3x" "OUTx6x" 1.24355
+cap "GRAY_INx7x" "GRAY_INx6x" 2.72673
+cap "OUTx1x" "GRAY_INx0x" 207.354
+cap "GRAY_INx5x" "a_1870_n1400#" 2.83315
+cap "a_1720_n1450#" "BIAS2" 46.0978
+cap "OUTx4x" "V_RAMP" 16.8079
+cap "OUTx2x" "a_1000_n1450#" 7.40103
+cap "READ" "GRAY_INx1x" 6.90673
+cap "a_2260_n1450#" "GRAY_INx0x" 56.548
+cap "OUTx3x" "a_1870_n1400#" 2.41406
+cap "OUTx7x" "a_1720_n1450#" 2.00937
+cap "OUTx3x" "GRAY_INx5x" 2.34351
+cap "a_1100_n1450#" "GRAY_INx2x" 1.58509
+cap "a_1720_n1450#" "GRAY_INx4x" 2.09698
+cap "OUTx4x" "GRAY_INx7x" 325.297
+cap "BIAS1" "GRAY_INx6x" 131.611
+cap "a_1000_n1450#" "V_RAMP" 82.448
+cap "GRAY_INx1x" "a_1720_n1450#" 2.17017
+cap "OUTx5x" "a_1100_n1450#" 3.46536
+cap "READ" "OUTx2x" 6.90673
+cap "V_IN" "GRAY_INx0x" 0.208384
+cap "OUTx1x" "GRAY_INx2x" 192.307
+cap "READ" "li_764_n2030#" 1.43022
+cap "a_2260_n1450#" "GRAY_INx2x" 11.8436
+cap "a_1000_n1450#" "GRAY_INx7x" 10.5237
+cap "BIAS2" "a_1100_n1450#" 94.6849
+cap "OUTx4x" "BIAS1" 44.2571
+cap "OUTx7x" "a_1100_n1450#" 2.09281
+cap "GRAY_INx4x" "a_1100_n1450#" 3.82942
+cap "READ" "V_RAMP" 6.42899
+cap "OUTx2x" "a_1720_n1450#" 3.7551
+cap "GRAY_INx6x" "GRAY_INx3x" 1.81565
+cap "OUTx5x" "a_2260_n1450#" 5.16631
+cap "OUTx1x" "BIAS2" 12.1398
+cap "V_IN" "GRAY_INx2x" 0.916992
+cap "a_1000_n1450#" "BIAS1" 47.7762
+cap "READ" "GRAY_INx7x" 6.92439
+cap "OUTx7x" "OUTx1x" 0.766667
+cap "GRAY_INx1x" "a_1100_n1450#" 1.10963
+cap "BIAS2" "a_2260_n1450#" 143.963
+cap "OUTx7x" "a_2260_n1450#" 1.87057
+cap "a_1720_n1450#" "V_RAMP" 38.9468
+cap "GRAY_INx4x" "a_2260_n1450#" 8.06462
+cap "OUTx5x" "V_IN" 1.69338
+cap "OUTx0x" "GRAY_INx6x" 1.68938
+cap "GRAY_INx1x" "OUTx1x" 2.11682
+cap "READ" "BIAS1" 86.1959
+cap "V_IN" "BIAS2" 69.2601
+cap "GRAY_INx7x" "a_1720_n1450#" 2.41228
+cap "GRAY_INx1x" "a_2260_n1450#" 72.3185
+cap "OUTx2x" "a_1100_n1450#" 2.5382
+cap "GRAY_INx6x" "VDD" 28.1456
+cap "OUTx7x" "V_IN" 37.2457
+cap "a_1000_n1450#" "GRAY_INx3x" 3.44566
+cap "GRAY_INx4x" "V_IN" 1.44758
+cap "OUTx2x" "OUTx1x" 2.02055
+cap "a_1100_n1450#" "V_RAMP" 47.6242
+cap "BIAS1" "a_1720_n1450#" 16.6903
+cap "OUTx6x" "GRAY_INx6x" 2.14881
+cap "OUTx4x" "VDD" 20.7242
+cap "GRAY_INx1x" "V_IN" 0.411883
+cap "OUTx2x" "a_2260_n1450#" 9.14974
+cap "READ" "GRAY_INx3x" 6.90673
+cap "OUTx0x" "a_1000_n1450#" 3.7793
+cap "GRAY_INx7x" "a_1100_n1450#" 2.37737
+cap "GRAY_INx6x" "a_1870_n1400#" 2.23358
+cap "OUTx1x" "V_RAMP" 12.0116
+cap "GRAY_INx5x" "GRAY_INx6x" 2.29742
+cap "a_1000_n1450#" "VDD" 247.849
+cap "a_2260_n1450#" "V_RAMP" 16.315
+cap "OUTx2x" "V_IN" 1.80461
+cap "BIAS2" "GRAY_INx0x" 10.6761
+cap "GRAY_INx7x" "OUTx1x" 1.19818
+cap "V_IN" "li_764_n2030#" 0.887306
+cap "a_1720_n1450#" "GRAY_INx3x" 4.46198
+cap "BIAS1" "a_1100_n1450#" 106.672
+cap "OUTx4x" "a_1870_n1400#" 1.79508
+cap "OUTx0x" "READ" 6.90673
+cap "GRAY_INx7x" "a_2260_n1450#" 3.62213
+cap "OUTx4x" "GRAY_INx5x" 462.923
+cap "a_1000_n1450#" "OUTx6x" 4.54127
+cap "OUTx4x" "OUTx3x" 1.82953
+cap "OUTx5x" "GRAY_INx2x" 0.342982
+cap "READ" "VDD" 36.7718
+cap "V_IN" "V_RAMP" 4.58473
+cap "GRAY_INx1x" "GRAY_INx0x" 10.213
+cap "BIAS1" "OUTx1x" 15.155
+cap "a_1000_n1450#" "a_1870_n1400#" 5.67061
+cap "BIAS2" "GRAY_INx2x" 14.8611
+cap "BIAS1" "a_2260_n1450#" 197.986
+cap "li_1640_n2140#" "a_1000_n1450#" 1.66235
+cap "GRAY_INx7x" "V_IN" 4.71705
+cap "OUTx0x" "a_1720_n1450#" 3.15324
+cap "a_1000_n1450#" "GRAY_INx5x" 5.34977
+cap "a_1000_n1450#" "OUTx3x" 4.2456
+cap "READ" "OUTx6x" 7.02901
+cap "GRAY_INx4x" "GRAY_INx2x" 0.494937
+cap "a_1100_n1450#" "GRAY_INx3x" 1.61145
+cap "a_1720_n1450#" "VDD" 278.914
+cap "OUTx5x" "BIAS2" 8.61245
+cap "OUTx2x" "GRAY_INx0x" 1.6556
+cap "OUTx7x" "OUTx5x" 0.482716
+cap "GRAY_INx1x" "GRAY_INx2x" 2.41838
+cap "BIAS1" "V_IN" 77.8114
+cap "READ" "a_1870_n1400#" 9.28674
+cap "OUTx5x" "GRAY_INx4x" 292.526
+cap "READ" "li_1640_n2140#" 1.31957
+cap "READ" "GRAY_INx5x" 6.90673
+cap "OUTx1x" "GRAY_INx3x" 2.56716
+cap "OUTx7x" "BIAS2" 9.94506
+cap "OUTx6x" "a_1720_n1450#" 1.45785
+cap "a_2260_n1450#" "GRAY_INx3x" 11.9736
+cap "READ" "OUTx3x" 4.99531
+cap "GRAY_INx4x" "BIAS2" 11.8688
+cap "GRAY_INx0x" "V_RAMP" 14.9889
+cap "GRAY_INx1x" "OUTx5x" 1.07973
+cap "OUTx0x" "a_1100_n1450#" 1.88157
+cap "a_1100_n1450#" "VDD" 86.1236
+cap "a_1720_n1450#" "a_1870_n1400#" 98.824
+cap "OUTx2x" "GRAY_INx2x" 2.04545
+cap "GRAY_INx1x" "BIAS2" 6.62824
+cap "GRAY_INx5x" "a_1720_n1450#" 3.12953
+cap "GRAY_INx7x" "GRAY_INx0x" 0.560837
+cap "GRAY_INx1x" "OUTx7x" 0.444584
+cap "OUTx3x" "a_1720_n1450#" 4.22614
+cap "OUTx0x" "OUTx1x" 2.29046
+cap "V_IN" "GRAY_INx3x" 1.09308
+cap "GRAY_INx1x" "GRAY_INx4x" 1.63103
+cap "OUTx2x" "OUTx5x" 2.04766
+cap "OUTx0x" "a_2260_n1450#" 11.074
+cap "OUTx1x" "VDD" 31.2837
+cap "OUTx6x" "a_1100_n1450#" 1.58234
+cap "GRAY_INx2x" "V_RAMP" 12.8097
+cap "VDD" "a_2260_n1450#" 121.765
+cap "BIAS1" "GRAY_INx0x" 18.7682
+cap "OUTx2x" "BIAS2" 7.64112
+cap "OUTx2x" "OUTx7x" 1.73276
+cap "BIAS2" "li_764_n2030#" 0.564727
+cap "a_1100_n1450#" "a_1870_n1400#" 1.10176
+cap "GRAY_INx7x" "GRAY_INx2x" 1.58547
+cap "OUTx2x" "GRAY_INx4x" 2.6947
+cap "li_1640_n2140#" "a_1100_n1450#" 2.90863
+cap "OUTx0x" "V_IN" 0.983432
cap "OUTx5x" "V_RAMP" 10.5099
cap "OUTx6x" "OUTx1x" 0.542456
-cap "OUTx6x" "GRAY_INx2x" 0.95202
-cap "OUTx6x" "GRAY_INx0x" 0.0653327
-cap "OUTx4x" "V_RAMP" 16.8079
-cap "GRAY_INx1x" "a_1870_n1400#" 2.57237
-cap "READ" "OUTx6x" 7.02901
-cap "GRAY_INx5x" "V_RAMP" 18.4046
-cap "OUTx2x" "V_RAMP" 22.5584
-cap "GRAY_INx3x" "V_RAMP" 17.5737
-cap "OUTx0x" "V_RAMP" 18.0102
-cap "a_1100_n1450#" "a_1000_n1450#" 106.971
-cap "a_2260_n1450#" "GRAY_INx6x" 4.61361
-cap "li_1640_n2140#" "BIAS2" 0.645755
-cap "GRAY_INx1x" "V_RAMP" 20.4094
-cap "a_1000_n1450#" "VDD" 247.849
-cap "a_2260_n1450#" "V_IN" 3.49524
-cap "a_1870_n1400#" "V_RAMP" 15.4114
-cap "GRAY_INx6x" "OUTx5x" 178.794
-cap "a_2260_n1450#" "BIAS1" 197.986
-cap "GRAY_INx6x" "OUTx4x" 2.87958
-cap "OUTx5x" "V_IN" 1.69338
-cap "OUTx2x" "GRAY_INx6x" 2.5129
-cap "GRAY_INx6x" "GRAY_INx5x" 2.29742
-cap "GRAY_INx6x" "GRAY_INx3x" 1.81565
-cap "OUTx4x" "V_IN" 2.29638
-cap "OUTx7x" "a_1000_n1450#" 5.79683
-cap "OUTx2x" "V_IN" 1.80461
-cap "V_IN" "GRAY_INx5x" 1.57629
-cap "GRAY_INx6x" "OUTx0x" 1.68938
-cap "BIAS2" "OUTx6x" 6.97704
-cap "BIAS1" "OUTx5x" 46.2606
-cap "GRAY_INx3x" "V_IN" 1.09308
-cap "BIAS1" "OUTx4x" 44.2571
-cap "a_1100_n1450#" "VDD" 86.1236
-cap "OUTx2x" "BIAS1" 23.6154
-cap "BIAS1" "GRAY_INx5x" 24.1926
-cap "OUTx0x" "V_IN" 0.983432
-cap "GRAY_INx6x" "GRAY_INx1x" 1.00188
-cap "BIAS1" "GRAY_INx3x" 21.7231
-cap "a_2260_n1450#" "a_1720_n1450#" 7.93385
-cap "GRAY_INx6x" "a_1870_n1400#" 2.23358
-cap "BIAS1" "OUTx0x" 21.2679
-cap "V_IN" "GRAY_INx1x" 0.411883
-cap "V_IN" "a_1870_n1400#" 0.649421
-cap "OUTx5x" "a_1720_n1450#" 2.26137
-cap "li_1640_n2140#" "a_1000_n1450#" 1.66235
-cap "BIAS1" "GRAY_INx1x" 22.5419
-cap "OUTx7x" "a_1100_n1450#" 2.09281
-cap "BIAS1" "a_1870_n1400#" 16.0471
-cap "OUTx4x" "a_1720_n1450#" 2.14051
-cap "GRAY_INx6x" "V_RAMP" 13.3188
-cap "OUTx2x" "a_1720_n1450#" 3.7551
-cap "a_1720_n1450#" "GRAY_INx5x" 3.12953
-cap "GRAY_INx3x" "a_1720_n1450#" 4.46198
-cap "OUTx7x" "VDD" 21.8656
-cap "V_IN" "V_RAMP" 4.58473
-cap "OUTx0x" "a_1720_n1450#" 3.15324
-cap "BIAS1" "V_RAMP" 951.073
-cap "a_1720_n1450#" "GRAY_INx1x" 2.17017
-cap "OUTx6x" "a_1000_n1450#" 4.54127
-cap "a_1720_n1450#" "a_1870_n1400#" 98.824
-cap "li_1640_n2140#" "a_1100_n1450#" 2.90863
-cap "a_2260_n1450#" "GRAY_INx7x" 3.62213
-cap "a_2260_n1450#" "OUTx3x" 7.54687
-cap "a_2260_n1450#" "GRAY_INx4x" 8.06462
-cap "a_2260_n1450#" "GRAY_INx2x" 11.8436
-cap "a_2260_n1450#" "OUTx1x" 65.0779
-cap "V_IN" "li_764_n2030#" 0.887306
-cap "a_2260_n1450#" "GRAY_INx0x" 56.548
-cap "li_1640_n2140#" "VDD" 2.22381
-cap "a_2260_n1450#" "READ" 25.7735
-cap "OUTx5x" "GRAY_INx7x" 2.35117
-cap "OUTx5x" "GRAY_INx4x" 292.526
-cap "a_1720_n1450#" "V_RAMP" 38.9468
-cap "GRAY_INx6x" "V_IN" 52.7923
-cap "OUTx4x" "GRAY_INx7x" 325.297
-cap "OUTx5x" "GRAY_INx2x" 0.342982
-cap "OUTx4x" "OUTx3x" 1.82953
-cap "OUTx4x" "GRAY_INx4x" 1.973
-cap "OUTx2x" "GRAY_INx4x" 2.6947
-cap "GRAY_INx5x" "GRAY_INx4x" 2.52547
-cap "OUTx4x" "OUTx1x" 1.38352
-cap "OUTx4x" "GRAY_INx2x" 1.64187
-cap "OUTx3x" "GRAY_INx3x" 1.73851
-cap "OUTx2x" "OUTx3x" 2.10059
-cap "OUTx3x" "GRAY_INx5x" 2.34351
-cap "GRAY_INx3x" "GRAY_INx4x" 2.11839
-cap "OUTx5x" "READ" 5.07725
-cap "a_1100_n1450#" "OUTx6x" 1.58234
-cap "OUTx2x" "OUTx1x" 2.02055
-cap "GRAY_INx5x" "OUTx1x" 2.00008
-cap "GRAY_INx3x" "GRAY_INx2x" 2.60018
-cap "OUTx2x" "GRAY_INx2x" 2.04545
-cap "GRAY_INx5x" "GRAY_INx2x" 2.29934
-cap "BIAS1" "GRAY_INx6x" 131.611
-cap "OUTx4x" "GRAY_INx0x" 0.938394
-cap "GRAY_INx3x" "OUTx1x" 2.56716
-cap "OUTx4x" "READ" 6.90673
-cap "OUTx2x" "GRAY_INx0x" 1.6556
-cap "GRAY_INx5x" "GRAY_INx0x" 1.58022
-cap "OUTx0x" "GRAY_INx4x" 2.31071
-cap "OUTx2x" "READ" 6.90673
-cap "READ" "GRAY_INx5x" 6.90673
-cap "GRAY_INx3x" "GRAY_INx0x" 2.31575
-cap "OUTx3x" "OUTx0x" 2.01523
-cap "BIAS1" "V_IN" 77.8114
-cap "GRAY_INx3x" "READ" 6.90673
-cap "OUTx0x" "OUTx1x" 2.29046
-cap "OUTx0x" "GRAY_INx2x" 3.02989
-cap "OUTx6x" "VDD" 12.5851
-cap "OUTx0x" "GRAY_INx0x" 2.07348
-cap "OUTx0x" "READ" 6.90673
-cap "OUTx3x" "GRAY_INx1x" 1.53177
-cap "GRAY_INx1x" "GRAY_INx4x" 1.63103
-cap "GRAY_INx7x" "a_1870_n1400#" 1.82615
-cap "GRAY_INx1x" "OUTx1x" 2.11682
-cap "GRAY_INx1x" "GRAY_INx2x" 2.41838
-cap "GRAY_INx4x" "a_1870_n1400#" 2.20436
-cap "OUTx3x" "a_1870_n1400#" 2.41406
-cap "GRAY_INx0x" "GRAY_INx1x" 10.213
-cap "GRAY_INx2x" "a_1870_n1400#" 5.87446
-cap "OUTx1x" "a_1870_n1400#" 10.9296
-cap "READ" "GRAY_INx1x" 6.90673
-cap "GRAY_INx6x" "a_1720_n1450#" 2.81697
-cap "GRAY_INx0x" "a_1870_n1400#" 2.90887
-cap "READ" "a_1870_n1400#" 9.28674
-cap "BIAS2" "a_2260_n1450#" 143.963
-cap "OUTx7x" "OUTx6x" 7.82061
-cap "V_IN" "a_1720_n1450#" 0.626756
-cap "GRAY_INx7x" "V_RAMP" 17.7634
-cap "OUTx3x" "V_RAMP" 68.8925
-cap "GRAY_INx4x" "V_RAMP" 439.035
-cap "GRAY_INx2x" "V_RAMP" 12.8097
-cap "BIAS1" "a_1720_n1450#" 16.6903
-cap "OUTx1x" "V_RAMP" 12.0116
-cap "BIAS2" "OUTx5x" 8.61245
-cap "READ" "V_RAMP" 6.42899
-cap "GRAY_INx0x" "V_RAMP" 14.9889
-cap "BIAS2" "OUTx4x" 6.50189
-cap "OUTx2x" "BIAS2" 7.64112
-cap "BIAS2" "GRAY_INx5x" 8.06454
-cap "BIAS2" "GRAY_INx3x" 10.5669
-cap "BIAS2" "OUTx0x" 8.38834
-cap "BIAS2" "GRAY_INx1x" 6.62824
-cap "GRAY_INx6x" "GRAY_INx7x" 2.72673
-cap "BIAS2" "a_1870_n1400#" 46.5525
-cap "READ" "li_764_n2030#" 1.43022
-cap "V_IN" "GRAY_INx7x" 4.71705
-cap "a_2260_n1450#" "a_1000_n1450#" 4.33884
-cap "OUTx3x" "V_IN" 1.65111
-cap "V_IN" "GRAY_INx4x" 1.44758
-cap "GRAY_INx6x" "READ" 7.46657
-cap "V_IN" "OUTx1x" 0.756156
-cap "V_IN" "GRAY_INx2x" 0.916992
-cap "BIAS1" "GRAY_INx7x" 28.581
-cap "BIAS1" "OUTx3x" 15.5267
-cap "BIAS1" "GRAY_INx4x" 17.4398
-cap "V_IN" "GRAY_INx0x" 0.208384
-cap "V_IN" "READ" 9.32086
-cap "BIAS1" "GRAY_INx2x" 17.4273
-cap "BIAS1" "OUTx1x" 15.155
-cap "BIAS2" "V_RAMP" 43.0991
-cap "OUTx5x" "a_1000_n1450#" 6.77171
-cap "BIAS1" "GRAY_INx0x" 18.7682
-cap "BIAS1" "READ" 86.1959
-cap "OUTx4x" "a_1000_n1450#" 7.0591
-cap "OUTx2x" "a_1000_n1450#" 7.40103
-cap "GRAY_INx5x" "a_1000_n1450#" 5.34977
-cap "GRAY_INx3x" "a_1000_n1450#" 3.44566
-cap "OUTx0x" "a_1000_n1450#" 3.7793
-cap "a_2260_n1450#" "a_1100_n1450#" 9.60873
-cap "a_1720_n1450#" "GRAY_INx7x" 2.41228
-cap "OUTx3x" "a_1720_n1450#" 4.22614
-cap "a_1720_n1450#" "GRAY_INx4x" 2.09698
-cap "a_1720_n1450#" "GRAY_INx2x" 10.8868
-cap "a_1720_n1450#" "OUTx1x" 3.14372
-cap "GRAY_INx1x" "a_1000_n1450#" 2.09814
-cap "BIAS2" "li_764_n2030#" 0.564727
-cap "a_2260_n1450#" "VDD" 121.765
-cap "a_1870_n1400#" "a_1000_n1450#" 5.67061
-cap "a_1720_n1450#" "GRAY_INx0x" 2.76708
-cap "READ" "a_1720_n1450#" 7.66535
-cap "OUTx5x" "a_1100_n1450#" 3.46536
-cap "BIAS2" "GRAY_INx6x" 10.0223
-cap "OUTx4x" "a_1100_n1450#" 3.09895
-cap "OUTx2x" "a_1100_n1450#" 2.5382
-cap "a_1100_n1450#" "GRAY_INx5x" 3.24316
-cap "BIAS2" "V_IN" 69.2601
-cap "GRAY_INx3x" "a_1100_n1450#" 1.61145
-cap "OUTx5x" "VDD" 29.2456
-cap "OUTx0x" "a_1100_n1450#" 1.88157
-cap "OUTx4x" "VDD" 20.7242
-cap "a_1000_n1450#" "V_RAMP" 82.448
-cap "a_2260_n1450#" "OUTx7x" 1.87057
-cap "OUTx2x" "VDD" 23.3622
-cap "GRAY_INx5x" "VDD" 25.1198
-cap "BIAS2" "BIAS1" 249.145
-cap "GRAY_INx3x" "VDD" 22.4013
-cap "a_1100_n1450#" "GRAY_INx1x" 1.10963
-cap "OUTx0x" "VDD" 21.5291
-cap "a_1100_n1450#" "a_1870_n1400#" 1.10176
-cap "OUTx5x" "OUTx7x" 0.482716
-cap "OUTx3x" "GRAY_INx7x" 1.80441
-cap "GRAY_INx7x" "GRAY_INx4x" 2.2334
-cap "GRAY_INx1x" "VDD" 15.8419
-cap "GRAY_INx7x" "OUTx1x" 1.19818
-cap "GRAY_INx7x" "GRAY_INx2x" 1.58547
-cap "OUTx3x" "GRAY_INx4x" 113.22
-cap "GRAY_INx2x" "GRAY_INx4x" 0.494937
-cap "OUTx4x" "OUTx7x" 2.20559
-cap "a_1870_n1400#" "VDD" 255.829
-cap "GRAY_INx0x" "GRAY_INx7x" 0.560837
-cap "OUTx3x" "GRAY_INx2x" 291.078
-cap "OUTx2x" "OUTx7x" 1.73276
-cap "OUTx7x" "GRAY_INx5x" 1.71934
-cap "READ" "GRAY_INx7x" 6.92439
-cap "GRAY_INx2x" "OUTx1x" 192.307
-cap "GRAY_INx3x" "OUTx7x" 1.19038
-cap "BIAS2" "a_1720_n1450#" 46.0978
-cap "OUTx3x" "READ" 4.99531
-cap "READ" "GRAY_INx4x" 6.71497
-cap "READ" "OUTx1x" 5.72333
-cap "GRAY_INx0x" "OUTx1x" 207.354
-cap "READ" "GRAY_INx2x" 6.8245
-cap "OUTx7x" "OUTx0x" 0.943415
-cap "a_1100_n1450#" "V_RAMP" 47.6242
-cap "GRAY_INx6x" "a_1000_n1450#" 14.3784
-cap "READ" "GRAY_INx0x" 7.15514
-cap "OUTx7x" "GRAY_INx1x" 0.444584
-cap "V_IN" "a_1000_n1450#" 137.415
-cap "V_RAMP" "VDD" 172.457
-cap "OUTx7x" "a_1870_n1400#" 1.41969
-cap "BIAS1" "a_1000_n1450#" 47.7762
-cap "a_2260_n1450#" "OUTx6x" 1.0819
-cap "OUTx7x" "V_RAMP" 10.7191
-cap "GRAY_INx6x" "a_1100_n1450#" 6.84082
-cap "li_764_n2030#" "VDD" 0.526083
-cap "OUTx5x" "OUTx6x" 1.8448
-cap "BIAS2" "GRAY_INx7x" 6.95009
-cap "V_IN" "a_1100_n1450#" 2.02691
-cap "BIAS2" "OUTx3x" 15.4895
-cap "BIAS2" "GRAY_INx4x" 11.8688
-cap "a_1720_n1450#" "a_1000_n1450#" 23.7038
-cap "GRAY_INx6x" "VDD" 28.1456
-cap "BIAS2" "OUTx1x" 12.1398
-cap "BIAS2" "GRAY_INx2x" 14.8611
-cap "BIAS2" "GRAY_INx0x" 10.6761
-cap "BIAS2" "READ" 29.5835
-cap "BIAS1" "a_1100_n1450#" 106.672
-cap "V_IN" "VDD" 23.2781
-cap "li_1640_n2140#" "V_RAMP" 2.9373
-cap "BIAS1" "VDD" 65.9299
-cap "GRAY_INx6x" "OUTx7x" 222.445
-cap "OUTx6x" "a_1870_n1400#" 0.931511
-cap "OUTx7x" "V_IN" 37.2457
-cap "a_1100_n1450#" "a_1720_n1450#" 76.4086
-cap "BIAS1" "OUTx7x" 19.3486
-cap "li_1640_n2140#" "li_764_n2030#" 5.40359
-cap "OUTx6x" "V_RAMP" 5.03727
-cap "a_1720_n1450#" "VDD" 278.914
-cap "GRAY_INx7x" "a_1000_n1450#" 10.5237
-cap "OUTx3x" "a_1000_n1450#" 4.2456
-cap "GRAY_INx4x" "a_1000_n1450#" 11.5747
-cap "GRAY_INx2x" "a_1000_n1450#" 3.48582
-cap "OUTx1x" "a_1000_n1450#" 3.63416
-cap "GRAY_INx0x" "a_1000_n1450#" 2.39003
-cap "READ" "a_1000_n1450#" 15.1134
-cap "OUTx7x" "a_1720_n1450#" 2.00937
-cap "li_1640_n2140#" "BIAS1" 0.336809
-cap "a_1100_n1450#" "GRAY_INx7x" 2.37737
-cap "GRAY_INx6x" "OUTx6x" 2.14881
-cap "OUTx3x" "a_1100_n1450#" 2.75922
-cap "a_1100_n1450#" "GRAY_INx4x" 3.82942
-cap "a_1100_n1450#" "OUTx1x" 1.86307
-cap "a_1100_n1450#" "GRAY_INx2x" 1.58509
-cap "V_IN" "OUTx6x" 9.39569
-cap "a_1100_n1450#" "GRAY_INx0x" 1.09107
-cap "READ" "a_1100_n1450#" 9.26602
-cap "GRAY_INx7x" "VDD" 17.3693
-cap "OUTx3x" "VDD" 28.2014
-cap "GRAY_INx4x" "VDD" 26.0297
+cap "GRAY_INx5x" "a_1100_n1450#" 3.24316
+cap "OUTx6x" "a_2260_n1450#" 1.0819
device msubckt sky130_fd_pr__nfet_01v8 2230 -1450 2231 -1449 l=30 w=200 "GND" "a_1870_n1400#" 60 0 "GND" 200 0 "a_2260_n1450#" 200 0
device msubckt sky130_fd_pr__nfet_01v8_lvt 1870 -1600 1871 -1599 l=200 w=200 "GND" "BIAS2" 400 0 "GND" 200 0 "a_1870_n1400#" 200 0
device msubckt sky130_fd_pr__nfet_01v8_lvt 1690 -1450 1691 -1449 l=30 w=200 "GND" "V_RAMP" 60 0 "a_1100_n1450#" 200 0 "a_1720_n1450#" 200 0
@@ -396,584 +396,584 @@
device msubckt sky130_fd_pr__pfet_01v8_lvt 1930 -1060 1931 -1059 l=90 w=200 "VDD" "a_1720_n1450#" 180 0 "VDD" 200 0 "a_1870_n1400#" 200 0
device msubckt sky130_fd_pr__pfet_01v8_lvt 1520 -1060 1521 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "VDD" 200 0 "a_1720_n1450#" 200 0
device msubckt sky130_fd_pr__pfet_01v8_lvt 1070 -1060 1071 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "a_1000_n1450#" 200 0 "VDD" 200 0
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0674668
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0181359
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.159674
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.247468
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0666906
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -6.09724e-05
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -8.54424e-05
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.57324
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.132554
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00020449
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0315754
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.000282779
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0406008
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0544076
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00102381
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0930028
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0225169
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0105251
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.48678e-05
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0603412
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.123171
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0510678
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -19.1352
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.171491
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -6.51667
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0872739
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -13.6154
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0453317
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0373118
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0790654
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.041835
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.098269
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.210274
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.195592
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1100_n1450#" 0.384583
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00083711
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "BIAS1" 2.85671
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00114193
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -3.78622e-06
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "BIAS2" 2.58365
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.00752321
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.239186
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.25736
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0577865
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0201137
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -2.76043e-06
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "VDD" 3.17851
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "GND" 9.58327
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00034688
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.421328
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GND" 1.42538
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.098269
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "GND" 0.670312
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.110951
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.154608
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 1.57514
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -14.4815
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -7.65029
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1000_n1450#" 1.43642
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0617132
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1720_n1450#" 5.73964
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.074722
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.45589
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.95524
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.39337
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.060956
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.6232
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS1" 2.0609
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1100_n1450#" 2.0457
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0285071
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.425348
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.37728
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.444991
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS2" 1.55813
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -14.4815
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0374578
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "BIAS2" 2.29099
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.118638
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "BIAS1" 9.97982
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.30843
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.350496
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.189831
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "BIAS2" 2.29199
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -27.536
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.405984
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.116761
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -8.5
-cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.8276
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.000238699
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.125115
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0621439
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -19.1351
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.117289
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "VDD" 0.708582
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "GND" 5.77192
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1100_n1450#" 0.201761
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0540618
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.0222617
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS1" 1.16663
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -27.2308
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0919385
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0125795
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0100182
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS2" 2.94269
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.491866
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 7.5
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000193271
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.62012
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.33393
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS1" 0.0382438
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 6.37813
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.63021
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0284849
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "BIAS1" 1.88344
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1000_n1450#" 1.59878
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0474576
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 3.74098
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -3.71821
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 11.6531
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "BIAS2" 1.51707
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS2" 2.20076
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.57981
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.8546
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "a_1000_n1450#" 0.302044
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0370006
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.09253
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0344911
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.33301
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.0760366
-cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.19679
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0920516
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.482716
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "a_1000_n1450#" 1.0895
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "GND" 3.28011
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.00148064
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 2.76928
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0291227
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_IN" 4.85972
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_IN" 3.1249
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.516809
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0341316
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0883216
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00155291
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.601185
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "VDD" 0.383609
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.146022
-cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.159169
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "GND" 7.82349
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "GND" 70.5412
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0904769
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.92947
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1720_n1450#" 1.17502
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.108546
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS1" 0.687434
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1000_n1450#" 0.329795
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0020125
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 15.2831
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 5.19873
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.117404
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.053718
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS2" 1.66447
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0390295
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0262757
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.13413
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1000_n1450#" 1.56957
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.187347
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -5.59752
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0498302
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.61617
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "BIAS1" 4.27689
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.69828
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.92544
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6832
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "a_1100_n1450#" 2.6079
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.03677
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "BIAS1" 4.69954
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_IN" 1.72248
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.12477
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS1" 6.49388
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.01343
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 5.50563
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "BIAS1" 3.26809
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "BIAS2" 2.27511
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00402917
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.0608144
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "BIAS2" 1.66447
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS2" 2.705
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.30688
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 5.99029
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GND" 0.000891146
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "BIAS2" 3.45146
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00292971
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.291584
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.103655
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0013419
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.437278
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "GND" 43.6867
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.200635
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 8.2221
-cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 7.73301
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -42.7637
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.00176326
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.744596
-cap "a_1100_n1450#" "BIAS1" -2.52094
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS2" 0.0945249
-cap "BIAS1" "BIAS2" -5.14804
-cap "a_1100_n1450#" "BIAS2" 0.135131
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.22872
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0453317
cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.60539
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.582232
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 41.0969
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.0388643
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "VDD" 2.49487
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.132846
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "GND" 10.0248
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 19.7181
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "BIAS1" 2.27313
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 1.22872
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 10.9194
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "BIAS1" 46.2224
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 6.11521
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS1" 2.27527
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "GND" 5.54063
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1100_n1450#" 0.345858
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00200893
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.44085
-cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.50669
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "BIAS2" 2.85005
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 1.83905
-cap "V_IN" "BIAS1" -2.51738
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS2" 25.2816
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "BIAS2" 2.98823
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0297725
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "a_1000_n1450#" 7.61082
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "GND" 0.366462
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "a_1000_n1450#" 1.30023
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -7.65029
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.00752321
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.17851
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.187347
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.117404
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "BIAS2" 3.45146
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 3.93281
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.110951
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 772.763
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.69828
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0181359
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.601185
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.444991
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "BIAS2" 2.27511
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.159674
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -19.1352
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "BIAS2" 2.58365
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -42.7637
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.76928
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.125115
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.51707
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.8546
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.139468
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.118638
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.670312
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.629186
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.94269
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0100182
+cap "BIAS1" "V_RAMP" -2.66289
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00155291
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0341316
cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 92.3
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -6.39044
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "a_1000_n1450#" 3.58449
-cap "a_1100_n1450#" "GND" 0.933335
-cap "GND" "BIAS1" -6.48079
-cap "VDD" "BIAS1" -2.52254
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "V_IN" 59.479
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.60978
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "a_1720_n1450#" 4.78653
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.439002
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.26772
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.00796
-cap "GND" "BIAS2" -0.719256
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.3092
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.830892
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.139468
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.139468
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "VDD" 1.55184
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "GND" 9.37596
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1000_n1450#" -0.992231
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "GND" 63.7693
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 9.40824
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 10.3286
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "GND" 3.93281
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.29528
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 0.231145
-cap "a_1720_n1450#" "BIAS1" -2.04805
-cap "BIAS1" "a_1000_n1450#" -1.35379
-cap "a_1100_n1450#" "a_1000_n1450#" 1.56068
-cap "V_IN" "GND" -0.416424
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.579418
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 136.959
-cap "BIAS2" "a_1000_n1450#" 0.838693
-cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 18.0666
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 7.86714
-cap "a_1720_n1450#" "BIAS2" 0.869605
-cap "V_RAMP" "a_1100_n1450#" -0.645355
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 0.629186
-cap "V_RAMP" "BIAS1" -2.66289
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "BIAS2" 17.3813
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "a_1000_n1450#" 2.17953
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 1.27401
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.9653
-cap "V_RAMP" "BIAS2" -0.117922
cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.919416
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.618264
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.353732
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0549252
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.249042
-cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 33.4171
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.52962
-cap "GND" "a_1000_n1450#" 1.12119
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 6.11521
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6832
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "a_1000_n1450#" 2.12477
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0284849
+cap "GND" "V_RAMP" -0.254294
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.103655
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -8.54424e-05
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0617132
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 2.0457
+cap "a_1100_n1450#" "BIAS2" 0.135131
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "BIAS1" 4.69954
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.99029
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 5.50563
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00083711
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -6.09724e-05
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0920516
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS2" 1.66447
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.582232
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.17953
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.33393
+cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.8276
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0370006
cap "VDD" "a_1000_n1450#" 3.45671
cap "a_1720_n1450#" "VDD" 0.025356
-cap "a_1720_n1450#" "GND" 0.26344
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "GND" 10.0248
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00200893
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.618264
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0549252
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0904769
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.59878
+cap "BIAS2" "a_1000_n1450#" 0.838693
+cap "a_1720_n1450#" "BIAS2" 0.869605
+cap "GND" "BIAS1" -6.48079
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "a_1000_n1450#" 3.58449
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0498302
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.71821
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.0510678
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 10.3286
cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 61.6339
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 772.763
-cap "V_RAMP" "GND" -0.254294
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1000_n1450#" 29.7137
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 8.52831
-cap "V_RAMP" "a_1000_n1450#" 0.604532
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 11.0576
-cap "a_1720_n1450#" "BIAS2" 3.1891
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1870_n1400#" 1.73757
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 6.032
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "VDD" 0.706079
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.99018
-cap "a_1720_n1450#" "a_1870_n1400#" 0.692513
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00773872
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0393076
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0134903
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1720_n1450#" 2.02989
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.077983
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000153749
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000266492
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.20043
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0723097
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.0332521
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.10399
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000401671
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000177049
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000319715
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0176446
-cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.69566
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -19.9654
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00380833
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000851373
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00848554
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.000755933
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.78299
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "GND" 4.29458
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.2807
-cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.62635
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.6698
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000522601
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.23441
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.87215
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 48.0744
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.0376
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0175938
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000684837
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 21.4123
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000224931
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0220217
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.70523
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0880644
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0379485
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "GND" 1.43665
-cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 51.2959
-cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 37.38
-cap "BIAS2" "GND" 3.7066
-cap "a_1720_n1450#" "VDD" 0.109424
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.89719
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "GND" 3.26588
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -8.89594e-05
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -8.89594e-05
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.44828e-05
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.16819
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.372723
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 26.6425
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GND" 0.254349
-cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 16.0201
-cap "GND" "a_1870_n1400#" 1.92409
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0628071
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.91911
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "GND" 7.67288
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.44193
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GND" 4.83645
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.116079
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0207214
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000180329
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0109873
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00161877
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000112148
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0157989
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.56834
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00735648
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.93821
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.08172
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.042945
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.140948
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.058652
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 3.15379
-cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.2317
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0271561
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -1.23879e-06
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.565274
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000117457
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.76761
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.022966
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.294791
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "a_1870_n1400#" 2.41616
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.28709
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0390765
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0472786
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.80202
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0424989
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.060956
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "BIAS2" 7.0193
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 4.36287
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0460312
-cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 9.80977
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0453581
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.04623
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -9.35
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.696885
-cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.93592
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0702659
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 51.3778
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.40716
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "BIAS2" 4.39505
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.063849
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0703315
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "GND" 14.3091
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "a_1870_n1400#" 7.42581
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0347718
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1870_n1400#" 5.34153
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0296036
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "BIAS2" 7.31129
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1870_n1400#" 0.598216
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 4.1577
-cap "BIAS2" "a_1870_n1400#" 2.05056
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.46478
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0432799
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.323989
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "a_1870_n1400#" 1.56722
-cap "a_1720_n1450#" "GND" 1.21244
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 10.1643
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.83823
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.44828e-05
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -19.1351
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0532087
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.826992
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -6.51667
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0511651
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -13.6154
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0896117
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0552098
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.171491
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "BIAS2" 4.78199
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.08821
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "BIAS2" 5.30455
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.60769
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.472353
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -3.78622e-06
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -27.2308
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.174367
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "a_1870_n1400#" 1.46628
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.562213
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1870_n1400#" 2.35246
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.802502
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.042945
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.0110033
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0302549
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.0882335
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0790691
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.210823
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0985772
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0701304
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.000238699
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.48678e-05
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00402917
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.405984
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 6.57981
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS2" 25.2816
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 17.3813
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.30843
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.00796
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.350496
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.132554
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.291584
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.000891146
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.171491
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "V_IN" 7.73301
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.0388643
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.421328
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.57324
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_IN" 3.1249
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.116761
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0666906
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -6.39044
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.27313
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00034688
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.0382438
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -3.6232
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.249042
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.0895
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0945249
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.92544
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.0222617
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.42538
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.302044
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.61617
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 9.37596
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.053718
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.00148064
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0760366
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 11.6531
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 70.5412
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.33301
+cap "BIAS2" "V_RAMP" -0.117922
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.830892
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.384583
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.63021
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0930028
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.231145
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -14.4815
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.437278
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.201761
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 15.2831
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_IN" 1.72248
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 4.78653
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "VDD" 2.49487
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 46.2224
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "a_1000_n1450#" 7.61082
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0262757
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 1.83905
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0315754
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0374578
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -14.4815
+cap "BIAS1" "VDD" -2.52254
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1000_n1450#" 1.43642
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 5.73964
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "BIAS2" 1.66447
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.041835
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.108546
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.3092
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.744596
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1000_n1450#" 1.56957
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.425348
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.09253
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 2.0609
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.60978
+cap "BIAS1" "BIAS2" -5.14804
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS1" 6.49388
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 63.7693
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.17502
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.329795
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0883216
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.45589
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.25736
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0544076
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.01343
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0291227
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0373118
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0577865
+cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 33.4171
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.0474576
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 5.77192
+cap "GND" "BIAS2" -0.719256
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 19.7181
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.03677
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -5.59752
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0406008
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.39337
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.210274
+cap "a_1100_n1450#" "a_1000_n1450#" 1.56068
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.62012
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.139468
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.439002
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 9.97982
cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.247468
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.631024
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0296036
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.291548
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.0760366
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "VDD" 4.08514
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0113908
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00059708
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -21.5657
-cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.9402
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -5.79259
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0281068
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "VDD" 19.875
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 8.61722
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.377527
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.061489
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "VDD" 3.58915
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.383079
-cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 4.91548
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.18676
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0443803
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0104909
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.55184
+cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.50669
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.117289
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0872739
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.383609
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.37728
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "V_RAMP" 2.95524
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 18.0666
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.345858
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00102381
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.0608144
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.85005
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0790654
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.44085
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.516809
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS2" 2.20076
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 6.37813
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 1.13413
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 5.19873
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0105251
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0020125
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 7.5
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.098269
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.146022
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -27.2308
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.19679
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0225169
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 1.27401
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 3.26809
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.123171
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 29.7137
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 8.52831
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.9653
+cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 8.2221
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.074722
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -8.5
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 4.27689
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.92947
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.85671
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 9.40824
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.88344
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.353732
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000193271
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0344911
+cap "a_1100_n1450#" "V_RAMP" -0.645355
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 5.54063
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.98823
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -3.78622e-06
+cap "BIAS1" "V_IN" -2.51738
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.200635
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.0297725
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.16663
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 41.0969
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.189831
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.708582
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.195592
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "VDD" 10.9194
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 9.58327
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.992231
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.29528
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0285071
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00292971
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0201137
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 7.82349
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.57514
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.55813
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.239186
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS2" 2.705
+cap "GND" "V_IN" -0.416424
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 3.28011
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.579418
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.132846
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -6.51667
+cap "a_1000_n1450#" "V_RAMP" 0.604532
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "a_1100_n1450#" 2.6079
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0603412
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.482716
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.0013419
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0674668
+cap "a_1100_n1450#" "BIAS1" -2.52094
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0621439
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -2.30688
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 5.52962
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 11.0576
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -27.536
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.687434
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00114193
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00020449
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 3.74098
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.098269
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0919385
+cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 59.479
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "a_1000_n1450#" 1.30023
+cap "a_1100_n1450#" "GND" 0.933335
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.491866
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -19.1351
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0125795
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_IN" 4.85972
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.76043e-06
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29199
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.060956
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 43.6867
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390295
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.000282779
+cap "a_1720_n1450#" "BIAS1" -2.04805
+cap "BIAS1" "a_1000_n1450#" -1.35379
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.29099
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 7.86714
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.154608
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.26772
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.159169
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0540618
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 136.959
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.00176326
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.27527
+cap "GND" "a_1000_n1450#" 1.12119
+cap "GND" "a_1720_n1450#" 0.26344
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.366462
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.93592
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 3.15379
cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "VDD" 3.15098
-cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.74027
-cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 3.85367
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 6.82222
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.0376
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 6.032
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -1.23879e-06
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.826992
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 1.99018
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0393076
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 37.38
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.000112148
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0985772
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000224931
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "BIAS1" 2.74027
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00161877
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.631024
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.291548
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "a_1870_n1400#" 7.42581
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.00848554
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.93821
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 3.26588
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1720_n1450#" 6.82222
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000117457
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.060956
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "VDD" 19.875
+cap "BIAS2" "a_1870_n1400#" 2.05056
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.472353
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0432799
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0790691
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.2317
+cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.02989
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.40716
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.70523
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0296036
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.562213
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "BIAS2" 3.85367
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.116079
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390765
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1720_n1450#" 0.814251
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 6.44193
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1870_n1400#" 5.34153
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.000266492
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 14.3091
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.140948
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.042945
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0701304
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0628071
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0702659
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -6.51667
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1720_n1450#" 10.1643
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "VDD" 8.61722
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0896117
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 4.39505
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.35246
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.000319715
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -9.35
+cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.9402
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS1" 1.18676
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0443803
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.706079
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0472786
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -4.2807
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0134903
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -4.23441
+cap "a_1870_n1400#" "a_1720_n1450#" 0.692513
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.802502
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.00735648
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1870_n1400#" 0.598216
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -19.9654
+cap "a_1720_n1450#" "VDD" 0.109424
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.0760366
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.00773872
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0220217
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.377527
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0880644
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1870_n1400#" 16.0201
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -3.78622e-06
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 5.78299
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 4.91548
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.0332521
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -8.89594e-05
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 51.3778
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0296036
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0511651
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.254349
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0110033
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 7.67288
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.058652
+cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.69566
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.41616
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.46478
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.44828e-05
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0552098
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -27.2308
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.000153749
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.56834
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "VDD" 4.08514
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 4.1577
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.08821
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.383079
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0104909
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.061489
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.247468
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -5.79259
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 3.89719
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 48.0744
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.323989
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0109873
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "VDD" 0.0175938
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.10399
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.063849
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.83823
+cap "GND" "BIAS2" 3.7066
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000684837
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "a_1870_n1400#" 1.56722
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "BIAS1" 2.80202
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1720_n1450#" 2.16819
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.565274
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -3.87215
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 7.31129
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 4.78199
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0723097
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0271561
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.022966
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "VDD" 3.58915
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0460312
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0207214
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000522601
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1720_n1450#" -1.28709
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0453581
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0703315
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0424989
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0176446
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 21.4123
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0882335
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0302549
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "BIAS2" 7.0193
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -19.1351
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.171491
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -21.5657
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 4.83645
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.000180329
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1870_n1400#" 1.73757
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS1" 4.36287
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.00380833
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.174367
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.210823
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.6698
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000401671
+cap "GND" "a_1720_n1450#" 1.21244
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.000177049
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1870_n1400#" 2.62635
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.000851373
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.60769
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -3.20043
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.43665
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" -2.08172
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.077983
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0379485
cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 388.424
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.814251
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.000785002
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0124444
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.00459401
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.629827
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.69157
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.157699
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "VDD" 1.22803
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.274985
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.126567
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "VDD" 2.08846
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_RAMP" 0.00495499
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "a_1000_n1450#" 0.00900749
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "VDD" 1.32252
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.79349
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.629827
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.765508
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.946276
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.946276
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.75744
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.582219
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "VDD" 1.46409
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "VDD" 1.06702
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.909122
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.80077
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "VDD" 2.67915
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 6.25991
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.837499
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.76761
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS2" 9.80977
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0157989
+cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.696885
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.042945
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -4.44828e-05
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 9.91911
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 26.6425
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.372723
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0113908
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0281068
+cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 5.30455
+cap "GND" "a_1870_n1400#" 1.92409
+cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 51.2959
+cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.29458
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00059708
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0347718
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0532087
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.000755933
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.46628
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.294791
+cap "BIAS2" "a_1720_n1450#" 3.1891
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -8.89594e-05
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.04623
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.946276
cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "VDD" 3.44589
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "VDD" 3.44799
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 2.47329
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.304511
-cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.634132
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0959047
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.14231
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 4.35076
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.67125
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.386156
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.16434
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.765508
cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "V_RAMP" 0.665406
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.250446
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.42616
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.16434
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "VDD" 0.723246
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.386156
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.78021
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "V_RAMP" 1.39549
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.116892
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.54101
-cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.013366
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 8.02498
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.307507
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.355936
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.69157
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "VDD" 1.46409
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_RAMP" 0.79349
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.116892
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1000_n1450#" 0.582219
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.629827
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.946276
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.634132
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.39549
cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "VDD" 2.82762
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0143353
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.946276
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "a_1870_n1400#" 0.131148
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1870_n1400#" 0.14259
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.1684e-19
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.662542
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0782307
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "a_1870_n1400#" 0.0212796
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.212311
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.156473
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.634132
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.67125
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.00459401
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.274985
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 0.14231
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "VDD" 1.06702
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.75744
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.67915
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.909122
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.78021
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "VDD" 0.723246
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 2.47329
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.629827
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.000785002
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "VDD" 1.42616
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "VDD" 2.08846
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1000_n1450#" 0.250446
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" 6.25991
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.126567
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.307507
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "VDD" 1.22803
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1000_n1450#" 1.80077
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "VDD" 3.44799
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "VDD" 4.35076
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.013366
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.355936
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1000_n1450#" 0.157699
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.304511
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0959047
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.837499
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 8.02498
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_RAMP" 0.00495499
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0124444
+cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.54101
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "VDD" 1.32252
+cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "a_1000_n1450#" 0.00900749
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0212796
cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 4.63311
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14017
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.619119
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00448159
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1720_n1450#" -0.000573118
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.274985
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.03607
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.69157
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "a_1870_n1400#" 0.252891
-cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1870_n1400#" -0.000268858
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.679031
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "VDD" 5.43565
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.10139
-cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.38334
-cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.946276
-cap "VDD" "a_1720_n1450#" 5.25775
-cap "VDD" "BIAS2" 7.44072
cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.00785
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.75744
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.662542
+cap "VDD" "V_RAMP" 0.798811
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1720_n1450#" 0.482735
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.69157
+cap "a_1870_n1400#" "VDD" 6.73852
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.320955
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.634132
+cap "GND" "VDD" 3.37587
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.03607
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1720_n1450#" -0.000573118
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1720_n1450#" 0.124726
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00448159
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.946276
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.75744
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "V_RAMP" 1.14017
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.131148
cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 2.50816
-cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.484979
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.320955
-cap "VDD" "a_1870_n1400#" 6.73852
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.94462
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.156473
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 5.43565
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1720_n1450#" 0.978212
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.252891
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1870_n1400#" 0.14259
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0143353
cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 1.96995
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.978212
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00847102
-cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "VDD" 3.51812
-cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.68865
-cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 1.94462
-cap "V_RAMP" "VDD" 0.798811
+cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.484979
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 3.51812
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00847102
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.619119
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 7.10139
+cap "VDD" "BIAS2" 7.44072
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.679031
cap "VDD" "BIAS1" 0.769393
-cap "VDD" "GND" 3.37587
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.482735
-cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.124726
+cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000268858
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0782307
+cap "VDD" "a_1720_n1450#" 5.25775
+cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.946276
+cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.274985
+cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.1684e-19
+cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.68865
+cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.38334
+cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.212311
merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GRAY_INx3x" -46.2737 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "OUTx2x" -40.0623 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "GRAY_INx5x" -42.7679 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
diff --git a/mag/bias_cell.ext b/mag/bias_cell.ext
index d141a92..4b5be05 100644
--- a/mag/bias_cell.ext
+++ b/mag/bias_cell.ext
@@ -35,35 +35,35 @@
node "BIAS2" 1265 1302.36 7480 -100 m3 0 0 0 0 0 0 0 0 100000 2200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 200000 2400 200000 2400 200000 2400 320000 2640 0 0 0 0 0 0
node "VDD" 2412 3116.97 870 -670 m1 0 0 0 0 478400 2880 0 0 20000 600 18000 580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 524300 3660 567100 3200 567100 3200 0 0 0 0 0 0 0 0
substrate "GND" 0 0 1650 -1540 m1 0 0 0 0 0 0 0 0 508800 9788 224000 3480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5990160 21420 6080000 20280 0 0 0 0 0 0 0 0 0 0
-cap "VDD" "NB2" 38.6086
-cap "BIAS2_OUT" "ADC_ON" 44.6716
-cap "BIAS2" "SA_IREF" 5.24356
-cap "NB1" "SF_IB" 157.135
-cap "ADC_ON" "AMP_IB" 5.65145
-cap "OUT_IB" "SF_IB" 7.31142
-cap "ADC_ON" "SA_IREF_OUT" 57.427
-cap "VDD" "NB1" 228.289
-cap "AMP_IB" "OUT_IB" 363.273
-cap "VDD" "OUT_IB" 4.01869
-cap "ADC_ON" "SA_IREF" 125.1
-cap "ADC_ON" "BIAS1_OUT" 46.1075
-cap "VDD" "SF_IB" 881.118
-cap "BIAS1" "SA_IREF" 370.743
-cap "BIAS2_OUT" "AMP_IB" 438.248
-cap "BIAS2_OUT" "SA_IREF_OUT" 5.48191
-cap "BIAS1" "BIAS1_OUT" 1379.04
-cap "BIAS2_OUT" "BIAS1_OUT" 641.34
-cap "SA_IREF" "SA_IREF_OUT" 1380.98
-cap "BIAS2" "ADC_ON" 112.951
-cap "AMP_IB" "BIAS1_OUT" 13.6902
-cap "BIAS1_OUT" "SA_IREF_OUT" 584.146
-cap "NB1" "NB2" 394.385
+cap "BIAS2" "BIAS2_OUT" 1404.57
+cap "SA_IREF_OUT" "BIAS1_OUT" 584.146
cap "NB2" "OUT_IB" 284.092
+cap "SF_IB" "OUT_IB" 7.31142
+cap "BIAS2" "ADC_ON" 112.951
+cap "BIAS1" "SA_IREF" 370.743
+cap "VDD" "NB1" 228.289
+cap "BIAS2_OUT" "AMP_IB" 438.248
+cap "BIAS2" "SA_IREF" 5.24356
+cap "ADC_ON" "BIAS2_OUT" 44.6716
+cap "OUT_IB" "AMP_IB" 363.273
+cap "ADC_ON" "AMP_IB" 5.65145
+cap "BIAS1" "BIAS1_OUT" 1379.04
+cap "NB2" "VDD" 38.6086
+cap "SF_IB" "VDD" 881.118
+cap "BIAS2_OUT" "SA_IREF_OUT" 5.48191
+cap "ADC_ON" "SA_IREF_OUT" 57.427
+cap "OUT_IB" "VDD" 4.01869
+cap "SA_IREF" "ADC_ON" 125.1
cap "BIAS2" "BIAS1" 299.213
-cap "NB2" "SF_IB" 65.6885
-cap "BIAS2_OUT" "BIAS2" 1404.57
-cap "ADC_ON" "BIAS1" 113.78
-cap "NB1" "OUT_IB" 51.7575
+cap "NB2" "NB1" 394.385
+cap "SF_IB" "NB1" 157.135
+cap "SA_IREF" "SA_IREF_OUT" 1380.98
+cap "BIAS2_OUT" "BIAS1_OUT" 641.34
+cap "OUT_IB" "NB1" 51.7575
+cap "AMP_IB" "BIAS1_OUT" 13.6902
+cap "ADC_ON" "BIAS1_OUT" 46.1075
+cap "SF_IB" "NB2" 65.6885
+cap "BIAS1" "ADC_ON" 113.78
device msubckt sky130_fd_pr__nfet_01v8 9580 -1450 9581 -1449 l=200 w=100 "GND" "SA_IREF_OUT" 400 0 "GND" 100 0 "SA_IREF_OUT" 100 0
device msubckt sky130_fd_pr__nfet_01v8 8460 -1450 8461 -1449 l=200 w=84 "GND" "BIAS1_OUT" 400 0 "GND" 84 0 "BIAS1_OUT" 84 0
device msubckt sky130_fd_pr__nfet_01v8_lvt 7630 -1420 7631 -1419 l=200 w=200 "GND" "BIAS2_OUT" 400 0 "GND" 200 0 "BIAS2_OUT" 200 0
diff --git a/mag/dram_array.ext b/mag/dram_array.ext
index 425ef53..625c1a9 100644
--- a/mag/dram_array.ext
+++ b/mag/dram_array.ext
@@ -15,69 +15,69 @@
node "a_7_n377#" 197 433.627 7 -377 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5568 360 0 0 2244 200 12966 782 4888 284 31300 1160 0 0 0 0 0 0
node "a_60_n65#" 153 70.0959 60 -65 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2850 250 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "a_60_n65#" "li_230_20#" 1.49879
-cap "li_348_163#" "li_0_n280#" 0.0763167
-cap "li_230_20#" "li_228_n102#" 135.265
-cap "li_0_210#" "li_230_20#" 4.69797
-cap "li_230_20#" "li_0_n160#" 356.063
-cap "a_60_n65#" "li_348_163#" 0.307802
-cap "a_7_n377#" "li_230_20#" 51.809
-cap "li_348_163#" "li_228_n102#" 31.6351
-cap "li_0_210#" "li_348_163#" 17.3411
-cap "li_0_n280#" "li_228_n102#" 0.0667699
-cap "li_0_210#" "li_0_n280#" 0.876257
-cap "li_348_163#" "li_0_n160#" 52.348
cap "li_0_n280#" "li_0_n160#" 11.4979
-cap "a_7_n377#" "li_348_163#" 39.1482
-cap "a_7_n377#" "li_0_n280#" 13.0584
-cap "a_60_n65#" "li_228_n102#" 0.376524
+cap "li_0_n280#" "li_228_n102#" 0.0667699
+cap "li_0_210#" "a_7_n377#" 18.8088
+cap "li_348_163#" "li_0_210#" 17.3411
+cap "li_0_n160#" "a_7_n377#" 219.417
+cap "li_230_20#" "a_60_n65#" 1.49879
+cap "li_228_n102#" "a_7_n377#" 70.9593
+cap "li_0_n160#" "li_348_163#" 52.348
+cap "li_228_n102#" "li_348_163#" 31.6351
+cap "li_0_n280#" "a_7_n377#" 13.0584
+cap "li_0_n280#" "li_348_163#" 0.0763167
+cap "li_230_20#" "li_0_210#" 4.69797
+cap "li_230_20#" "li_0_n160#" 356.063
+cap "li_348_163#" "a_7_n377#" 39.1482
+cap "li_230_20#" "li_228_n102#" 135.265
+cap "li_0_n280#" "li_230_20#" 0.0696857
cap "a_60_n65#" "li_0_210#" 0.237529
-cap "li_0_210#" "li_228_n102#" 210.959
-cap "a_60_n65#" "li_0_n160#" 1.84898
-cap "li_228_n102#" "li_0_n160#" 62.9293
-cap "li_0_210#" "li_0_n160#" 140.81
+cap "li_230_20#" "a_7_n377#" 51.809
+cap "li_0_n160#" "a_60_n65#" 1.84898
+cap "li_230_20#" "li_348_163#" 102.311
+cap "li_228_n102#" "a_60_n65#" 0.376524
+cap "li_0_n160#" "li_0_210#" 140.81
+cap "li_228_n102#" "li_0_210#" 210.959
cap "a_60_n65#" "a_7_n377#" 2.76266
-cap "a_7_n377#" "li_228_n102#" 70.9593
-cap "a_7_n377#" "li_0_210#" 18.8088
-cap "li_348_163#" "li_230_20#" 102.311
-cap "a_7_n377#" "li_0_n160#" 219.417
-cap "li_230_20#" "li_0_n280#" 0.0696857
-cap "dram_cell_1/RWL" "dram_cell_1/WWL" 2.18712
-cap "dram_cell_0/WBL" "dram_cell_0/RBL" 2.53837
-cap "dram_cell_1/RWL" "dram_cell_1/WBL" 6.14084
-cap "dram_cell_1/RWL" "dram_cell_0/WBL" 0.33996
-cap "dram_cell_0/RWL" "dram_cell_0/RBL" 13.0238
-cap "dram_cell_0/RBL" "dram_cell_0/storage" 15.4855
-cap "dram_cell_0/RWL" "dram_cell_1/RWL" 20.2535
-cap "dram_cell_1/RBL" "dram_cell_0/RBL" 11.5227
-cap "dram_cell_1/RWL" "dram_cell_0/storage" 0.429482
-cap "dram_cell_1/WBL" "dram_cell_1/WWL" 14.9871
-cap "dram_cell_0/WBL" "dram_cell_1/WWL" 2.89656
-cap "dram_cell_1/RWL" "dram_cell_1/RBL" -0.516477
-cap "dram_cell_0/WBL" "dram_cell_1/WBL" 14.7197
-cap "dram_cell_1/storage" "dram_cell_0/RBL" 11.4474
-cap "dram_cell_1/WWL" "dram_cell_0/storage" 7.63897
-cap "dram_cell_0/RWL" "dram_cell_1/WWL" 4.75772
-cap "dram_cell_1/RWL" "dram_cell_1/storage" 0.436311
-cap "dram_cell_0/RWL" "dram_cell_1/WBL" 1.40204
-cap "dram_cell_1/WBL" "dram_cell_0/storage" 12.9481
-cap "dram_cell_1/RBL" "dram_cell_1/WWL" 3.07768
-cap "dram_cell_1/RBL" "dram_cell_1/WBL" 3.6311
-cap "dram_cell_0/RWL" "dram_cell_0/WBL" 1.94476
-cap "dram_cell_0/WBL" "dram_cell_0/storage" 37.4231
-cap "dram_cell_0/WBL" "dram_cell_1/RBL" 0.633176
-cap "dram_cell_1/storage" "dram_cell_1/WWL" 54.3891
-cap "dram_cell_0/RWL" "dram_cell_0/storage" 11.5727
+cap "li_0_n280#" "li_0_210#" 0.876257
+cap "li_348_163#" "a_60_n65#" 0.307802
+cap "li_0_n160#" "li_228_n102#" 62.9293
+cap "dram_cell_1/storage" "dram_cell_1/RWL" 0.436311
+cap "dram_cell_0/storage" "dram_cell_1/RWL" 0.429482
cap "dram_cell_1/storage" "dram_cell_1/WBL" 4.40135
-cap "dram_cell_1/RWL" "dram_cell_0/RBL" 4.35185
-cap "dram_cell_0/RWL" "dram_cell_1/RBL" 3.16207
-cap "dram_cell_1/RBL" "dram_cell_0/storage" 7.25935
+cap "dram_cell_1/WBL" "dram_cell_0/storage" 12.9481
cap "dram_cell_1/storage" "dram_cell_0/WBL" 0.986025
-cap "dram_cell_0/RWL" "dram_cell_1/storage" 5.05907
-cap "dram_cell_1/storage" "dram_cell_0/storage" 32.2037
-cap "dram_cell_0/RBL" "dram_cell_1/WWL" 3.28261
-cap "dram_cell_0/RBL" "dram_cell_1/WBL" 0.608887
cap "dram_cell_1/storage" "dram_cell_1/RBL" 7.34975
+cap "dram_cell_1/WWL" "dram_cell_0/RBL" 3.28261
+cap "dram_cell_0/storage" "dram_cell_1/RBL" 7.25935
+cap "dram_cell_0/WBL" "dram_cell_0/storage" 37.4231
+cap "dram_cell_1/WWL" "dram_cell_0/RWL" 4.75772
+cap "dram_cell_1/WBL" "dram_cell_1/RWL" 6.14084
+cap "dram_cell_0/RWL" "dram_cell_0/RBL" 13.0238
+cap "dram_cell_0/WBL" "dram_cell_1/RWL" 0.33996
+cap "dram_cell_1/RWL" "dram_cell_1/RBL" -0.516477
+cap "dram_cell_1/storage" "dram_cell_1/WWL" 54.3891
+cap "dram_cell_1/WBL" "dram_cell_1/RBL" 3.6311
+cap "dram_cell_0/WBL" "dram_cell_1/WBL" 14.7197
+cap "dram_cell_1/WWL" "dram_cell_0/storage" 7.63897
+cap "dram_cell_0/WBL" "dram_cell_1/RBL" 0.633176
+cap "dram_cell_1/storage" "dram_cell_0/RBL" 11.4474
+cap "dram_cell_0/storage" "dram_cell_0/RBL" 15.4855
+cap "dram_cell_1/storage" "dram_cell_0/RWL" 5.05907
+cap "dram_cell_1/WWL" "dram_cell_1/RWL" 2.18712
+cap "dram_cell_0/RWL" "dram_cell_0/storage" 11.5727
+cap "dram_cell_1/WWL" "dram_cell_1/WBL" 14.9871
+cap "dram_cell_0/RBL" "dram_cell_1/RWL" 4.35185
+cap "dram_cell_1/WWL" "dram_cell_1/RBL" 3.07768
+cap "dram_cell_1/WWL" "dram_cell_0/WBL" 2.89656
+cap "dram_cell_1/storage" "dram_cell_0/storage" 32.2037
+cap "dram_cell_1/WBL" "dram_cell_0/RBL" 0.608887
+cap "dram_cell_0/RWL" "dram_cell_1/RWL" 20.2535
+cap "dram_cell_0/RWL" "dram_cell_1/WBL" 1.40204
+cap "dram_cell_0/RBL" "dram_cell_1/RBL" 11.5227
+cap "dram_cell_0/WBL" "dram_cell_0/RBL" 2.53837
+cap "dram_cell_0/RWL" "dram_cell_1/RBL" 3.16207
+cap "dram_cell_0/RWL" "dram_cell_0/WBL" 1.94476
merge "dram_cell_0/RWL" "li_348_163#" -106.118 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3518 -294 0 0 0 0 0 0 0 0 0 0 0 0
merge "dram_cell_0/VSUBS" "dram_cell_1/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
merge "dram_cell_1/VSUBS" "VSUBS"
diff --git a/mag/dram_cell.ext b/mag/dram_cell.ext
index 6a3a496..9b9d843 100644
--- a/mag/dram_cell.ext
+++ b/mag/dram_cell.ext
@@ -16,15 +16,15 @@
node "WWL" 418 57.7445 33 154 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7800 580 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
node "storage" 995 217.734 132 186 li 0 0 0 0 0 0 0 0 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11274 754 0 0 19600 1028 0 0 0 0 0 0 0 0 0 0 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "RWL" "RBL" 90.6652
-cap "WWL" "storage" 5.46676
-cap "RWL" "WBL" 0.303046
-cap "WBL" "RBL" 0.381765
-cap "RWL" "WWL" 0.0898708
-cap "RWL" "storage" 3.30838
-cap "RBL" "WWL" 0.203425
-cap "RBL" "storage" 116.972
cap "WBL" "WWL" 0.092861
-cap "WBL" "storage" 90.7551
+cap "RBL" "WBL" 0.381765
+cap "RWL" "storage" 3.30838
+cap "RWL" "WBL" 0.303046
+cap "RBL" "WWL" 0.203425
+cap "storage" "WBL" 90.7551
+cap "RWL" "WWL" 0.0898708
+cap "RWL" "RBL" 90.6652
+cap "storage" "WWL" 5.46676
+cap "RBL" "storage" 116.972
device msubckt sky130_fd_pr__nfet_01v8 250 -70 251 -69 l=30 w=200 "VSUBS" "storage" 60 0 "RBL" 200 0 "RWL" 200 0
device msubckt sky130_fd_pr__nfet_01v8 20 -70 21 -69 l=30 w=200 "VSUBS" "WWL" 60 0 "WBL" 200 0 "storage" 200 0
diff --git a/mag/sens_amp.ext b/mag/sens_amp.ext
index 812c4c1..f3cc8a3 100644
--- a/mag/sens_amp.ext
+++ b/mag/sens_amp.ext
@@ -21,34 +21,34 @@
node "GN" 2690 1245.57 640 -2220 ndif 0 0 0 0 0 0 0 0 58000 1820 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65100 1560 0 0 82100 2940 117110 4770 0 0 0 0 0 0 0 0 0 0
node "VDD" 10051 2635.35 600 600 m1 0 0 0 0 680000 4680 0 0 52400 1080 72000 2440 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 119000 4000 68000 1080 0 0 0 0 0 0 0 0 0 0
substrate "GND" 0 0 660 -2940 m1 0 0 0 0 0 0 0 0 24000 940 27200 840 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51200 1600 85048 1848 87856 4016 0 0 0 0 0 0 0 0
-cap "GN" "SA_IREF" 34.4763
-cap "GN" "net2" 393.9
-cap "VDD" "V_IN" 164.427
-cap "OUT" "net1" 161.173
-cap "OUT" "SA_IREF" 35.7969
-cap "OUT" "net2" 43.4476
-cap "GN" "VDD" 438.341
-cap "SA_IREF" "net1" 4.48275
-cap "net2" "net1" 396.364
-cap "OUT" "VDD" 196.007
-cap "SA_IREF" "net2" 17.5566
-cap "REF" "V_IN" 80.4455
-cap "VDD" "net1" 349.364
-cap "SA_IREF" "VDD" 0.012455
-cap "REF" "GN" 127.538
-cap "VDD" "net2" 1.46875
-cap "REF" "OUT" 48.6315
-cap "GN" "V_IN" 35.1114
+cap "net2" "VDD" 1.46875
+cap "V_IN" "OUT" 97.9036
cap "REF" "net1" 21.5495
-cap "REF" "SA_IREF" 123.24
-cap "OUT" "V_IN" 97.9036
-cap "REF" "net2" 31.1038
-cap "V_IN" "net1" 209.966
cap "OUT" "GN" 114.567
-cap "SA_IREF" "V_IN" 12.1123
+cap "SA_IREF" "OUT" 35.7969
+cap "V_IN" "GN" 35.1114
+cap "V_IN" "SA_IREF" 12.1123
cap "REF" "VDD" 9.96654
+cap "REF" "net2" 31.1038
+cap "SA_IREF" "GN" 34.4763
+cap "net1" "OUT" 161.173
+cap "V_IN" "net1" 209.966
+cap "OUT" "VDD" 196.007
+cap "net1" "GN" 638.65
+cap "SA_IREF" "net1" 4.48275
+cap "V_IN" "VDD" 164.427
+cap "net2" "OUT" 43.4476
cap "V_IN" "net2" 30.474
-cap "GN" "net1" 638.65
+cap "VDD" "GN" 438.341
+cap "SA_IREF" "VDD" 0.012455
+cap "net2" "GN" 393.9
+cap "SA_IREF" "net2" 17.5566
+cap "REF" "OUT" 48.6315
+cap "REF" "V_IN" 80.4455
+cap "REF" "GN" 127.538
+cap "REF" "SA_IREF" 123.24
+cap "net1" "VDD" 349.364
+cap "net2" "net1" 396.364
device msubckt sky130_fd_pr__nfet_01v8_lvt 730 -2660 731 -2659 l=200 w=100 "GND" "SA_IREF" 400 0 "GND" 100 0 "net2" 100 0
device msubckt sky130_fd_pr__nfet_01v8_lvt 820 -2220 821 -2219 l=30 w=800 "GND" "V_IN" 60 0 "net2" 800 0 "net1" 800 0
device msubckt sky130_fd_pr__nfet_01v8_lvt 710 -2220 711 -2219 l=30 w=800 "GND" "REF" 60 0 "GN" 800 0 "net2" 800 0
diff --git a/mag/user_analog_project_wrapper.ext b/mag/user_analog_project_wrapper.ext
index 249ba75..97b225c 100644
--- a/mag/user_analog_project_wrapper.ext
+++ b/mag/user_analog_project_wrapper.ext
@@ -1,4 +1,4 @@
-timestamp 1662151999
+timestamp 1662155535
version 8.3
tech sky130B
style ngspice()
@@ -79,9 +79,9 @@
port "vssa1" 565 582340 136830 584800 141630 m3
port "vssa1" 564 582340 146830 584800 151630 m3
port "vssd1" 569 582340 181430 584800 186230 m3
-port "vssd1" 568 582340 191430 584800 196230 m3
port "vssd2" 571 0 162888 1660 167688 m3
port "vssd2" 570 0 172888 1660 177688 m3
+port "vssd1" 568 582340 191430 584800 196230 m3
port "vdda1" 559 582340 225230 584800 230030 m3
port "vdda1" 558 582340 235230 584800 240030 m3
port "gpio_analog[0]" 0 583520 269230 584800 269342 m3
@@ -769,10 +769,9 @@
node "vssa1" 0 5994.57 582340 136830 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vssa1" 0 5994.57 582340 146830 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vssd1" 0 5994.57 582340 181430 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "vssd1" 0 5994.57 582340 191430 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vssd2" 0 7639.02 0 162888 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15628380 17626 0 0 0 0 0 0
node "vssd2" 0 5994.57 0 172888 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
-node "m3_51655_199490#" 1 226.375 51655 199490 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89600 2700 0 0 0 0 0 0
+node "vssd1" 0 5994.57 582340 191430 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vdda1" 0 5994.57 582340 225230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "vdda1" 0 5994.57 582340 235230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11808000 14520 0 0 0 0 0 0
node "gpio_analog[0]" 1 524.737 583520 269230 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
@@ -827,13 +826,13 @@
node "io_in[20]" 1 493.355 -800 248852 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in_3v3[20]" 1 493.355 -800 250034 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "gpio_noesd[13]" 1 493.355 -800 251216 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
-node "gpio_analog[13]" 1 524.737 -800 252398 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_analog[13]" 0 33602.9 -800 252398 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3996062 74540 4884744 139704 0 0 0 0
node "io_oeb[19]" 1 524.737 -800 289510 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_out[19]" 1 493.355 -800 290692 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in[19]" 1 493.355 -800 291874 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in_3v3[19]" 1 493.355 -800 293056 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "gpio_noesd[12]" 1 493.355 -800 294238 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
-node "gpio_analog[12]" 1 524.737 -800 295420 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
+node "gpio_analog[12]" 0 52449.6 -800 295420 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4352416 80074 6639552 221340 0 0 0 0
node "io_oeb[18]" 1 524.737 -800 332732 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_out[18]" 1 493.355 -800 333914 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
node "io_in[18]" 1 493.355 -800 335096 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 143360 2784 0 0 0 0 0 0
@@ -1380,7 +1379,7 @@
node "m2_55523_202892#" 1 328.021 55523 202892 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11584 508 13200 460 40056 1454 0 0 0 0
node "m2_54833_202912#" 1 205.7 54833 202912 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12784 548 9900 400 23136 890 0 0 0 0
node "m2_54170_202730#" 1 224.617 54170 202730 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17292 534 17418 536 19776 778 0 0 0 0
-node "m2_53493_202942#" 1 210.588 53493 202942 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 628 12000 440 29616 1106 0 0 0 0
+node "m2_53493_202942#" 1 209.848 53493 202942 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15184 628 12000 440 29616 1106 0 0 0 0
node "m2_54520_202790#" 2 137.546 54520 202790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18470 1188 0 0 0 0 0 0 0 0
node "m2_55208_202785#" 1 61.8604 55208 202785 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13752 692 0 0 0 0 0 0 0 0
node "m2_53840_202790#" 3 77.9433 53840 202790 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32400 1700 0 0 0 0 0 0 0 0
@@ -1389,2497 +1388,2526 @@
node "la_data_in[122]" 16 263082 558428 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1134072 24152 57016 1320 204800 2560 230294528 1439952 0 0
node "la_data_in[124]" 20 279711 565520 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1015352 25092 36416 1080 204800 2560 237509568 1485046 0 0
node "la_data_in[126]" 25 290738 572612 -800 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1125912 29612 44416 1180 204800 2560 243689088 1523668 0 0
-node "m2_34420_199220#" 2 167592 34420 199220 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40770400 1014420 526200 9260 0 0 0 0 0 0
+node "m2_34420_199220#" 2 167289 34420 199220 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40770400 1014420 526200 9260 0 0 0 0 0 0
node "m2_33290_207480#" 0 135557 33290 207480 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38580000 964660 1536576 51338 0 0 0 0 0 0
node "io_analog[10]" 0 36628.6 0 680242 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 53231170 65142 20750000 21600 0 0 0 0 0 0
node "io_analog[6]" 0 101230 165594 702300 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6244920 9996 158693890 301340 25275000 25220 0 0 0 0
-node "m1_49580_204344#" 24 151166 49580 204344 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 262920 8884 39701400 992860 59400 1360 1140768 38142 0 0 0 0
+node "m1_49580_204344#" 24 151024 49580 204344 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 262920 8884 39701400 992860 59400 1360 1140768 38142 0 0 0 0
node "vccd1" 0 2.0063e+06 582340 639784 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1256388700 1069330 1239652700 993160 2892727300 1960740 0 0 0 0 0 0
-node "vssa2" 0 813276 0 559442 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75036427 208680 34002391 62844 332296207 305910 1870720968 1510314 0 0 0 0
+node "vssa2" 0 856448 0 559442 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 75036427 208680 34002391 62844 464395276 446826 1827315934 1475024 0 0 0 0
node "vccd2" 1 232955 0 643842 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9203100 13140 9203100 13140 247956140 230800 12976664 27088 472105605 378896 0 0
substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-cap "io_in_3v3[14]" "gpio_noesd[7]" 67.2299
-cap "vssa2" "vccd1" 6.18595
-cap "la_data_out[11]" "la_data_in[11]" 46.7738
-cap "la_oenb[46]" "la_data_out[46]" 46.7738
-cap "la_data_in[124]" "la_data_in[126]" 587.278
-cap "m2_53160_202790#" "m2_54170_202730#" 3.72999
-cap "la_oenb[108]" "la_data_in[109]" 46.7738
-cap "gpio_analog[4]" "gpio_noesd[4]" 67.2299
-cap "wbs_sel_i[0]" "wbs_adr_i[1]" 46.7738
-cap "la_oenb[46]" "la_data_in[47]" 46.7738
-cap "la_data_in[122]" "la_data_in[126]" 12.9992
-cap "la_data_out[82]" "la_oenb[82]" 46.7738
-cap "m2_53493_202942#" "m2_54170_202730#" 28.1398
-cap "la_data_in[126]" "la_oenb[125]" 46.7738
-cap "gpio_analog[15]" "gpio_noesd[15]" 67.2299
-cap "io_in_3v3[4]" "io_oeb[3]" 67.2299
-cap "m2_54170_202730#" "m2_54833_202912#" 39.2811
-cap "la_oenb[80]" "la_data_out[80]" 46.7738
-cap "io_analog[6]" "io_analog[6]" 22388.4
-cap "la_data_in[82]" "la_data_out[82]" 46.7738
-cap "io_oeb[4]" "io_out[4]" 67.2299
-cap "la_oenb[80]" "la_data_in[81]" 46.7738
-cap "la_oenb[47]" "la_data_in[48]" 46.7738
-cap "la_data_out[81]" "la_data_in[81]" 46.7738
-cap "m2_53493_202942#" "m2_53160_202790#" 113.43
-cap "la_data_out[11]" "la_oenb[11]" 46.7738
-cap "la_oenb[45]" "la_data_out[45]" 46.7738
-cap "la_data_out[47]" "la_data_in[47]" 46.7738
-cap "la_oenb[81]" "la_data_out[81]" 46.7738
-cap "la_data_out[8]" "la_data_out[7]" 37030.3
-cap "m2_53160_202790#" "m2_54833_202912#" 1.04826
-cap "la_oenb[105]" "la_data_out[105]" 46.7738
-cap "la_data_in[82]" "la_oenb[81]" 46.7738
-cap "la_data_out[6]" "la_data_out[7]" 38749.5
-cap "la_oenb[104]" "la_data_out[104]" 46.7738
-cap "io_analog[5]" "io_clamp_low[1]" 735.436
-cap "m2_53493_202942#" "m2_54833_202912#" 8.08772
-cap "la_oenb[108]" "la_data_out[108]" 46.7738
-cap "m2_54520_202790#" "m2_54170_202730#" 15.5886
-cap "wbs_cyc_i" "wbs_stb_i" 46.7738
-cap "la_data_out[13]" "la_data_in[13]" 46.7738
-cap "wb_clk_i" "wb_rst_i" 46.7738
-cap "la_data_out[2]" "la_data_in[2]" 46.7738
-cap "la_data_out[2]" "la_oenb[2]" 46.7738
-cap "la_oenb[11]" "la_data_in[12]" 46.7738
-cap "la_data_in[53]" "la_oenb[52]" 46.7738
-cap "la_oenb[104]" "la_data_in[105]" 46.7738
-cap "la_data_out[58]" "la_data_in[58]" 46.7738
-cap "wbs_adr_i[0]" "wbs_dat_i[0]" 46.7738
-cap "la_oenb[47]" "la_data_out[47]" 46.7738
-cap "la_oenb[10]" "la_data_in[11]" 46.7738
-cap "la_data_in[109]" "la_data_out[109]" 46.7738
-cap "m1_49580_204344#" "gpio_analog[7]" 160.193
-cap "la_data_out[6]" "la_data_out[5]" 40267.9
-cap "la_data_out[66]" "la_oenb[66]" 46.7738
-cap "m2_53493_202942#" "m2_54520_202790#" 2.14488
-cap "la_data_in[65]" "la_data_out[65]" 46.7738
-cap "io_analog[4]" "vccd2" 1212.09
-cap "io_out[2]" "io_oeb[2]" 67.2299
-cap "m2_54520_202790#" "m2_54833_202912#" 32.9276
-cap "la_data_in[105]" "la_data_out[105]" 46.7738
-cap "la_data_in[107]" "la_oenb[106]" 46.7738
-cap "io_in_3v3[8]" "gpio_noesd[1]" 67.2299
-cap "m1_49580_204344#" "io_analog[5]" 0.690053
-cap "la_data_out[12]" "la_data_in[12]" 46.7738
-cap "vccd2" "io_analog[6]" 12755
-cap "la_data_in[124]" "io_analog[2]" 1.4621
-cap "la_data_out[113]" "la_oenb[113]" 46.7738
-cap "la_data_out[12]" "la_oenb[12]" 46.7738
-cap "gpio_analog[11]" "gpio_noesd[11]" 67.2299
-cap "io_analog[2]" "la_data_in[122]" 1.4621
-cap "la_data_out[43]" "la_data_in[43]" 46.7738
-cap "la_data_out[118]" "la_data_in[118]" 46.7738
-cap "la_data_in[125]" "la_data_in[123]" 980.991
-cap "io_analog[2]" "m2_54170_202730#" 0.161373
-cap "m2_55208_202785#" "vccd1" 6.16121
-cap "la_oenb[57]" "la_data_in[58]" 46.7738
-cap "la_data_out[4]" "la_data_out[3]" 43187.7
-cap "la_data_out[43]" "la_oenb[43]" 46.7738
-cap "wbs_dat_i[2]" "wbs_dat_o[2]" 46.7738
-cap "la_oenb[7]" "la_data_out[7]" 46.7738
-cap "la_data_out[55]" "la_data_in[55]" 46.7738
-cap "la_data_out[111]" "la_oenb[111]" 46.7738
-cap "la_data_in[123]" "vccd1" 2112.75
-cap "la_data_in[8]" "la_data_out[8]" 46.7738
-cap "io_clamp_high[1]" "io_analog[5]" 468.333
-cap "io_oeb[0]" "io_in_3v3[1]" 67.2299
-cap "io_analog[2]" "m2_53160_202790#" 0.362355
-cap "la_data_out[60]" "la_data_in[60]" 46.7738
-cap "la_oenb[8]" "la_data_out[8]" 46.7738
-cap "la_oenb[12]" "la_data_in[13]" 46.7738
-cap "io_in_3v3[10]" "gpio_noesd[3]" 67.2299
-cap "m2_53493_202942#" "io_analog[2]" 0.227745
-cap "io_analog[2]" "la_data_in[126]" 1.4621
-cap "io_in[26]" "io_in_3v3[26]" 67.2299
-cap "io_analog[2]" "m2_54833_202912#" 0.147405
-cap "la_oenb[43]" "la_data_in[44]" 46.7738
-cap "la_data_in[108]" "la_data_out[108]" 46.7738
-cap "la_data_in[107]" "la_data_out[107]" 46.7738
-cap "la_data_in[7]" "la_data_out[7]" 46.7738
-cap "la_data_in[5]" "la_data_out[5]" 46.7738
-cap "la_data_out[45]" "la_data_in[45]" 46.7738
-cap "la_data_out[5]" "la_oenb[5]" 46.7738
-cap "la_data_out[2]" "la_data_out[3]" 23122.2
-cap "io_analog[2]" "m2_54520_202790#" 0.165659
-cap "la_data_out[107]" "la_oenb[107]" 46.7738
-cap "la_data_out[122]" "la_oenb[122]" 46.7738
-cap "la_data_in[111]" "la_data_out[111]" 46.7738
-cap "la_data_out[6]" "la_data_in[6]" 46.7738
-cap "la_data_out[6]" "la_oenb[6]" 46.7738
-cap "la_data_in[9]" "la_oenb[8]" 46.7738
-cap "la_data_in[43]" "la_oenb[42]" 46.7738
-cap "la_data_in[9]" "la_data_out[9]" 46.7738
-cap "io_analog[5]" "io_analog[5]" 22388.4
-cap "la_data_out[9]" "la_oenb[9]" 46.7738
-cap "la_oenb[10]" "la_data_out[10]" 46.7738
-cap "la_data_out[44]" "la_data_in[44]" 46.7738
-cap "la_data_in[108]" "la_oenb[107]" 46.7738
-cap "la_data_out[117]" "la_oenb[117]" 46.7738
-cap "la_data_in[8]" "la_oenb[7]" 46.7738
-cap "la_oenb[9]" "la_data_in[10]" 46.7738
-cap "vssa2" "vccd2" 88369.5
-cap "la_data_out[44]" "la_oenb[44]" 46.7738
-cap "vccd2" "io_analog[8]" 781.607
-cap "la_data_out[10]" "la_data_in[10]" 46.7738
-cap "io_out[5]" "io_oeb[5]" 67.2299
-cap "la_data_in[45]" "la_oenb[44]" 46.7738
-cap "wbs_sel_i[0]" "wbs_dat_o[0]" 46.7738
-cap "la_data_in[115]" "la_data_out[115]" 46.7738
-cap "io_in[24]" "io_in_3v3[24]" 67.2299
-cap "io_analog[5]" "io_clamp_low[1]" 493.833
-cap "la_data_in[5]" "la_oenb[4]" 46.7738
-cap "io_analog[5]" "io_analog[5]" 26259.4
-cap "io_out[14]" "io_in[14]" 67.2299
-cap "la_data_in[127]" "la_oenb[126]" 46.7738
-cap "io_in[16]" "io_out[16]" 67.2299
-cap "m3_51655_199490#" "m2_34420_199220#" 286.62
-cap "la_data_out[123]" "la_data_in[123]" 46.7738
-cap "la_data_in[101]" "la_data_out[101]" 46.7738
-cap "io_out[3]" "io_in[3]" 67.2299
-cap "la_oenb[3]" "la_data_in[4]" 46.7738
-cap "la_oenb[5]" "la_data_in[6]" 46.7738
-cap "la_oenb[83]" "la_data_out[83]" 46.7738
-cap "io_analog[7]" "vccd2" 10115.8
-cap "la_data_out[59]" "la_oenb[59]" 46.7738
-cap "io_out[15]" "io_oeb[15]" 67.2299
-cap "io_out[6]" "io_in[6]" 67.2299
-cap "la_data_in[84]" "la_oenb[83]" 46.7738
-cap "io_analog[6]" "io_clamp_low[2]" 493.833
-cap "la_data_in[7]" "la_oenb[6]" 46.7738
-cap "la_data_out[40]" "la_oenb[40]" 46.7738
-cap "io_out[7]" "io_in[7]" 67.2299
-cap "la_data_out[100]" "la_oenb[100]" 46.7738
-cap "io_in_3v3[24]" "gpio_noesd[17]" 67.2299
-cap "gpio_analog[3]" "gpio_noesd[3]" 67.2299
-cap "m1_49580_204344#" "vccd1" 0.88795
-cap "la_oenb[40]" "la_data_in[41]" 46.7738
-cap "io_in[23]" "io_in_3v3[23]" 67.2299
-cap "la_oenb[0]" "la_data_out[0]" 46.7738
-cap "la_data_out[120]" "la_data_in[120]" 46.7738
-cap "la_data_in[120]" "la_data_in[121]" 86330.4
-cap "la_data_out[62]" "la_oenb[62]" 46.7738
-cap "la_data_in[41]" "la_data_out[41]" 46.7738
-cap "la_data_in[111]" "la_oenb[110]" 46.7738
-cap "la_data_in[127]" "la_data_in[120]" 0.481245
-cap "la_data_out[84]" "la_data_in[84]" 46.7738
-cap "io_analog[4]" "m2_33290_207480#" 2.08078
-cap "la_oenb[0]" "la_data_in[1]" 46.7738
-cap "io_analog[4]" "io_analog[4]" 26922
-cap "la_oenb[42]" "la_data_out[42]" 46.7738
-cap "la_data_in[120]" "la_oenb[119]" 46.7738
-cap "io_out[1]" "io_oeb[1]" 67.2299
-cap "la_data_out[0]" "la_data_in[0]" 46.7738
-cap "io_in_3v3[7]" "io_in[7]" 67.2299
-cap "la_oenb[41]" "la_data_out[41]" 46.7738
-cap "io_out[10]" "io_in[10]" 67.2299
-cap "la_data_in[121]" "m2_33290_207480#" 3.42049
-cap "la_oenb[1]" "la_data_in[2]" 46.7738
-cap "la_data_out[115]" "la_oenb[115]" 46.7738
-cap "la_data_out[40]" "la_data_in[40]" 46.7738
-cap "la_oenb[41]" "la_data_in[42]" 46.7738
-cap "la_data_in[3]" "la_oenb[2]" 46.7738
-cap "la_data_in[127]" "m2_33290_207480#" 3.28801
-cap "io_in_3v3[6]" "io_in[6]" 67.2299
-cap "la_data_in[83]" "la_data_out[83]" 46.7738
-cap "la_oenb[114]" "la_data_out[114]" 46.7738
-cap "gpio_analog[17]" "gpio_noesd[17]" 67.2299
-cap "wbs_adr_i[30]" "wbs_dat_o[29]" 46.7738
-cap "la_oenb[63]" "la_data_in[64]" 46.7738
-cap "wbs_dat_i[30]" "wbs_adr_i[30]" 46.7738
-cap "la_data_in[42]" "la_data_out[42]" 46.7738
-cap "gpio_analog[6]" "gpio_noesd[6]" 67.2299
-cap "wbs_stb_i" "wbs_we_i" 46.7738
-cap "wbs_dat_i[30]" "wbs_dat_o[30]" 46.7738
-cap "io_analog[6]" "io_clamp_high[2]" 493.833
-cap "vccd2" "m3_26500_684896#" 205.187
-cap "wbs_dat_o[31]" "la_data_in[0]" 46.7738
-cap "la_data_in[112]" "la_data_out[112]" 46.7738
-cap "wbs_adr_i[31]" "wbs_dat_o[30]" 46.7738
-cap "la_data_in[110]" "la_data_out[110]" 46.7738
-cap "wbs_dat_i[31]" "wbs_adr_i[31]" 46.7738
-cap "wbs_dat_i[29]" "wbs_dat_o[29]" 46.7738
-cap "la_data_out[56]" "la_oenb[56]" 46.7738
-cap "vssa2" "la_data_out[4]" 893.783
-cap "wbs_dat_i[31]" "wbs_dat_o[31]" 46.7738
-cap "vccd2" "gpio_analog[7]" 743.088
-cap "la_data_in[125]" "vccd1" 2064.36
-cap "la_oenb[51]" "la_data_in[52]" 46.7738
-cap "la_oenb[110]" "la_data_out[110]" 46.7738
-cap "vccd2" "io_analog[5]" 2114.88
-cap "la_oenb[3]" "la_data_out[3]" 46.7738
-cap "io_in[3]" "io_in_3v3[3]" 67.2299
-cap "la_data_in[127]" "la_data_out[127]" 46.7738
-cap "la_data_out[2]" "la_data_out[1]" 27417.9
-cap "io_analog[4]" "io_clamp_high[0]" 468.333
-cap "io_analog[4]" "io_clamp_high[0]" 493.833
-cap "io_in[16]" "io_in_3v3[16]" 67.2299
-cap "wbs_adr_i[27]" "wbs_dat_i[27]" 46.7738
-cap "la_oenb[59]" "la_data_in[60]" 46.7738
-cap "la_data_in[124]" "la_data_in[121]" 17.9665
-cap "la_data_in[3]" "la_data_out[3]" 46.7738
-cap "vssa2" "m2_33290_207480#" 4013.42
-cap "wbs_dat_o[1]" "wbs_sel_i[1]" 46.7738
-cap "la_data_in[124]" "la_data_in[127]" 50.9691
-cap "la_data_in[122]" "la_data_in[121]" 49581.4
-cap "wbs_dat_o[27]" "wbs_dat_i[27]" 46.7738
-cap "wbs_adr_i[29]" "wbs_dat_i[29]" 46.7738
-cap "la_data_out[2]" "vssa2" 870.097
-cap "wbs_dat_o[26]" "wbs_adr_i[27]" 46.7738
-cap "la_data_in[127]" "la_data_in[122]" 41.1623
-cap "wbs_dat_o[27]" "wbs_adr_i[28]" 46.7738
-cap "wbs_dat_i[28]" "wbs_adr_i[28]" 46.7738
-cap "vssa2" "io_analog[10]" 2072.82
-cap "wbs_dat_o[28]" "wbs_dat_i[28]" 46.7738
-cap "io_analog[6]" "io_analog[6]" 26259.4
-cap "la_data_in[121]" "la_data_in[126]" 9.37546
-cap "wbs_dat_o[28]" "wbs_adr_i[29]" 46.7738
-cap "la_data_out[86]" "la_data_in[86]" 46.7738
-cap "la_data_out[98]" "la_oenb[98]" 46.7738
-cap "la_data_in[127]" "la_data_in[126]" 27401.1
-cap "la_data_out[59]" "la_data_in[59]" 46.7738
-cap "la_oenb[124]" "la_data_in[125]" 46.7738
-cap "wbs_dat_i[24]" "wbs_dat_o[24]" 46.7738
-cap "io_out[25]" "io_in[25]" 67.2299
-cap "la_data_in[40]" "la_oenb[39]" 46.7738
-cap "m1_49580_204344#" "vccd2" 394.016
-cap "wbs_dat_o[24]" "wbs_adr_i[25]" 46.7738
-cap "io_in_3v3[15]" "io_in[15]" 67.2299
-cap "la_oenb[37]" "la_data_in[38]" 46.7738
-cap "io_in[4]" "io_in_3v3[4]" 67.2299
-cap "wbs_adr_i[1]" "wbs_dat_i[1]" 46.7738
-cap "io_analog[9]" "vssa2" 1623.5
-cap "wbs_adr_i[25]" "wbs_dat_i[25]" 46.7738
-cap "m2_55208_202785#" "m2_55523_202892#" 32.4727
-cap "la_oenb[86]" "la_data_out[86]" 46.7738
-cap "io_analog[9]" "io_analog[8]" 1693.25
-cap "gpio_analog[0]" "gpio_noesd[0]" 67.2299
-cap "io_in[8]" "io_in_3v3[8]" 67.2299
-cap "gpio_noesd[11]" "io_in_3v3[18]" 67.2299
-cap "la_data_in[120]" "la_data_in[123]" 6.54701
-cap "wbs_dat_o[25]" "wbs_dat_i[25]" 46.7738
-cap "wbs_dat_o[26]" "wbs_dat_i[26]" 46.7738
-cap "la_oenb[84]" "la_data_in[85]" 46.7738
-cap "m2_53840_202790#" "m2_55523_202892#" 2.37837
-cap "la_data_in[38]" "la_data_out[38]" 46.7738
-cap "io_in[5]" "io_out[5]" 67.2299
-cap "io_in[5]" "io_in_3v3[5]" 67.2299
-cap "wbs_adr_i[24]" "wbs_dat_i[24]" 46.7738
-cap "la_data_in[101]" "la_oenb[100]" 46.7738
-cap "io_out[12]" "io_in[12]" 67.2299
-cap "m2_55208_202785#" "m2_33290_207480#" 0.757998
-cap "la_oenb[37]" "la_data_out[37]" 46.7738
-cap "la_data_out[125]" "la_oenb[125]" 46.7738
-cap "io_oeb[6]" "io_out[6]" 67.2299
-cap "la_oenb[38]" "la_data_out[38]" 46.7738
-cap "io_out[23]" "io_oeb[23]" 67.2299
-cap "io_analog[2]" "la_data_in[121]" 2.11832
-cap "vssa2" "la_data_out[7]" 874.91
-cap "m2_33290_207480#" "la_data_in[123]" 3.42049
-cap "la_oenb[86]" "la_data_in[87]" 46.7738
-cap "la_data_in[127]" "io_analog[2]" 74.5519
-cap "io_in_3v3[12]" "io_in[12]" 67.2299
-cap "m2_53840_202790#" "m2_33290_207480#" 1.95285
-cap "la_oenb[38]" "la_data_in[39]" 46.7738
-cap "la_oenb[85]" "la_data_in[86]" 46.7738
-cap "io_analog[7]" "io_analog[9]" 1.41681
-cap "wbs_dat_o[25]" "wbs_adr_i[26]" 46.7738
-cap "m2_53160_202790#" "vssa2" 111.446
-cap "la_data_in[57]" "la_oenb[56]" 46.7738
-cap "vssa2" "m2_34420_199220#" 4724.99
-cap "io_analog[6]" "io_analog[6]" 26792.4
-cap "m2_53493_202942#" "vssa2" 113.123
-cap "la_data_out[87]" "la_data_in[87]" 46.7738
-cap "la_data_out[87]" "la_oenb[87]" 46.7738
-cap "la_data_out[39]" "la_data_in[39]" 46.7738
-cap "io_in[24]" "io_out[24]" 67.2299
-cap "la_data_out[39]" "la_oenb[39]" 46.7738
-cap "la_data_in[112]" "la_oenb[111]" 46.7738
-cap "vssa2" "la_data_out[5]" 894.594
-cap "wbs_dat_i[26]" "wbs_adr_i[26]" 46.7738
-cap "la_oenb[109]" "la_data_out[109]" 46.7738
-cap "vssa2" "la_data_out[8]" 1498.48
-cap "io_out[21]" "io_oeb[21]" 67.2299
-cap "la_oenb[124]" "la_data_out[124]" 46.7738
-cap "la_data_out[6]" "vssa2" 886.965
-cap "io_in_3v3[26]" "io_oeb[25]" 67.2299
-cap "io_in_3v3[19]" "gpio_noesd[12]" 67.2299
-cap "io_analog[6]" "io_clamp_high[2]" 735.436
-cap "wbs_adr_i[22]" "wbs_dat_o[21]" 46.7738
-cap "la_oenb[57]" "la_data_out[57]" 46.7738
-cap "wbs_adr_i[22]" "wbs_dat_i[22]" 46.7738
-cap "wbs_adr_i[24]" "wbs_dat_o[23]" 46.7738
-cap "io_oeb[0]" "io_out[0]" 67.2299
-cap "la_oenb[85]" "la_data_out[85]" 46.7738
-cap "gpio_analog[13]" "gpio_noesd[13]" 67.2299
-cap "gpio_analog[7]" "m2_33290_207480#" 153.875
-cap "wbs_dat_o[22]" "wbs_dat_i[22]" 46.7738
-cap "la_data_out[63]" "la_oenb[63]" 46.7738
-cap "la_data_in[118]" "la_oenb[117]" 46.7738
-cap "io_in_3v3[20]" "gpio_noesd[13]" 67.2299
-cap "m3_26500_684896#" "io_analog[10]" 38.7515
-cap "wbs_dat_o[22]" "wbs_adr_i[23]" 46.7738
-cap "la_data_out[37]" "la_data_in[37]" 46.7738
-cap "la_data_out[35]" "la_data_in[35]" 46.7738
-cap "io_in_3v3[2]" "io_oeb[1]" 67.2299
-cap "la_data_out[57]" "la_data_in[57]" 46.7738
-cap "io_in_3v3[20]" "io_in[20]" 67.2299
-cap "wbs_dat_i[21]" "wbs_dat_o[21]" 46.7738
-cap "gpio_analog[10]" "gpio_noesd[10]" 67.2299
-cap "gpio_noesd[2]" "io_in_3v3[9]" 67.2299
-cap "m2_55208_202785#" "m2_54170_202730#" 2.66226
-cap "wbs_adr_i[23]" "wbs_dat_i[23]" 46.7738
-cap "la_data_out[35]" "la_oenb[35]" 46.7738
-cap "la_data_in[124]" "la_data_in[123]" 30971.2
-cap "io_analog[2]" "vssa2" 72.4962
-cap "wbs_dat_o[23]" "wbs_dat_i[23]" 46.7738
-cap "la_data_in[36]" "la_oenb[35]" 46.7738
-cap "la_data_in[122]" "la_data_in[123]" 32987.8
-cap "la_data_in[36]" "la_data_out[36]" 46.7738
-cap "la_data_out[36]" "la_oenb[36]" 46.7738
-cap "la_data_out[0]" "la_data_out[1]" 5.79259
-cap "la_oenb[36]" "la_data_in[37]" 46.7738
-cap "la_data_out[54]" "la_data_in[54]" 46.7738
-cap "la_oenb[116]" "la_data_in[117]" 46.7738
-cap "la_data_in[122]" "la_oenb[121]" 46.7738
-cap "gpio_analog[5]" "gpio_noesd[5]" 67.2299
-cap "m2_53840_202790#" "m2_54170_202730#" 83.6871
-cap "io_out[7]" "io_oeb[7]" 67.2299
-cap "m2_55208_202785#" "m2_53493_202942#" 0.24742
-cap "la_oenb[0]" "la_data_out[1]" 5.79259
-cap "la_oenb[87]" "la_data_in[88]" 46.7738
-cap "la_data_out[117]" "la_data_in[117]" 46.7738
-cap "la_oenb[34]" "la_data_in[35]" 46.7738
-cap "m2_55208_202785#" "m2_54833_202912#" 26.4727
-cap "la_data_out[56]" "la_data_in[56]" 46.7738
-cap "la_data_in[1]" "la_data_out[1]" 52.5664
-cap "la_oenb[1]" "la_data_out[1]" 46.7738
-cap "io_analog[4]" "io_analog[3]" 14425.7
-cap "m2_53160_202790#" "m2_53840_202790#" 82.4543
-cap "io_analog[5]" "io_analog[5]" 26792.4
-cap "la_data_in[123]" "la_data_in[126]" 27.9166
-cap "m2_53493_202942#" "m2_53840_202790#" 41.1462
-cap "la_data_in[0]" "la_data_out[1]" 5.79259
-cap "la_data_out[1]" "wbs_dat_o[29]" 5.79259
-cap "wbs_adr_i[30]" "la_data_out[1]" 5.79259
-cap "io_in_3v3[15]" "gpio_noesd[8]" 67.2299
-cap "m2_53840_202790#" "m2_54833_202912#" 8.15576
-cap "wbs_dat_i[30]" "la_data_out[1]" 5.79259
-cap "la_oenb[88]" "la_data_in[89]" 46.7738
-cap "user_irq[2]" "user_irq[1]" 46.7738
-cap "io_analog[4]" "io_clamp_low[0]" 468.333
-cap "io_in_3v3[14]" "io_in[14]" 67.2299
-cap "m2_55208_202785#" "m2_54520_202790#" 8.16064
-cap "la_data_out[1]" "wbs_dat_o[30]" 5.79259
-cap "wbs_adr_i[31]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[19]" "wbs_dat_i[19]" 46.7738
-cap "la_oenb[109]" "la_data_in[110]" 46.7738
-cap "io_analog[4]" "io_clamp_high[0]" 735.436
-cap "wbs_dat_i[31]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[31]" "la_data_out[1]" 5.79259
-cap "la_data_in[99]" "la_oenb[98]" 46.7738
-cap "wbs_adr_i[21]" "wbs_dat_i[21]" 46.7738
-cap "wbs_dat_o[19]" "wbs_dat_i[19]" 46.7738
-cap "wbs_adr_i[20]" "wbs_dat_o[19]" 46.7738
-cap "wbs_dat_i[29]" "la_data_out[1]" 5.79259
-cap "m2_54520_202790#" "m2_53840_202790#" 21.0574
-cap "m1_49580_204344#" "m2_33290_207480#" 30589.7
-cap "wbs_adr_i[27]" "la_data_out[1]" 5.79259
-cap "la_data_out[89]" "la_data_in[89]" 46.7738
-cap "wbs_dat_o[18]" "wbs_adr_i[19]" 46.7738
-cap "la_oenb[88]" "la_data_out[88]" 46.7738
-cap "wbs_dat_i[20]" "wbs_adr_i[20]" 46.7738
-cap "la_oenb[32]" "la_data_out[32]" 46.7738
-cap "io_clamp_low[1]" "io_analog[5]" 468.333
-cap "io_out[17]" "io_oeb[17]" 67.2299
-cap "la_data_out[89]" "la_oenb[89]" 46.7738
-cap "io_clamp_high[2]" "io_clamp_low[2]" 468.333
-cap "wbs_dat_i[27]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[27]" "la_data_out[1]" 5.79259
-cap "la_data_in[90]" "la_oenb[89]" 46.7738
-cap "wbs_dat_i[20]" "wbs_dat_o[20]" 46.7738
-cap "la_data_in[33]" "la_oenb[32]" 46.7738
-cap "la_data_in[90]" "la_data_out[90]" 46.7738
-cap "wbs_adr_i[28]" "la_data_out[1]" 5.79259
-cap "wbs_ack_o" "wb_rst_i" 46.7738
-cap "la_data_in[33]" "la_data_out[33]" 46.7738
-cap "la_oenb[34]" "la_data_out[34]" 46.7738
-cap "la_data_out[98]" "la_data_in[98]" 46.7738
-cap "wbs_dat_i[28]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[28]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[20]" "wbs_adr_i[21]" 46.7738
-cap "wbs_dat_o[26]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[29]" "la_data_out[1]" 5.79259
-cap "m2_55208_202785#" "io_analog[2]" 0.0603769
-cap "la_data_in[32]" "la_data_out[32]" 46.7738
-cap "wbs_dat_i[24]" "la_data_out[1]" 5.79259
-cap "la_oenb[33]" "la_data_out[33]" 46.7738
-cap "wbs_dat_o[24]" "la_data_out[1]" 5.79259
-cap "io_in_3v3[10]" "io_in[10]" 67.2299
-cap "io_in_3v3[13]" "io_in[13]" 67.2299
-cap "io_analog[5]" "io_clamp_high[1]" 493.833
-cap "gpio_analog[7]" "m2_34420_199220#" 4360.58
-cap "m3_51655_199490#" "vssa2" 160.694
-cap "wbs_adr_i[25]" "la_data_out[1]" 5.79259
-cap "la_oenb[33]" "la_data_in[34]" 46.7738
-cap "io_analog[2]" "la_data_in[123]" 2.11832
-cap "io_in_3v3[13]" "gpio_noesd[6]" 67.2299
-cap "wbs_dat_i[25]" "la_data_out[1]" 5.79259
-cap "la_data_in[114]" "la_oenb[113]" 46.7738
-cap "la_data_in[88]" "la_data_out[88]" 46.7738
-cap "io_analog[2]" "m2_53840_202790#" 0.0675945
-cap "wbs_dat_o[2]" "wbs_sel_i[2]" 46.7738
-cap "la_data_out[1]" "la_data_out[3]" 0.370339
-cap "la_data_out[34]" "la_data_in[34]" 46.7738
-cap "la_data_out[91]" "la_oenb[91]" 46.7738
-cap "wbs_dat_o[25]" "la_data_out[1]" 5.79259
-cap "la_oenb[90]" "la_data_out[90]" 46.7738
-cap "la_oenb[91]" "la_data_in[92]" 46.7738
-cap "la_oenb[29]" "la_data_in[30]" 46.7738
-cap "io_analog[4]" "io_analog[4]" 26259.4
-cap "io_clamp_low[2]" "io_analog[6]" 468.333
-cap "vssa2" "io_analog[3]" 6607.54
-cap "wbs_dat_i[18]" "wbs_dat_o[18]" 46.7738
-cap "la_data_out[30]" "la_data_in[30]" 46.7738
-cap "la_data_out[51]" "la_data_in[51]" 46.7738
-cap "io_analog[4]" "io_analog[4]" 21353.1
-cap "la_data_in[120]" "la_data_in[125]" 1.94287
-cap "la_data_out[1]" "wbs_adr_i[26]" 5.79259
-cap "wbs_dat_i[26]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[24]" "la_data_out[1]" 5.79259
-cap "wbs_dat_i[16]" "wbs_dat_o[16]" 46.7738
-cap "la_data_in[100]" "la_oenb[99]" 46.7738
-cap "vssa2" "la_data_out[3]" 883.584
-cap "wbs_adr_i[17]" "wbs_dat_o[16]" 46.7738
-cap "la_data_out[30]" "la_oenb[30]" 46.7738
-cap "la_data_in[32]" "la_oenb[31]" 46.7738
-cap "la_data_out[92]" "la_data_in[92]" 46.7738
-cap "gpio_noesd[14]" "io_in_3v3[21]" 67.2299
-cap "wbs_adr_i[17]" "wbs_dat_i[17]" 46.7738
-cap "la_oenb[30]" "la_data_in[31]" 46.7738
-cap "la_data_out[91]" "la_data_in[91]" 46.7738
-cap "m2_55523_202892#" "vccd1" 42.2459
-cap "io_in[0]" "io_in_3v3[0]" 67.2299
-cap "la_data_in[31]" "la_data_out[31]" 46.7738
-cap "la_data_out[116]" "la_oenb[116]" 46.7738
-cap "la_data_in[120]" "vccd1" 75630.8
-cap "wbs_dat_o[21]" "la_data_out[1]" 5.79259
-cap "la_data_out[92]" "la_oenb[92]" 46.7738
-cap "gpio_analog[1]" "gpio_noesd[1]" 67.2299
-cap "wbs_adr_i[22]" "la_data_out[1]" 5.79259
-cap "la_oenb[29]" "la_data_out[29]" 46.7738
-cap "la_data_in[61]" "la_oenb[60]" 46.7738
-cap "io_in_3v3[17]" "gpio_noesd[10]" 67.2299
-cap "wbs_dat_i[16]" "wbs_adr_i[16]" 46.7738
-cap "la_data_out[126]" "la_oenb[126]" 46.7738
-cap "io_oeb[24]" "io_in_3v3[25]" 67.2299
-cap "wbs_dat_o[17]" "wbs_dat_i[17]" 46.7738
-cap "la_data_in[93]" "la_oenb[92]" 46.7738
-cap "wbs_dat_i[22]" "la_data_out[1]" 5.79259
-cap "m2_33290_207480#" "la_data_in[125]" 3.42049
-cap "wbs_dat_o[22]" "la_data_out[1]" 5.79259
-cap "la_data_out[31]" "la_oenb[31]" 46.7738
-cap "io_in[17]" "io_in_3v3[17]" 67.2299
-cap "wbs_dat_o[17]" "wbs_adr_i[18]" 46.7738
-cap "wbs_adr_i[23]" "la_data_out[1]" 5.79259
-cap "io_analog[6]" "io_analog[6]" 21353.1
-cap "la_data_out[1]" "wbs_dat_i[23]" 5.79259
-cap "wbs_dat_i[18]" "wbs_adr_i[18]" 46.7738
-cap "la_oenb[90]" "la_data_in[91]" 46.7738
-cap "io_in[0]" "io_out[0]" 67.2299
-cap "la_oenb[65]" "la_data_out[65]" 46.7738
-cap "io_in[23]" "io_out[23]" 67.2299
-cap "wbs_dat_o[23]" "la_data_out[1]" 5.79259
-cap "m2_33290_207480#" "vccd1" 87.7272
-cap "m2_53160_202790#" "m1_49580_204344#" 1.11147
-cap "wbs_dat_o[0]" "wbs_dat_i[0]" 46.7738
-cap "wbs_dat_i[21]" "la_data_out[1]" 5.79259
-cap "la_data_in[61]" "la_data_out[61]" 46.7738
-cap "m1_49580_204344#" "m2_34420_199220#" 52.3618
-cap "m2_53493_202942#" "m1_49580_204344#" 1.85563
-cap "la_data_in[27]" "la_data_out[27]" 46.7738
-cap "wbs_adr_i[19]" "la_data_out[1]" 5.79259
-cap "la_oenb[27]" "la_data_out[27]" 46.7738
-cap "io_analog[5]" "io_analog[5]" 21353.1
-cap "wbs_dat_o[13]" "wbs_adr_i[14]" 46.7738
-cap "wbs_dat_i[19]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[19]" "la_data_out[1]" 5.79259
-cap "la_oenb[27]" "la_data_in[28]" 46.7738
-cap "la_data_out[51]" "la_oenb[51]" 46.7738
-cap "wbs_adr_i[20]" "la_data_out[1]" 5.79259
-cap "la_data_out[94]" "la_data_in[94]" 46.7738
-cap "la_data_out[28]" "la_data_in[28]" 46.7738
-cap "wbs_dat_i[20]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[20]" "la_data_out[1]" 5.79259
-cap "la_data_out[28]" "la_oenb[28]" 46.7738
-cap "la_data_in[29]" "la_data_out[29]" 46.7738
-cap "la_data_in[127]" "la_data_in[121]" 7.83251
-cap "wbs_adr_i[21]" "la_data_out[1]" 5.79259
-cap "la_data_out[93]" "la_data_in[93]" 46.7738
-cap "io_in[22]" "io_out[22]" 67.2299
-cap "wbs_dat_o[18]" "la_data_out[1]" 5.79259
-cap "wbs_dat_i[14]" "wbs_adr_i[14]" 46.7738
-cap "la_data_out[94]" "la_oenb[94]" 46.7738
-cap "la_data_in[29]" "la_oenb[28]" 46.7738
-cap "wbs_adr_i[16]" "wbs_dat_o[15]" 46.7738
-cap "la_data_in[27]" "la_oenb[26]" 46.7738
-cap "la_data_out[120]" "la_oenb[120]" 46.7738
-cap "la_data_out[52]" "la_oenb[52]" 46.7738
-cap "la_data_out[119]" "la_oenb[119]" 46.7738
-cap "la_oenb[120]" "la_data_in[121]" 46.7738
-cap "wbs_dat_o[14]" "wbs_dat_i[14]" 46.7738
-cap "la_data_out[121]" "la_data_in[121]" 46.7738
-cap "la_data_out[52]" "la_data_in[52]" 46.7738
-cap "la_data_in[54]" "la_oenb[53]" 46.7738
-cap "wbs_dat_o[13]" "wbs_dat_i[13]" 46.7738
-cap "la_data_out[119]" "la_data_in[119]" 46.7738
-cap "io_oeb[24]" "io_out[24]" 67.2299
-cap "wbs_dat_i[16]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[16]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[17]" "la_data_out[1]" 5.79259
-cap "la_data_in[119]" "la_oenb[118]" 46.7738
-cap "wbs_dat_i[17]" "la_data_out[1]" 5.79259
-cap "la_data_in[95]" "la_oenb[94]" 46.7738
-cap "la_data_in[124]" "la_data_in[125]" 40363.9
-cap "la_oenb[58]" "la_data_in[59]" 46.7738
-cap "la_data_out[95]" "la_data_in[95]" 46.7738
-cap "wbs_dat_o[17]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[18]" "la_data_out[1]" 5.79259
-cap "wbs_dat_o[14]" "wbs_adr_i[15]" 46.7738
-cap "la_data_in[122]" "la_data_in[125]" 34.4614
-cap "wbs_adr_i[16]" "la_data_out[1]" 5.79259
-cap "wbs_dat_i[18]" "la_data_out[1]" 5.79259
-cap "la_data_out[95]" "la_oenb[95]" 46.7738
-cap "io_analog[2]" "m1_49580_204344#" 22.2661
-cap "wbs_dat_o[13]" "la_data_out[1]" 5.79259
-cap "la_data_out[53]" "la_data_in[53]" 46.7738
-cap "la_data_in[124]" "vccd1" 2122.7
-cap "wbs_dat_i[15]" "wbs_adr_i[15]" 46.7738
-cap "la_data_out[116]" "la_data_in[116]" 46.7738
-cap "la_data_in[122]" "vccd1" 2490.74
-cap "la_oenb[24]" "la_data_out[24]" 46.7738
-cap "m2_54170_202730#" "vccd1" 0.00723639
-cap "la_oenb[24]" "la_data_in[25]" 46.7738
-cap "wbs_dat_i[15]" "wbs_dat_o[15]" 46.7738
-cap "wbs_adr_i[14]" "la_data_out[1]" 5.79259
-cap "la_data_in[125]" "la_data_in[126]" 41930.2
-cap "la_data_in[25]" "la_data_out[25]" 46.7738
-cap "io_clamp_low[0]" "io_clamp_high[0]" 468.333
-cap "wbs_dat_i[14]" "la_data_out[1]" 5.79259
-cap "la_oenb[26]" "la_data_out[26]" 46.7738
-cap "la_data_in[24]" "la_data_out[24]" 46.7738
-cap "la_oenb[96]" "la_data_in[97]" 46.7738
-cap "io_analog[4]" "vssa2" 12792.7
-cap "wbs_dat_o[14]" "la_data_out[1]" 5.79259
-cap "la_oenb[25]" "la_data_out[25]" 46.7738
-cap "io_analog[5]" "io_clamp_high[1]" 735.436
-cap "m2_53493_202942#" "vccd1" 0.0162526
-cap "la_data_in[83]" "la_oenb[82]" 46.7738
+cap "la_data_in[125]" "m2_33290_207480#" 3.42049
+cap "wbs_dat_o[31]" "wbs_dat_i[31]" 46.7738
+cap "la_oenb[113]" "la_data_in[114]" 46.7738
+cap "io_out[8]" "io_oeb[8]" 67.2299
+cap "wbs_sel_i[2]" "wbs_adr_i[3]" 46.7738
cap "la_data_out[99]" "la_oenb[99]" 46.7738
-cap "la_data_in[122]" "la_data_out[122]" 46.7738
-cap "vssa2" "io_analog[6]" 10672.1
-cap "la_data_in[126]" "vccd1" 2146.23
-cap "la_data_in[26]" "la_oenb[25]" 46.7738
-cap "la_data_in[26]" "la_data_out[26]" 46.7738
-cap "m2_54833_202912#" "vccd1" 1.79184
-cap "wbs_adr_i[15]" "la_data_out[1]" 5.79259
-cap "la_data_in[65]" "la_oenb[64]" 46.7738
-cap "la_data_in[96]" "la_oenb[95]" 46.7738
-cap "wbs_ack_o" "wbs_cyc_i" 46.7738
-cap "wbs_adr_i[11]" "wbs_dat_i[11]" 46.7738
-cap "wbs_dat_i[15]" "la_data_out[1]" 5.79259
-cap "gpio_analog[7]" "io_analog[3]" 84.3
-cap "io_out[3]" "io_oeb[3]" 67.2299
-cap "wbs_dat_o[11]" "wbs_dat_i[11]" 46.7738
-cap "wbs_dat_o[15]" "la_data_out[1]" 5.79259
-cap "la_data_in[22]" "la_oenb[21]" 46.7738
-cap "wbs_dat_i[13]" "la_data_out[1]" 5.79259
-cap "wbs_adr_i[11]" "la_data_out[1]" 5.79259
-cap "la_data_out[64]" "la_oenb[64]" 46.7738
-cap "m2_54520_202790#" "vccd1" 0.152921
-cap "la_data_out[1]" "wbs_dat_i[11]" 5.79259
-cap "wbs_dat_o[11]" "wbs_adr_i[12]" 46.7738
-cap "wbs_dat_o[11]" "la_data_out[1]" 5.79259
-cap "wbs_dat_i[13]" "wbs_adr_i[13]" 46.7738
-cap "io_in_3v3[22]" "io_in[22]" 67.2299
-cap "la_data_in[22]" "la_data_out[22]" 46.7738
-cap "io_in[2]" "io_in_3v3[2]" 67.2299
-cap "la_data_in[114]" "la_data_out[114]" 46.7738
-cap "wbs_adr_i[12]" "la_data_out[1]" 5.79259
-cap "io_in[18]" "io_in_3v3[18]" 67.2299
-cap "la_data_in[24]" "la_oenb[23]" 46.7738
-cap "io_analog[7]" "io_analog[6]" 2427.12
-cap "wbs_adr_i[11]" "wbs_dat_o[10]" 46.7738
-cap "wbs_dat_i[12]" "wbs_adr_i[12]" 46.7738
-cap "io_out[18]" "io_in[18]" 67.2299
-cap "wbs_dat_o[12]" "la_data_out[1]" 5.79259
-cap "la_oenb[22]" "la_data_out[22]" 46.7738
-cap "la_data_in[67]" "la_oenb[66]" 46.7738
-cap "vccd2" "m2_33290_207480#" 366.573
-cap "wbs_dat_i[12]" "la_data_out[1]" 5.79259
-cap "la_data_in[124]" "la_data_out[124]" 46.7738
-cap "wbs_adr_i[13]" "la_data_out[1]" 5.79259
-cap "la_data_in[63]" "la_oenb[62]" 46.7738
-cap "la_oenb[21]" "la_data_out[21]" 46.7738
-cap "io_analog[2]" "la_data_in[125]" 2.11832
-cap "la_oenb[22]" "la_data_in[23]" 46.7738
-cap "la_data_in[64]" "la_data_out[64]" 46.7738
-cap "io_in_3v3[9]" "io_in[9]" 67.2299
-cap "wbs_dat_o[12]" "wbs_dat_i[12]" 46.7738
-cap "io_in_3v3[7]" "gpio_noesd[0]" 67.2299
-cap "wbs_dat_o[12]" "wbs_adr_i[13]" 46.7738
-cap "io_in[8]" "io_out[8]" 67.2299
-cap "wbs_dat_o[10]" "la_data_out[1]" 5.79259
-cap "la_data_out[126]" "la_data_in[126]" 46.7738
-cap "io_analog[2]" "vccd1" 2251.66
-cap "vssa2" "la_data_out[1]" 1495.21
-cap "io_oeb[26]" "io_out[26]" 67.2299
-cap "la_data_in[23]" "la_data_out[23]" 46.7738
-cap "io_oeb[22]" "io_out[22]" 67.2299
-cap "gpio_noesd[9]" "io_in_3v3[16]" 67.2299
-cap "vccd2" "io_analog[10]" 13360.7
-cap "la_data_in[85]" "la_data_out[85]" 46.7738
-cap "la_data_out[69]" "la_data_in[69]" 46.7738
+cap "la_oenb[8]" "la_data_out[8]" 46.7738
+cap "la_data_in[65]" "la_data_out[65]" 46.7738
+cap "gpio_analog[7]" "m2_33290_207480#" 153.875
+cap "la_data_out[57]" "la_data_in[57]" 46.7738
+cap "wbs_adr_i[16]" "wbs_dat_o[15]" 46.7738
+cap "la_oenb[97]" "la_data_out[97]" 46.7738
cap "wbs_adr_i[9]" "la_data_out[1]" 5.79259
-cap "wbs_dat_i[9]" "la_data_out[1]" 5.79259
-cap "la_data_out[123]" "la_oenb[123]" 46.7738
-cap "wbs_dat_o[9]" "la_data_out[1]" 5.79259
-cap "la_data_in[66]" "la_data_out[66]" 46.7738
-cap "io_in_3v3[12]" "gpio_noesd[5]" 67.2299
-cap "la_oenb[23]" "la_data_out[23]" 46.7738
-cap "wbs_adr_i[10]" "la_data_out[1]" 5.79259
-cap "la_oenb[61]" "la_data_out[61]" 46.7738
-cap "gpio_noesd[12]" "gpio_analog[12]" 67.2299
-cap "gpio_noesd[8]" "gpio_analog[8]" 67.2299
-cap "wbs_dat_i[10]" "la_data_out[1]" 5.79259
-cap "io_in[26]" "io_out[26]" 67.2299
-cap "user_irq[0]" "user_irq[1]" 46.7738
-cap "io_out[25]" "io_oeb[25]" 67.2299
-cap "io_out[10]" "io_oeb[10]" 67.2299
-cap "wbs_adr_i[3]" "wbs_sel_i[2]" 46.7738
-cap "vssa2" "io_analog[8]" 1645.69
-cap "la_data_in[67]" "la_data_out[67]" 46.7738
-cap "io_clamp_low[2]" "io_analog[6]" 735.436
-cap "la_data_in[116]" "la_oenb[115]" 46.7738
-cap "la_data_in[121]" "la_data_in[123]" 372.972
-cap "la_data_in[96]" "la_data_out[96]" 46.7738
-cap "wbs_dat_i[8]" "wbs_dat_o[8]" 46.7738
-cap "la_oenb[93]" "la_data_in[94]" 46.7738
-cap "io_analog[9]" "vccd2" 1461.73
-cap "la_oenb[114]" "la_data_in[115]" 46.7738
-cap "la_data_in[127]" "la_data_in[123]" 16.4928
-cap "io_in_3v3[19]" "io_in[19]" 67.2299
-cap "wbs_dat_o[8]" "wbs_adr_i[9]" 46.7738
-cap "la_oenb[68]" "la_data_in[69]" 46.7738
-cap "wbs_dat_o[10]" "wbs_dat_i[10]" 46.7738
-cap "io_out[2]" "io_in[2]" 67.2299
-cap "io_analog[4]" "io_analog[4]" 22465.6
-cap "wbs_dat_i[9]" "wbs_adr_i[9]" 46.7738
-cap "la_oenb[67]" "la_data_out[67]" 46.7738
-cap "la_data_out[19]" "la_data_in[19]" 46.7738
-cap "la_data_out[19]" "la_oenb[19]" 46.7738
-cap "io_out[15]" "io_in[15]" 67.2299
-cap "io_in[19]" "io_out[19]" 67.2299
-cap "wbs_dat_i[8]" "wbs_adr_i[8]" 46.7738
-cap "io_in_3v3[3]" "io_oeb[2]" 67.2299
-cap "wbs_dat_i[9]" "wbs_dat_o[9]" 46.7738
-cap "io_oeb[19]" "io_out[19]" 67.2299
-cap "la_oenb[19]" "la_data_in[20]" 46.7738
-cap "wbs_adr_i[10]" "wbs_dat_o[9]" 46.7738
-cap "la_oenb[67]" "la_data_in[68]" 46.7738
-cap "la_data_out[21]" "la_data_in[21]" 46.7738
-cap "io_oeb[8]" "io_out[8]" 67.2299
-cap "la_data_out[121]" "la_oenb[121]" 46.7738
-cap "wbs_adr_i[10]" "wbs_dat_i[10]" 46.7738
-cap "io_oeb[9]" "io_out[9]" 67.2299
-cap "io_analog[7]" "vssa2" 6815.3
-cap "la_data_in[20]" "la_data_out[20]" 46.7738
-cap "la_data_out[69]" "la_oenb[69]" 46.7738
-cap "la_data_out[68]" "la_data_in[68]" 46.7738
-cap "gpio_analog[7]" "gpio_noesd[7]" 67.2299
-cap "la_data_out[93]" "la_oenb[93]" 46.7738
-cap "io_analog[7]" "io_analog[8]" 3486.67
-cap "la_oenb[20]" "la_data_out[20]" 46.7738
-cap "io_in[20]" "io_out[20]" 67.2299
-cap "wbs_adr_i[6]" "wbs_dat_o[5]" 46.7738
-cap "io_out[9]" "io_in[9]" 67.2299
-cap "la_oenb[68]" "la_data_out[68]" 46.7738
-cap "io_out[21]" "io_in[21]" 67.2299
-cap "wbs_adr_i[6]" "wbs_dat_i[6]" 46.7738
-cap "la_oenb[20]" "la_data_in[21]" 46.7738
-cap "vccd2" "m2_34420_199220#" 425.076
-cap "la_oenb[18]" "la_data_in[19]" 46.7738
-cap "io_in[17]" "io_out[17]" 67.2299
-cap "wbs_dat_o[6]" "wbs_dat_i[6]" 46.7738
-cap "io_analog[4]" "io_analog[5]" 15915.8
-cap "gpio_noesd[2]" "gpio_analog[2]" 67.2299
-cap "la_oenb[54]" "la_data_in[55]" 46.7738
-cap "wbs_dat_o[6]" "wbs_adr_i[7]" 46.7738
-cap "wbs_dat_i[2]" "wbs_adr_i[2]" 46.7738
-cap "wbs_adr_i[8]" "wbs_dat_o[7]" 46.7738
-cap "la_data_in[113]" "la_data_out[113]" 46.7738
-cap "la_oenb[71]" "la_data_in[72]" 46.7738
-cap "io_analog[5]" "io_analog[6]" 5298.76
-cap "io_out[20]" "io_oeb[20]" 67.2299
-cap "wbs_dat_o[5]" "wbs_dat_i[5]" 46.7738
-cap "la_data_in[113]" "la_oenb[112]" 46.7738
-cap "wbs_dat_i[7]" "wbs_adr_i[7]" 46.7738
+cap "io_in_3v3[14]" "io_in[14]" 67.2299
+cap "la_data_in[28]" "la_data_out[28]" 46.7738
+cap "vccd1" "m2_54833_202912#" 1.79184
+cap "wbs_dat_o[19]" "wbs_adr_i[20]" 46.7738
cap "la_data_out[60]" "la_oenb[60]" 46.7738
-cap "io_in[11]" "io_out[11]" 67.2299
-cap "la_oenb[112]" "la_data_out[112]" 46.7738
-cap "vssa2" "m2_53840_202790#" 0.938238
-cap "wbs_dat_o[7]" "wbs_dat_i[7]" 46.7738
-cap "la_oenb[97]" "la_data_in[98]" 46.7738
-cap "la_oenb[55]" "la_data_in[56]" 46.7738
-cap "la_data_in[70]" "la_oenb[69]" 46.7738
-cap "wbs_dat_o[1]" "wbs_dat_i[1]" 46.7738
-cap "io_out[18]" "io_oeb[18]" 67.2299
-cap "la_data_out[71]" "la_oenb[71]" 46.7738
-cap "user_clock2" "la_oenb[127]" 46.7738
-cap "io_oeb[16]" "io_out[16]" 67.2299
-cap "io_clamp_low[1]" "io_clamp_high[1]" 468.333
-cap "io_analog[4]" "io_clamp_low[0]" 735.436
-cap "io_in_3v3[1]" "io_in[1]" 67.2299
-cap "wbs_dat_i[3]" "wbs_dat_o[3]" 46.7738
-cap "wbs_sel_i[3]" "wbs_dat_o[3]" 46.7738
-cap "la_data_in[63]" "la_data_out[63]" 46.7738
-cap "la_data_in[66]" "la_oenb[65]" 46.7738
-cap "la_data_in[70]" "la_data_out[70]" 46.7738
-cap "wbs_sel_i[3]" "wbs_adr_i[4]" 46.7738
-cap "la_data_out[72]" "la_data_in[72]" 46.7738
-cap "m2_33290_207480#" "m2_55523_202892#" 6.94958
-cap "la_data_in[120]" "m2_33290_207480#" 2.65181
-cap "la_data_out[16]" "la_oenb[16]" 46.7738
-cap "la_oenb[70]" "la_data_out[70]" 46.7738
-cap "io_analog[2]" "vccd2" 10711.3
-cap "io_out[14]" "io_oeb[14]" 67.2299
-cap "wbs_dat_i[4]" "wbs_adr_i[4]" 46.7738
-cap "la_data_in[62]" "la_data_out[62]" 46.7738
-cap "vssa2" "m3_26500_684896#" 1183.07
-cap "io_out[1]" "io_in[1]" 67.2299
-cap "wbs_adr_i[5]" "wbs_dat_i[5]" 46.7738
-cap "wbs_dat_i[4]" "wbs_dat_o[4]" 46.7738
-cap "la_oenb[70]" "la_data_in[71]" 46.7738
-cap "wbs_adr_i[3]" "wbs_dat_i[3]" 46.7738
-cap "la_data_in[62]" "la_oenb[61]" 46.7738
-cap "la_oenb[50]" "la_data_out[50]" 46.7738
-cap "wbs_sel_i[1]" "wbs_adr_i[2]" 46.7738
-cap "la_data_out[118]" "la_oenb[118]" 46.7738
-cap "la_data_out[71]" "la_data_in[71]" 46.7738
-cap "la_data_in[17]" "la_oenb[16]" 46.7738
-cap "vssa2" "gpio_analog[7]" 39652.2
-cap "wbs_adr_i[5]" "wbs_dat_o[4]" 46.7738
-cap "la_data_out[54]" "la_oenb[54]" 46.7738
-cap "la_oenb[74]" "la_data_out[74]" 46.7738
-cap "vssa2" "io_analog[5]" 14585.2
-cap "la_oenb[127]" "la_data_out[127]" 46.7738
-cap "io_in_3v3[23]" "gpio_noesd[16]" 67.2299
-cap "la_data_out[100]" "la_data_in[100]" 46.7738
-cap "la_oenb[72]" "la_data_out[72]" 46.7738
-cap "user_irq[0]" "user_clock2" 46.7738
-cap "m2_55208_202785#" "m2_53840_202790#" 0.236247
+cap "la_oenb[122]" "la_data_out[122]" 46.7738
+cap "vssa2" "la_data_out[8]" 1498.48
+cap "la_data_out[63]" "la_data_in[63]" 46.7738
+cap "la_data_in[41]" "la_oenb[40]" 46.7738
+cap "la_data_in[109]" "la_oenb[108]" 46.7738
+cap "io_analog[6]" "io_clamp_high[2]" 735.436
+cap "vccd1" "io_analog[2]" 2251.66
+cap "la_data_in[28]" "la_oenb[27]" 46.7738
+cap "la_data_in[121]" "la_oenb[120]" 46.7738
+cap "la_oenb[43]" "la_data_in[44]" 46.7738
cap "la_data_out[18]" "la_oenb[18]" 46.7738
-cap "la_data_out[58]" "la_oenb[58]" 46.7738
-cap "io_in[11]" "io_in_3v3[11]" 67.2299
-cap "la_data_in[17]" "la_data_out[17]" 46.7738
-cap "la_data_in[16]" "la_data_out[16]" 46.7738
-cap "la_data_in[74]" "la_data_out[74]" 46.7738
-cap "la_oenb[72]" "la_data_in[73]" 46.7738
-cap "la_data_out[48]" "la_oenb[48]" 46.7738
-cap "la_data_in[75]" "la_oenb[74]" 46.7738
-cap "la_data_in[49]" "la_oenb[48]" 46.7738
-cap "la_data_out[73]" "la_data_in[73]" 46.7738
-cap "io_oeb[12]" "io_out[12]" 67.2299
-cap "la_oenb[17]" "la_data_out[17]" 46.7738
-cap "wbs_adr_i[0]" "wbs_we_i" 46.7738
-cap "la_data_in[123]" "la_oenb[122]" 46.7738
-cap "la_oenb[73]" "la_data_out[73]" 46.7738
-cap "io_in_3v3[21]" "io_in[21]" 67.2299
-cap "io_oeb[11]" "io_out[11]" 67.2299
-cap "la_data_in[74]" "la_oenb[73]" 46.7738
-cap "la_data_in[18]" "la_oenb[17]" 46.7738
-cap "la_oenb[50]" "la_data_in[51]" 46.7738
-cap "io_in_3v3[22]" "gpio_noesd[15]" 67.2299
-cap "m2_54170_202730#" "m2_55523_202892#" 3.85136
-cap "la_data_in[122]" "la_data_in[120]" 53.131
-cap "la_data_in[77]" "la_data_out[77]" 46.7738
-cap "la_data_out[53]" "la_oenb[53]" 46.7738
-cap "gpio_noesd[14]" "gpio_analog[14]" 67.2299
-cap "la_data_out[49]" "la_data_in[49]" 46.7738
-cap "la_data_out[4]" "la_data_out[5]" 41443
-cap "la_data_in[75]" "la_data_out[75]" 46.7738
-cap "la_data_out[75]" "la_oenb[75]" 46.7738
-cap "la_data_in[124]" "m2_33290_207480#" 2.87201
-cap "m2_53160_202790#" "m2_55523_202892#" 0.270747
-cap "la_data_in[77]" "la_oenb[76]" 46.7738
-cap "gpio_noesd[9]" "gpio_analog[9]" 67.2299
-cap "la_data_in[76]" "la_oenb[75]" 46.7738
-cap "la_oenb[96]" "la_data_out[96]" 46.7738
-cap "m1_49580_204344#" "vssa2" 4217.68
-cap "la_data_in[121]" "la_data_in[125]" 18.8163
-cap "m2_53493_202942#" "m2_55523_202892#" 0.157044
-cap "la_data_in[18]" "la_data_out[18]" 46.7738
-cap "la_data_in[76]" "la_data_out[76]" 46.7738
-cap "la_oenb[77]" "la_data_out[77]" 46.7738
-cap "la_data_in[122]" "m2_33290_207480#" 2.87201
-cap "m2_54170_202730#" "m2_33290_207480#" 6.99285
-cap "m2_54833_202912#" "m2_55523_202892#" 53.9085
-cap "la_data_in[127]" "la_data_in[125]" 817.487
-cap "la_oenb[76]" "la_data_out[76]" 46.7738
-cap "la_data_in[121]" "vccd1" 4804.4
-cap "la_oenb[79]" "la_data_in[80]" 46.7738
-cap "la_oenb[77]" "la_data_in[78]" 46.7738
-cap "m2_53160_202790#" "m2_33290_207480#" 3.33846
-cap "la_data_in[127]" "vccd1" 2058.2
-cap "la_data_out[48]" "la_data_in[48]" 46.7738
-cap "vccd2" "io_analog[3]" 1369.55
-cap "la_data_out[49]" "la_oenb[49]" 46.7738
-cap "la_data_out[78]" "la_data_in[78]" 46.7738
-cap "la_data_in[106]" "la_data_out[106]" 46.7738
-cap "m2_33290_207480#" "m2_34420_199220#" 9072.85
-cap "m2_53493_202942#" "m2_33290_207480#" 2.99625
-cap "m2_33290_207480#" "la_data_in[126]" 2.87201
-cap "m2_54520_202790#" "m2_55523_202892#" 2.3884
-cap "m2_54833_202912#" "m2_33290_207480#" 7.50519
-cap "la_data_in[50]" "la_oenb[49]" 46.7738
-cap "la_data_in[14]" "la_oenb[13]" 46.7738
-cap "la_data_out[78]" "la_oenb[78]" 46.7738
-cap "la_data_in[50]" "la_data_out[50]" 46.7738
-cap "io_out[13]" "io_oeb[13]" 67.2299
-cap "la_data_out[84]" "la_oenb[84]" 46.7738
-cap "la_data_in[16]" "la_oenb[15]" 46.7738
-cap "la_data_in[103]" "la_oenb[102]" 46.7738
-cap "io_out[13]" "io_in[13]" 67.2299
-cap "la_data_in[14]" "la_data_out[14]" 46.7738
-cap "la_data_in[99]" "la_data_out[99]" 46.7738
-cap "la_oenb[14]" "la_data_out[14]" 46.7738
-cap "io_in_3v3[25]" "io_in[25]" 67.2299
-cap "la_oenb[14]" "la_data_in[15]" 46.7738
-cap "la_data_out[103]" "la_data_in[103]" 46.7738
-cap "m2_54520_202790#" "m2_33290_207480#" 1.36477
-cap "la_data_out[13]" "la_oenb[13]" 46.7738
-cap "la_oenb[105]" "la_data_in[106]" 46.7738
-cap "la_data_out[4]" "la_data_in[4]" 46.7738
-cap "la_data_in[15]" "la_data_out[15]" 46.7738
-cap "la_oenb[55]" "la_data_out[55]" 46.7738
+cap "wbs_adr_i[18]" "la_data_out[1]" 5.79259
+cap "la_data_in[20]" "la_data_out[20]" 46.7738
+cap "wbs_dat_i[10]" "wbs_adr_i[10]" 46.7738
+cap "io_analog[2]" "la_data_in[124]" 1.4621
+cap "wbs_dat_o[14]" "wbs_adr_i[15]" 46.7738
+cap "la_oenb[39]" "la_data_in[40]" 46.7738
+cap "la_data_in[32]" "la_data_out[32]" 46.7738
+cap "m2_54170_202730#" "m2_54520_202790#" 15.5886
+cap "la_data_out[0]" "la_data_out[1]" 5.79259
+cap "la_data_out[67]" "la_data_in[67]" 46.7738
+cap "gpio_analog[8]" "gpio_noesd[8]" 67.2299
+cap "la_data_out[3]" "la_data_out[2]" 23122.2
+cap "io_analog[3]" "gpio_analog[7]" 84.3
+cap "m2_55523_202892#" "m2_33290_207480#" 6.94958
+cap "wbs_dat_o[15]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[6]" "wbs_adr_i[6]" 46.7738
+cap "la_data_in[35]" "la_data_out[35]" 46.7738
+cap "io_in[16]" "io_in_3v3[16]" 67.2299
+cap "io_analog[5]" "io_analog[6]" 5298.76
+cap "io_in[26]" "io_out[26]" 67.2299
+cap "m2_33290_207480#" "la_data_in[122]" 2.87201
+cap "gpio_noesd[11]" "io_in_3v3[18]" 67.2299
+cap "gpio_noesd[4]" "gpio_analog[4]" 67.2299
+cap "la_oenb[22]" "la_data_out[22]" 46.7738
+cap "la_data_out[56]" "la_data_in[56]" 46.7738
+cap "la_data_in[100]" "la_oenb[99]" 46.7738
+cap "la_data_out[44]" "la_oenb[44]" 46.7738
+cap "la_oenb[47]" "la_data_in[48]" 46.7738
+cap "la_oenb[86]" "la_data_in[87]" 46.7738
+cap "io_analog[2]" "la_data_in[125]" 2.11832
+cap "wbs_adr_i[1]" "wbs_dat_i[1]" 46.7738
+cap "la_data_out[111]" "la_oenb[111]" 46.7738
+cap "wbs_dat_o[31]" "la_data_in[0]" 46.7738
+cap "wbs_dat_i[25]" "wbs_dat_o[25]" 46.7738
+cap "wbs_dat_i[7]" "wbs_dat_o[7]" 46.7738
cap "la_data_in[79]" "la_oenb[78]" 46.7738
-cap "la_data_out[97]" "la_data_in[97]" 46.7738
-cap "la_oenb[79]" "la_data_out[79]" 46.7738
-cap "io_in_3v3[11]" "gpio_noesd[4]" 67.2299
-cap "la_data_out[4]" "la_oenb[4]" 46.7738
-cap "la_oenb[103]" "la_data_in[104]" 46.7738
-cap "la_data_in[102]" "la_oenb[101]" 46.7738
-cap "la_oenb[15]" "la_data_out[15]" 46.7738
-cap "la_data_out[97]" "la_oenb[97]" 46.7738
-cap "gpio_analog[16]" "gpio_noesd[16]" 67.2299
-cap "la_data_in[102]" "la_data_out[102]" 46.7738
+cap "la_data_in[84]" "la_data_out[84]" 46.7738
+cap "la_data_in[87]" "la_data_out[87]" 46.7738
+cap "gpio_analog[6]" "gpio_noesd[6]" 67.2299
+cap "wbs_dat_o[22]" "la_data_out[1]" 5.79259
+cap "la_data_out[6]" "la_oenb[6]" 46.7738
+cap "io_out[13]" "io_oeb[13]" 67.2299
+cap "wbs_dat_i[13]" "wbs_dat_o[13]" 46.7738
+cap "m2_54170_202730#" "m2_53493_202942#" 28.1398
+cap "wbs_dat_i[21]" "wbs_adr_i[21]" 46.7738
+cap "la_oenb[75]" "la_data_out[75]" 46.7738
+cap "vssa2" "io_analog[6]" 10672.1
+cap "m2_34420_199220#" "m2_33290_207480#" 9072.85
+cap "wbs_adr_i[30]" "la_data_out[1]" 5.79259
+cap "la_oenb[82]" "la_data_out[82]" 46.7738
+cap "la_oenb[32]" "la_data_in[33]" 46.7738
+cap "m2_53493_202942#" "m2_53160_202790#" 113.198
+cap "la_oenb[102]" "la_data_in[103]" 46.7738
+cap "io_oeb[3]" "io_out[3]" 67.2299
+cap "m1_49580_204344#" "m2_33290_207480#" 30587.7
+cap "wbs_dat_i[20]" "la_data_out[1]" 5.79259
+cap "io_analog[4]" "io_analog[4]" 26922
+cap "m2_55523_202892#" "m2_54833_202912#" 53.9085
+cap "wbs_dat_i[14]" "la_data_out[1]" 5.79259
+cap "io_in[3]" "io_out[3]" 67.2299
+cap "la_data_in[101]" "la_data_out[101]" 46.7738
cap "io_analog[2]" "m2_55523_202892#" 0.147298
-cap "la_data_in[80]" "la_data_out[80]" 46.7738
-cap "io_analog[2]" "la_data_in[120]" 4.42856
-cap "la_oenb[106]" "la_data_out[106]" 46.7738
-cap "la_oenb[101]" "la_data_out[101]" 46.7738
-cap "la_oenb[102]" "la_data_out[102]" 46.7738
-cap "la_data_in[125]" "la_data_out[125]" 46.7738
-cap "la_data_in[124]" "la_data_in[122]" 302.51
-cap "la_data_in[79]" "la_data_out[79]" 46.7738
-cap "la_data_in[104]" "la_data_out[104]" 46.7738
+cap "la_data_in[69]" "la_data_out[69]" 46.7738
+cap "wbs_adr_i[0]" "wbs_we_i" 46.7738
+cap "io_in_3v3[4]" "io_in[4]" 67.2299
+cap "la_data_out[46]" "la_data_in[46]" 46.7738
+cap "la_data_out[6]" "la_data_out[5]" 40267.9
+cap "la_oenb[62]" "la_data_out[62]" 46.7738
+cap "wbs_dat_i[16]" "wbs_dat_o[16]" 46.7738
+cap "io_analog[2]" "la_data_in[122]" 1.4621
+cap "wbs_dat_o[11]" "la_data_out[1]" 5.79259
+cap "wbs_cyc_i" "wbs_stb_i" 46.7738
+cap "io_analog[8]" "io_analog[9]" 1693.25
+cap "io_in[8]" "io_out[8]" 67.2299
+cap "la_oenb[79]" "la_data_in[80]" 46.7738
+cap "wbs_adr_i[29]" "wbs_dat_i[29]" 46.7738
+cap "la_oenb[5]" "la_data_out[5]" 46.7738
+cap "wbs_adr_i[13]" "wbs_dat_i[13]" 46.7738
+cap "la_data_in[121]" "m2_33290_207480#" 3.42049
+cap "la_data_out[43]" "la_oenb[43]" 46.7738
+cap "la_data_out[77]" "la_oenb[77]" 46.7738
+cap "la_data_in[95]" "la_data_out[95]" 46.7738
+cap "io_analog[4]" "io_clamp_low[0]" 468.333
+cap "wbs_adr_i[14]" "la_data_out[1]" 5.79259
+cap "la_data_out[25]" "la_oenb[25]" 46.7738
+cap "la_data_out[3]" "la_data_out[1]" 0.370339
+cap "vssa2" "m2_53493_202942#" 79.9183
+cap "wbs_dat_i[3]" "wbs_adr_i[3]" 46.7738
+cap "vccd2" "m2_33290_207480#" 366.573
+cap "la_data_out[49]" "la_data_in[49]" 46.7738
+cap "la_data_out[96]" "la_data_in[96]" 46.7738
+cap "wbs_adr_i[27]" "wbs_dat_i[27]" 46.7738
+cap "la_oenb[32]" "la_data_out[32]" 46.7738
+cap "la_data_in[116]" "la_data_out[116]" 46.7738
+cap "gpio_noesd[2]" "io_in_3v3[9]" 67.2299
+cap "io_analog[4]" "io_analog[4]" 26259.4
+cap "wbs_adr_i[25]" "wbs_dat_o[24]" 46.7738
+cap "la_data_in[2]" "la_data_out[2]" 46.7738
+cap "la_data_out[24]" "la_oenb[24]" 46.7738
+cap "wbs_adr_i[12]" "la_data_out[1]" 5.79259
+cap "wb_clk_i" "wb_rst_i" 46.7738
+cap "la_data_out[83]" "la_oenb[83]" 46.7738
+cap "la_oenb[67]" "la_data_in[68]" 46.7738
+cap "m1_49580_204344#" "io_analog[2]" 22.2661
+cap "vccd1" "m2_55208_202785#" 6.16121
+cap "wbs_adr_i[25]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[28]" "wbs_dat_i[28]" 46.7738
+cap "m2_54170_202730#" "m2_53160_202790#" 3.72999
+cap "la_data_out[61]" "la_data_in[61]" 46.7738
+cap "io_out[22]" "io_in[22]" 67.2299
+cap "io_out[23]" "io_in[23]" 67.2299
+cap "wbs_adr_i[16]" "wbs_dat_i[16]" 46.7738
+cap "gpio_analog[12]" "m2_53493_202942#" 57.8844
+cap "la_oenb[20]" "la_data_in[21]" 46.7738
+cap "la_data_out[52]" "la_data_in[52]" 46.7738
+cap "la_data_in[29]" "la_oenb[28]" 46.7738
+cap "wbs_adr_i[30]" "wbs_dat_o[29]" 46.7738
+cap "vccd2" "io_analog[3]" 1369.55
+cap "la_data_in[100]" "la_data_out[100]" 46.7738
+cap "la_oenb[122]" "la_data_in[123]" 46.7738
+cap "la_data_out[45]" "la_oenb[45]" 46.7738
+cap "la_data_out[84]" "la_oenb[84]" 46.7738
+cap "la_data_in[121]" "io_analog[2]" 2.11832
+cap "wbs_dat_i[27]" "la_data_out[1]" 5.79259
+cap "la_oenb[29]" "la_data_out[29]" 46.7738
+cap "gpio_noesd[7]" "io_in_3v3[14]" 67.2299
+cap "la_data_in[82]" "la_data_out[82]" 46.7738
+cap "la_oenb[56]" "la_data_out[56]" 46.7738
+cap "la_data_out[91]" "la_oenb[91]" 46.7738
+cap "io_in_3v3[12]" "gpio_noesd[5]" 67.2299
+cap "m2_33290_207480#" "m2_53840_202790#" 1.95285
+cap "wbs_adr_i[6]" "wbs_dat_o[5]" 46.7738
+cap "la_data_in[13]" "la_oenb[12]" 46.7738
+cap "la_oenb[59]" "la_data_in[60]" 46.7738
+cap "la_data_out[69]" "la_oenb[69]" 46.7738
+cap "la_oenb[98]" "la_data_out[98]" 46.7738
+cap "gpio_noesd[9]" "gpio_analog[9]" 67.2299
+cap "io_in_3v3[17]" "gpio_noesd[10]" 67.2299
+cap "wbs_dat_i[25]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[3]" "wbs_dat_o[3]" 46.7738
+cap "user_clock2" "user_irq[0]" 46.7738
+cap "la_data_out[7]" "la_data_out[8]" 37030.3
+cap "wbs_dat_i[16]" "la_data_out[1]" 5.79259
+cap "la_data_in[93]" "la_oenb[92]" 46.7738
+cap "vccd2" "io_analog[2]" 10711.3
+cap "la_data_in[50]" "la_data_out[50]" 46.7738
+cap "la_data_in[102]" "la_data_out[102]" 46.7738
+cap "la_data_out[77]" "la_data_in[77]" 46.7738
+cap "io_oeb[9]" "io_out[9]" 67.2299
+cap "la_data_in[102]" "la_oenb[101]" 46.7738
+cap "vssa2" "m2_53160_202790#" 111.361
+cap "user_clock2" "la_oenb[127]" 46.7738
+cap "la_data_in[8]" "la_data_out[8]" 46.7738
+cap "io_in[9]" "io_in_3v3[9]" 67.2299
+cap "vssa2" "io_analog[5]" 14585.2
+cap "wbs_dat_o[10]" "la_data_out[1]" 5.79259
+cap "la_data_in[54]" "la_data_out[54]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 22388.4
+cap "la_data_in[127]" "la_data_in[123]" 16.4928
cap "io_in[4]" "io_out[4]" 67.2299
-cap "la_data_in[124]" "la_oenb[123]" 46.7738
-cap "la_oenb[103]" "la_data_out[103]" 46.7738
-cap "la_oenb[45]" "la_data_in[46]" 46.7738
-cap "io_analog[2]" "m2_33290_207480#" 3359.84
+cap "la_data_out[113]" "la_data_in[113]" 46.7738
+cap "la_oenb[14]" "la_data_in[15]" 46.7738
+cap "la_data_out[0]" "la_data_in[0]" 46.7738
+cap "io_in_3v3[2]" "io_in[2]" 67.2299
+cap "vccd2" "io_analog[7]" 10115.8
+cap "io_in[7]" "io_in_3v3[7]" 67.2299
+cap "la_oenb[117]" "la_data_in[118]" 46.7738
+cap "wbs_dat_o[1]" "wbs_sel_i[1]" 46.7738
+cap "la_oenb[58]" "la_data_in[59]" 46.7738
+cap "la_data_in[101]" "la_oenb[100]" 46.7738
+cap "gpio_noesd[9]" "io_in_3v3[16]" 67.2299
+cap "la_data_out[18]" "la_data_in[18]" 46.7738
+cap "io_analog[4]" "io_analog[5]" 15915.8
+cap "vssa2" "gpio_analog[13]" 11589.5
+cap "gpio_analog[12]" "m2_53160_202790#" 5.51548
+cap "io_out[10]" "io_in[10]" 67.2299
+cap "wbs_dat_i[11]" "la_data_out[1]" 5.79259
+cap "m2_55523_202892#" "m2_55208_202785#" 32.4727
+cap "wbs_adr_i[22]" "wbs_dat_i[22]" 46.7738
+cap "wbs_dat_i[18]" "la_data_out[1]" 5.79259
+cap "la_data_in[106]" "la_data_out[106]" 46.7738
+cap "la_data_in[127]" "la_data_in[126]" 27401.1
+cap "wbs_dat_i[7]" "wbs_adr_i[7]" 46.7738
+cap "m2_54833_202912#" "m2_53840_202790#" 8.15576
+cap "la_data_in[127]" "la_data_in[120]" 0.481245
+cap "io_analog[2]" "m2_53840_202790#" 0.0675945
+cap "la_data_in[31]" "la_data_out[31]" 46.7738
+cap "la_oenb[49]" "la_data_out[49]" 46.7738
+cap "io_out[18]" "io_in[18]" 67.2299
+cap "la_data_in[91]" "la_oenb[90]" 46.7738
+cap "wbs_adr_i[22]" "wbs_dat_o[21]" 46.7738
+cap "la_oenb[36]" "la_data_in[37]" 46.7738
+cap "vccd1" "la_data_in[124]" 2122.7
+cap "wbs_adr_i[17]" "wbs_dat_o[16]" 46.7738
+cap "wbs_dat_i[13]" "la_data_out[1]" 5.79259
+cap "la_data_out[89]" "la_data_in[89]" 46.7738
+cap "wbs_adr_i[4]" "wbs_sel_i[3]" 46.7738
+cap "la_data_in[53]" "la_oenb[52]" 46.7738
+cap "la_oenb[112]" "la_data_in[113]" 46.7738
+cap "la_data_out[3]" "la_data_in[3]" 46.7738
+cap "io_out[15]" "io_oeb[15]" 67.2299
+cap "la_data_in[55]" "la_data_out[55]" 46.7738
+cap "la_oenb[72]" "la_data_out[72]" 46.7738
+cap "vssa2" "io_analog[4]" 12792.7
+cap "la_data_out[85]" "la_oenb[85]" 46.7738
+cap "vssa2" "gpio_analog[12]" 4194.44
+cap "la_data_out[58]" "la_oenb[58]" 46.7738
+cap "la_data_out[46]" "la_oenb[46]" 46.7738
+cap "la_oenb[110]" "la_data_out[110]" 46.7738
+cap "la_oenb[35]" "la_data_out[35]" 46.7738
+cap "la_data_out[41]" "la_data_in[41]" 46.7738
+cap "la_data_out[41]" "la_oenb[41]" 46.7738
+cap "la_oenb[71]" "la_data_in[72]" 46.7738
+cap "la_data_out[111]" "la_data_in[111]" 46.7738
+cap "la_oenb[97]" "la_data_in[98]" 46.7738
+cap "wbs_dat_o[9]" "wbs_adr_i[10]" 46.7738
+cap "io_in[17]" "io_out[17]" 67.2299
+cap "vssa2" "la_data_out[2]" 870.097
+cap "vccd1" "la_data_in[125]" 2064.36
+cap "m2_54520_202790#" "m2_33290_207480#" 1.36477
+cap "wbs_adr_i[29]" "la_data_out[1]" 5.79259
+cap "la_oenb[30]" "la_data_out[30]" 46.7738
+cap "la_data_in[50]" "la_oenb[49]" 46.7738
+cap "wbs_adr_i[23]" "la_data_out[1]" 5.79259
+cap "la_data_out[102]" "la_oenb[102]" 46.7738
+cap "io_analog[5]" "io_analog[5]" 26259.4
+cap "la_data_in[30]" "la_oenb[29]" 46.7738
+cap "gpio_analog[15]" "gpio_noesd[15]" 67.2299
+cap "io_out[2]" "io_in[2]" 67.2299
+cap "la_data_in[124]" "la_data_in[125]" 40363.9
+cap "la_oenb[94]" "la_data_out[94]" 46.7738
+cap "la_data_out[37]" "la_data_in[37]" 46.7738
+cap "la_data_in[51]" "la_data_out[51]" 46.7738
+cap "la_oenb[71]" "la_data_out[71]" 46.7738
+cap "io_in[14]" "io_out[14]" 67.2299
+cap "la_oenb[54]" "la_data_out[54]" 46.7738
+cap "la_data_out[58]" "la_data_in[58]" 46.7738
+cap "la_oenb[65]" "la_data_out[65]" 46.7738
+cap "gpio_analog[0]" "gpio_noesd[0]" 67.2299
+cap "wbs_dat_i[9]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[17]" "wbs_adr_i[18]" 46.7738
+cap "wbs_adr_i[23]" "wbs_dat_i[23]" 46.7738
+cap "la_oenb[33]" "la_data_in[34]" 46.7738
+cap "wbs_dat_o[20]" "la_data_out[1]" 5.79259
+cap "la_data_out[68]" "la_data_in[68]" 46.7738
+cap "io_analog[6]" "io_analog[6]" 26792.4
+cap "la_oenb[16]" "la_data_out[16]" 46.7738
+cap "la_data_out[48]" "la_data_in[48]" 46.7738
+cap "wbs_dat_o[13]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[10]" "wbs_dat_i[10]" 46.7738
+cap "io_out[10]" "io_oeb[10]" 67.2299
+cap "io_clamp_low[2]" "io_analog[6]" 468.333
+cap "la_oenb[1]" "la_data_in[2]" 46.7738
+cap "io_in[0]" "io_out[0]" 67.2299
+cap "wbs_dat_i[29]" "la_data_out[1]" 5.79259
+cap "io_analog[4]" "io_clamp_low[0]" 735.436
+cap "wbs_dat_o[21]" "wbs_dat_i[21]" 46.7738
+cap "wbs_dat_i[30]" "wbs_adr_i[30]" 46.7738
+cap "m2_53493_202942#" "m2_33290_207480#" 2.99625
+cap "vccd1" "m2_55523_202892#" 42.2459
+cap "la_data_in[123]" "la_data_in[126]" 27.9166
+cap "io_in[25]" "io_in_3v3[25]" 67.2299
+cap "la_data_in[104]" "la_oenb[103]" 46.7738
+cap "la_data_in[65]" "la_oenb[64]" 46.7738
+cap "la_data_out[125]" "la_oenb[125]" 46.7738
+cap "la_oenb[15]" "la_data_in[16]" 46.7738
+cap "la_data_in[43]" "la_oenb[42]" 46.7738
+cap "la_data_in[123]" "la_data_in[120]" 6.54701
+cap "la_oenb[127]" "la_data_out[127]" 46.7738
+cap "vccd1" "la_data_in[122]" 2490.74
+cap "la_data_out[63]" "la_oenb[63]" 46.7738
+cap "wbs_dat_o[8]" "wbs_adr_i[9]" 46.7738
+cap "m2_54520_202790#" "m2_54833_202912#" 32.9276
+cap "wbs_adr_i[17]" "la_data_out[1]" 5.79259
+cap "gpio_noesd[13]" "io_in_3v3[20]" 67.2299
+cap "wbs_adr_i[28]" "la_data_out[1]" 5.79259
cap "io_analog[6]" "io_clamp_high[2]" 468.333
-cap "la_data_in[46]" "la_data_out[46]" 46.7738
+cap "wbs_dat_i[15]" "wbs_dat_o[15]" 46.7738
+cap "io_oeb[2]" "io_out[2]" 67.2299
+cap "m2_54520_202790#" "io_analog[2]" 0.165659
+cap "user_irq[1]" "user_irq[2]" 46.7738
+cap "wbs_adr_i[13]" "la_data_out[1]" 5.79259
+cap "vccd2" "io_analog[8]" 781.607
+cap "la_data_in[124]" "la_data_in[122]" 302.51
+cap "la_data_out[4]" "la_data_out[5]" 41443
+cap "la_data_out[92]" "la_oenb[92]" 46.7738
+cap "io_in_3v3[24]" "io_in[24]" 67.2299
+cap "vccd2" "io_analog[9]" 1461.73
+cap "wbs_adr_i[24]" "la_data_out[1]" 5.79259
+cap "wbs_stb_i" "wbs_we_i" 46.7738
+cap "la_data_in[19]" "la_oenb[18]" 46.7738
+cap "la_data_out[60]" "la_data_in[60]" 46.7738
+cap "la_data_in[26]" "la_oenb[25]" 46.7738
+cap "la_data_in[79]" "la_data_out[79]" 46.7738
+cap "la_oenb[93]" "la_data_out[93]" 46.7738
+cap "vssa2" "la_data_out[1]" 1495.21
+cap "gpio_noesd[2]" "gpio_analog[2]" 67.2299
+cap "la_data_in[29]" "la_data_out[29]" 46.7738
+cap "wbs_dat_o[25]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[25]" "wbs_adr_i[26]" 46.7738
+cap "la_oenb[94]" "la_data_in[95]" 46.7738
+cap "io_analog[7]" "io_analog[6]" 2427.12
+cap "la_data_out[90]" "la_oenb[90]" 46.7738
+cap "la_oenb[26]" "la_data_out[26]" 46.7738
+cap "la_oenb[41]" "la_data_in[42]" 46.7738
+cap "la_data_out[101]" "la_oenb[101]" 46.7738
+cap "la_oenb[107]" "la_data_in[108]" 46.7738
+cap "la_data_in[125]" "la_data_in[122]" 34.4614
+cap "m1_49580_204344#" "vccd1" 0.88795
+cap "la_data_in[127]" "m2_33290_207480#" 3.28801
+cap "m2_53493_202942#" "m2_54833_202912#" 8.08772
+cap "la_data_out[48]" "la_oenb[48]" 46.7738
+cap "m2_55208_202785#" "m2_53840_202790#" 0.236247
+cap "io_out[7]" "io_oeb[7]" 67.2299
+cap "io_analog[2]" "m2_53493_202942#" 0.227745
+cap "wbs_dat_i[27]" "wbs_dat_o[27]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 21353.1
+cap "io_analog[6]" "io_analog[6]" 22388.4
+cap "wbs_dat_o[10]" "wbs_adr_i[11]" 46.7738
+cap "wbs_adr_i[19]" "la_data_out[1]" 5.79259
+cap "io_out[7]" "io_in[7]" 67.2299
+cap "io_clamp_low[2]" "io_clamp_high[2]" 468.333
+cap "wbs_adr_i[2]" "wbs_sel_i[1]" 46.7738
+cap "m2_54170_202730#" "m2_33290_207480#" 6.99285
+cap "io_analog[6]" "io_clamp_low[2]" 493.833
+cap "io_in_3v3[18]" "io_in[18]" 67.2299
+cap "la_data_in[83]" "la_oenb[82]" 46.7738
+cap "wbs_dat_i[18]" "wbs_dat_o[18]" 46.7738
+cap "la_data_out[126]" "la_data_in[126]" 46.7738
+cap "la_data_out[45]" "la_data_in[45]" 46.7738
+cap "la_oenb[0]" "la_data_in[1]" 46.7738
+cap "m2_53160_202790#" "m2_33290_207480#" 3.33846
+cap "io_in_3v3[22]" "gpio_noesd[15]" 67.2299
+cap "la_data_out[73]" "la_oenb[73]" 46.7738
+cap "wbs_dat_i[29]" "wbs_dat_o[29]" 46.7738
+cap "gpio_noesd[3]" "io_in_3v3[10]" 67.2299
+cap "la_oenb[2]" "la_data_out[2]" 46.7738
+cap "io_in_3v3[8]" "gpio_noesd[1]" 67.2299
+cap "la_data_in[121]" "vccd1" 4804.4
+cap "wbs_adr_i[17]" "wbs_dat_i[17]" 46.7738
+cap "la_data_out[4]" "la_data_in[4]" 46.7738
+cap "io_in[5]" "io_out[5]" 67.2299
+cap "io_out[17]" "io_oeb[17]" 67.2299
+cap "la_data_out[2]" "la_data_out[1]" 27417.9
+cap "wbs_dat_o[4]" "wbs_adr_i[5]" 46.7738
+cap "wbs_dat_i[22]" "wbs_dat_o[22]" 46.7738
+cap "wbs_dat_o[16]" "la_data_out[1]" 5.79259
+cap "wbs_adr_i[1]" "wbs_sel_i[0]" 46.7738
+cap "la_data_out[85]" "la_data_in[85]" 46.7738
+cap "wbs_dat_i[0]" "wbs_dat_o[0]" 46.7738
+cap "la_data_out[103]" "la_data_in[103]" 46.7738
+cap "la_oenb[50]" "la_data_out[50]" 46.7738
+cap "la_data_out[59]" "la_oenb[59]" 46.7738
+cap "vssa2" "la_data_out[7]" 874.91
+cap "wbs_dat_o[20]" "wbs_adr_i[21]" 46.7738
+cap "la_oenb[4]" "la_data_out[4]" 46.7738
+cap "la_data_out[125]" "la_data_in[125]" 46.7738
+cap "gpio_analog[7]" "m2_34420_199220#" 4360.58
+cap "la_data_in[121]" "la_data_in[124]" 17.9665
+cap "wbs_adr_i[13]" "wbs_dat_o[12]" 46.7738
+cap "la_data_in[81]" "la_data_out[81]" 46.7738
+cap "wbs_dat_i[11]" "wbs_adr_i[11]" 46.7738
+cap "io_out[1]" "io_in[1]" 67.2299
+cap "io_analog[5]" "io_analog[5]" 21353.1
+cap "la_data_in[99]" "la_data_out[99]" 46.7738
+cap "io_analog[6]" "io_clamp_high[2]" 493.833
+cap "io_in_3v3[23]" "gpio_noesd[16]" 67.2299
+cap "m1_49580_204344#" "gpio_analog[7]" 160.193
+cap "la_oenb[26]" "la_data_in[27]" 46.7738
+cap "la_data_out[34]" "la_oenb[34]" 46.7738
+cap "la_oenb[65]" "la_data_in[66]" 46.7738
+cap "io_in[10]" "io_in_3v3[10]" 67.2299
+cap "la_oenb[55]" "la_data_in[56]" 46.7738
+cap "la_oenb[88]" "la_data_in[89]" 46.7738
+cap "vssa2" "m2_33290_207480#" 4013.42
+cap "la_oenb[124]" "la_data_out[124]" 46.7738
+cap "la_data_in[127]" "io_analog[2]" 74.5519
+cap "la_data_out[104]" "la_oenb[104]" 46.7738
+cap "wbs_adr_i[27]" "la_data_out[1]" 5.79259
+cap "la_data_in[121]" "la_data_in[125]" 18.8163
+cap "wbs_adr_i[20]" "wbs_dat_i[20]" 46.7738
+cap "la_oenb[42]" "la_data_out[42]" 46.7738
+cap "la_data_in[88]" "la_data_out[88]" 46.7738
+cap "io_out[24]" "io_in[24]" 67.2299
+cap "m2_54170_202730#" "m2_54833_202912#" 39.2811
+cap "la_oenb[35]" "la_data_in[36]" 46.7738
+cap "io_in[11]" "io_in_3v3[11]" 67.2299
+cap "wbs_dat_o[28]" "wbs_adr_i[29]" 46.7738
+cap "m3_26500_684896#" "io_analog[10]" 38.7515
+cap "m2_54170_202730#" "io_analog[2]" 0.161373
+cap "m2_54833_202912#" "m2_53160_202790#" 1.04826
+cap "la_data_out[103]" "la_oenb[103]" 46.7738
+cap "io_clamp_low[1]" "io_analog[5]" 468.333
+cap "la_oenb[112]" "la_data_out[112]" 46.7738
+cap "wbs_adr_i[16]" "la_data_out[1]" 5.79259
+cap "io_analog[2]" "m2_53160_202790#" 0.362355
+cap "la_data_out[37]" "la_oenb[37]" 46.7738
+cap "gpio_noesd[13]" "gpio_analog[13]" 67.2299
+cap "wbs_dat_o[6]" "wbs_dat_i[6]" 46.7738
+cap "io_analog[4]" "m2_33290_207480#" 2.08078
+cap "io_clamp_low[1]" "io_clamp_high[1]" 468.333
+cap "la_data_in[123]" "m2_33290_207480#" 3.42049
+cap "wbs_adr_i[8]" "wbs_dat_o[7]" 46.7738
+cap "vccd2" "gpio_analog[7]" 743.088
+cap "la_oenb[107]" "la_data_out[107]" 46.7738
+cap "la_oenb[0]" "la_data_out[0]" 46.7738
+cap "gpio_noesd[11]" "gpio_analog[11]" 67.2299
+cap "vssa2" "io_analog[3]" 6607.54
+cap "gpio_analog[12]" "m2_33290_207480#" 262.521
+cap "la_oenb[19]" "la_data_in[20]" 46.7738
+cap "la_data_out[21]" "la_data_in[21]" 46.7738
+cap "gpio_noesd[7]" "gpio_analog[7]" 67.2299
+cap "la_data_in[10]" "la_data_out[10]" 46.7738
+cap "m2_54520_202790#" "m2_55208_202785#" 8.16064
+cap "wbs_dat_o[24]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[12]" "wbs_adr_i[12]" 46.7738
+cap "wbs_cyc_i" "wbs_ack_o" 46.7738
+cap "la_data_out[52]" "la_oenb[52]" 46.7738
+cap "la_oenb[116]" "la_data_in[117]" 46.7738
+cap "io_analog[6]" "io_analog[6]" 26259.4
+cap "wbs_ack_o" "wb_rst_i" 46.7738
+cap "la_data_in[75]" "la_oenb[74]" 46.7738
+cap "la_data_out[11]" "la_data_in[11]" 46.7738
+cap "la_data_in[88]" "la_oenb[87]" 46.7738
+cap "io_oeb[23]" "io_out[23]" 67.2299
+cap "wbs_adr_i[26]" "la_data_out[1]" 5.79259
+cap "la_data_in[17]" "la_data_out[17]" 46.7738
+cap "la_oenb[113]" "la_data_out[113]" 46.7738
+cap "io_in_3v3[13]" "io_in[13]" 67.2299
+cap "vssa2" "io_analog[2]" 72.4962
+cap "la_data_in[121]" "la_data_in[122]" 49581.4
+cap "gpio_noesd[14]" "io_in_3v3[21]" 67.2299
+cap "vccd2" "io_analog[10]" 13360.7
+cap "la_data_in[126]" "m2_33290_207480#" 2.87201
+cap "la_data_out[24]" "la_data_in[24]" 46.7738
+cap "la_oenb[30]" "la_data_in[31]" 46.7738
+cap "la_data_out[106]" "la_oenb[106]" 46.7738
+cap "io_analog[4]" "io_analog[3]" 14425.7
+cap "la_oenb[63]" "la_data_in[64]" 46.7738
+cap "m1_49580_204344#" "m2_34420_199220#" 47.9789
+cap "wbs_dat_o[6]" "wbs_adr_i[7]" 46.7738
+cap "m2_33290_207480#" "la_data_in[120]" 2.65181
+cap "wbs_adr_i[19]" "wbs_dat_i[19]" 46.7738
+cap "la_data_out[108]" "la_oenb[108]" 46.7738
+cap "wbs_dat_i[23]" "la_data_out[1]" 5.79259
+cap "la_data_in[7]" "la_data_out[7]" 46.7738
+cap "la_data_out[9]" "la_oenb[9]" 46.7738
+cap "la_data_in[112]" "la_oenb[111]" 46.7738
+cap "la_data_in[115]" "la_data_out[115]" 46.7738
+cap "la_oenb[88]" "la_data_out[88]" 46.7738
+cap "la_oenb[66]" "la_data_out[66]" 46.7738
+cap "la_data_out[14]" "la_oenb[14]" 46.7738
+cap "la_oenb[51]" "la_data_out[51]" 46.7738
+cap "la_data_in[42]" "la_data_out[42]" 46.7738
+cap "la_oenb[96]" "la_data_out[96]" 46.7738
+cap "la_data_in[53]" "la_data_out[53]" 46.7738
+cap "io_in_3v3[24]" "gpio_noesd[17]" 67.2299
+cap "la_oenb[121]" "la_data_in[122]" 46.7738
+cap "m2_53493_202942#" "m2_55208_202785#" 0.24742
+cap "wbs_dat_i[14]" "wbs_dat_o[14]" 46.7738
+cap "la_data_out[74]" "la_data_in[74]" 46.7738
+cap "la_data_in[73]" "la_data_out[73]" 46.7738
+cap "gpio_noesd[12]" "io_in_3v3[19]" 67.2299
+cap "vssa2" "io_analog[7]" 6815.3
+cap "la_data_in[123]" "io_analog[2]" 2.11832
+cap "la_oenb[3]" "la_data_in[4]" 46.7738
+cap "io_analog[2]" "gpio_analog[12]" 157.466
+cap "io_in_3v3[26]" "io_oeb[25]" 67.2299
+cap "la_data_out[47]" "la_data_in[47]" 46.7738
+cap "la_data_in[62]" "la_oenb[61]" 46.7738
+cap "io_oeb[1]" "io_out[1]" 67.2299
+cap "la_data_in[106]" "la_oenb[105]" 46.7738
+cap "vccd2" "m2_34420_199220#" 425.076
+cap "wbs_adr_i[19]" "wbs_dat_o[18]" 46.7738
+cap "vccd2" "m3_26500_684896#" 205.187
+cap "wbs_dat_o[27]" "wbs_adr_i[28]" 46.7738
+cap "io_in[21]" "io_out[21]" 67.2299
+cap "la_data_in[71]" "la_data_out[71]" 46.7738
+cap "la_data_out[91]" "la_data_in[91]" 46.7738
+cap "wbs_adr_i[31]" "la_data_out[1]" 5.79259
+cap "m1_49580_204344#" "vccd2" 394.016
+cap "la_data_in[12]" "la_data_out[12]" 46.7738
+cap "la_data_out[59]" "la_data_in[59]" 46.7738
+cap "la_data_in[77]" "la_oenb[76]" 46.7738
+cap "la_data_out[67]" "la_oenb[67]" 46.7738
+cap "wbs_dat_i[17]" "la_data_out[1]" 5.79259
+cap "m2_55523_202892#" "m2_53840_202790#" 2.37837
+cap "wbs_dat_o[8]" "wbs_dat_i[8]" 46.7738
+cap "la_data_in[118]" "la_data_out[118]" 46.7738
+cap "la_oenb[40]" "la_data_out[40]" 46.7738
+cap "la_data_out[61]" "la_oenb[61]" 46.7738
+cap "la_data_in[105]" "la_oenb[104]" 46.7738
+cap "io_oeb[2]" "io_in_3v3[3]" 67.2299
+cap "io_out[20]" "io_oeb[20]" 67.2299
+cap "io_analog[2]" "la_data_in[126]" 1.4621
+cap "wbs_dat_o[12]" "la_data_out[1]" 5.79259
+cap "wbs_adr_i[2]" "wbs_dat_i[2]" 46.7738
+cap "la_data_in[75]" "la_data_out[75]" 46.7738
+cap "io_in[5]" "io_in_3v3[5]" 67.2299
+cap "vssa2" "la_data_out[6]" 886.965
+cap "io_analog[2]" "la_data_in[120]" 4.42856
+cap "io_analog[6]" "io_analog[6]" 21353.1
+cap "la_oenb[70]" "la_data_out[70]" 46.7738
+cap "io_oeb[0]" "io_in_3v3[1]" 67.2299
+cap "vccd1" "m2_54520_202790#" 0.152921
+cap "la_data_in[13]" "la_data_out[13]" 46.7738
+cap "gpio_noesd[8]" "io_in_3v3[15]" 67.2299
+cap "la_data_out[3]" "la_data_out[4]" 43187.7
+cap "wbs_dat_o[29]" "la_data_out[1]" 5.79259
+cap "la_data_out[97]" "la_data_in[97]" 46.7738
+cap "io_out[6]" "io_oeb[6]" 67.2299
+cap "la_data_in[69]" "la_oenb[68]" 46.7738
+cap "wbs_adr_i[15]" "la_data_out[1]" 5.79259
+cap "la_oenb[31]" "la_data_out[31]" 46.7738
+cap "wbs_dat_o[26]" "wbs_adr_i[27]" 46.7738
+cap "la_data_in[74]" "la_oenb[73]" 46.7738
+cap "io_oeb[12]" "io_out[12]" 67.2299
+cap "la_oenb[19]" "la_data_out[19]" 46.7738
+cap "la_data_in[24]" "la_oenb[23]" 46.7738
+cap "la_oenb[1]" "la_data_out[1]" 46.7738
+cap "la_data_in[9]" "la_oenb[8]" 46.7738
+cap "la_data_in[94]" "la_oenb[93]" 46.7738
+cap "io_analog[4]" "io_analog[4]" 22465.6
+cap "la_oenb[91]" "la_data_in[92]" 46.7738
+cap "la_data_in[18]" "la_oenb[17]" 46.7738
+cap "io_in_3v3[17]" "io_in[17]" 67.2299
+cap "la_data_in[110]" "la_data_out[110]" 46.7738
+cap "m2_54170_202730#" "m2_55208_202785#" 2.66226
+cap "gpio_analog[17]" "gpio_noesd[17]" 67.2299
+cap "la_oenb[28]" "la_data_out[28]" 46.7738
+cap "la_data_in[107]" "la_oenb[106]" 46.7738
+cap "la_data_out[116]" "la_oenb[116]" 46.7738
+cap "wbs_adr_i[24]" "wbs_dat_o[23]" 46.7738
+cap "la_data_in[62]" "la_data_out[62]" 46.7738
+cap "la_data_in[9]" "la_data_out[9]" 46.7738
+cap "wbs_dat_i[10]" "la_data_out[1]" 5.79259
+cap "wbs_adr_i[21]" "la_data_out[1]" 5.79259
+cap "la_data_in[35]" "la_oenb[34]" 46.7738
+cap "la_data_out[92]" "la_data_in[92]" 46.7738
+cap "la_data_in[99]" "la_oenb[98]" 46.7738
+cap "la_data_out[117]" "la_data_in[117]" 46.7738
+cap "la_oenb[100]" "la_data_out[100]" 46.7738
+cap "wbs_dat_i[31]" "la_data_out[1]" 5.79259
+cap "io_in[25]" "io_out[25]" 67.2299
+cap "la_data_in[110]" "la_oenb[109]" 46.7738
+cap "la_data_in[115]" "la_oenb[114]" 46.7738
+cap "la_oenb[60]" "la_data_in[61]" 46.7738
+cap "wbs_dat_i[19]" "la_data_out[1]" 5.79259
+cap "io_analog[4]" "io_clamp_high[0]" 468.333
+cap "io_in[19]" "io_in_3v3[19]" 67.2299
+cap "wbs_dat_o[30]" "la_data_out[1]" 5.79259
+cap "la_data_in[14]" "la_oenb[13]" 46.7738
+cap "la_data_in[45]" "la_oenb[44]" 46.7738
cap "io_analog[4]" "io_clamp_low[0]" 493.833
-cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" 8.88178e-16
-cap "8bit_sens_0/GND" "8bit_sens_0/OUTx5x" 8.88178e-16
+cap "vccd1" "m2_53493_202942#" 0.0162526
+cap "wbs_adr_i[4]" "wbs_dat_i[4]" 46.7738
+cap "gpio_noesd[14]" "gpio_analog[14]" 67.2299
+cap "la_data_in[72]" "la_data_out[72]" 46.7738
+cap "la_oenb[11]" "la_data_in[12]" 46.7738
+cap "la_data_out[95]" "la_oenb[95]" 46.7738
+cap "io_out[21]" "io_oeb[21]" 67.2299
+cap "wbs_dat_i[26]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[26]" "la_data_out[1]" 5.79259
+cap "wbs_sel_i[0]" "wbs_dat_o[0]" 46.7738
+cap "wbs_dat_i[26]" "wbs_adr_i[26]" 46.7738
+cap "la_oenb[80]" "la_data_out[80]" 46.7738
+cap "wbs_dat_o[19]" "la_data_out[1]" 5.79259
+cap "la_oenb[10]" "la_data_out[10]" 46.7738
+cap "la_oenb[2]" "la_data_in[3]" 46.7738
+cap "la_data_in[10]" "la_oenb[9]" 46.7738
+cap "user_irq[1]" "user_irq[0]" 46.7738
+cap "io_in_3v3[4]" "io_oeb[3]" 67.2299
+cap "la_data_out[17]" "la_oenb[17]" 46.7738
+cap "la_data_in[96]" "la_oenb[95]" 46.7738
+cap "la_oenb[70]" "la_data_in[71]" 46.7738
+cap "io_out[15]" "io_in[15]" 67.2299
+cap "la_oenb[21]" "la_data_out[21]" 46.7738
+cap "gpio_analog[12]" "gpio_noesd[12]" 67.2299
+cap "la_data_in[27]" "la_data_out[27]" 46.7738
+cap "la_data_in[82]" "la_oenb[81]" 46.7738
+cap "la_oenb[79]" "la_data_out[79]" 46.7738
+cap "wbs_dat_o[18]" "la_data_out[1]" 5.79259
+cap "la_data_out[74]" "la_oenb[74]" 46.7738
+cap "m2_54520_202790#" "m2_55523_202892#" 2.3884
+cap "vssa2" "io_analog[8]" 1645.69
+cap "io_oeb[5]" "io_out[5]" 67.2299
+cap "wbs_dat_o[28]" "la_data_out[1]" 5.79259
+cap "io_in_3v3[3]" "io_in[3]" 67.2299
+cap "vssa2" "io_analog[9]" 1623.5
+cap "la_data_out[15]" "la_data_in[15]" 46.7738
+cap "la_oenb[64]" "la_data_out[64]" 46.7738
+cap "io_in[20]" "io_in_3v3[20]" 67.2299
+cap "wbs_dat_i[31]" "wbs_adr_i[31]" 46.7738
+cap "io_analog[5]" "io_clamp_high[1]" 468.333
+cap "wbs_dat_i[9]" "wbs_dat_o[9]" 46.7738
+cap "vccd1" "la_data_in[127]" 2058.2
+cap "la_data_in[0]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[30]" "wbs_adr_i[31]" 46.7738
+cap "wbs_adr_i[11]" "la_data_out[1]" 5.79259
+cap "io_analog[5]" "io_analog[5]" 26792.4
+cap "la_oenb[51]" "la_data_in[52]" 46.7738
+cap "vccd1" "m2_54170_202730#" 0.00723639
+cap "la_data_out[23]" "la_oenb[23]" 46.7738
+cap "la_data_in[127]" "la_data_in[124]" 50.9691
+cap "io_out[25]" "io_oeb[25]" 67.2299
+cap "la_data_out[122]" "la_data_in[122]" 46.7738
+cap "la_oenb[89]" "la_data_in[90]" 46.7738
+cap "la_data_out[120]" "la_data_in[120]" 46.7738
+cap "m2_54833_202912#" "m2_33290_207480#" 7.50519
+cap "wbs_dat_o[3]" "wbs_sel_i[3]" 46.7738
+cap "wbs_dat_i[14]" "wbs_adr_i[14]" 46.7738
+cap "wbs_sel_i[2]" "wbs_dat_o[2]" 46.7738
+cap "la_oenb[33]" "la_data_out[33]" 46.7738
+cap "m2_53493_202942#" "m2_55523_202892#" 0.157044
+cap "la_data_out[117]" "la_oenb[117]" 46.7738
+cap "wbs_dat_o[27]" "la_data_out[1]" 5.79259
+cap "la_data_out[3]" "la_oenb[3]" 46.7738
+cap "la_data_out[119]" "la_data_in[119]" 46.7738
+cap "io_analog[2]" "m2_33290_207480#" 3359.84
+cap "la_data_in[39]" "la_oenb[38]" 46.7738
+cap "io_in_3v3[1]" "io_in[1]" 67.2299
+cap "la_data_out[43]" "la_data_in[43]" 46.7738
+cap "wbs_dat_o[5]" "wbs_dat_i[5]" 46.7738
+cap "gpio_analog[16]" "gpio_noesd[16]" 67.2299
+cap "la_data_in[36]" "la_data_out[36]" 46.7738
+cap "la_data_in[127]" "la_data_in[125]" 817.487
+cap "io_out[13]" "io_in[13]" 67.2299
+cap "la_data_in[33]" "la_data_out[33]" 46.7738
+cap "io_in[20]" "io_out[20]" 67.2299
+cap "la_data_in[22]" "la_data_out[22]" 46.7738
+cap "la_data_out[114]" "la_oenb[114]" 46.7738
+cap "la_oenb[12]" "la_data_out[12]" 46.7738
+cap "la_data_in[70]" "la_oenb[69]" 46.7738
+cap "io_oeb[1]" "io_in_3v3[2]" 67.2299
+cap "la_data_in[19]" "la_data_out[19]" 46.7738
+cap "io_in_3v3[13]" "gpio_noesd[6]" 67.2299
+cap "la_oenb[77]" "la_data_in[78]" 46.7738
+cap "io_in_3v3[15]" "io_in[15]" 67.2299
+cap "la_oenb[62]" "la_data_in[63]" 46.7738
+cap "la_data_out[120]" "la_oenb[120]" 46.7738
+cap "vccd1" "vssa2" 6.18595
+cap "wbs_dat_o[23]" "la_data_out[1]" 5.79259
+cap "la_data_out[64]" "la_data_in[64]" 46.7738
+cap "la_oenb[55]" "la_data_out[55]" 46.7738
+cap "la_data_out[76]" "la_data_in[76]" 46.7738
+cap "wbs_dat_i[30]" "la_data_out[1]" 5.79259
+cap "io_in[21]" "io_in_3v3[21]" 67.2299
+cap "la_data_out[81]" "la_oenb[81]" 46.7738
+cap "la_oenb[89]" "la_data_out[89]" 46.7738
+cap "wbs_dat_o[11]" "wbs_adr_i[12]" 46.7738
+cap "la_data_out[25]" "la_data_in[25]" 46.7738
+cap "wbs_adr_i[18]" "wbs_dat_i[18]" 46.7738
+cap "la_oenb[125]" "la_data_in[126]" 46.7738
+cap "la_oenb[123]" "la_data_in[124]" 46.7738
+cap "wbs_dat_i[19]" "wbs_dat_o[19]" 46.7738
+cap "wbs_dat_i[23]" "wbs_dat_o[23]" 46.7738
+cap "la_data_in[93]" "la_data_out[93]" 46.7738
+cap "la_oenb[124]" "la_data_in[125]" 46.7738
+cap "vssa2" "la_data_out[5]" 894.594
+cap "vccd2" "io_analog[6]" 12755
+cap "la_data_out[6]" "la_data_out[7]" 38749.5
+cap "m1_49580_204344#" "m2_53493_202942#" 1.78921
+cap "la_data_in[104]" "la_data_out[104]" 46.7738
+cap "io_in[12]" "io_out[12]" 67.2299
+cap "la_data_in[49]" "la_oenb[48]" 46.7738
+cap "io_analog[2]" "m2_54833_202912#" 0.147405
+cap "vccd1" "la_data_in[123]" 2112.75
+cap "wbs_dat_o[26]" "wbs_dat_i[26]" 46.7738
+cap "io_oeb[18]" "io_out[18]" 67.2299
+cap "io_oeb[4]" "io_out[4]" 67.2299
+cap "io_in_3v3[12]" "io_in[12]" 67.2299
+cap "la_data_in[127]" "la_data_in[122]" 41.1623
+cap "la_data_in[6]" "la_data_out[6]" 46.7738
+cap "io_oeb[11]" "io_out[11]" 67.2299
+cap "m2_54170_202730#" "m2_55523_202892#" 3.85136
+cap "la_data_in[123]" "la_data_in[124]" 30971.2
+cap "m2_55523_202892#" "m2_53160_202790#" 0.270747
+cap "la_data_in[94]" "la_data_out[94]" 46.7738
+cap "la_oenb[87]" "la_data_out[87]" 46.7738
+cap "la_data_in[127]" "la_oenb[126]" 46.7738
+cap "la_data_in[6]" "la_oenb[5]" 46.7738
+cap "la_data_in[73]" "la_oenb[72]" 46.7738
+cap "la_data_in[119]" "la_oenb[118]" 46.7738
+cap "vssa2" "gpio_analog[7]" 39652.2
+cap "wbs_dat_o[17]" "la_data_out[1]" 5.79259
+cap "la_data_in[105]" "la_data_out[105]" 46.7738
+cap "gpio_noesd[4]" "io_in_3v3[11]" 67.2299
+cap "io_out[24]" "io_oeb[24]" 67.2299
+cap "la_data_out[78]" "la_oenb[78]" 46.7738
+cap "la_oenb[123]" "la_data_out[123]" 46.7738
+cap "io_in_3v3[25]" "io_oeb[24]" 67.2299
+cap "vccd1" "la_data_in[126]" 2146.23
+cap "io_in_3v3[22]" "io_in[22]" 67.2299
+cap "la_data_in[16]" "la_data_out[16]" 46.7738
+cap "io_out[26]" "io_oeb[26]" 67.2299
+cap "wbs_dat_i[15]" "la_data_out[1]" 5.79259
+cap "vccd1" "la_data_in[120]" 75630.8
+cap "io_analog[5]" "io_clamp_high[1]" 493.833
+cap "wbs_dat_i[9]" "wbs_adr_i[9]" 46.7738
+cap "la_oenb[119]" "la_data_in[120]" 46.7738
+cap "la_data_in[123]" "la_data_in[125]" 980.991
+cap "wbs_dat_i[1]" "wbs_dat_o[1]" 46.7738
+cap "la_oenb[53]" "la_data_out[53]" 46.7738
+cap "io_oeb[0]" "io_out[0]" 67.2299
+cap "la_data_out[14]" "la_data_in[14]" 46.7738
+cap "io_in[11]" "io_out[11]" 67.2299
+cap "la_data_in[124]" "la_data_in[126]" 587.278
+cap "la_oenb[96]" "la_data_in[97]" 46.7738
+cap "io_in[6]" "io_out[6]" 67.2299
+cap "m2_54520_202790#" "m2_53840_202790#" 21.0574
+cap "la_data_in[109]" "la_data_out[109]" 46.7738
+cap "wbs_dat_i[24]" "wbs_adr_i[24]" 46.7738
+cap "vssa2" "io_analog[10]" 2072.82
+cap "la_data_out[13]" "la_oenb[13]" 46.7738
+cap "la_oenb[6]" "la_data_in[7]" 46.7738
+cap "wbs_adr_i[28]" "wbs_dat_i[28]" 46.7738
+cap "la_data_in[47]" "la_oenb[46]" 46.7738
+cap "la_oenb[54]" "la_data_in[55]" 46.7738
+cap "la_data_in[123]" "la_data_out[123]" 46.7738
+cap "la_data_out[11]" "la_oenb[11]" 46.7738
+cap "vssa2" "la_data_out[4]" 893.783
+cap "la_data_out[86]" "la_data_in[86]" 46.7738
+cap "la_data_in[54]" "la_oenb[53]" 46.7738
+cap "la_data_in[81]" "la_oenb[80]" 46.7738
+cap "m1_49580_204344#" "m2_53160_202790#" 1.11147
+cap "wbs_adr_i[25]" "wbs_dat_i[25]" 46.7738
+cap "la_data_in[44]" "la_data_out[44]" 46.7738
+cap "wbs_dat_i[12]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[22]" "la_data_out[1]" 5.79259
+cap "m1_49580_204344#" "io_analog[5]" 0.690053
+cap "la_data_out[112]" "la_data_in[112]" 46.7738
+cap "io_oeb[19]" "io_out[19]" 67.2299
+cap "la_data_in[125]" "la_data_in[126]" 41930.2
+cap "wbs_dat_o[11]" "wbs_dat_i[11]" 46.7738
+cap "la_data_in[121]" "la_data_in[127]" 7.83251
+cap "la_oenb[57]" "la_data_in[58]" 46.7738
+cap "la_data_in[108]" "la_data_out[108]" 46.7738
+cap "gpio_analog[1]" "gpio_noesd[1]" 67.2299
+cap "la_data_in[125]" "la_data_in[120]" 1.94287
+cap "m2_55208_202785#" "m2_33290_207480#" 0.757998
+cap "la_data_out[70]" "la_data_in[70]" 46.7738
+cap "la_data_out[78]" "la_data_in[78]" 46.7738
+cap "io_in[8]" "io_in_3v3[8]" 67.2299
+cap "la_oenb[45]" "la_data_in[46]" 46.7738
+cap "la_data_out[86]" "la_oenb[86]" 46.7738
+cap "io_analog[5]" "io_clamp_high[1]" 735.436
+cap "wbs_dat_i[17]" "wbs_dat_o[17]" 46.7738
+cap "wbs_dat_o[21]" "la_data_out[1]" 5.79259
+cap "la_data_in[39]" "la_data_out[39]" 46.7738
+cap "m2_53493_202942#" "m2_53840_202790#" 41.1462
+cap "wbs_adr_i[20]" "la_data_out[1]" 5.79259
+cap "wbs_dat_o[22]" "wbs_adr_i[23]" 46.7738
+cap "io_clamp_low[0]" "io_clamp_high[0]" 468.333
+cap "la_data_in[80]" "la_data_out[80]" 46.7738
+cap "la_oenb[66]" "la_data_in[67]" 46.7738
+cap "m2_34420_199220#" "gpio_analog[13]" 1533.31
+cap "la_data_in[123]" "la_data_in[122]" 32987.8
+cap "la_data_in[38]" "la_oenb[37]" 46.7738
+cap "la_data_out[38]" "la_oenb[38]" 46.7738
+cap "wbs_dat_o[9]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[30]" "wbs_dat_o[30]" 46.7738
+cap "vssa2" "m2_34420_199220#" 7364.13
+cap "io_analog[4]" "io_clamp_high[0]" 493.833
+cap "la_data_in[26]" "la_data_out[26]" 46.7738
+cap "vssa2" "m3_26500_684896#" 1183.07
+cap "wbs_dat_o[31]" "la_data_out[1]" 5.79259
+cap "m1_49580_204344#" "gpio_analog[13]" 42.5368
+cap "la_data_in[17]" "la_oenb[16]" 46.7738
+cap "la_data_out[34]" "la_data_in[34]" 46.7738
+cap "la_data_out[119]" "la_oenb[119]" 46.7738
+cap "m1_49580_204344#" "vssa2" 7931.42
+cap "io_in[9]" "io_out[9]" 67.2299
+cap "gpio_noesd[3]" "gpio_analog[3]" 67.2299
+cap "la_data_in[5]" "la_data_out[5]" 46.7738
+cap "vccd2" "io_analog[5]" 2114.88
+cap "la_oenb[10]" "la_data_in[11]" 46.7738
+cap "wbs_dat_i[2]" "wbs_dat_o[2]" 46.7738
+cap "la_oenb[24]" "la_data_in[25]" 46.7738
+cap "io_analog[4]" "io_clamp_high[0]" 735.436
+cap "wbs_adr_i[22]" "la_data_out[1]" 5.79259
+cap "io_in[26]" "io_in_3v3[26]" 67.2299
+cap "wbs_adr_i[15]" "wbs_dat_i[15]" 46.7738
+cap "la_oenb[22]" "la_data_in[23]" 46.7738
+cap "la_data_in[126]" "la_data_in[122]" 12.9992
+cap "io_in_3v3[23]" "io_in[23]" 67.2299
+cap "wbs_dat_i[20]" "wbs_dat_o[20]" 46.7738
+cap "wbs_dat_i[0]" "wbs_adr_i[0]" 46.7738
+cap "la_data_out[15]" "la_oenb[15]" 46.7738
+cap "gpio_analog[12]" "m2_34420_199220#" 117.714
+cap "la_data_in[122]" "la_data_in[120]" 53.131
+cap "la_data_in[90]" "la_data_out[90]" 46.7738
+cap "gpio_noesd[0]" "io_in_3v3[7]" 67.2299
+cap "la_data_in[127]" "la_data_out[127]" 46.7738
+cap "wbs_adr_i[10]" "la_data_out[1]" 5.79259
+cap "m2_54833_202912#" "m2_55208_202785#" 26.4727
+cap "la_data_in[121]" "la_data_out[121]" 46.7738
+cap "gpio_noesd[5]" "gpio_analog[5]" 67.2299
+cap "la_oenb[56]" "la_data_in[57]" 46.7738
+cap "m1_49580_204344#" "gpio_analog[12]" 237.933
+cap "io_analog[2]" "m2_55208_202785#" 0.0603769
+cap "la_data_out[38]" "la_data_in[38]" 46.7738
+cap "wbs_dat_o[12]" "wbs_dat_i[12]" 46.7738
+cap "io_oeb[16]" "io_out[16]" 67.2299
+cap "io_in[6]" "io_in_3v3[6]" 67.2299
+cap "vccd2" "vssa2" 88369.5
+cap "la_oenb[47]" "la_data_out[47]" 46.7738
+cap "la_data_out[118]" "la_oenb[118]" 46.7738
+cap "la_oenb[115]" "la_data_in[116]" 46.7738
+cap "io_clamp_low[2]" "io_analog[6]" 735.436
+cap "la_oenb[20]" "la_data_out[20]" 46.7738
+cap "la_data_in[83]" "la_data_out[83]" 46.7738
+cap "wbs_dat_o[4]" "wbs_dat_i[4]" 46.7738
+cap "m2_54170_202730#" "m2_53840_202790#" 83.6871
+cap "wbs_adr_i[14]" "wbs_dat_o[13]" 46.7738
+cap "la_oenb[121]" "la_data_out[121]" 46.7738
+cap "la_data_in[121]" "la_data_in[123]" 372.972
+cap "wbs_dat_o[14]" "la_data_out[1]" 5.79259
+cap "wbs_dat_i[8]" "wbs_adr_i[8]" 46.7738
+cap "la_oenb[21]" "la_data_in[22]" 46.7738
+cap "io_clamp_low[1]" "io_analog[5]" 735.436
+cap "m2_53160_202790#" "m2_53840_202790#" 82.4543
+cap "la_oenb[110]" "la_data_in[111]" 46.7738
+cap "la_oenb[0]" "la_data_out[1]" 5.79259
+cap "la_data_in[23]" "la_data_out[23]" 46.7738
+cap "la_data_in[32]" "la_oenb[31]" 46.7738
+cap "io_in[19]" "io_out[19]" 67.2299
+cap "vccd1" "m2_33290_207480#" 87.7272
+cap "la_oenb[4]" "la_data_in[5]" 46.7738
+cap "wbs_dat_i[24]" "wbs_dat_o[24]" 46.7738
+cap "la_oenb[68]" "la_data_out[68]" 46.7738
+cap "la_oenb[75]" "la_data_in[76]" 46.7738
+cap "la_data_out[126]" "la_oenb[126]" 46.7738
+cap "vccd2" "io_analog[4]" 1212.09
+cap "io_in_3v3[0]" "io_in[0]" 67.2299
+cap "io_in[16]" "io_out[16]" 67.2299
+cap "la_data_in[98]" "la_data_out[98]" 46.7738
+cap "la_data_in[1]" "la_data_out[1]" 52.5664
+cap "io_out[22]" "io_oeb[22]" 67.2299
+cap "wbs_dat_i[24]" "la_data_out[1]" 5.79259
+cap "la_oenb[7]" "la_data_out[7]" 46.7738
+cap "la_data_in[124]" "m2_33290_207480#" 2.87201
+cap "m2_54520_202790#" "m2_53493_202942#" 2.14488
+cap "la_oenb[105]" "la_data_out[105]" 46.7738
+cap "la_oenb[115]" "la_data_out[115]" 46.7738
+cap "wbs_dat_i[21]" "la_data_out[1]" 5.79259
+cap "la_data_out[40]" "la_data_in[40]" 46.7738
+cap "la_oenb[84]" "la_data_in[85]" 46.7738
+cap "io_analog[7]" "io_analog[8]" 3486.67
+cap "la_data_in[8]" "la_oenb[7]" 46.7738
+cap "la_data_in[121]" "la_data_in[126]" 9.37546
+cap "wbs_adr_i[5]" "wbs_dat_i[5]" 46.7738
+cap "la_data_out[27]" "la_oenb[27]" 46.7738
+cap "la_oenb[50]" "la_data_in[51]" 46.7738
+cap "io_analog[7]" "io_analog[9]" 1.41681
+cap "la_data_out[57]" "la_oenb[57]" 46.7738
+cap "la_oenb[109]" "la_data_out[109]" 46.7738
+cap "io_oeb[14]" "io_out[14]" 67.2299
+cap "la_data_in[30]" "la_data_out[30]" 46.7738
+cap "la_data_in[107]" "la_data_out[107]" 46.7738
+cap "la_data_in[86]" "la_oenb[85]" 46.7738
+cap "la_data_in[121]" "la_data_in[120]" 86330.4
+cap "la_data_out[76]" "la_oenb[76]" 46.7738
+cap "vssa2" "m2_53840_202790#" 0.938238
+cap "wbs_dat_i[28]" "la_data_out[1]" 5.79259
+cap "io_clamp_low[1]" "io_analog[5]" 493.833
+cap "la_data_out[66]" "la_data_in[66]" 46.7738
+cap "la_data_in[84]" "la_oenb[83]" 46.7738
+cap "la_data_in[124]" "la_data_out[124]" 46.7738
+cap "la_data_out[39]" "la_oenb[39]" 46.7738
+cap "la_data_out[114]" "la_data_in[114]" 46.7738
+cap "vssa2" "la_data_out[3]" 883.584
+cap "gpio_analog[10]" "gpio_noesd[10]" 67.2299
+cap "la_data_out[36]" "la_oenb[36]" 46.7738
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" -6.66134e-16
cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" -5.55112e-17
-cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" -1.11022e-16
-cap "8bit_sens_0/OUTx0x" "8bit_sens_0/GND" 3.33067e-16
-cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 1.77636e-15
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 1.11022e-16
-cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" -6.88338e-15
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" -8.88178e-16
-cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx0x" 1.33227e-15
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx6x" -12.6429
-cap "8bit_sens_0/VREF" "8bit_sens_0/GND" -2.43448
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" 0.097116
-cap "8bit_sens_0/OUTx7x" "8bit_sens_0/SA_IREF" 25.0196
-cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" 0.0265611
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.281005
-cap "8bit_sens_0/OUTx7x" "8bit_sens_0/OUTx6x" -12.6429
-cap "8bit_sens_0/VREF" "8bit_sens_0/SA_IREF" -7.306
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/GND" 89.5079
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx4x" -6.32143
+cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" -5.55112e-17
+cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" -2.22045e-15
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx5x" 2.22045e-16
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx3x" -1.77636e-15
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx7x" -1.38778e-17
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" -6.93889e-17
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx2x" -5.32907e-15
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx0x" 4.44089e-16
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx1x" 1.77636e-15
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx4x" -2.44249e-15
+cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/GND" 8.88178e-16
+cap "8bit_sens_0/OUTx4x" "8bit_sens_0/OUTx5x" -6.32143
+cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 19.0329
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/OUTx7x" -12.6429
+cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx7x" 25.0196
+cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx6x" 10.8301
cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/GND" 0.0331839
cap "8bit_sens_0/sens_amp_2/net2" "8bit_sens_0/GND" 0.169501
-cap "8bit_sens_0/sens_amp_1/net2" "8bit_sens_0/GND" 0.287108
-cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/GND" 0.373021
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 19.0329
-cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 24.4068
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/SA_IREF" 9.36696
+cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" 0.097116
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/GND" 74.051
-cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/GND" -0.577617
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx6x" 10.8301
cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 0.00477041
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/OUTx2x" -12.6429
-cap "8bit_sens_0/OUTx1x" "8bit_sens_0/OUTx0x" -6.32143
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/GND" 76.6531
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 14.8476
-cap "8bit_sens_0/GND" "vccd1" 3.21876
-cap "8bit_sens_0/OUTx1x" "8bit_sens_0/OUTx2x" -12.6429
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 0.16042
+cap "8bit_sens_0/sens_amp_1/net2" "8bit_sens_0/GND" 0.287108
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 24.4068
+cap "8bit_sens_0/SA_IREF" "8bit_sens_0/GND" 89.5079
+cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/GND" 0.373021
+cap "8bit_sens_0/SA_IREF" "8bit_sens_0/VREF" -7.306
+cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.281005
+cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/GND" -0.577617
+cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" 0.0265611
+cap "8bit_sens_0/VREF" "8bit_sens_0/GND" -2.43448
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/OUTx5x" -12.6429
+cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx5x" 9.36696
cap "8bit_sens_0/GND" "8bit_sens_0/OUTx0x" 0.118975
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/GND" 13.5713
-cap "8bit_sens_0/GND" "8bit_sens_0/OUTx2x" 13.3401
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx4x" 8.38595
-cap "8bit_sens_0/SA_IREF" "vccd1" 3.31434
-cap "8bit_sens_0/OUTx1x" "8bit_sens_0/GND" 13.1055
-cap "8bit_sens_0/GND" "8bit_sens_0/OUTx7x" 0.0664863
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx3x" 13.5713
+cap "8bit_sens_0/OUTx2x" "8bit_sens_0/OUTx1x" -12.6429
+cap "8bit_sens_0/OUTx2x" "8bit_sens_0/SA_IREF" 7.99091
+cap "8bit_sens_0/OUTx1x" "8bit_sens_0/SA_IREF" 7.99091
+cap "8bit_sens_0/OUTx4x" "8bit_sens_0/SA_IREF" 8.38595
+cap "8bit_sens_0/OUTx2x" "8bit_sens_0/GND" 13.3401
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx1x" 13.1055
+cap "vccd1" "8bit_sens_0/OUTx3x" 0.00125677
+cap "8bit_sens_0/GND" "8bit_sens_0/SA_IREF" 76.6531
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx4x" 14.8476
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/OUTx4x" -6.32143
-cap "8bit_sens_0/OUTx3x" "vccd1" 0.00125677
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/OUTx4x" -12.6429
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/SA_IREF" 7.99533
-cap "vccd1" "8bit_sens_0/OUTx2x" 1.35388
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx2x" 7.99091
-cap "8bit_sens_0/OUTx1x" "vccd1" 3.96202
-cap "8bit_sens_0/SA_IREF" "8bit_sens_0/OUTx1x" 7.99091
-cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" 0.112585
-cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/GND" 12.924
-cap "8bit_sens_0/sens_amp_7/SA_IREF" "8bit_sens_0/sens_amp_7/GND" 21.394
-cap "8bit_sens_0/sens_amp_7/GND" "vccd1" 60.8494
-cap "8bit_sens_0/sens_amp_4/net2" "vccd1" 0.000830487
-cap "8bit_sens_0/OUTx2x" "8bit_sens_0/sens_amp_7/GND" 0.0469076
-cap "8bit_sens_0/OUTx3x" "vccd1" 0.00133855
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/sens_amp_7/GND" 0.0201973
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx5x" 0.16042
+cap "8bit_sens_0/OUTx2x" "vccd1" 1.35388
+cap "vccd1" "8bit_sens_0/OUTx1x" 3.96202
+cap "vccd1" "8bit_sens_0/SA_IREF" 3.31434
cap "8bit_sens_0/OUTx0x" "8bit_sens_0/OUTx1x" -6.32143
-cap "vccd1" "8bit_sens_0/OUTx1x" 0.97411
-cap "8bit_sens_0/sens_amp_7/net2" "vccd1" 0.349358
-cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/SA_IREF" 7.90954
-cap "8bit_sens_0/OUTx0x" "vccd1" 28.0943
+cap "8bit_sens_0/OUTx2x" "8bit_sens_0/OUTx3x" -12.6429
+cap "8bit_sens_0/OUTx3x" "8bit_sens_0/SA_IREF" 7.99533
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx6x" 0.112585
+cap "8bit_sens_0/GND" "vccd1" 3.21876
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx7x" 0.0664863
+cap "8bit_sens_0/OUTx4x" "8bit_sens_0/OUTx3x" -12.6429
cap "8bit_sens_0/sens_amp_7/SA_IREF" "vccd1" 30.0592
-cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx5x" 0.00265253
-cap "8bit_sens_0/sens_amp_6/net2" "vccd1" 0.251959
-cap "8bit_sens_0/sens_amp_5/net2" "vccd1" 0.126747
+cap "8bit_sens_0/OUTx3x" "vccd1" 0.00133855
+cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/SA_IREF" 7.90954
+cap "vccd1" "8bit_sens_0/sens_amp_5/net2" 0.126747
+cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx4x" 0.0201973
+cap "8bit_sens_0/OUTx0x" "vccd1" 28.0943
cap "8bit_sens_0/OUTx2x" "vccd1" 0.498735
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/sens_amp_7/GND" 0.0355126
+cap "8bit_sens_0/sens_amp_7/net2" "vccd1" 0.349358
cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx1x" 0.0531246
-cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/GND" 0.921743
+cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/sens_amp_7/SA_IREF" 21.394
+cap "8bit_sens_0/OUTx5x" "8bit_sens_0/sens_amp_7/GND" 0.00265253
+cap "8bit_sens_0/OUTx3x" "8bit_sens_0/sens_amp_7/GND" 0.0355126
+cap "8bit_sens_0/OUTx1x" "vccd1" 0.97411
+cap "8bit_sens_0/sens_amp_6/net2" "vccd1" 0.251959
+cap "8bit_sens_0/sens_amp_7/GND" "vccd1" 60.8494
+cap "vccd1" "8bit_sens_0/sens_amp_4/net2" 0.000830487
+cap "8bit_sens_0/OUTx0x" "8bit_sens_0/OUTx1x" -6.32143
+cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/OUTx2x" 0.0469076
+cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/GND" 12.924
+cap "8bit_sens_0/VREF" "8bit_sens_0/GND" -2.84217e-14
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/GN" 6.14071
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/VREF" 4.41884
+cap "8bit_sens_0/sens_amp_2/net1" "8bit_sens_0/GND" 2.94126
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_0/net2" 0.355576
+cap "8bit_sens_0/GND" "8bit_sens_0/OUTx4x" 0.20749
+cap "8bit_sens_0/sens_amp_0/V_IN" "8bit_sens_0/GND" 20.9299
+cap "8bit_sens_0/sens_amp_3/V_IN" "8bit_sens_0/GND" 0.0624547
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/V_IN" 1.73793
+cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/GND" 12.9026
+cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/VREF" 0.956371
+cap "8bit_sens_0/sens_amp_2/net2" "8bit_sens_0/GND" 6.11903
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_1/net2" 11.1413
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/net2" 6.11903
+cap "8bit_sens_0/OUTx7x" "8bit_sens_0/VREF" 21.2448
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/GN" 160.955
-cap "8bit_sens_0/sens_amp_2/GN" "8bit_sens_0/GND" 6.14071
-cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/VREF" 0.346563
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/V_IN" 0.0624547
+cap "8bit_sens_0/sens_amp_1/GN" "8bit_sens_0/GND" 9.68531
+cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 7.8019
+cap "8bit_sens_0/VREF" "8bit_sens_0/GND" 31.9355
+cap "8bit_sens_0/sens_amp_3/net1" "8bit_sens_0/GND" 0.0454266
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_1/net1" 8.43054
+cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 17.2805
+cap "8bit_sens_0/sens_amp_3/GN" "8bit_sens_0/GND" 1.83476
cap "8bit_sens_0/VREF" "8bit_sens_0/SA_IREF" -7.306
-cap "8bit_sens_0/sens_amp_1/net1" "8bit_sens_0/GND" 8.43054
+cap "8bit_sens_0/sens_amp_0/V_IN" "8bit_sens_0/VREF" 1.65597
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/V_IN" 0.030099
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/net2" 19.9562
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net2" 0.921743
cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/net2" 0.059207
cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_1/net2" 0.140127
-cap "8bit_sens_0/sens_amp_1/GN" "8bit_sens_0/GND" 9.68531
-cap "8bit_sens_0/OUTx6x" "8bit_sens_0/GND" 17.2805
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/net1" 12.9026
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/V_IN" 1.73793
-cap "8bit_sens_0/OUTx5x" "8bit_sens_0/GND" 7.8019
-cap "8bit_sens_0/OUTx6x" "8bit_sens_0/VREF" 4.41884
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.0454266
-cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/V_IN" 0.030099
-cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/GND" 9.68278
cap "8bit_sens_0/OUTx5x" "8bit_sens_0/VREF" 2.69102
-cap "8bit_sens_0/sens_amp_2/net1" "8bit_sens_0/GND" 2.94126
-cap "8bit_sens_0/sens_amp_3/GN" "8bit_sens_0/GND" 1.83476
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_0/V_IN" 20.9299
-cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/VREF" 0.956371
-cap "8bit_sens_0/sens_amp_0/V_IN" "8bit_sens_0/VREF" 1.64367
-cap "8bit_sens_0/GND" "8bit_sens_0/VREF" 31.9201
+cap "8bit_sens_0/sens_amp_1/V_IN" "8bit_sens_0/GND" 9.68278
cap "8bit_sens_0/OUTx7x" "8bit_sens_0/GND" 87.5014
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.20749
-cap "8bit_sens_0/OUTx7x" "8bit_sens_0/VREF" 20.7466
-cap "8bit_sens_0/sens_amp_0/net2" "8bit_sens_0/GND" 19.9562
-cap "8bit_sens_0/OUTx4x" "8bit_sens_0/VREF" 1.51852
-cap "8bit_sens_0/OUTx2x" "8bit_sens_0/VREF" 1.02099
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_6/GN" 1.35525
-cap "8bit_sens_0/sens_amp_2/net1" "8bit_sens_0/GND" 1.05257
-cap "8bit_sens_0/OUTx1x" "8bit_sens_0/VREF" 1.02099
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_5/GN" 1.35525
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/V_IN" 0.130599
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00487782
-cap "8bit_sens_0/GND" "8bit_sens_0/VREF" 13.8517
-cap "8bit_sens_0/sens_amp_3/V_IN" "8bit_sens_0/VREF" 0.0968678
-cap "8bit_sens_0/sens_amp_6/V_IN" "vccd1" 0.514685
-cap "8bit_sens_0/OUTx3x" "8bit_sens_0/VREF" 1.03075
-cap "8bit_sens_0/sens_amp_5/V_IN" "vccd1" 3.12832
cap "8bit_sens_0/sens_amp_6/net2" "vccd1" 2.27431
-cap "8bit_sens_0/sens_amp_5/net2" "vccd1" 0.800337
-cap "8bit_sens_0/sens_amp_4/net2" "vccd1" 0.00039027
-cap "8bit_sens_0/sens_amp_4/V_IN" "vccd1" 0.200479
-cap "8bit_sens_0/OUTx2x" "vccd1" 3.91462
-cap "8bit_sens_0/sens_amp_4/net1" "vccd1" 0.0396777
-cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/GND" 0.968036
-cap "8bit_sens_0/OUTx1x" "vccd1" 9.65709
-cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.787218
-cap "8bit_sens_0/sens_amp_6/GN" "vccd1" 0.846347
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_3/net2" 0.0197323
+cap "vccd1" "8bit_sens_0/GND" 2.92156
+cap "8bit_sens_0/OUTx4x" "8bit_sens_0/VREF" 1.51852
+cap "8bit_sens_0/sens_amp_3/GN" "8bit_sens_0/GND" 0.787218
+cap "8bit_sens_0/sens_amp_6/V_IN" "vccd1" 0.514685
+cap "vccd1" "8bit_sens_0/OUTx2x" 3.91462
+cap "vccd1" "8bit_sens_0/VREF" 0.489321
+cap "vccd1" "8bit_sens_0/sens_amp_4/net2" 0.00039027
+cap "8bit_sens_0/OUTx3x" "8bit_sens_0/VREF" 1.03075
+cap "vccd1" "8bit_sens_0/sens_amp_5/net2" 0.800337
+cap "vccd1" "8bit_sens_0/sens_amp_4/V_IN" 0.200479
+cap "vccd1" "8bit_sens_0/OUTx1x" 9.65709
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_6/GN" 1.35525
+cap "vccd1" "8bit_sens_0/sens_amp_5/GN" 0.223338
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/net1" 1.05257
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/V_IN" 0.130599
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_2/V_IN" 2.43521
+cap "vccd1" "8bit_sens_0/OUTx3x" 0.012011
cap "8bit_sens_0/sens_amp_6/net1" "vccd1" 0.130132
-cap "8bit_sens_0/sens_amp_5/GN" "vccd1" 0.223338
-cap "8bit_sens_0/sens_amp_2/V_IN" "8bit_sens_0/GND" 2.43521
-cap "8bit_sens_0/GND" "vccd1" 2.92156
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.968036
+cap "8bit_sens_0/GND" "8bit_sens_0/VREF" 13.8517
+cap "vccd1" "8bit_sens_0/sens_amp_5/V_IN" 3.12832
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_3/V_IN" 0.0968678
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_2/V_IN" 0.382231
+cap "8bit_sens_0/VREF" "8bit_sens_0/OUTx2x" 1.02099
+cap "8bit_sens_0/VREF" "8bit_sens_0/sens_amp_4/net2" 0.00050636
cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net2" 0.086469
cap "8bit_sens_0/OUTx4x" "8bit_sens_0/GND" 0.346226
-cap "8bit_sens_0/OUTx3x" "vccd1" 0.012011
-cap "8bit_sens_0/sens_amp_2/V_IN" "8bit_sens_0/VREF" 0.382231
-cap "8bit_sens_0/VREF" "vccd1" 0.489321
-cap "8bit_sens_0/sens_amp_3/net2" "8bit_sens_0/VREF" 0.0197323
-cap "8bit_sens_0/sens_amp_4/net2" "8bit_sens_0/VREF" 0.00050636
-cap "8bit_sens_0/sens_amp_5/net1" "vccd1" 0.530241
-cap "vccd1" "8bit_sens_0/sens_amp_7/net2" 21.9497
-cap "vccd1" "8bit_sens_0/sens_amp_5/net2" 4.35189
-cap "vccd1" "8bit_sens_0/sens_amp_6/net2" 8.6511
-cap "8bit_sens_0/sens_amp_7/V_IN" "8bit_sens_0/sens_amp_7/net1" -0.0342863
-cap "vccd1" "8bit_sens_0/OUTx1x" 3.43359
-cap "8bit_sens_0/sens_amp_7/REF" "8bit_sens_0/sens_amp_7/GND" 3.85327
-cap "vccd1" "8bit_sens_0/sens_amp_7/net1" 123.385
-cap "vccd1" "8bit_sens_0/sens_amp_4/net1" 0.887485
-cap "vccd1" "8bit_sens_0/sens_amp_7/GND" 14.7299
-cap "vccd1" "8bit_sens_0/sens_amp_6/net1" 9.33374
+cap "8bit_sens_0/sens_amp_4/net1" "vccd1" 0.0396777
+cap "vccd1" "8bit_sens_0/sens_amp_5/net1" 0.530241
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_5/GN" 1.35525
+cap "8bit_sens_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00487782
+cap "vccd1" "8bit_sens_0/sens_amp_6/GN" 0.846347
+cap "8bit_sens_0/VREF" "8bit_sens_0/OUTx1x" 1.02099
+cap "8bit_sens_0/sens_amp_7/REF" "8bit_sens_0/sens_amp_7/V_IN" -0.194099
cap "vccd1" "8bit_sens_0/sens_amp_5/net1" 4.88252
-cap "vccd1" "8bit_sens_0/sens_amp_5/GN" 2.57483
-cap "vccd1" "8bit_sens_0/sens_amp_6/GN" 6.69563
-cap "vccd1" "8bit_sens_0/sens_amp_7/GN" 11.7452
-cap "vccd1" "8bit_sens_0/sens_amp_4/V_IN" 0.33888
-cap "8bit_sens_0/OUTx0x" "8bit_sens_0/sens_amp_7/REF" 1.02099
-cap "8bit_sens_0/sens_amp_7/V_IN" "8bit_sens_0/sens_amp_7/REF" -0.194099
-cap "vccd1" "8bit_sens_0/OUTx2x" 1.82132
-cap "8bit_sens_0/OUTx0x" "vccd1" 63.5416
-cap "vccd1" "8bit_sens_0/sens_amp_7/REF" 16.8039
-cap "vccd1" "8bit_sens_0/sens_amp_4/net2" 0.00868596
-cap "8bit_sens_0/sens_amp_7/V_IN" "vccd1" 65.3675
-cap "vccd1" "8bit_sens_0/OUTx3x" 0.0708511
-cap "vccd1" "8bit_sens_0/sens_amp_6/V_IN" 10.5086
cap "vccd1" "8bit_sens_0/sens_amp_5/V_IN" 2.473
-cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/GND" 1.16164
-cap "adc_0/GND" "8bit_sens_0/VDD" 156.822
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 66.3972
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.00356583
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.62612
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "adc_0/GND" 11.7749
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/VDD" 0.00392936
-cap "8bit_sens_0/sens_amp_0/GN" "adc_0/GND" 91.2977
-cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/VDD" -5.14306
+cap "vccd1" "8bit_sens_0/sens_amp_4/net2" 0.00868596
+cap "8bit_sens_0/sens_amp_4/V_IN" "vccd1" 0.33888
+cap "vccd1" "8bit_sens_0/sens_amp_4/net1" 0.887485
+cap "8bit_sens_0/sens_amp_7/net1" "vccd1" 123.385
+cap "8bit_sens_0/sens_amp_7/GND" "vccd1" 14.7299
+cap "vccd1" "8bit_sens_0/OUTx0x" 63.5416
+cap "8bit_sens_0/OUTx3x" "vccd1" 0.0708511
+cap "vccd1" "8bit_sens_0/sens_amp_6/GN" 6.69563
+cap "8bit_sens_0/sens_amp_7/net1" "8bit_sens_0/sens_amp_7/V_IN" -0.0342863
+cap "8bit_sens_0/sens_amp_7/net2" "vccd1" 21.9497
+cap "vccd1" "8bit_sens_0/sens_amp_6/net1" 9.33374
+cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/sens_amp_7/GN" 1.16164
+cap "vccd1" "8bit_sens_0/sens_amp_7/V_IN" 65.3675
+cap "vccd1" "8bit_sens_0/sens_amp_7/GN" 11.7452
+cap "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/sens_amp_7/REF" 3.85327
+cap "vccd1" "8bit_sens_0/sens_amp_5/net2" 4.35189
+cap "8bit_sens_0/sens_amp_7/REF" "vccd1" 16.8039
+cap "8bit_sens_0/sens_amp_7/REF" "8bit_sens_0/OUTx0x" 1.02099
+cap "vccd1" "8bit_sens_0/sens_amp_6/V_IN" 10.5086
+cap "vccd1" "8bit_sens_0/sens_amp_5/GN" 2.57483
+cap "vccd1" "8bit_sens_0/OUTx1x" 3.43359
+cap "vccd1" "8bit_sens_0/OUTx2x" 1.82132
+cap "vccd1" "8bit_sens_0/sens_amp_6/net2" 8.6511
cap "adc_0/GND" "8bit_sens_0/sens_amp_1/GN" 12.1075
-cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 4.07279
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.494835
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.000145326
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/GN" 0.000722111
-cap "adc_0/GND" "8bit_sens_0/sens_amp_0/net1" 39.1704
-cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 5.5773
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.467675
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 2.89451
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_0/net1" -12.2782
-cap "8bit_sens_0/sens_amp_0/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.102927
-cap "adc_0/GND" "8bit_sens_0/sens_amp_2/OUT" 5.10821
-cap "adc_0/GND" "8bit_sens_0/sens_amp_1/OUT" 12.0665
-cap "adc_0/GND" "8bit_sens_0/sens_amp_0/OUT" 52.9101
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 1.99139
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/OUT" 0.19763
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/GN" 0.303566
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/GN" 0.273461
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/READ" 0.0843564
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_0/net1" 0.175357
-cap "8bit_sens_0/sens_amp_1/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0627715
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0483017
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.000722111
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.62612
+cap "adc_0/READ" "8bit_sens_0/sens_amp_2/net1" 0.0843564
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.000423023
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/net1" 0.0483017
+cap "8bit_sens_0/sens_amp_1/net1" "adc_0/READ" 0.0127235
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/net1" 0.0627715
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/OUT" 0.00211512
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.111884
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/GN" 0.157883
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/GN" 0.457219
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0282082
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.000927367
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 4.07279
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.00356583
+cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/VDD" -12.2782
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 11.7749
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.000145326
+cap "8bit_sens_0/sens_amp_0/net1" "adc_0/READ" 0.0127235
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_0/net1" 0.175357
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00159606
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/net1" 0.0992089
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/net1" 0.246821
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00159606
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/OUT" 0.00570518
-cap "8bit_sens_0/sens_amp_0/GN" "8bit_sens_0/sens_amp_0/net1" -4.61959
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/GN" 1.14389
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/OUT" 0.000506156
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_5/GN" 1.22164
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/GN" 0.0808306
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/READ" 0.591551
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_4/OUT" 0.0357335
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/GN" 0.708908
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/OUT" 6.3654e-05
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/GN" 0.0014115
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/GN" 0.0400408
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_6/GN" 0.435347
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.42888
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 0.683984
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0409452
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.490914
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.0425475
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.0158366
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/READ" 1.95307
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/GN" 2.41969
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/GN" 0.121543
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0144699
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/GN" 0.0331687
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.579283
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.36833
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.1354
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/GN" 0.48721
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_6/GN" 0.582767
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.440383
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/GN" 0.00218938
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.00147748
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/READ" 0.536569
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0612079
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.0571292
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GND" 0.0418919
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.0711138
-cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 4.39768
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 0.123162
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 0.0421109
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/GND" 0.497005
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0338702
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/VDD" 0.00493103
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "adc_0/GND" 3.21112
-cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.00237033
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.0168158
-cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.296232
-cap "8bit_sens_0/VDD" "adc_0/GND" 0.580863
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/OUT" 0.000537226
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/OUT" 0.0117192
-cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.00533579
-cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.00750245
-cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/GND" 0.0928868
-cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.000115921
-cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0343946
-cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/VDD" 2.72813
+cap "adc_0/GND" "8bit_sens_0/sens_amp_0/GN" 91.2977
+cap "8bit_sens_0/sens_amp_1/GN" "adc_0/READ" 0.303118
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_1/GN" 0.303566
+cap "adc_0/GND" "8bit_sens_0/sens_amp_0/OUT" 52.9101
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/VDD" 0.00392936
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/GN" 0.111884
+cap "adc_0/READ" "8bit_sens_0/sens_amp_2/GN" 1.99139
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/OUT" 5.10821
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 2.89451
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/GN" 0.273461
+cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 5.5773
+cap "adc_0/GND" "8bit_sens_0/sens_amp_1/OUT" 12.0665
+cap "adc_0/GND" "8bit_sens_0/VDD" 156.822
+cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_0/GN" -5.14306
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.494835
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_1/GN" 0.157883
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 66.3972
+cap "adc_0/GND" "8bit_sens_0/sens_amp_0/net1" 39.1704
+cap "adc_0/READ" "8bit_sens_0/sens_amp_0/GN" 0.303118
+cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/sens_amp_0/GN" -4.61959
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_0/GN" 0.102927
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/GN" 0.457219
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.467675
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/net1" 0.0282082
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/OUT" 0.000927367
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/OUT" 0.19763
+cap "adc_0/READ" "8bit_sens_0/sens_amp_4/GN" 0.306517
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.414702
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.86122
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.529835
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.57267
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/OUT" 0.000337437
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_6/GN" 0.435347
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.246526
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_4/net1" 0.00233038
+cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0331687
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00815426
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.0723122
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00169209
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.0571292
+cap "8bit_sens_0/sens_amp_5/OUT" "8bit_sens_0/VDD" 1.83224
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_4/GN" 0.57267
+cap "adc_0/READ" "8bit_sens_0/sens_amp_6/net1" 0.0604473
cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.00133403
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/GN" 0.703745
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/READ" 0.306517
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/OUT" 1.83224
-cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/VDD" 0.0246887
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/net1" 0.244359
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/net1" 0.237107
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.246526
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.179271
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.000359135
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/net1" 0.124794
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/READ" 0.0140308
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GND" 0.0484713
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/net1" 0.0220289
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.447979
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0713977
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.166987
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00466909
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_6/net1" 0.236328
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 0.136542
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.00815426
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.00233038
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/OUT" 0.00169209
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.196463
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/net1" 0.0723122
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/net1" 0.1354
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/OUT" 0.0928868
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/net1" 0.024713
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.10959
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/READ" 0.0127659
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/READ" 0.0126424
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/net1" 0.373979
-cap "8bit_sens_0/sens_amp_4/net1" "8bit_sens_0/VDD" 0.00176569
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0100531
-cap "adc_0/READ" "8bit_sens_0/sens_amp_6/net1" 0.0604473
-cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_6/net1" 0.962288
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_5/net1" 0.447979
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/GN" 0.0808306
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_5/GN" 2.34629
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/OUT" 0.00533579
+cap "adc_0/READ" "8bit_sens_0/sens_amp_3/GN" 0.536569
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.529835
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.166987
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 0.123162
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/GN" 0.0400408
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.0418919
+cap "adc_0/GND" "8bit_sens_0/VDD" 0.580863
+cap "8bit_sens_0/sens_amp_6/GN" "8bit_sens_0/VDD" 0.582767
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.86122
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/GN" 0.48721
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.0168158
cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_sens_0/sens_amp_4/OUT" 0.00133464
-cap "8bit_sens_0/sens_amp_4/net1" "8bit_sens_0/sens_amp_7/VDD" 0.0228878
-cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_5/GN" 3.30792
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0289867
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.139851
-cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_4/GN" 0.22836
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_7/VDD" 0.199942
-cap "8bit_sens_0/sens_amp_7/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0232407
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_7/GN" 0.228534
-cap "8bit_sens_0/sens_amp_6/net1" "8bit_sens_0/sens_amp_7/VDD" 4.92012
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0650655
-cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.684429
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.793108
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.196463
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/OUT" 0.0117192
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/OUT" 6.3654e-05
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.42888
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/OUT" 0.000115921
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.36833
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/GN" 0.121543
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_4/OUT" 0.000506156
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_sens_0/sens_amp_3/OUT" 0.000537226
+cap "8bit_sens_0/sens_amp_5/net1" "8bit_sens_0/VDD" 0.373979
+cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_5/GN" 0.708908
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/VDD" 4.39768
+cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.10959
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_3/GN" 0.579283
+cap "8bit_sens_0/sens_amp_4/net1" "8bit_sens_0/VDD" 0.00176569
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_5/GN" 1.22164
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/VDD" 0.00237033
+cap "adc_0/READ" "8bit_sens_0/sens_amp_3/net1" 0.0140308
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/net1" 0.0220289
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.179271
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.0484713
+cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 2.41969
+cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/VDD" 0.0246887
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0409452
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 0.136542
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_3/net1" 0.124794
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/GN" 1.14389
+cap "8bit_sens_0/sens_amp_6/net1" "8bit_sens_0/VDD" 0.962288
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.440383
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0612079
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00147748
+cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/VDD" 2.72813
+cap "adc_0/READ" "8bit_sens_0/sens_amp_6/GN" 1.95307
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_3/net1" 0.237107
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/GN" 0.00218938
+cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.490914
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.236328
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00466909
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "adc_0/GND" 3.21112
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_5/OUT" 0.000337437
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/VDD" 0.296232
+cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.00750245
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_5/OUT" 0.0343946
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_sens_0/sens_amp_3/net1" 0.000359135
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_2/net1" 0.0425475
+cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.244359
+cap "adc_0/READ" "8bit_sens_0/sens_amp_2/GN" 0.0421109
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/net1" 0.0144699
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0158366
+cap "8bit_sens_0/sens_amp_4/OUT" "8bit_sens_0/VDD" 0.0357335
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/GND" 0.497005
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/VDD" 0.00493103
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0338702
+cap "adc_0/READ" "8bit_sens_0/sens_amp_5/net1" 0.0126424
+cap "adc_0/READ" "8bit_sens_0/sens_amp_5/GN" 0.591551
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/GN" 0.0014115
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 0.683984
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0713977
+cap "adc_0/READ" "8bit_sens_0/sens_amp_4/net1" 0.0127659
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_2/GN" 0.0711138
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0100531
+cap "8bit_sens_0/sens_amp_7/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.199942
cap "8bit_sens_0/sens_amp_7/OUT" "8bit_sens_0/sens_amp_7/VDD" 56.0737
-cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/sens_amp_7/VDD" 7.2726
-cap "8bit_sens_0/sens_amp_4/OUT" "8bit_sens_0/sens_amp_7/VDD" 0.267803
-cap "8bit_sens_0/sens_amp_5/OUT" "8bit_sens_0/sens_amp_7/VDD" 3.55975
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.011391
-cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.266718
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0802203
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_sens_0/sens_amp_7/GN" 0.345086
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_7/VDD" 65.8171
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0113439
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_7/VDD" 12.8326
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.0215808
-cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.27861
-cap "8bit_sens_0/sens_amp_7/net1" "8bit_sens_0/sens_amp_7/GN" -2.48043
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.140414
-cap "8bit_sens_0/sens_amp_6/GN" "8bit_sens_0/sens_amp_7/VDD" 8.31155
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.103561
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_sens_0/sens_amp_7/VDD" 1.02129
-cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/VDD" 34.3183
-cap "8bit_sens_0/sens_amp_5/net1" "8bit_sens_0/sens_amp_7/VDD" 2.18103
-cap "8bit_sens_0/sens_amp_7/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00113212
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_6/net1" 0.139851
+cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_4/OUT" 0.267803
cap "8bit_sens_0/sens_amp_7/net1" "8bit_sens_0/sens_amp_7/VDD" 92.266
-cap "adc_0/GND" "8bit_sens_0/VDD" 476.975
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00663047
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GND" 0.0215565
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_7/net1" 0.0113439
+cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_6/GN" 8.31155
+cap "8bit_sens_0/sens_amp_4/GN" "8bit_sens_0/sens_amp_7/VDD" 0.22836
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_6/GN" 0.011391
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.27861
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.345086
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.684429
+cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_5/net1" 2.18103
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0289867
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.103561
+cap "8bit_sens_0/sens_amp_7/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.02129
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0802203
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_sens_0/sens_amp_7/VDD" 12.8326
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.228534
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0215808
+cap "8bit_sens_0/sens_amp_7/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.0232407
+cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.140414
+cap "8bit_sens_0/sens_amp_6/OUT" "8bit_sens_0/sens_amp_7/VDD" 7.2726
+cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/net1" -2.48043
+cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.793108
+cap "8bit_sens_0/sens_amp_5/GN" "8bit_sens_0/sens_amp_7/VDD" 3.30792
+cap "8bit_sens_0/sens_amp_7/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00113212
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_6/GN" 0.0650655
+cap "8bit_sens_0/sens_amp_7/GN" "8bit_sens_0/sens_amp_7/VDD" 34.3183
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_sens_0/sens_amp_7/VDD" 65.8171
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.266718
+cap "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/sens_amp_4/net1" 0.0228878
+cap "8bit_sens_0/sens_amp_6/net1" "8bit_sens_0/sens_amp_7/VDD" 4.92012
+cap "8bit_sens_0/sens_amp_5/OUT" "8bit_sens_0/sens_amp_7/VDD" 3.55975
+cap "8bit_sens_0/sens_amp_0/net1" "adc_0/READ" 0.829009
+cap "8bit_sens_0/sens_amp_1/GN" "adc_0/READ" 0.0516825
+cap "adc_0/READ" "adc_0/GND" 0.046628
+cap "8bit_sens_0/sens_amp_0/GN" "adc_0/READ" 0.875494
+cap "adc_0/OUTx7x" "adc_0/READ" 0.970755
+cap "8bit_sens_0/VDD" "adc_0/READ" 26.4364
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 1.31407
+cap "adc_0/GND" "adc_0/V_RAMP" -0.00166719
+cap "adc_0/GND" "adc_0/OUTx6x" 128.19
+cap "adc_0/OUTx7x" "adc_0/BIAS1" -0.100564
+cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_1/GN" 0.615347
+cap "adc_0/GND" "adc_0/GRAY_INx2x" 0.369575
cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.839293
-cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/VDD" -4.58957
-cap "adc_0/V_IN" "8bit_sens_0/VDD" 0.179184
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.256578
-cap "8bit_sens_0/sens_amp_0/net1" "adc_0/GND" 15.7267
-cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 7.83787
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/GND" 1.31407
-cap "adc_0/V_RAMP" "adc_0/GND" -0.00166719
-cap "adc_0/BIAS2" "adc_0/OUTx6x" -0.690007
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.045174
-cap "adc_0/GND" "8bit_sens_0/sens_amp_0/GN" 14.8289
-cap "8bit_sens_0/sens_amp_1/GN" "adc_0/GND" 13.9906
-cap "adc_0/GND" "adc_0/OUTx4x" 1.68602
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/VDD" 0.529274
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.0410053
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0055825
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.24459
-cap "adc_0/READ" "adc_0/OUTx6x" 31.322
-cap "adc_0/OUTx5x" "adc_0/OUTx6x" -2.45627
-cap "adc_0/OUTx6x" "adc_0/BIAS1" -0.464168
-cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00125642
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/V_IN" 0.000545017
-cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/sens_amp_0/GN" -1.44537
-cap "vccd1" "adc_0/READ" 0.260488
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0469935
-cap "8bit_sens_0/VDD" "adc_0/OUTx7x" 10.2713
-cap "adc_0/GND" "adc_0/OUTx7x" 52.0699
-cap "adc_0/OUTx1x" "adc_0/GND" 0.171874
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.181686
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/GND" 0.0047473
-cap "8bit_sens_0/sens_amp_1/OUT" "adc_0/OUTx7x" 0.00725774
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx7x" 0.0467264
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx7x" 0.498847
-cap "8bit_sens_0/sens_amp_1/net1" "adc_0/OUTx7x" 0.323423
-cap "8bit_sens_0/sens_amp_0/net1" "adc_0/OUTx7x" 0.0577243
-cap "adc_0/V_IN" "adc_0/OUTx7x" 0.183996
-cap "adc_0/OUTx4x" "adc_0/OUTx7x" 0.253751
-cap "adc_0/V_RAMP" "adc_0/OUTx7x" -0.0338338
-cap "8bit_sens_0/sens_amp_1/GN" "adc_0/OUTx7x" 0.615347
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx7x" 0.275768
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.05896
-cap "adc_0/GRAY_INx4x" "adc_0/GND" 0.970299
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/VDD" 4.01677
-cap "adc_0/BIAS2" "8bit_sens_0/VDD" 0.0520965
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.09686
-cap "adc_0/GRAY_INx7x" "adc_0/GND" 9.08509
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.173705
-cap "adc_0/GND" "adc_0/GRAY_INx5x" 2.95633
cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.10418
-cap "adc_0/OUTx0x" "adc_0/GND" 0.170792
-cap "vccd1" "adc_0/OUTx6x" 0.145948
-cap "adc_0/READ" "8bit_sens_0/VDD" 46.7899
+cap "adc_0/OUTx1x" "adc_0/GND" 0.171874
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.0215565
cap "adc_0/READ" "adc_0/VDD" 0.139243
-cap "adc_0/GND" "adc_0/GRAY_INx6x" 2.27164
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/net1" 0.163076
-cap "adc_0/READ" "adc_0/GND" 137.881
-cap "adc_0/OUTx5x" "adc_0/GND" 4.74121
-cap "adc_0/GND" "adc_0/BIAS1" -0.00241621
-cap "adc_0/GND" "adc_0/OUTx3x" 2.45492
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0901808
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.446446
-cap "adc_0/GRAY_INx2x" "adc_0/GND" 0.369575
cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.00793409
-cap "adc_0/READ" "8bit_sens_0/sens_amp_2/net1" 0.415491
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 13.1914
-cap "adc_0/V_RAMP" "adc_0/READ" 0.291005
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0227248
-cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.00123831
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx7x" 0.0824328
-cap "adc_0/GRAY_INx7x" "adc_0/OUTx7x" 0.029749
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.0144116
-cap "adc_0/READ" "adc_0/OUTx7x" 37.2468
-cap "adc_0/OUTx5x" "adc_0/OUTx7x" -0.17
-cap "adc_0/BIAS1" "adc_0/OUTx7x" -0.100564
-cap "adc_0/OUTx6x" "adc_0/VDD" 0.0631894
-cap "adc_0/OUTx6x" "8bit_sens_0/VDD" 96.7482
-cap "adc_0/OUTx6x" "adc_0/GND" 118.315
-cap "adc_0/GND" "adc_0/OUTx2x" 1.01954
-cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/OUT" 0.302986
-cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/net1" 1.57896
-cap "vccd1" "adc_0/GND" -0.000898652
-cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx6x" 9.01557
-cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/net1" 6.40104
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.446446
+cap "adc_0/READ" "vccd1" 0.260488
cap "adc_0/OUTx6x" "adc_0/OUTx4x" -0.961303
+cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.045174
+cap "adc_0/READ" "8bit_sens_0/sens_amp_0/GN" 2.14038
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.00663047
+cap "adc_0/GND" "adc_0/GRAY_INx7x" 9.08509
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" 0.0227248
+cap "adc_0/GND" "adc_0/OUTx7x" 50.8628
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/net1" 0.163076
+cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.529274
+cap "adc_0/GND" "adc_0/GRAY_INx4x" 0.970299
cap "adc_0/V_RAMP" "adc_0/OUTx6x" 0.034461
+cap "8bit_sens_0/VDD" "adc_0/READ" 74.3403
+cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/GN" 9.01557
+cap "adc_0/GND" "adc_0/OUTx0x" 0.170792
+cap "adc_0/OUTx7x" "adc_0/OUTx4x" 0.253751
+cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0824328
+cap "8bit_sens_0/sens_amp_0/net1" "adc_0/READ" 1.01789
+cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/net1" 1.57896
+cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0410053
+cap "adc_0/BIAS2" "adc_0/OUTx6x" -0.690007
+cap "adc_0/GND" "vccd1" -0.000898652
+cap "adc_0/GND" "8bit_sens_0/sens_amp_0/GN" 13.4921
+cap "adc_0/OUTx7x" "adc_0/V_RAMP" -0.0338338
+cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_2/GN" 0.498847
+cap "adc_0/READ" "8bit_sens_0/sens_amp_1/net1" 0.888678
+cap "adc_0/OUTx7x" "adc_0/OUTx6x" -5.68191
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0047473
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.05896
+cap "adc_0/OUTx3x" "adc_0/GND" 2.45492
+cap "8bit_sens_0/VDD" "adc_0/GND" 452.835
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "vccd1" 0.00125642
+cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_2/net1" 0.0467264
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0055825
+cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.00123831
+cap "adc_0/V_IN" "8bit_sens_0/sens_amp_2/GN" 0.000545017
+cap "adc_0/GND" "8bit_sens_0/sens_amp_0/net1" 15.024
+cap "adc_0/OUTx7x" "adc_0/GRAY_INx7x" 0.029749
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.256578
cap "adc_0/V_IN" "adc_0/OUTx6x" 0.141758
-cap "8bit_sens_0/sens_amp_1/GN" "adc_0/OUTx6x" 3.78179
-cap "adc_0/GRAY_INx3x" "adc_0/GND" 1.27589
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.4948
-cap "adc_0/BIAS2" "adc_0/READ" 2.42618
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.179839
-cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0164328
-cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.00174371
-cap "adc_0/OUTx6x" "adc_0/OUTx7x" -5.68191
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/VDD" 0.156399
-cap "adc_0/READ" "adc_0/BIAS1" 2.551
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.6439
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.0950629
+cap "adc_0/OUTx6x" "adc_0/VDD" 0.0631894
+cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 4.01677
+cap "adc_0/OUTx6x" "vccd1" 0.145948
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.173705
+cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.156399
+cap "adc_0/GND" "8bit_sens_0/sens_amp_1/net1" 7.13519
+cap "adc_0/GND" "adc_0/GRAY_INx3x" 1.27589
+cap "adc_0/GND" "adc_0/OUTx2x" 1.01954
+cap "adc_0/GRAY_INx5x" "adc_0/GND" 2.95633
+cap "8bit_sens_0/VDD" "adc_0/OUTx6x" 96.7482
+cap "adc_0/BIAS1" "adc_0/READ" 1.55631
+cap "adc_0/READ" "8bit_sens_0/sens_amp_1/GN" 2.1222
+cap "adc_0/V_IN" "adc_0/OUTx7x" 0.183996
cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx7x" 0.00241902
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.27989
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 2.61852
-cap "adc_0/GND" "adc_0/VDD" 11.5888
-cap "adc_0/V_IN" "adc_0/VDD" 2.39161
-cap "adc_0/a_1000_n1450#" "adc_0/VDD" 0.334655
-cap "adc_0/a_1720_n1450#" "adc_0/VDD" 0.256808
-cap "8bit_sens_0/sens_amp_6/OUT" "adc_0/OUTx0x" 0.750956
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/GN" 1.1903
-cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_2/GN" 3.05663
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx4x" -0.00119257
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -1.77485
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GRAY_INx6x" -0.0161971
-cap "adc_0/GRAY_INx4x" "adc_0/OUTx4x" -0.0014868
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx4x" -0.00384267
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx7x" 1.659
-cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_2/GN" 0.177705
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GRAY_INx7x" -2.35733
-cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx7x" -0.00135158
-cap "adc_0/OUTx3x" "adc_0/GRAY_INx4x" 14.5447
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx4x" -0.00153296
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx5x" 3.70053
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx4x" 0.538846
-cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx4x" -0.00496884
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx6x" -0.00119747
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/OUTx4x" 3.80667
-cap "adc_0/OUTx6x" "adc_0/OUTx4x" -6.18725
-cap "adc_0/GRAY_INx6x" "adc_0/OUTx4x" -0.000998441
-cap "adc_0/READ" "8bit_sens_0/sens_amp_2/GN" 1.47446
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx6x" -0.000390028
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.00239769
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.103354
-cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29712
-cap "adc_0/OUTx6x" "adc_0/OUTx7x" 20.3389
-cap "adc_0/READ" "adc_0/GRAY_INx4x" -2.92799
-cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.934061
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx6x" -7.09689
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx7x" -0.498991
-cap "adc_0/OUTx6x" "adc_0/OUTx5x" 5.77365
-cap "adc_0/OUTx6x" "adc_0/OUTx3x" -0.117724
-cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.90521
-cap "adc_0/OUTx7x" "adc_0/OUTx4x" -0.453278
-cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx7x" 0.00252296
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx6x" -0.000956435
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.48031
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx6x" 59.832
-cap "adc_0/OUTx5x" "adc_0/OUTx4x" 17.379
-cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx6x" -0.000739663
-cap "adc_0/OUTx3x" "adc_0/OUTx4x" -2.43468
-cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.024305
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.00205703
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.318626
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00685071
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -2.54453
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx1x" -0.000778297
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00585743
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.90901
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -0.132168
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx7x" -0.675707
-cap "adc_0/OUTx6x" "adc_0/READ" 0.2005
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/net1" 0.281215
-cap "adc_0/OUTx1x" "adc_0/OUTx4x" 0.450912
-cap "adc_0/OUTx6x" "adc_0/BIAS1" -0.0275125
-cap "adc_0/OUTx5x" "adc_0/OUTx7x" 13.9109
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.422993
-cap "adc_0/GND" "8bit_sens_0/sens_amp_5/net1" 0.00878094
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx3x" 0.182126
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx7x" 14.0586
-cap "adc_0/OUTx3x" "adc_0/GRAY_INx7x" 0.0232261
-cap "adc_0/READ" "adc_0/GRAY_INx6x" 0.00898644
-cap "adc_0/a_1100_n1450#" "adc_0/OUTx4x" 0.193556
-cap "adc_0/BIAS1" "adc_0/OUTx4x" -0.922934
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx3x" 1.60864
-cap "adc_0/READ" "adc_0/OUTx4x" 31.9477
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx5x" 0.0100576
-cap "adc_0/OUTx5x" "adc_0/OUTx3x" -3.28179
-cap "adc_0/GRAY_INx3x" "adc_0/OUTx3x" 0.0234924
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" -0.0868261
-cap "adc_0/READ" "adc_0/GRAY_INx1x" -0.0114114
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx3x" 0.00905904
-cap "adc_0/BIAS2" "adc_0/OUTx4x" 0.208944
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" 0.00858993
-cap "adc_0/OUTx5x" "adc_0/OUTx1x" -0.118123
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/VDD" 0.175788
-cap "adc_0/OUTx3x" "adc_0/OUTx1x" -1.50771
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx1x" 0.0157817
-cap "adc_0/READ" "adc_0/OUTx7x" 0.624011
-cap "adc_0/OUTx7x" "adc_0/BIAS1" -0.206538
-cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0201386
-cap "adc_0/OUTx5x" "adc_0/a_1100_n1450#" 1.28942
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx4x" 1.10244
-cap "adc_0/READ" "adc_0/GRAY_INx7x" -1.24273
-cap "adc_0/READ" "adc_0/OUTx5x" 40.5383
-cap "adc_0/OUTx3x" "adc_0/a_1100_n1450#" 0.643658
-cap "adc_0/OUTx3x" "adc_0/BIAS1" -0.385619
-cap "adc_0/OUTx5x" "adc_0/BIAS1" 3.40646
-cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.207787
-cap "adc_0/GRAY_INx5x" "adc_0/READ" -1.38451
-cap "adc_0/READ" "adc_0/OUTx3x" 25.3042
-cap "adc_0/GND" "8bit_sens_0/sens_amp_4/net1" 0.00371336
-cap "adc_0/READ" "adc_0/GRAY_INx3x" -2.0571
-cap "adc_0/BIAS2" "adc_0/OUTx5x" 0.951676
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.314181
-cap "adc_0/READ" "adc_0/OUTx1x" 0.163117
-cap "adc_0/BIAS2" "adc_0/OUTx3x" 0.948413
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GRAY_INx7x" -1.33305
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx5x" 1.93238
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx5x" 1.01317
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx5x" -0.366214
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/VDD" 0.00706276
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 0.04391
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.0674098
-cap "adc_0/GND" "8bit_sens_0/sens_amp_6/GN" 0.10187
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.118608
-cap "adc_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.142041
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/GND" 0.0673912
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00444633
-cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0180222
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/VDD" 0.0699164
-cap "adc_0/OUTx0x" "adc_0/V_RAMP" -0.134294
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.0278411
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/VDD" 2.8147e-05
-cap "adc_0/OUTx2x" "adc_0/a_1870_n1400#" 0.784228
-cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.134338
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.0767923
-cap "adc_0/GND" "adc_0/OUTx0x" 0.956117
-cap "adc_0/GRAY_INx2x" "adc_0/GND" 0.355663
-cap "adc_0/OUTx0x" "adc_0/VDD" 42.8299
+cap "8bit_sens_0/sens_amp_1/OUT" "adc_0/OUTx6x" 0.302986
+cap "adc_0/BIAS2" "8bit_sens_0/VDD" 0.0520965
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0901808
+cap "adc_0/GND" "adc_0/OUTx5x" 4.74121
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.24459
+cap "adc_0/GND" "adc_0/READ" 49.894
+cap "8bit_sens_0/VDD" "adc_0/OUTx7x" 10.2713
+cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/net1" 6.40104
+cap "adc_0/GND" "adc_0/BIAS1" -0.00241621
+cap "8bit_sens_0/sens_amp_1/OUT" "adc_0/OUTx7x" 0.00725774
+cap "adc_0/GND" "8bit_sens_0/sens_amp_1/GN" 12.6538
+cap "8bit_sens_0/sens_amp_0/net1" "adc_0/OUTx7x" 0.0577243
+cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.179839
+cap "adc_0/GND" "adc_0/GRAY_INx6x" 2.27164
+cap "adc_0/V_IN" "8bit_sens_0/VDD" 0.179184
+cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_1/net1" 0.323423
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0469935
+cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0164328
+cap "adc_0/READ" "8bit_sens_0/sens_amp_2/GN" 13.1914
+cap "adc_0/V_RAMP" "adc_0/READ" 0.291005
+cap "adc_0/OUTx5x" "adc_0/OUTx6x" -2.45627
+cap "adc_0/OUTx7x" "adc_0/OUTx2x" -0.00174371
+cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.4948
+cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.0144116
+cap "adc_0/OUTx6x" "adc_0/READ" 20.0341
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0950629
+cap "8bit_sens_0/sens_amp_0/net1" "8bit_sens_0/sens_amp_0/GN" -1.44537
+cap "adc_0/READ" "8bit_sens_0/sens_amp_2/net1" 0.415491
+cap "adc_0/BIAS2" "adc_0/READ" 1.69521
+cap "adc_0/OUTx6x" "adc_0/BIAS1" -0.464168
+cap "adc_0/OUTx6x" "8bit_sens_0/sens_amp_1/GN" 3.78179
+cap "adc_0/GND" "adc_0/OUTx4x" 1.68602
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.09686
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/GND" 0.181686
+cap "adc_0/OUTx7x" "adc_0/OUTx5x" -0.17
+cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.275768
+cap "8bit_sens_0/VDD" "8bit_sens_0/sens_amp_0/net1" -4.58957
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.6439
+cap "adc_0/OUTx7x" "adc_0/READ" 38.4182
+cap "adc_0/GRAY_INx7x" "adc_0/VDD" 41.927
cap "adc_0/GRAY_INx2x" "adc_0/VDD" 43.2998
-cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.34939
-cap "adc_0/OUTx2x" "adc_0/GND" 7.98103
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.23223
-cap "adc_0/V_IN" "8bit_sens_0/sens_amp_3/GN" 0.00522501
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.0729032
-cap "adc_0/OUTx2x" "adc_0/VDD" 98.3794
-cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.756483
-cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/OUT" 1.78456
-cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -5.5826e-05
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx4x" 0.725899
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/OUTx0x" 8.42612
-cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.716144
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx7x" -0.871526
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/READ" 4.37209
+cap "adc_0/a_1720_n1450#" "adc_0/OUTx3x" 1.03866
+cap "adc_0/OUTx4x" "8bit_sens_0/sens_amp_3/GN" 2.91383
+cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/GN" 11.33
+cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GND" 0.0729032
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/GND" 0.10187
+cap "adc_0/OUTx1x" "adc_0/OUTx5x" -0.118123
cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.23391
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.40563
-cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.76156
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.850562
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.591716
-cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/net1" 18.0563
-cap "adc_0/GRAY_INx4x" "8bit_sens_0/sens_amp_4/OUT" 0.0162939
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx0x" 9.18392
-cap "adc_0/GRAY_INx2x" "8bit_sens_0/sens_amp_6/GN" 0.454578
-cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/GN" 19.2186
-cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/OUT" 0.0458033
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.0952982
-cap "adc_0/GRAY_INx2x" "adc_0/OUTx0x" -0.00319922
-cap "adc_0/OUTx2x" "adc_0/OUTx0x" -9.90548
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/OUT" 0.0134536
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.0513499
-cap "adc_0/OUTx6x" "adc_0/V_RAMP" 0.0744745
-cap "adc_0/GND" "adc_0/GRAY_INx4x" 3.06306
-cap "adc_0/OUTx4x" "adc_0/V_RAMP" -0.146449
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GND" 6.89687
-cap "adc_0/OUTx7x" "adc_0/V_RAMP" -0.00905909
-cap "adc_0/GRAY_INx4x" "adc_0/VDD" 31.2316
-cap "adc_0/OUTx5x" "adc_0/V_RAMP" -0.0183478
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 55.0151
-cap "adc_0/OUTx3x" "adc_0/V_RAMP" 0.325178
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/GND" 1.24398
-cap "adc_0/OUTx6x" "adc_0/GND" 1.65607
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.266949
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00159236
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/OUT" 0.00017554
-cap "adc_0/GND" "adc_0/GRAY_INx6x" 8.93649
-cap "adc_0/GND" "adc_0/OUTx4x" 17.6465
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 61.0801
-cap "adc_0/OUTx6x" "adc_0/VDD" 29.9881
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 59.0096
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 33.6348
-cap "adc_0/OUTx7x" "adc_0/V_IN" 0.842577
-cap "adc_0/GRAY_INx6x" "adc_0/VDD" 28.4936
-cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.909544
-cap "adc_0/OUTx7x" "adc_0/GND" 31.3875
-cap "adc_0/OUTx5x" "adc_0/V_IN" 1.78702
-cap "adc_0/OUTx4x" "adc_0/VDD" 93.8213
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.931227
-cap "adc_0/GND" "adc_0/GRAY_INx7x" 19.8029
-cap "adc_0/OUTx5x" "adc_0/GND" 11.4116
-cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.014368
-cap "adc_0/GND" "adc_0/OUTx3x" 2.77818
-cap "adc_0/GRAY_INx5x" "adc_0/GND" 9.21274
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0338576
-cap "adc_0/GND" "adc_0/GRAY_INx3x" 1.91467
-cap "adc_0/GND" "adc_0/OUTx1x" 0.0160753
-cap "adc_0/OUTx7x" "adc_0/VDD" 17.395
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx5x" 3.70053
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_4/net1" 0.00706276
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/net1" 0.0201185
cap "adc_0/OUTx5x" "adc_0/VDD" 34.2796
-cap "adc_0/GRAY_INx7x" "adc_0/VDD" 41.927
-cap "adc_0/OUTx3x" "adc_0/VDD" 69.4918
-cap "adc_0/GRAY_INx5x" "adc_0/VDD" 36.5092
-cap "adc_0/READ" "adc_0/GND" 6.80631
-cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.113861
-cap "adc_0/GRAY_INx3x" "adc_0/VDD" 26.5269
-cap "adc_0/OUTx5x" "adc_0/a_1000_n1450#" 1.36774
-cap "adc_0/OUTx1x" "adc_0/VDD" 9.54271
-cap "adc_0/OUTx3x" "adc_0/a_1720_n1450#" 1.03866
-cap "adc_0/READ" "adc_0/VDD" 245.208
-cap "adc_0/BIAS1" "adc_0/VDD" 3.88585
-cap "adc_0/a_1100_n1450#" "adc_0/VDD" 2.23919
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.708267
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GND" 3.21855
-cap "adc_0/BIAS2" "adc_0/VDD" 4.8223
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 7.59596
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.51779
-cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0131309
-cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/OUT" 0.0650129
-cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/OUT" 0.0010894
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.83968
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 2.65252
-cap "adc_0/GRAY_INx4x" "8bit_sens_0/sens_amp_4/net1" 2.96639
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/net1" 0.153801
-cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/net1" 0.94854
-cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/GRAY_INx6x" 0.0118911
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/OUTx1x" 1.56932
-cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/OUTx4x" 0.59734
-cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/net1" 1.49853
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/READ" 3.65718
-cap "adc_0/READ" "8bit_sens_0/sens_amp_5/net1" 1.02277
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/GRAY_INx4x" 1.64367
-cap "8bit_sens_0/sens_amp_3/OUT" "adc_0/OUTx5x" 0.0413391
-cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/net1" 0.00775749
-cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/net1" 1.73986
-cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_5/net1" 0.000396814
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 4.64724
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0204091
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/GN" 4.73773
-cap "adc_0/READ" "8bit_sens_0/sens_amp_4/net1" 1.59082
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 5.40068
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx6x" 0.315457
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/OUTx4x" 4.15902
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/OUTx4x" 1.89637
-cap "adc_0/GRAY_INx4x" "adc_0/OUTx0x" -0.00443477
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.340759
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx7x" 0.045347
-cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/GN" 0.522041
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/GRAY_INx3x" 0.123248
-cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/net1" 0.669192
-cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/GN" 6.58442
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/OUTx3x" 11.33
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx1x" 0.216952
-cap "adc_0/READ" "8bit_sens_0/sens_amp_6/GN" 17.575
-cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx7x" 0.00466911
-cap "adc_0/OUTx6x" "adc_0/OUTx0x" -7.28584e-16
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx0x" 0.161983
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/READ" 2.65106
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx4x" -0.00518706
-cap "adc_0/READ" "8bit_sens_0/sens_amp_3/net1" 5.25867
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/BIAS1" 0.447368
-cap "adc_0/READ" "8bit_sens_0/sens_amp_4/GN" 3.72963
-cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_6/GN" 0.165584
-cap "adc_0/OUTx4x" "adc_0/OUTx0x" 0.152769
-cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.000555492
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx0x" -0.0216959
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_3/GN" 0.153156
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 4.30704
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.35808
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.00306463
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.683638
-cap "adc_0/OUTx7x" "adc_0/OUTx0x" -0.165415
-cap "adc_0/OUTx2x" "adc_0/OUTx6x" 8.88178e-16
-cap "adc_0/OUTx5x" "adc_0/OUTx0x" -0.182552
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.2083
-cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 7.90201
-cap "adc_0/OUTx3x" "adc_0/OUTx0x" -0.171818
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx6x" -0.000853634
-cap "adc_0/GRAY_INx2x" "adc_0/OUTx3x" -7.09593
+cap "adc_0/VDD" "adc_0/a_1100_n1450#" 2.23919
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/GND" 0.00159236
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/OUT" 0.0134536
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx6x" 7.90944
-cap "adc_0/OUTx1x" "adc_0/OUTx0x" 4.34163
-cap "adc_0/OUTx2x" "adc_0/OUTx4x" -9.94157
-cap "adc_0/GRAY_INx0x" "adc_0/READ" -0.0807173
-cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 0.203364
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 60.6555
-cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/GN" 6.09883
-cap "adc_0/OUTx4x" "8bit_sens_0/sens_amp_3/GN" 2.91383
-cap "adc_0/READ" "adc_0/OUTx0x" 2.54988
-cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.400078
-cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.522468
-cap "adc_0/GRAY_INx2x" "adc_0/READ" -3.47051
-cap "adc_0/OUTx2x" "adc_0/OUTx5x" -0.232732
-cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.0661293
-cap "adc_0/OUTx2x" "adc_0/OUTx3x" 23.7209
-cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_3/GN" 0.00390518
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx7x" 0.609511
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx5x" 0.0389332
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx3x" 56.5709
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GRAY_INx7x" 3.25119
-cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/GN" 1.20005
-cap "adc_0/OUTx2x" "adc_0/OUTx1x" -2.9493
-cap "adc_0/OUTx2x" "adc_0/READ" 37.8257
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx4x" 1.10244
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx7x" 0.716144
+cap "adc_0/OUTx1x" "8bit_sens_0/sens_amp_6/GN" 0.216952
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/OUT" 0.0413391
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.708267
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_3/GN" 0.153156
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/net1" 0.153801
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_6/GN" 0.0699164
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/OUTx5x" 2.29712
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx1x" 0.318626
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" -0.0868261
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx5x" -0.000956435
+cap "adc_0/BIAS1" "8bit_sens_0/sens_amp_4/GN" 0.447368
+cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/net1" 0.315457
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 33.6348
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx5x" 14.0586
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 7.59596
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx7x" -7.09689
cap "adc_0/OUTx2x" "adc_0/BIAS1" -2.47224
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/READ" 4.37209
-cap "adc_0/READ" "8bit_sens_0/sens_amp_3/GN" 11.2252
-cap "adc_0/OUTx2x" "adc_0/BIAS2" 3.59631
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.15041
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.00205703
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/OUTx0x" 8.42612
+cap "adc_0/GRAY_INx7x" "8bit_sens_0/sens_amp_3/GN" 3.25119
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/GRAY_INx5x" 6.58442
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/net1" 0.00775749
+cap "adc_0/GRAY_INx1x" "adc_0/OUTx0x" -0.0216959
+cap "adc_0/GRAY_INx2x" "8bit_sens_0/sens_amp_6/GN" 0.454578
+cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0131309
+cap "adc_0/OUTx5x" "adc_0/a_1100_n1450#" 1.28942
+cap "adc_0/BIAS1" "adc_0/OUTx6x" -0.0275125
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.23223
+cap "adc_0/GRAY_INx5x" "adc_0/READ" -0.77153
+cap "adc_0/OUTx2x" "adc_0/OUTx3x" 23.7209
+cap "adc_0/OUTx3x" "adc_0/READ" 25.3869
+cap "adc_0/READ" "8bit_sens_0/sens_amp_3/net1" 5.25867
+cap "adc_0/OUTx3x" "8bit_sens_0/sens_amp_5/net1" 0.94854
+cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.0661293
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/GN" 1.20005
+cap "adc_0/READ" "adc_0/OUTx7x" 1.60071
+cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.522468
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/GRAY_INx4x" 1.64367
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GND" 3.21855
+cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.48031
+cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.134338
+cap "adc_0/OUTx3x" "adc_0/OUTx6x" -0.117724
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_2/net1" 4.30704
+cap "adc_0/READ" "adc_0/GRAY_INx4x" -2.62436
+cap "adc_0/OUTx2x" "adc_0/GRAY_INx4x" -0.00518706
+cap "adc_0/GRAY_INx0x" "adc_0/READ" -0.0807173
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx5x" 1.01317
+cap "adc_0/VDD" "adc_0/V_IN" 2.39161
+cap "adc_0/OUTx6x" "adc_0/OUTx7x" 20.3389
+cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/GN" 0.123248
+cap "adc_0/V_RAMP" "adc_0/OUTx6x" 0.0744745
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 4.64724
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.51779
cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00884229
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/net1" 0.0113099
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/net1" 1.05086
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.138556
+cap "adc_0/GRAY_INx4x" "adc_0/OUTx6x" -0.00119257
+cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.850562
+cap "8bit_sens_0/sens_amp_4/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00017554
+cap "adc_0/BIAS1" "adc_0/OUTx4x" -0.922934
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx7x" 0.177705
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.35808
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00685071
+cap "adc_0/OUTx3x" "adc_0/OUTx4x" -2.43468
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.103354
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GRAY_INx7x" -1.33305
+cap "adc_0/OUTx4x" "8bit_sens_0/sens_amp_3/net1" 4.15902
+cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx6x" -0.000739663
+cap "adc_0/GRAY_INx5x" "adc_0/GND" 9.04473
+cap "adc_0/OUTx3x" "adc_0/GND" 2.77818
+cap "adc_0/BIAS1" "adc_0/VDD" 3.88585
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx6x" -0.000390028
+cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GND" 0.00444633
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_2/net1" 0.0389332
+cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.014368
+cap "adc_0/OUTx4x" "adc_0/OUTx7x" -0.453278
+cap "adc_0/OUTx5x" "adc_0/V_IN" 1.78702
+cap "adc_0/V_RAMP" "adc_0/OUTx4x" -0.146449
+cap "adc_0/OUTx7x" "adc_0/GND" 31.3875
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" 0.0157817
+cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/OUT" 1.78456
+cap "adc_0/OUTx1x" "adc_0/OUTx3x" -1.50771
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx5x" 1.93238
+cap "adc_0/GRAY_INx4x" "adc_0/OUTx4x" -0.0014868
+cap "adc_0/GRAY_INx5x" "adc_0/VDD" 36.5092
+cap "adc_0/GRAY_INx4x" "adc_0/GND" 3.06306
+cap "adc_0/OUTx3x" "adc_0/VDD" 69.4918
+cap "adc_0/V_IN" "8bit_sens_0/sens_amp_3/GN" 0.00522501
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx7x" 0.00466911
+cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0180222
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/READ" 3.65718
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx7x" 1.659
+cap "adc_0/VDD" "adc_0/a_1000_n1450#" 0.334655
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx2x" 56.5709
+cap "adc_0/VDD" "adc_0/OUTx7x" 17.395
+cap "adc_0/GRAY_INx3x" "adc_0/READ" -1.9658
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.0513499
+cap "adc_0/GRAY_INx1x" "adc_0/READ" -0.0114114
+cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/net1" 1.49853
+cap "adc_0/V_RAMP" "adc_0/VDD" 0.12972
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/GRAY_INx5x" -0.934061
+cap "adc_0/VDD" "adc_0/GRAY_INx4x" 31.2316
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/OUTx3x" 0.909544
+cap "adc_0/OUTx2x" "adc_0/BIAS2" 3.59631
+cap "adc_0/OUTx5x" "adc_0/BIAS1" 3.40646
+cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_5/net1" 0.000396814
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx3x" 0.0232261
+cap "adc_0/GRAY_INx7x" "8bit_sens_0/sens_amp_3/net1" 0.045347
+cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.295252
+cap "adc_0/GRAY_INx2x" "adc_0/OUTx3x" -7.09593
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx7x" -0.675707
+cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0767923
+cap "adc_0/GRAY_INx5x" "8bit_sens_0/sens_amp_4/net1" 1.73986
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 5.40068
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx5x" 0.0100576
+cap "adc_0/OUTx5x" "adc_0/OUTx3x" -3.28179
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_3/net1" 0.669192
+cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx4x" -0.00135158
+cap "adc_0/OUTx3x" "adc_0/a_1100_n1450#" 0.643658
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.000555492
+cap "adc_0/OUTx5x" "adc_0/a_1000_n1450#" 1.36774
+cap "adc_0/OUTx5x" "adc_0/OUTx7x" 13.9109
+cap "adc_0/OUTx5x" "adc_0/V_RAMP" -0.0183478
+cap "adc_0/GRAY_INx4x" "8bit_sens_0/sens_amp_4/net1" 2.96639
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/net1" 0.15041
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx4x" 0.538846
+cap "adc_0/OUTx7x" "8bit_sens_0/sens_amp_3/GN" 0.00390518
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00585743
cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.128619
+cap "adc_0/GRAY_INx3x" "adc_0/GND" 1.90252
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx5x" -0.366214
+cap "adc_0/OUTx4x" "adc_0/BIAS2" 0.208944
+cap "adc_0/OUTx1x" "8bit_sens_0/sens_amp_6/net1" 1.56932
+cap "adc_0/OUTx2x" "adc_0/OUTx0x" -9.90548
+cap "adc_0/OUTx0x" "adc_0/READ" 2.5507
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0201386
+cap "adc_0/GRAY_INx3x" "adc_0/VDD" 26.5269
+cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -5.5826e-05
+cap "adc_0/OUTx0x" "adc_0/OUTx6x" -7.28584e-16
+cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.90789
+cap "adc_0/VDD" "adc_0/BIAS2" 4.8223
+cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 7.90201
+cap "adc_0/OUTx2x" "adc_0/a_1870_n1400#" 0.784228
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 0.04391
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_sens_0/sens_amp_5/net1" 2.65252
+cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.931227
cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.352258
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0201185
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 0.295252
+cap "adc_0/READ" "8bit_sens_0/sens_amp_5/GN" 2.65106
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx2x" -0.00306463
+cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.756483
+cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/GN" 19.2186
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/OUTx7x" 0.609511
+cap "adc_0/V_IN" "adc_0/OUTx7x" 0.842577
+cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.591716
cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.6445
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0236306
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 1.52549
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/net1" 0.0113099
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx5x" 0.00905904
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.314181
+cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.000778297
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0338576
+cap "adc_0/OUTx0x" "adc_0/OUTx4x" 0.152769
+cap "adc_0/OUTx0x" "adc_0/GND" 0.956032
+cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/OUT" 0.750956
+cap "adc_0/OUTx5x" "adc_0/BIAS2" 0.951676
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx2x" -0.000853634
+cap "adc_0/GRAY_INx6x" "adc_0/READ" 0.843044
+cap "adc_0/BIAS1" "adc_0/OUTx3x" -0.385619
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 1.83968
+cap "adc_0/OUTx1x" "adc_0/OUTx0x" 4.34163
+cap "adc_0/BIAS2" "8bit_sens_0/sens_amp_6/GN" 0.165584
+cap "adc_0/OUTx0x" "adc_0/VDD" 42.8299
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/GND" 0.266949
+cap "adc_0/BIAS1" "adc_0/OUTx7x" -0.206538
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx6x" -0.00119747
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/READ" 3.72963
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx5x" 1.60864
+cap "adc_0/OUTx2x" "adc_0/READ" 38.2051
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/GND" 0.0673912
+cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.422993
+cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.113861
+cap "adc_0/READ" "8bit_sens_0/sens_amp_5/net1" 1.02277
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 59.0096
+cap "adc_0/OUTx2x" "8bit_sens_0/sens_amp_5/net1" 18.0563
cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.32181
-cap "adc_0/VDD" "adc_0/V_RAMP" 0.12972
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.168165
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx4x" 0.725899
+cap "adc_0/OUTx3x" "adc_0/V_RAMP" 0.325178
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GND" 4.2083
+cap "adc_0/OUTx0x" "adc_0/GRAY_INx2x" -0.00319922
+cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx4x" -0.00153296
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx4x" 14.5447
+cap "adc_0/V_RAMP" "adc_0/OUTx7x" -0.00905909
+cap "adc_0/OUTx2x" "adc_0/OUTx6x" 8.88178e-16
cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.00251029
-cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 9.04343
-cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" -0.437982
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0810341
-cap "adc_0/GRAY_INx1x" "8bit_sens_0/sens_amp_7/GN" 1.15023
-cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -1.13467
-cap "adc_0/VDD" "8bit_sens_0/sens_amp_4/GN" 0.00136439
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/VDD" 0.888871
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/VDD" 0.110949
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_7/GN" 0.0675601
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 0.848429
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.807124
-cap "adc_0/VDD" "8bit_sens_0/sens_amp_6/net1" 2.24439
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/net1" 0.0032509
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.08478
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00342536
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/net1" 0.527436
-cap "adc_0/GND" "adc_0/OUTx0x" 0.581515
-cap "adc_0/GND" "adc_0/OUTx1x" 0.123497
-cap "adc_0/OUTx2x" "adc_0/OUTx0x" -0.465476
-cap "adc_0/OUTx2x" "adc_0/OUTx1x" -2.93762
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" 7.84213
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx1x" -3.20485
-cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0988289
-cap "adc_0/GND" "adc_0/VDD" 0.224545
-cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.677825
-cap "adc_0/OUTx2x" "adc_0/VDD" 0.387613
-cap "adc_0/BIAS2" "adc_0/OUTx1x" 0.040046
-cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.631704
-cap "adc_0/BIAS1" "adc_0/OUTx1x" -0.12899
-cap "adc_0/GRAY_INx0x" "adc_0/VDD" 75.1741
+cap "adc_0/READ" "adc_0/OUTx6x" 0.182357
+cap "adc_0/a_1720_n1450#" "adc_0/VDD" 0.256808
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.0278411
+cap "adc_0/OUTx5x" "adc_0/OUTx0x" -0.182552
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx4x" -0.000998441
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 60.6555
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/READ" 1.47446
+cap "adc_0/GRAY_INx6x" "adc_0/GND" 8.93649
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 2.61852
+cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/GN" 9.18392
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/GN" 0.118608
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/OUTx6x" 3.05663
+cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.0161971
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx0x" 0.161983
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/OUTx4x" 1.89637
+cap "adc_0/GRAY_INx6x" "adc_0/VDD" 28.4936
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/GND" 0.142041
+cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.871526
+cap "adc_0/READ" "adc_0/OUTx4x" 33.3241
+cap "adc_0/OUTx2x" "adc_0/OUTx4x" -9.94157
+cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/OUT" 0.0118911
+cap "adc_0/READ" "adc_0/GND" 6.80631
+cap "adc_0/OUTx2x" "adc_0/GND" 7.9079
+cap "8bit_sens_0/sens_amp_5/net1" "adc_0/GND" 0.00878094
+cap "8bit_sens_0/sens_amp_5/OUT" "adc_0/OUTx3x" 0.0650129
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/net1" 1.05086
+cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.76156
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/VDD" 2.8147e-05
+cap "adc_0/OUTx1x" "adc_0/READ" 0.163117
+cap "adc_0/OUTx1x" "adc_0/OUTx2x" -2.9493
+cap "adc_0/OUTx4x" "adc_0/OUTx6x" -6.18725
+cap "adc_0/OUTx6x" "adc_0/GND" 1.65607
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx7x" 0.00252296
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/READ" -0.0123961
+cap "adc_0/READ" "adc_0/VDD" 245.208
+cap "adc_0/OUTx2x" "adc_0/VDD" 98.3794
+cap "8bit_sens_0/sens_amp_4/OUT" "adc_0/GRAY_INx5x" 0.0458033
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx3x" 0.0234924
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_5/net1" 0.175788
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 1.52549
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/GN" 0.138556
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_4/GN" 4.73773
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/OUTx6x" 0.340759
+cap "adc_0/OUTx1x" "adc_0/OUTx6x" -0.024305
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx7x" 0.182126
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx5x" 59.832
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/READ" -2.53655
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.0674098
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/OUTx6x" -1.77485
+cap "adc_0/OUTx3x" "adc_0/BIAS2" 0.948413
+cap "adc_0/VDD" "adc_0/OUTx6x" 29.9881
+cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.34939
+cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx4x" -0.00496884
+cap "8bit_sens_0/sens_amp_4/OUT" "adc_0/GRAY_INx4x" 0.0162939
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx4x" -0.00384267
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/net1" 0.281215
+cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.207787
+cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/GN" 6.09883
+cap "adc_0/GRAY_INx7x" "adc_0/READ" 0.265567
+cap "8bit_sens_0/sens_amp_2/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.1903
+cap "adc_0/GRAY_INx2x" "adc_0/READ" -3.44747
+cap "adc_0/OUTx5x" "8bit_sens_0/sens_amp_4/GN" 0.522041
+cap "adc_0/OUTx4x" "adc_0/GND" 17.1856
+cap "adc_0/READ" "8bit_sens_0/sens_amp_4/net1" 1.59082
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx6x" -0.498991
+cap "adc_0/OUTx5x" "adc_0/READ" 40.9643
+cap "adc_0/OUTx2x" "adc_0/OUTx5x" -0.232732
+cap "adc_0/OUTx1x" "adc_0/OUTx4x" 0.450912
+cap "adc_0/OUTx1x" "adc_0/GND" 0.0160753
+cap "adc_0/OUTx0x" "adc_0/BIAS1" -0.400078
+cap "adc_0/READ" "8bit_sens_0/sens_amp_3/GN" 11.2252
+cap "adc_0/READ" "8bit_sens_0/sens_amp_6/GN" 17.575
+cap "adc_0/VDD" "adc_0/OUTx4x" 93.8213
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GND" 6.89687
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0236306
+cap "adc_0/OUTx5x" "adc_0/OUTx6x" 5.77365
+cap "adc_0/VDD" "adc_0/GND" 11.5888
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.683638
+cap "adc_0/OUTx4x" "8bit_sens_0/sens_amp_3/OUT" 0.59734
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/READ" -0.132168
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/OUTx4x" 3.80667
+cap "8bit_sens_0/sens_amp_2/OUT" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0204091
+cap "adc_0/OUTx1x" "adc_0/VDD" 9.54271
+cap "adc_0/OUTx0x" "adc_0/OUTx3x" -0.171818
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/GND" 1.24398
+cap "adc_0/GRAY_INx3x" "8bit_sens_0/sens_amp_5/OUT" 0.0010894
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 55.0151
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/GND" 0.168165
+cap "adc_0/OUTx0x" "adc_0/OUTx7x" -0.165415
+cap "adc_0/OUTx0x" "adc_0/V_RAMP" -0.134294
+cap "adc_0/GRAY_INx7x" "adc_0/GND" 19.1756
+cap "adc_0/GRAY_INx2x" "adc_0/GND" 0.355663
+cap "adc_0/OUTx0x" "adc_0/GRAY_INx4x" -0.00443477
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 61.0801
+cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.90521
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.0952982
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" 0.00858993
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 7.27989
+cap "adc_0/OUTx5x" "adc_0/OUTx4x" 17.379
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/GND" 0.00371336
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 0.203364
+cap "adc_0/OUTx4x" "adc_0/a_1100_n1450#" 0.193556
+cap "adc_0/OUTx5x" "adc_0/GND" 11.4116
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/GRAY_INx7x" -2.35733
+cap "adc_0/VDD" "adc_0/GRAY_INx2x" 1.68103
+cap "adc_0/VDD" "adc_0/GRAY_INx1x" 61.1837
cap "adc_0/OUTx0x" "adc_0/VDD" 157.842
-cap "adc_0/VDD" "adc_0/OUTx1x" 24.4041
-cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.395936
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" -0.00186608
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 7.04787
+cap "adc_0/OUTx1x" "adc_0/VDD" 24.4041
+cap "adc_0/VDD" "adc_0/BIAS2" 0.568848
+cap "adc_0/VDD" "adc_0/OUTx2x" 0.387613
+cap "adc_0/GRAY_INx1x" "8bit_sens_0/sens_amp_7/GN" 1.15023
+cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/GN" 16.3165
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_6/GN" 0.545507
+cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 2.94733
+cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -1.13467
+cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.0224807
+cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.13133
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx3x" -0.00282864
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.000568322
+cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.434238
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_6/GN" 1.78378
cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 13.6045
cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.108829
-cap "adc_0/a_1870_n1400#" "adc_0/OUTx1x" 0.184272
-cap "adc_0/V_RAMP" "adc_0/OUTx1x" -0.0432902
-cap "adc_0/BIAS2" "adc_0/VDD" 0.568848
-cap "adc_0/OUTx3x" "adc_0/OUTx1x" -0.251285
-cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/GN" 1.0749
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" -0.00186608
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/OUTx1x" 0.118384
-cap "adc_0/OUTx5x" "adc_0/OUTx1x" -0.118123
-cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0107875
-cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 6.84134
-cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" -0.00282864
-cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.167769
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 27.1321
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.000568322
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 11.3443
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx0x" 0.00047027
-cap "adc_0/OUTx3x" "adc_0/VDD" 0.126884
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00257041
-cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.28298
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx1x" -0.0484037
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx0x" 60.6016
-cap "adc_0/OUTx4x" "adc_0/OUTx0x" 0.0575966
-cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.0759572
-cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.020233
-cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/GN" 8.14737
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/OUTx0x" 15.5606
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/VDD" 1.78378
-cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/net1" 0.412847
-cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/GN" 16.3165
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx0x" 2.94733
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/OUTx1x" 1.13133
-cap "adc_0/GRAY_INx3x" "adc_0/VDD" 0.745508
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 59.4963
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 0.203364
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 0.202701
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 7.04787
-cap "adc_0/GRAY_INx1x" "adc_0/VDD" 61.1837
-cap "adc_0/VDD" "8bit_sens_0/sens_amp_7/GN" 3.4502
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/VDD" 17.927
-cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.434238
-cap "adc_0/GND" "8bit_sens_0/sens_amp_6/net1" 0.000928339
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 30.0801
-cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.360981
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.545507
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00627251
+cap "8bit_sens_0/sens_amp_5/net1" "adc_0/VDD" 0.888871
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_6/net1" 1.08478
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_7/net1" 0.0810341
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 0.848429
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.173762
+cap "adc_0/OUTx0x" "adc_0/GRAY_INx0x" 7.84213
cap "adc_0/GRAY_INx1x" "adc_0/OUTx3x" 0.0199684
-cap "adc_0/VDD" "adc_0/GRAY_INx2x" 1.68103
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" 0.00721156
+cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx1x" 0.00047027
+cap "adc_0/OUTx0x" "adc_0/GND" 0.581515
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/OUT" 1.51098
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx1x" 0.0224807
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_sens_0/sens_amp_6/GN" 0.173762
+cap "adc_0/OUTx1x" "adc_0/OUTx3x" -0.251285
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx1x" -3.20485
+cap "adc_0/OUTx1x" "adc_0/GND" 0.123497
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/VDD" 2.24439
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_4/GN" 0.00136439
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_7/net1" 17.927
+cap "adc_0/VDD" "adc_0/a_1870_n1400#" 0.167769
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.527436
+cap "adc_0/OUTx0x" "adc_0/GRAY_INx1x" 60.6016
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 0.203364
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx1x" -0.437982
+cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.28298
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx1x" -0.0484037
+cap "8bit_sens_0/sens_amp_4/net1" "adc_0/VDD" 0.110949
+cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0988289
+cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.677825
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0032509
+cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.00257041
+cap "adc_0/OUTx0x" "adc_0/OUTx2x" -0.465476
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/net1" 0.00627251
+cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.040046
+cap "adc_0/OUTx1x" "adc_0/OUTx2x" -2.93762
+cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/GN" 1.0749
+cap "adc_0/GND" "8bit_sens_0/sens_amp_6/net1" 0.000928339
+cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/net1" 0.412847
+cap "adc_0/OUTx1x" "8bit_sens_0/sens_amp_6/GN" 0.118384
+cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_7/net1" 15.5606
cap "adc_0/OUTx0x" "8bit_sens_0/sens_amp_6/net1" 1.62315
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/VDD" 59.4963
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/net1" 0.00342536
cap "adc_0/OUTx1x" "8bit_sens_0/sens_amp_6/net1" 0.707811
-cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.155666
+cap "adc_0/OUTx0x" "adc_0/BIAS1" -0.631704
+cap "adc_0/OUTx0x" "adc_0/a_1870_n1400#" 0.395936
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_sens_0/sens_amp_7/GN" 9.04343
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.202701
+cap "adc_0/OUTx1x" "adc_0/BIAS1" -0.12899
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/VDD" 0.807124
+cap "adc_0/OUTx1x" "adc_0/a_1870_n1400#" 0.184272
+cap "adc_0/VDD" "8bit_sens_0/sens_amp_7/GN" 3.4502
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 30.0801
+cap "adc_0/VDD" "adc_0/GRAY_INx3x" 0.745508
+cap "8bit_sens_0/sens_amp_7/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0675601
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 27.1321
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/GRAY_INx0x" 0.0107875
+cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.020233
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.360981
+cap "adc_0/OUTx0x" "adc_0/OUTx4x" 0.0575966
+cap "adc_0/GRAY_INx0x" "adc_0/VDD" 75.1741
+cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.0759572
+cap "adc_0/GND" "adc_0/VDD" 0.224545
+cap "adc_0/VDD" "adc_0/OUTx3x" 0.126884
+cap "adc_0/OUTx1x" "adc_0/V_RAMP" -0.0432902
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx1x" 0.00721156
+cap "adc_0/GRAY_INx0x" "8bit_sens_0/sens_amp_7/GN" 8.14737
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/OUTx0x" 6.84134
+cap "adc_0/OUTx5x" "adc_0/OUTx1x" -0.118123
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/GRAY_INx1x" -0.155666
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/OUTx1x" 11.3443
cap "io_analog[2]" "adc_0/GND" 0.00691822
-cap "adc_0/GND" "m2_33290_207480#" 0.0254068
-cap "adc_0/BIAS2" "adc_0/GRAY_INx5x" 0.692629
-cap "adc_0/BIAS2" "adc_0/OUTx3x" 0.353329
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.0639255
-cap "adc_0/GND" "adc_0/V_RAMP" 1.43581
-cap "adc_0/BIAS2" "adc_0/BIAS1" 9.18833
-cap "adc_0/BIAS2" "adc_0/OUTx2x" 0.528351
-cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 0.0103339
-cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.171096
-cap "adc_0/GRAY_INx6x" "adc_0/GND" 5.21166
-cap "adc_0/BIAS2" "adc_0/OUTx6x" 11.6304
-cap "adc_0/BIAS1" "adc_0/OUTx6x" 23.7114
-cap "adc_0/V_IN" "adc_0/GND" 30.8154
-cap "adc_0/GND" "adc_0/GRAY_INx4x" 3.35427
-cap "adc_0/OUTx4x" "adc_0/GND" 4.8424
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0376022
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/GND" 1.35734
-cap "adc_0/BIAS2" "adc_0/GRAY_INx2x" 0.323507
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.0255192
-cap "adc_0/OUTx5x" "adc_0/GND" 4.22452
-cap "adc_0/VDD" "adc_0/V_RAMP" -0.105008
-cap "adc_0/BIAS2" "adc_0/READ" 0.16815
-cap "adc_0/BIAS1" "adc_0/READ" 7.47213
-cap "adc_0/VDD" "adc_0/V_IN" 0.622585
-cap "8bit_sens_0/VDD" "adc_0/V_IN" 0.11189
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.00378144
-cap "adc_0/BIAS2" "adc_0/V_RAMP" 3.94799
-cap "adc_0/OUTx6x" "adc_0/V_RAMP" 22.084
-cap "adc_0/BIAS2" "adc_0/OUTx4x" 0.782367
-cap "adc_0/BIAS2" "adc_0/V_IN" 14.8936
-cap "adc_0/BIAS2" "adc_0/GRAY_INx6x" 0.889568
-cap "adc_0/BIAS2" "adc_0/GRAY_INx4x" 0.673636
-cap "adc_0/V_IN" "adc_0/BIAS1" 1.52674
-cap "adc_0/V_IN" "adc_0/OUTx6x" -0.00316111
-cap "adc_0/BIAS2" "adc_0/OUTx5x" 0.585344
-cap "adc_0/READ" "adc_0/V_RAMP" 0.50167
-cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.485072
-cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.350313
-cap "adc_0/V_IN" "adc_0/V_RAMP" 0.240334
-cap "adc_0/V_IN" "8bit_sens_0/sens_amp_2/GN" 0.000283854
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 69.1744
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.118527
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0118577
-cap "vccd1" "adc_0/GND" -0.249633
-cap "adc_0/GRAY_INx7x" "adc_0/GND" 14.9717
-cap "adc_0/OUTx7x" "adc_0/GND" 36.5851
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.897105
-cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.072571
-cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.18713
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" 0.0257985
-cap "adc_0/OUTx1x" "adc_0/GND" 0.0679257
-cap "adc_0/GRAY_INx3x" "adc_0/GND" 2.80485
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/GND" 16.7483
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.018809
-cap "adc_0/VDD" "adc_0/GND" -2.08868
-cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.4509
-cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.127801
-cap "adc_0/a_1870_n1400#" "adc_0/GND" 0.132542
-cap "adc_0/a_1720_n1450#" "adc_0/GND" 0.977945
-cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.000453928
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0582996
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.188055
-cap "8bit_sens_0/VDD" "adc_0/GND" 0.831031
-cap "adc_0/a_1000_n1450#" "adc_0/GND" 2.03303
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.100071
-cap "adc_0/BIAS2" "vccd1" 0.691863
-cap "adc_0/BIAS2" "adc_0/GRAY_INx7x" 0.879863
-cap "vccd1" "adc_0/OUTx6x" 7.7258
-cap "adc_0/a_1100_n1450#" "adc_0/GND" 4.44552
-cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.943646
-cap "adc_0/BIAS2" "adc_0/OUTx7x" 0.750125
-cap "adc_0/OUTx7x" "adc_0/BIAS1" 0.905213
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0785371
-cap "vccd1" "adc_0/READ" 0.277243
-cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.0874398
-cap "adc_0/BIAS2" "adc_0/GRAY_INx3x" 0.38098
-cap "adc_0/GRAY_INx5x" "adc_0/GND" 6.17564
-cap "adc_0/OUTx3x" "adc_0/GND" 2.30368
-cap "adc_0/BIAS2" "adc_0/GND" 3.21007
-cap "adc_0/BIAS1" "adc_0/GND" 188.732
-cap "adc_0/OUTx2x" "adc_0/GND" 2.94139
+cap "m2_33290_207480#" "adc_0/GND" 0.0254068
cap "8bit_sens_0/sens_amp_2/net1" "adc_0/GND" 0.000620416
-cap "adc_0/GND" "adc_0/OUTx6x" 200.75
-cap "adc_0/OUTx0x" "adc_0/GND" 0.503927
-cap "adc_0/BIAS2" "adc_0/GRAY_INx1x" 0.00711746
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 0.184857
-cap "adc_0/GRAY_INx2x" "adc_0/GND" 1.27402
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_RAMP" 0.170305
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" 0.0167998
-cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.02792
-cap "adc_0/BIAS2" "adc_0/VDD" 7.03064
-cap "adc_0/VDD" "adc_0/BIAS1" -0.101831
-cap "adc_0/BIAS2" "adc_0/a_1720_n1450#" 3.69327
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/GN" 0.394808
cap "8bit_sens_0/VDD" "adc_0/BIAS2" 0.189809
-cap "adc_0/READ" "adc_0/GND" 13.5743
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 2.51318
-cap "adc_0/VDD" "adc_0/OUTx6x" 1.08208
-cap "adc_0/BIAS2" "adc_0/a_1870_n1400#" 2.60796
-cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.691028
-cap "adc_0/BIAS2" "adc_0/a_1000_n1450#" 6.66027
-cap "adc_0/BIAS2" "adc_0/a_1100_n1450#" 5.6902
+cap "adc_0/OUTx7x" "adc_0/GND" 36.5851
+cap "adc_0/BIAS1" "adc_0/OUTx6x" 23.2399
+cap "adc_0/BIAS1" "adc_0/GND" 39.192
+cap "adc_0/GND" "adc_0/a_1000_n1450#" 2.03303
+cap "adc_0/OUTx0x" "adc_0/GND" 0.503927
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_IN" -0.691028
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.897105
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/READ" -0.0785371
+cap "adc_0/OUTx6x" "adc_0/V_RAMP" 22.084
+cap "adc_0/BIAS2" "adc_0/GND" 3.21007
+cap "adc_0/BIAS2" "adc_0/OUTx6x" 11.6304
+cap "adc_0/GND" "adc_0/V_RAMP" 1.43581
+cap "adc_0/GRAY_INx2x" "adc_0/GND" 1.27402
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.0639255
+cap "adc_0/a_2260_n1450#" "adc_0/BIAS2" 0.71284
+cap "adc_0/V_IN" "8bit_sens_0/sens_amp_2/GN" 0.000283854
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GND" 0.118527
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.100071
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.00378144
+cap "vccd1" "adc_0/OUTx6x" 7.7258
+cap "vccd1" "adc_0/GND" -0.249633
+cap "adc_0/OUTx7x" "adc_0/V_IN" 0.00795876
+cap "adc_0/a_1100_n1450#" "adc_0/GND" 4.44552
+cap "adc_0/BIAS1" "adc_0/V_IN" 1.52674
+cap "adc_0/VDD" "adc_0/BIAS1" -0.101831
+cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.0874398
+cap "adc_0/BIAS1" "adc_0/READ" 6.47744
+cap "adc_0/GND" "adc_0/a_1870_n1400#" 0.132542
+cap "8bit_sens_0/VDD" "adc_0/GND" 0.831031
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "vccd1" 0.000453928
+cap "adc_0/GRAY_INx7x" "adc_0/BIAS2" 0.879863
+cap "adc_0/BIAS2" "adc_0/V_IN" 14.8936
+cap "adc_0/VDD" "adc_0/BIAS2" 7.03064
+cap "adc_0/V_IN" "adc_0/V_RAMP" 0.240334
+cap "adc_0/BIAS2" "adc_0/READ" -2.88658e-15
+cap "adc_0/READ" "adc_0/V_RAMP" 0.50167
+cap "adc_0/VDD" "adc_0/V_RAMP" -0.105008
+cap "adc_0/BIAS2" "adc_0/a_1720_n1450#" 3.69327
+cap "adc_0/GND" "adc_0/OUTx6x" 200.75
+cap "adc_0/BIAS2" "adc_0/OUTx5x" 0.585344
cap "vccd1" "adc_0/V_IN" 0.383251
+cap "vccd1" "adc_0/READ" 0.277243
+cap "adc_0/BIAS2" "adc_0/GRAY_INx6x" 0.889568
+cap "adc_0/GRAY_INx3x" "adc_0/BIAS2" 0.38098
+cap "8bit_sens_0/VDD" "adc_0/V_IN" 0.11189
+cap "adc_0/OUTx1x" "adc_0/GND" 0.0679257
+cap "adc_0/BIAS2" "adc_0/OUTx4x" 0.782367
+cap "adc_0/OUTx6x" "adc_0/V_IN" -0.00316111
+cap "adc_0/GRAY_INx7x" "adc_0/GND" 14.9717
+cap "adc_0/VDD" "adc_0/OUTx6x" 1.08208
+cap "adc_0/VDD" "adc_0/GND" -2.08868
+cap "adc_0/GND" "adc_0/V_IN" 30.8154
+cap "adc_0/GND" "adc_0/READ" 13.5743
+cap "adc_0/BIAS2" "adc_0/OUTx3x" 0.353329
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/GN" 0.394808
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.0118577
+cap "adc_0/GRAY_INx1x" "adc_0/BIAS2" 0.00711746
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0582996
+cap "adc_0/GND" "adc_0/a_1720_n1450#" 0.977945
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.35734
+cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.350313
+cap "adc_0/GND" "adc_0/OUTx5x" 4.22452
+cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.4509
+cap "adc_0/BIAS2" "adc_0/GRAY_INx5x" 0.692629
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/GN" 0.0255192
+cap "adc_0/GND" "adc_0/GRAY_INx6x" 5.21166
+cap "8bit_sens_0/sens_amp_2/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.02792
+cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.127801
+cap "adc_0/GRAY_INx3x" "adc_0/GND" 2.80485
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_RAMP" 0.170305
+cap "adc_0/BIAS2" "adc_0/OUTx2x" 0.528351
+cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0257985
+cap "adc_0/VDD" "adc_0/V_IN" 0.622585
cap "adc_0/VDD" "adc_0/READ" 0.157368
-cap "adc_0/V_IN" "adc_0/OUTx7x" 0.00795876
-cap "adc_0/BIAS2" "adc_0/a_2260_n1450#" 0.71284
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -2.46916
-cap "adc_0/V_RAMP" "adc_0/OUTx3x" -1.22185
-cap "adc_0/a_1720_n1450#" "adc_0/OUTx6x" -0.0039073
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.521457
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx7x" -1.4115
-cap "adc_0/GRAY_INx2x" "adc_0/a_1870_n1400#" -0.258898
-cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.83413
-cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.78091
-cap "adc_0/a_1720_n1450#" "adc_0/OUTx3x" 0.0324566
-cap "adc_0/GRAY_INx2x" "adc_0/V_RAMP" -2.59343
-cap "adc_0/GRAY_INx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.01736
-cap "adc_0/GRAY_INx2x" "adc_0/a_1720_n1450#" -0.374624
-cap "adc_0/VDD" "adc_0/OUTx1x" 4.43665
-cap "adc_0/V_RAMP" "adc_0/a_1870_n1400#" -0.868431
-cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.774957
-cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.00564446
-cap "adc_0/GND" "adc_0/OUTx0x" 0.328734
-cap "adc_0/V_RAMP" "adc_0/a_1720_n1450#" -2.34235
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.00309223
-cap "adc_0/OUTx7x" "adc_0/OUTx0x" -0.00287057
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.0116736
-cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.076852
-cap "adc_0/VDD" "adc_0/GRAY_INx1x" -0.000655092
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.237223
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
-cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.098673
-cap "adc_0/GRAY_INx4x" "adc_0/OUTx0x" -0.0090045
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0797386
-cap "adc_0/GND" "8bit_sens_0/sens_amp_4/net1" 0.0238539
-cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.00864429
-cap "adc_0/OUTx3x" "adc_0/OUTx0x" -0.00585898
-cap "adc_0/GRAY_INx2x" "adc_0/OUTx0x" -0.0102886
-cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0347412
-cap "adc_0/VDD" "adc_0/a_1000_n1450#" 67.3169
-cap "adc_0/V_RAMP" "adc_0/OUTx0x" -1.81075
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 3.05952
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 13.7358
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.322553
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/net1" 0.481951
-cap "adc_0/VDD" "adc_0/OUTx5x" 21.2422
-cap "8bit_sens_0/sens_amp_4/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.832171
-cap "adc_0/VDD" "adc_0/a_1100_n1450#" 23.3587
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/net1" 0.779593
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0932343
-cap "adc_0/VDD" "adc_0/GRAY_INx6x" -5.94381
-cap "adc_0/VDD" "adc_0/GRAY_INx3x" 1.52812
-cap "adc_0/VDD" "adc_0/GND" 34.8106
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx3x" 0.0514982
-cap "adc_0/GND" "adc_0/OUTx1x" 0.00175627
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.00217775
-cap "adc_0/OUTx4x" "adc_0/VDD" 28.2314
-cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.00278335
-cap "adc_0/VDD" "adc_0/OUTx7x" 38.4304
-cap "adc_0/VDD" "adc_0/GRAY_INx0x" -0.000468515
-cap "adc_0/OUTx7x" "adc_0/OUTx1x" -0.383333
+cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.184857
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/GND" 2.51318
+cap "adc_0/GND" "adc_0/OUTx4x" 4.8424
+cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.485072
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.0376022
+cap "adc_0/BIAS2" "adc_0/GRAY_INx4x" 0.673636
+cap "adc_0/GND" "adc_0/OUTx3x" 2.30368
+cap "adc_0/OUTx7x" "adc_0/BIAS2" 0.750125
+cap "adc_0/BIAS1" "adc_0/BIAS2" 2.24622
+cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.18713
+cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.171096
+cap "adc_0/BIAS2" "adc_0/a_1000_n1450#" 6.66027
+cap "vccd1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.072571
+cap "adc_0/GND" "adc_0/GRAY_INx5x" 6.17564
+cap "adc_0/BIAS2" "adc_0/V_RAMP" 3.94799
+cap "adc_0/GRAY_INx2x" "adc_0/BIAS2" 0.323507
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx6x" -0.188055
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 69.1744
+cap "8bit_sens_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.943646
+cap "adc_0/GND" "adc_0/OUTx2x" 2.94139
+cap "vccd1" "adc_0/BIAS2" 0.691863
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.018809
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/GN" 0.0103339
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" 0.0167998
+cap "adc_0/a_1100_n1450#" "adc_0/BIAS2" 5.6902
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 16.7483
+cap "adc_0/GND" "adc_0/GRAY_INx4x" 3.35427
+cap "adc_0/BIAS2" "adc_0/a_1870_n1400#" 2.60796
+cap "adc_0/a_1720_n1450#" "adc_0/VDD" 20.7118
+cap "adc_0/a_1870_n1400#" "adc_0/VDD" 15.8
cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 12.0239
-cap "adc_0/VDD" "adc_0/BIAS1" -1.63654
-cap "adc_0/OUTx1x" "adc_0/BIAS1" 0.117885
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0927804
-cap "adc_0/VDD" "adc_0/OUTx2x" 35.095
-cap "adc_0/OUTx2x" "adc_0/OUTx1x" -0.00404213
-cap "adc_0/VDD" "adc_0/GRAY_INx5x" -4.67059
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx1x" 0.0397904
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 8.42068
-cap "adc_0/VDD" "adc_0/BIAS2" 27.9299
-cap "adc_0/OUTx1x" "adc_0/BIAS2" 0.0461409
-cap "adc_0/VDD" "adc_0/GRAY_INx4x" 3.58556
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx6x" -0.0388247
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx3x" -4.72
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 10.1777
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0932343
-cap "adc_0/VDD" "adc_0/V_IN" 20.226
-cap "adc_0/READ" "adc_0/VDD" 2.66143
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.0120092
-cap "adc_0/a_1000_n1450#" "adc_0/OUTx5x" 0.0876459
-cap "adc_0/VDD" "adc_0/OUTx6x" 26.5805
-cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.00239261
-cap "adc_0/VDD" "adc_0/OUTx3x" 20.9427
-cap "adc_0/VDD" "adc_0/GRAY_INx7x" 6.37109
-cap "adc_0/GRAY_INx7x" "adc_0/OUTx1x" -0.045179
-cap "adc_0/VDD" "adc_0/GRAY_INx2x" 2.98684
-cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 2.125
-cap "adc_0/GRAY_INx1x" "adc_0/BIAS2" -0.000416707
-cap "adc_0/VDD" "adc_0/a_1870_n1400#" 15.8
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx4x" -0.0747682
-cap "adc_0/VDD" "adc_0/V_RAMP" -73.6423
-cap "adc_0/V_RAMP" "adc_0/OUTx1x" -0.33173
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 122.325
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.412947
-cap "adc_0/VDD" "adc_0/a_1720_n1450#" 20.7118
-cap "adc_0/GND" "adc_0/a_1000_n1450#" 0.621255
-cap "adc_0/a_1000_n1450#" "adc_0/GRAY_INx6x" -0.506943
-cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.029255
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0372119
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx3x" -0.00316169
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.64121
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.119647
-cap "adc_0/a_1100_n1450#" "adc_0/OUTx5x" 3.77589
-cap "adc_0/a_1000_n1450#" "adc_0/BIAS1" 3.91615
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.42532
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0353042
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.134469
-cap "adc_0/OUTx2x" "adc_0/a_1000_n1450#" 0.00697881
-cap "adc_0/GRAY_INx5x" "adc_0/a_1000_n1450#" 0.4578
-cap "adc_0/a_1000_n1450#" "adc_0/BIAS2" 5.14751
-cap "adc_0/a_1000_n1450#" "adc_0/GRAY_INx4x" -0.493464
-cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.498606
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx3x" -0.0047554
-cap "adc_0/OUTx5x" "adc_0/GRAY_INx6x" 0.431919
-cap "adc_0/GND" "adc_0/OUTx5x" 12.8379
-cap "adc_0/OUTx4x" "adc_0/OUTx5x" -0.00694119
-cap "adc_0/OUTx6x" "adc_0/a_1000_n1450#" -0.0163236
-cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx6x" 1.54794
-cap "adc_0/GND" "adc_0/a_1100_n1450#" 5.26434
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/OUTx5x" 0.37756
-cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.0255662
-cap "adc_0/GRAY_INx7x" "adc_0/a_1000_n1450#" 0.803113
-cap "adc_0/OUTx4x" "adc_0/a_1100_n1450#" 4.09496
-cap "adc_0/OUTx5x" "adc_0/BIAS1" 0.670808
-cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 3.0484
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/net1" 0.832171
+cap "adc_0/a_1720_n1450#" "adc_0/V_RAMP" -2.34235
+cap "adc_0/a_1870_n1400#" "adc_0/V_RAMP" -0.868431
cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.224953
-cap "adc_0/OUTx2x" "adc_0/OUTx5x" -0.00585898
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx5x" -0.00536871
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.638007
-cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx6x" -0.170256
-cap "adc_0/OUTx5x" "adc_0/BIAS2" 1.31886
-cap "adc_0/VDD" "adc_0/OUTx0x" 40.1956
-cap "adc_0/GND" "adc_0/GRAY_INx3x" 6.31398
-cap "adc_0/GND" "adc_0/GRAY_INx6x" 11.3685
-cap "adc_0/OUTx1x" "adc_0/OUTx0x" 0.0150278
-cap "adc_0/a_1100_n1450#" "adc_0/BIAS1" 7.07985
-cap "adc_0/V_RAMP" "adc_0/a_1000_n1450#" -5.2222
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/GND" 0.0421513
-cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.690966
-cap "adc_0/OUTx4x" "adc_0/GRAY_INx6x" -0.00961801
-cap "adc_0/OUTx4x" "adc_0/GND" 22.3976
-cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx5x" 4.69768
-cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx3x" -0.173544
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx3x" 0.11361
-cap "adc_0/a_1100_n1450#" "adc_0/BIAS2" 0.578953
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx6x" 12.576
-cap "adc_0/GND" "adc_0/OUTx7x" 55.431
-cap "adc_0/V_IN" "adc_0/OUTx5x" 1.35219
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 5.39888
-cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx4x" 2.40226
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/GRAY_INx6x" 0.00628184
-cap "adc_0/GND" "8bit_sens_0/sens_amp_5/GN" 0.012717
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.012717
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
-cap "adc_0/GND" "8bit_sens_0/sens_amp_5/net1" 0.0505881
-cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29299
-cap "adc_0/OUTx4x" "adc_0/GRAY_INx0x" -0.00144721
-cap "adc_0/OUTx6x" "adc_0/OUTx5x" -0.010886
-cap "adc_0/OUTx4x" "adc_0/OUTx7x" -0.00676338
-cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.3797
-cap "adc_0/GND" "adc_0/BIAS1" 42.9459
-cap "adc_0/GRAY_INx6x" "adc_0/BIAS1" -0.0321626
-cap "adc_0/GRAY_INx3x" "adc_0/BIAS1" -0.738573
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/GRAY_INx6x" 0.0299014
-cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00940778
-cap "adc_0/GRAY_INx7x" "adc_0/OUTx5x" -0.00726852
-cap "adc_0/READ" "adc_0/a_1100_n1450#" 4.37015
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx6x" -0.00838425
-cap "adc_0/OUTx2x" "adc_0/GND" 9.38513
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx3x" -9.44
-cap "adc_0/OUTx4x" "adc_0/BIAS1" -0.156277
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx6x" -0.32439
-cap "adc_0/GRAY_INx3x" "adc_0/BIAS2" 0.708909
-cap "adc_0/GND" "adc_0/GRAY_INx5x" 18.3809
-cap "adc_0/GND" "adc_0/BIAS2" 5.08116
-cap "adc_0/GRAY_INx6x" "adc_0/BIAS2" 2.15791
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0306163
-cap "adc_0/OUTx7x" "adc_0/BIAS1" 14.3381
-cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx3x" -0.221482
-cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx6x" -4.35655
-cap "adc_0/a_1100_n1450#" "adc_0/OUTx3x" 0.42129
-cap "adc_0/GND" "adc_0/GRAY_INx4x" 4.91741
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.100669
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/BIAS2" 0.165584
-cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx7x" 0.979723
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.09615
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 9.77621
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx0x" -0.00249368
-cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.00529229
-cap "adc_0/OUTx4x" "adc_0/BIAS2" 1.43092
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx0x" -0.119988
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx5x" 0.163627
-cap "adc_0/OUTx4x" "adc_0/GRAY_INx4x" -0.00656107
-cap "adc_0/OUTx7x" "adc_0/BIAS2" 8.42633
-cap "adc_0/GRAY_INx0x" "adc_0/BIAS2" -0.000422549
-cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0015652
-cap "adc_0/V_RAMP" "adc_0/OUTx5x" -0.334144
-cap "adc_0/V_IN" "adc_0/GRAY_INx6x" 1.67684
-cap "adc_0/V_IN" "adc_0/GND" 12.3007
-cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.887439
-cap "adc_0/READ" "adc_0/GRAY_INx6x" 0.0427375
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.339041
-cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3114
-cap "adc_0/READ" "adc_0/GND" 1.81993
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/BIAS2" 0.00135237
-cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.35102
-cap "adc_0/GND" "adc_0/OUTx6x" -0.0988091
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx6x" 0.0718316
-cap "adc_0/OUTx2x" "adc_0/BIAS1" -2.97995
-cap "adc_0/GRAY_INx5x" "adc_0/BIAS1" 0.142296
-cap "adc_0/BIAS2" "adc_0/BIAS1" 7.02243
-cap "adc_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.276916
-cap "adc_0/OUTx3x" "adc_0/GRAY_INx3x" -0.00536871
-cap "adc_0/V_IN" "adc_0/OUTx7x" 1.95822
-cap "adc_0/GND" "adc_0/OUTx3x" 3.24878
-cap "adc_0/READ" "adc_0/OUTx7x" -1.22611
-cap "adc_0/GRAY_INx4x" "adc_0/BIAS1" 0.205244
-cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx6x" -0.456465
-cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3603
-cap "adc_0/GND" "adc_0/GRAY_INx7x" 32.8055
-cap "adc_0/V_IN" "8bit_sens_0/sens_amp_3/GN" 0.0093189
-cap "adc_0/OUTx2x" "adc_0/BIAS2" 1.03207
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/BIAS1" 1.75346
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx0x" 0.00185566
-cap "adc_0/OUTx7x" "adc_0/OUTx6x" -2.31355
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx3x" -0.247084
-cap "adc_0/GRAY_INx5x" "adc_0/BIAS2" 1.10186
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx4x" -0.0105103
-cap "adc_0/GRAY_INx2x" "adc_0/GND" 2.71802
-cap "adc_0/OUTx4x" "adc_0/OUTx3x" -0.00683876
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx4x" -0.44335
-cap "adc_0/GRAY_INx4x" "adc_0/BIAS2" 1.43604
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_4/GN" 0.165875
-cap "adc_0/V_IN" "adc_0/BIAS1" -1.6388
-cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx0x" -0.0156495
-cap "adc_0/OUTx7x" "adc_0/GRAY_INx7x" -1.79215
-cap "adc_0/READ" "adc_0/BIAS1" 0.0964531
-cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 3.2382
-cap "adc_0/OUTx4x" "adc_0/GRAY_INx2x" -0.00527605
-cap "adc_0/a_1870_n1400#" "adc_0/GRAY_INx3x" -0.0350848
-cap "adc_0/GND" "adc_0/a_1870_n1400#" 0.000155045
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx0x" -3.21709
-cap "adc_0/OUTx6x" "adc_0/BIAS1" 13.2975
-cap "adc_0/V_IN" "adc_0/BIAS2" 0.000833376
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx3x" -2.85436
-cap "adc_0/V_RAMP" "adc_0/GND" 0.311667
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx6x" -1.15454
-cap "8bit_sens_0/sens_amp_4/GN" "adc_0/BIAS1" 0.223684
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
-cap "adc_0/OUTx3x" "adc_0/BIAS1" -0.0236294
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.85889
-cap "adc_0/GRAY_INx7x" "adc_0/BIAS1" 0.109954
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6831
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx6x" 3.4409
-cap "adc_0/a_1720_n1450#" "adc_0/GRAY_INx3x" -0.112858
-cap "adc_0/a_1720_n1450#" "adc_0/GND" 0.0869556
-cap "adc_0/OUTx6x" "adc_0/BIAS2" -0.179115
-cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 3.93029
-cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.7696
-cap "adc_0/OUTx4x" "adc_0/V_RAMP" 0.443272
-cap "adc_0/OUTx2x" "adc_0/OUTx3x" -0.00787517
-cap "adc_0/GRAY_INx2x" "adc_0/BIAS1" -0.303442
-cap "adc_0/OUTx6x" "adc_0/GRAY_INx4x" 0.0948886
-cap "adc_0/GRAY_INx5x" "adc_0/OUTx3x" -0.0081548
-cap "adc_0/V_RAMP" "adc_0/OUTx7x" 11.1757
-cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx7x" -3.14667
-cap "adc_0/OUTx3x" "adc_0/BIAS2" 0.533499
-cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.09042
-cap "adc_0/GRAY_INx7x" "adc_0/BIAS2" 1.538
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0358097
-cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.830997
-cap "adc_0/READ" "adc_0/V_IN" 0.839431
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
-cap "adc_0/OUTx2x" "adc_0/GRAY_INx2x" -0.00656107
-cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx4x" -0.102108
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx5x" -0.2044
-cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.574617
-cap "adc_0/a_1870_n1400#" "adc_0/BIAS1" 0.0626166
-cap "adc_0/GRAY_INx2x" "adc_0/BIAS2" 1.09507
-cap "8bit_sens_0/sens_amp_3/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.08216
-cap "8bit_sens_0/sens_amp_5/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.361432
-cap "adc_0/V_IN" "adc_0/OUTx6x" 3.83505
-cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.616512
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx4x" -3.95949
-cap "adc_0/V_RAMP" "adc_0/BIAS1" -664.117
-cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.106864
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS1" 11.1342
-cap "8bit_sens_0/sens_amp_3/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.301637
-cap "adc_0/V_IN" "adc_0/GRAY_INx7x" 4.313
-cap "adc_0/OUTx2x" "adc_0/a_1870_n1400#" 0.190204
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.52405
-cap "adc_0/READ" "adc_0/GRAY_INx7x" -1.02775
-cap "adc_0/a_1720_n1450#" "adc_0/BIAS1" 0.488532
-cap "adc_0/a_1870_n1400#" "adc_0/BIAS2" 0.15769
-cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.82752
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx5x" -2.06275
-cap "adc_0/OUTx3x" "adc_0/OUTx6x" -0.00664346
-cap "adc_0/GRAY_INx7x" "adc_0/OUTx6x" -0.665321
-cap "adc_0/V_RAMP" "adc_0/BIAS2" 3.36643
-cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.27281
-cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.93195
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.14728
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx4x" -2.15318
-cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.189804
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS2" -0.315697
+cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.78091
+cap "adc_0/OUTx6x" "adc_0/OUTx1x" -0.00239261
+cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.4409
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx5x" 2.93195
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/GN" 1.08216
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/OUTx2x" 0.498606
+cap "adc_0/OUTx6x" "adc_0/a_1000_n1450#" -0.0163236
cap "adc_0/GRAY_INx2x" "adc_0/OUTx6x" 0.0583673
-cap "adc_0/OUTx3x" "adc_0/GRAY_INx7x" -0.00626754
-cap "adc_0/a_1720_n1450#" "adc_0/BIAS2" 0.636786
-cap "adc_0/GRAY_INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.0844
-cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.385079
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.53528
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.14469
-cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx7x" -0.0728974
-cap "adc_0/V_IN" "adc_0/V_RAMP" 0.485135
-cap "adc_0/READ" "adc_0/V_RAMP" 0.0142196
-cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.10722
-cap "adc_0/OUTx6x" "adc_0/a_1870_n1400#" -0.000808123
+cap "adc_0/OUTx2x" "adc_0/OUTx1x" -0.00404213
+cap "adc_0/GRAY_INx4x" "adc_0/BIAS2" 1.43604
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx1x" -0.00316169
+cap "adc_0/GRAY_INx4x" "adc_0/VDD" 3.58556
+cap "adc_0/OUTx3x" "adc_0/a_1000_n1450#" 0.0255662
+cap "adc_0/BIAS1" "adc_0/OUTx1x" 0.117885
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx0x" -3.21709
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.53528
+cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx3x" -0.173544
+cap "adc_0/V_IN" "adc_0/OUTx6x" 3.83505
+cap "adc_0/GND" "adc_0/OUTx6x" -0.0988091
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx3x" -0.00536871
cap "adc_0/OUTx5x" "adc_0/OUTx0x" -0.00458679
-cap "adc_0/READ" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.77255
-cap "adc_0/V_RAMP" "adc_0/OUTx6x" 7.77541
-cap "adc_0/VDD" "adc_0/GRAY_INx1x" 68.1305
-cap "adc_0/GRAY_INx0x" "adc_0/GND" -0.0424416
-cap "adc_0/VDD" "adc_0/a_1870_n1400#" 14.0906
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx4x" -0.00159611
-cap "adc_0/OUTx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -9.4198e-05
-cap "adc_0/GND" "adc_0/VDD" 7.25567
-cap "adc_0/BIAS1" "adc_0/OUTx1x" 7.08287
-cap "adc_0/VDD" "adc_0/OUTx4x" 0.0069177
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 11.1423
-cap "adc_0/GRAY_INx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.87334
-cap "adc_0/a_1870_n1400#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00247492
-cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx7x" -0.0198035
-cap "adc_0/GRAY_INx0x" "adc_0/BIAS2" 4.54572
-cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0870435
-cap "adc_0/GRAY_INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000349614
+cap "adc_0/OUTx2x" "adc_0/a_1000_n1450#" 0.00697881
+cap "adc_0/GRAY_INx4x" "adc_0/V_RAMP" -2.15318
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_5/net1" 0.134469
+cap "adc_0/a_1100_n1450#" "adc_0/OUTx5x" 3.77589
+cap "adc_0/GRAY_INx2x" "adc_0/OUTx2x" -0.00656107
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/VDD" 0.0927804
+cap "adc_0/OUTx4x" "adc_0/BIAS2" 1.43092
+cap "8bit_sens_0/sens_amp_4/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.165875
+cap "adc_0/BIAS1" "adc_0/a_1000_n1450#" 3.91615
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14728
+cap "adc_0/OUTx4x" "adc_0/VDD" 28.2314
+cap "adc_0/GND" "adc_0/OUTx3x" 3.24878
+cap "adc_0/GRAY_INx2x" "adc_0/BIAS1" -0.303442
+cap "adc_0/BIAS1" "adc_0/GRAY_INx3x" -0.738573
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx0x" -0.00564446
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_sens_0/sens_amp_2/net1" 0.481951
+cap "adc_0/GND" "adc_0/OUTx2x" 9.38513
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_RAMP" 0.106864
+cap "adc_0/BIAS1" "adc_0/V_IN" -1.6388
+cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx7x" 0.979723
+cap "adc_0/OUTx4x" "adc_0/V_RAMP" 0.443272
+cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.690966
+cap "adc_0/GRAY_INx6x" "adc_0/a_1100_n1450#" 1.54794
+cap "adc_0/READ" "adc_0/V_IN" 0.839431
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx1x" 0.412947
+cap "adc_0/GND" "adc_0/BIAS1" 42.9459
+cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx5x" 4.69768
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx7x" -1.79215
+cap "adc_0/GND" "adc_0/READ" 1.81993
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx7x" 12.576
+cap "adc_0/GRAY_INx5x" "adc_0/OUTx7x" 0.163627
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/GN" 0.100669
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.42532
+cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.616512
+cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.3797
+cap "adc_0/GRAY_INx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.01736
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.237223
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx3x" 2.85889
+cap "adc_0/GND" "8bit_sens_0/sens_amp_5/net1" 0.0505881
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_IN" 4.10722
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6831
+cap "adc_0/OUTx6x" "adc_0/BIAS2" -0.179115
+cap "adc_0/OUTx4x" "adc_0/GRAY_INx4x" -0.00656107
+cap "adc_0/VDD" "adc_0/OUTx6x" 26.5805
+cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0150278
+cap "adc_0/GRAY_INx0x" "adc_0/BIAS2" -0.000422549
+cap "adc_0/GND" "8bit_sens_0/sens_amp_5/GN" 0.012717
+cap "adc_0/GRAY_INx0x" "adc_0/VDD" -0.000468515
+cap "adc_0/OUTx3x" "adc_0/BIAS2" 0.533499
+cap "adc_0/OUTx3x" "adc_0/VDD" 20.9427
+cap "adc_0/OUTx7x" "adc_0/OUTx1x" -0.383333
+cap "adc_0/OUTx6x" "adc_0/V_RAMP" 7.77541
+cap "adc_0/OUTx2x" "adc_0/BIAS2" 1.03207
+cap "adc_0/OUTx2x" "adc_0/VDD" 35.095
+cap "adc_0/GRAY_INx2x" "adc_0/OUTx0x" -0.0102886
+cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.0120092
+cap "adc_0/a_1720_n1450#" "adc_0/OUTx6x" -0.0039073
+cap "adc_0/BIAS1" "adc_0/BIAS2" 7.02243
+cap "adc_0/GND" "8bit_sens_0/sens_amp_6/GN" 0.0421513
+cap "adc_0/OUTx3x" "adc_0/V_RAMP" -1.22185
+cap "adc_0/a_1870_n1400#" "adc_0/OUTx6x" -0.000808123
+cap "adc_0/BIAS1" "adc_0/VDD" -1.63654
+cap "adc_0/READ" "adc_0/VDD" 2.66143
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx7x" -0.00726852
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx5x" 0.431919
+cap "adc_0/OUTx2x" "adc_0/V_RAMP" -0.82752
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx5x" -0.00536871
+cap "adc_0/OUTx3x" "adc_0/a_1720_n1450#" 0.0324566
+cap "adc_0/GND" "adc_0/OUTx0x" 0.328734
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx7x" 0.11361
+cap "adc_0/BIAS1" "adc_0/V_RAMP" -664.117
+cap "adc_0/GND" "adc_0/a_1100_n1450#" 5.26434
+cap "adc_0/READ" "adc_0/V_RAMP" 0.0142196
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.09615
+cap "adc_0/V_IN" "adc_0/OUTx7x" 1.95822
+cap "adc_0/OUTx2x" "adc_0/a_1720_n1450#" 0.189804
+cap "adc_0/a_1870_n1400#" "adc_0/OUTx2x" 0.190204
+cap "adc_0/GND" "adc_0/OUTx7x" 55.431
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx7x" -0.456465
+cap "adc_0/BIAS1" "adc_0/a_1720_n1450#" 0.488532
+cap "8bit_sens_0/sens_amp_5/net1" "adc_0/BIAS2" 0.00135237
+cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx5x" -3.14667
+cap "adc_0/a_1870_n1400#" "adc_0/BIAS1" 0.0626166
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx5x" -0.32439
+cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/GN" 0.00628184
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.53528
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS2" -0.315697
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_IN" 3.93029
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 9.77621
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 122.325
+cap "adc_0/GRAY_INx4x" "adc_0/OUTx6x" 0.0948886
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_RAMP" 0.774957
+cap "adc_0/BIAS1" "8bit_sens_0/sens_amp_4/GN" 0.223684
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/BIAS2" 0.339041
+cap "adc_0/GRAY_INx4x" "adc_0/OUTx2x" -0.0105103
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 1.14728
+cap "adc_0/GRAY_INx4x" "adc_0/BIAS1" 0.205244
+cap "adc_0/OUTx4x" "adc_0/GRAY_INx0x" -0.00144721
+cap "adc_0/OUTx3x" "adc_0/OUTx4x" -0.00683876
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/BIAS2" 0.165584
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx1x" -0.00217775
+cap "adc_0/OUTx5x" "adc_0/a_1000_n1450#" 0.0876459
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/BIAS1" 0.887439
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx1x" -0.045179
+cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.098673
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_4/GN" 0.521457
+cap "adc_0/GRAY_INx5x" "adc_0/OUTx1x" 0.0397904
+cap "adc_0/OUTx4x" "adc_0/BIAS1" -0.156277
+cap "adc_0/OUTx0x" "adc_0/VDD" 40.1956
+cap "adc_0/OUTx5x" "adc_0/GRAY_INx3x" -0.0047554
+cap "adc_0/a_1100_n1450#" "adc_0/BIAS2" 0.578953
+cap "adc_0/a_1100_n1450#" "adc_0/VDD" 23.3587
+cap "adc_0/OUTx7x" "adc_0/BIAS2" 8.42633
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0932343
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx1x" -0.0388247
+cap "adc_0/GND" "8bit_sens_0/sens_amp_2/net1" 0.00864429
+cap "adc_0/OUTx5x" "adc_0/V_IN" 1.35219
+cap "adc_0/GRAY_INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.0844
+cap "adc_0/VDD" "adc_0/OUTx7x" 38.4304
+cap "adc_0/OUTx0x" "adc_0/V_RAMP" -1.81075
+cap "adc_0/GRAY_INx7x" "adc_0/a_1000_n1450#" 0.803113
+cap "adc_0/GND" "adc_0/OUTx5x" 12.8379
+cap "adc_0/GRAY_INx6x" "adc_0/a_1000_n1450#" -0.506943
+cap "adc_0/GRAY_INx5x" "adc_0/a_1000_n1450#" 0.4578
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx7x" -0.0728974
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx3x" -0.170256
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx5x" -0.2044
+cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx5x" -9.44
+cap "adc_0/OUTx7x" "adc_0/V_RAMP" 11.1757
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 10.1777
+cap "adc_0/GND" "8bit_sens_0/sens_amp_4/net1" 0.0238539
+cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0347412
+cap "adc_0/GRAY_INx7x" "adc_0/V_IN" 4.313
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.322553
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.52405
+cap "adc_0/GRAY_INx6x" "adc_0/V_IN" 1.67684
+cap "adc_0/GND" "adc_0/GRAY_INx7x" 32.8055
+cap "adc_0/GND" "adc_0/GRAY_INx6x" 11.3685
+cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.09042
+cap "8bit_sens_0/sens_amp_3/GN" "adc_0/V_IN" 0.0093189
+cap "adc_0/GND" "adc_0/GRAY_INx5x" 18.3809
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/GN" 0.012717
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_3/net1" 0.301637
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/V_RAMP" 0.385079
+cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 3.0484
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx6x" 0.00185566
+cap "adc_0/OUTx3x" "adc_0/OUTx6x" -0.00664346
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0306163
+cap "adc_0/GRAY_INx4x" "adc_0/OUTx0x" -0.0090045
+cap "adc_0/BIAS1" "adc_0/OUTx6x" 13.2975
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx2x" -0.00249368
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/GRAY_INx3x" -0.0372119
+cap "adc_0/a_1100_n1450#" "adc_0/GRAY_INx4x" 2.40226
+cap "adc_0/OUTx3x" "adc_0/OUTx2x" -0.00787517
+cap "adc_0/OUTx3x" "adc_0/BIAS1" -0.0236294
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.64121
+cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 2.125
+cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0514982
+cap "adc_0/BIAS1" "adc_0/OUTx2x" -2.97995
+cap "adc_0/OUTx5x" "adc_0/BIAS2" 1.31886
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.119647
+cap "adc_0/OUTx5x" "adc_0/VDD" 21.2422
+cap "adc_0/OUTx4x" "adc_0/a_1100_n1450#" 4.09496
+cap "adc_0/GND" "adc_0/OUTx1x" 0.00175627
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx3x" -4.72
+cap "adc_0/BIAS1" "adc_0/READ" 0.0964531
+cap "adc_0/OUTx4x" "adc_0/OUTx7x" -0.00676338
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx6x" -2.46916
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx3x" -0.247084
+cap "adc_0/OUTx5x" "adc_0/V_RAMP" -0.334144
+cap "adc_0/GRAY_INx7x" "adc_0/BIAS2" 1.538
+cap "adc_0/GRAY_INx6x" "adc_0/BIAS2" 2.15791
+cap "adc_0/GND" "adc_0/a_1000_n1450#" 0.621255
+cap "adc_0/GRAY_INx5x" "adc_0/BIAS2" 1.10186
+cap "adc_0/GRAY_INx7x" "adc_0/VDD" 6.37109
+cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.83413
+cap "adc_0/GRAY_INx6x" "adc_0/VDD" -5.94381
+cap "adc_0/VDD" "adc_0/GRAY_INx5x" -4.67059
+cap "adc_0/GND" "adc_0/GRAY_INx2x" 2.71802
+cap "adc_0/GND" "adc_0/GRAY_INx3x" 6.31398
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx2x" 6.27281
+cap "adc_0/GRAY_INx7x" "adc_0/V_RAMP" -1.4115
+cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.37756
+cap "adc_0/GND" "adc_0/V_IN" 12.3007
+cap "adc_0/GRAY_INx6x" "adc_0/V_RAMP" -1.15454
+cap "adc_0/GRAY_INx5x" "adc_0/V_RAMP" -2.06275
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS1" 11.1342
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/READ" 1.77255
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 8.42068
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0353042
+cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0015652
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_5/net1" 0.361432
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 13.7358
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" -0.00309223
+cap "adc_0/OUTx6x" "adc_0/OUTx7x" -2.31355
+cap "adc_0/OUTx3x" "adc_0/OUTx0x" -0.00585898
+cap "adc_0/BIAS2" "adc_0/OUTx1x" 0.0461409
+cap "adc_0/OUTx3x" "adc_0/a_1100_n1450#" 0.42129
+cap "adc_0/VDD" "adc_0/OUTx1x" 4.43665
+cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx7x" -0.102108
+cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx4x" -4.35655
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx6x" 0.0358097
+cap "adc_0/OUTx4x" "adc_0/OUTx5x" -0.00694119
+cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx5x" -0.44335
+cap "adc_0/GRAY_INx1x" "adc_0/BIAS2" -0.000416707
+cap "adc_0/BIAS1" "adc_0/OUTx0x" -0.076852
+cap "adc_0/GRAY_INx1x" "adc_0/VDD" -0.000655092
+cap "8bit_sens_0/sens_amp_5/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.574617
+cap "adc_0/V_RAMP" "adc_0/OUTx1x" -0.33173
+cap "adc_0/a_1000_n1450#" "adc_0/BIAS2" 5.14751
+cap "adc_0/OUTx2x" "adc_0/OUTx7x" -0.00529229
+cap "adc_0/a_1100_n1450#" "adc_0/BIAS1" 7.07985
+cap "adc_0/VDD" "adc_0/a_1000_n1450#" 67.3169
+cap "adc_0/a_1100_n1450#" "adc_0/READ" 4.37015
+cap "adc_0/GRAY_INx2x" "adc_0/BIAS2" 1.09507
+cap "adc_0/BIAS1" "adc_0/OUTx7x" 14.3381
+cap "adc_0/GRAY_INx3x" "adc_0/BIAS2" 0.708909
+cap "adc_0/READ" "adc_0/OUTx7x" -1.22611
+cap "adc_0/GRAY_INx2x" "adc_0/VDD" 2.98684
+cap "adc_0/VDD" "adc_0/GRAY_INx3x" 1.52812
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx4x" -0.00961801
+cap "adc_0/V_IN" "adc_0/BIAS2" 0.000833376
+cap "adc_0/V_RAMP" "adc_0/a_1000_n1450#" -5.2222
+cap "adc_0/GRAY_INx6x" "8bit_sens_0/sens_amp_3/net1" 0.0299014
+cap "adc_0/GND" "adc_0/BIAS2" 5.08116
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.638007
+cap "8bit_sens_0/sens_amp_6/GN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.7696
+cap "adc_0/VDD" "adc_0/V_IN" 20.226
+cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.75346
+cap "adc_0/GRAY_INx2x" "adc_0/V_RAMP" -2.59343
+cap "adc_0/GND" "adc_0/VDD" 34.8106
+cap "adc_0/GRAY_INx3x" "adc_0/V_RAMP" -2.85436
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 3.05952
+cap "adc_0/V_IN" "adc_0/V_RAMP" 0.485135
+cap "adc_0/GND" "adc_0/V_RAMP" 0.311667
+cap "adc_0/GRAY_INx2x" "adc_0/a_1720_n1450#" -0.374624
+cap "adc_0/a_1720_n1450#" "adc_0/GRAY_INx3x" -0.112858
+cap "adc_0/a_1870_n1400#" "adc_0/GRAY_INx2x" -0.258898
+cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3603
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.53528
+cap "adc_0/a_1870_n1400#" "adc_0/GRAY_INx3x" -0.0350848
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0797386
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx7x" 0.830997
+cap "adc_0/GND" "adc_0/a_1720_n1450#" 0.0869556
+cap "adc_0/GND" "adc_0/a_1870_n1400#" 0.000155045
+cap "adc_0/GND" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 5.39888
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.14469
+cap "adc_0/OUTx5x" "adc_0/OUTx6x" -0.010886
+cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx1x" -0.0747682
+cap "adc_0/GRAY_INx4x" "adc_0/a_1000_n1450#" -0.493464
+cap "adc_0/OUTx4x" "adc_0/OUTx1x" -0.00278335
+cap "adc_0/GND" "8bit_sens_0/sens_amp_4/GN" 0.276916
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx4x" -3.95949
+cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx3x" -0.221482
+cap "adc_0/GRAY_INx7x" "adc_0/OUTx6x" -0.665321
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx6x" 0.0718316
+cap "adc_0/OUTx5x" "adc_0/OUTx2x" -0.00585898
+cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx7x" -0.0156495
+cap "adc_0/GND" "adc_0/GRAY_INx4x" 4.91741
+cap "adc_0/OUTx5x" "adc_0/BIAS1" 0.670808
+cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx5x" -0.119988
+cap "adc_0/OUTx4x" "adc_0/a_1000_n1450#" 0.029255
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx7x" -0.00626754
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx5x" -0.0081548
+cap "adc_0/OUTx0x" "adc_0/OUTx7x" -0.00287057
+cap "adc_0/OUTx4x" "adc_0/GRAY_INx2x" -0.00527605
+cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29299
+cap "adc_0/VDD" "adc_0/BIAS2" 27.9299
+cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0932343
+cap "adc_0/GRAY_INx6x" "adc_0/OUTx2x" -0.00838425
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "adc_0/V_IN" 3.2382
+cap "adc_0/GND" "8bit_sens_0/sens_amp_6/net1" 0.0116736
+cap "adc_0/GRAY_INx7x" "adc_0/BIAS1" 0.109954
+cap "adc_0/GRAY_INx6x" "adc_0/BIAS1" -0.0321626
+cap "adc_0/GRAY_INx7x" "adc_0/READ" -1.02775
+cap "adc_0/GND" "adc_0/OUTx4x" 22.3976
+cap "adc_0/GRAY_INx6x" "adc_0/READ" 0.0427375
+cap "adc_0/V_RAMP" "adc_0/BIAS2" 3.36643
+cap "adc_0/BIAS1" "adc_0/GRAY_INx5x" 0.142296
+cap "adc_0/GND" "8bit_sens_0/sens_amp_3/net1" 0.00940778
+cap "adc_0/VDD" "adc_0/V_RAMP" -73.6423
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_2/net1" 0.779593
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "adc_0/OUTx7x" -0.35102
+cap "adc_0/a_1720_n1450#" "adc_0/BIAS2" 0.636786
+cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.3114
+cap "adc_0/a_1870_n1400#" "adc_0/BIAS2" 0.15769
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "adc_0/VDD" 0.321641
cap "adc_0/BIAS2" "adc_0/VDD" 10.1046
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx2x" -0.124801
-cap "adc_0/OUTx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000240055
-cap "adc_0/GRAY_INx0x" "adc_0/BIAS1" 10.405
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.102219
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx1x" 3.62037
-cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx1x" -4.72
-cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.82764
-cap "adc_0/GRAY_INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00015116
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.792228
-cap "adc_0/BIAS1" "adc_0/VDD" -14.9879
-cap "adc_0/OUTx1x" "adc_0/VDD" 37.931
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS2" 2.38282
-cap "adc_0/OUTx0x" "adc_0/a_1870_n1400#" 0.0383805
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0957691
-cap "adc_0/OUTx0x" "adc_0/GND" 0.0136061
-cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 12.1482
-cap "adc_0/a_1100_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00171971
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.00111014
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.60045
-cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0796942
-cap "adc_0/OUTx3x" "adc_0/GRAY_INx1x" -0.00159371
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS1" 1.62116
-cap "adc_0/OUTx1x" "adc_0/OUTx2x" -0.00411871
-cap "adc_0/GRAY_INx0x" "adc_0/VDD" 7.91641
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx2x" 2.125
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx1x" -3.30576
-cap "adc_0/OUTx0x" "adc_0/BIAS2" 0.582774
-cap "adc_0/V_RAMP" "adc_0/a_1870_n1400#" -0.138808
-cap "adc_0/GRAY_INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000211158
-cap "adc_0/GRAY_INx3x" "adc_0/OUTx1x" 0.0289899
-cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.37088
-cap "adc_0/OUTx0x" "adc_0/BIAS1" -0.19389
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 131.301
-cap "adc_0/OUTx0x" "adc_0/OUTx1x" 0.0267024
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx2x" -0.00278237
-cap "adc_0/GRAY_INx1x" "adc_0/OUTx7x" 0.031177
-cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx2x" -3.21709
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 0.611897
-cap "adc_0/VDD" "adc_0/OUTx2x" 0.106822
-cap "adc_0/VDD" "adc_0/GRAY_INx2x" 0.914055
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" 0.0222222
-cap "adc_0/a_1720_n1450#" "adc_0/VDD" 1.32721
-cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx0x" -0.232955
-cap "adc_0/OUTx1x" "adc_0/OUTx6x" -0.0244687
-cap "adc_0/GND" "adc_0/GRAY_INx1x" -0.0298699
-cap "adc_0/V_RAMP" "adc_0/BIAS1" -168.6
-cap "adc_0/OUTx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000368924
-cap "adc_0/GRAY_INx3x" "adc_0/VDD" 1.0876
-cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx1x" -0.0970765
-cap "adc_0/OUTx0x" "adc_0/GRAY_INx0x" 0.0964878
-cap "adc_0/V_RAMP" "adc_0/OUTx1x" -1.84773
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx1x" -0.341106
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx2x" -0.000439698
-cap "adc_0/a_1720_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00188537
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.920638
cap "adc_0/OUTx0x" "adc_0/VDD" 1.7365
-cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx5x" -0.159847
-cap "adc_0/BIAS2" "adc_0/GRAY_INx1x" 5.16337
-cap "adc_0/GRAY_INx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00040454
-cap "adc_0/BIAS2" "adc_0/a_1870_n1400#" 0.314414
-cap "adc_0/GRAY_INx0x" "adc_0/OUTx6x" 0.00169993
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00254282
-cap "adc_0/VDD" "adc_0/GRAY_INx5x" 0.0207213
-cap "adc_0/BIAS2" "adc_0/GND" 0.0418438
-cap "adc_0/OUTx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 2.54482
cap "adc_0/OUTx1x" "adc_0/OUTx7x" -0.383333
-cap "adc_0/OUTx3x" "adc_0/VDD" 0.10052
-cap "adc_0/a_1000_n1450#" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000739431
-cap "8bit_sens_0/sens_amp_6/net1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0887912
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx0x" -6.4132
-cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/BIAS2" 3.22123
-cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000607848
-cap "adc_0/BIAS1" "adc_0/GRAY_INx1x" 11.739
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx1x" 0.0740505
-cap "adc_0/BIAS1" "adc_0/a_1870_n1400#" 2.43712
-cap "adc_0/V_RAMP" "adc_0/VDD" 41.8575
-cap "adc_0/OUTx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000222031
-cap "adc_0/OUTx1x" "adc_0/a_1870_n1400#" 0.351124
-cap "adc_0/GRAY_INx5x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000305267
-cap "8bit_sens_0/sens_amp_7/net1" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.211299
-cap "adc_0/OUTx3x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000309981
-cap "adc_0/BIAS1" "adc_0/GND" 1.189
-cap "adc_0/OUTx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000249469
-cap "adc_0/OUTx1x" "adc_0/GND" 0.0702307
-cap "adc_0/BIAS1" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.71877
+cap "adc_0/GRAY_INx3x" "adc_0/GRAY_INx0x" -0.232955
+cap "adc_0/a_1720_n1450#" "adc_0/VDD" 1.32721
+cap "adc_0/BIAS2" "adc_0/OUTx0x" 0.582774
+cap "adc_0/OUTx6x" "adc_0/GRAY_INx0x" 0.00169993
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx1x" 2.60045
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/V_RAMP" 0.00533453
+cap "adc_0/OUTx3x" "adc_0/GRAY_INx1x" -0.00159371
+cap "adc_0/GRAY_INx2x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000439698
+cap "adc_0/GRAY_INx0x" "adc_0/BIAS1" 10.405
+cap "adc_0/OUTx1x" "adc_0/OUTx2x" -0.00411871
+cap "adc_0/GND" "adc_0/BIAS1" 1.189
+cap "8bit_sens_0/sens_amp_6/net1" "adc_0/GND" 0.00254282
+cap "adc_0/GRAY_INx1x" "adc_0/OUTx5x" -0.00111014
cap "adc_0/OUTx1x" "adc_0/OUTx4x" -0.00277148
-cap "adc_0/V_RAMP" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.00533453
-cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.648694
-cap "adc_0/VDD" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.321641
-cap "adc_0/BIAS2" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.54716
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx3x" -0.00040454
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx6x" -0.000249469
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS1" 12.1482
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_6/net1" 0.102219
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx1x" 0.0740505
+cap "adc_0/V_RAMP" "adc_0/GRAY_INx1x" -3.30576
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx6x" -0.000211158
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx1x" -0.124801
+cap "adc_0/V_IN" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000607848
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx4x" -0.000349614
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx3x" -4.72
+cap "adc_0/GRAY_INx5x" "adc_0/GRAY_INx0x" -0.159847
+cap "adc_0/GRAY_INx0x" "adc_0/VDD" 7.91641
+cap "adc_0/GRAY_INx1x" "adc_0/BIAS1" 11.739
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/a_1870_n1400#" -0.00247492
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx0x" 0.0964878
+cap "adc_0/BIAS2" "adc_0/GRAY_INx0x" 4.54572
+cap "adc_0/GND" "adc_0/VDD" 7.25567
+cap "adc_0/GND" "adc_0/OUTx0x" 0.0136061
+cap "adc_0/GND" "adc_0/BIAS2" 0.0418438
cap "adc_0/GRAY_INx6x" "adc_0/GRAY_INx1x" -0.0561326
-cap "adc_0/BIAS1" "adc_0/BIAS2" 2.29663
-cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.0468572
-cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx1x" -0.648975
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/GN" 0.920638
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/a_1100_n1450#" -0.00171971
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx5x" -0.000305267
+cap "adc_0/GRAY_INx7x" "adc_0/GRAY_INx0x" -0.0198035
+cap "adc_0/GRAY_INx4x" "adc_0/GRAY_INx1x" -0.0970765
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 131.301
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/VDD" 0.792228
+cap "adc_0/OUTx1x" "adc_0/V_RAMP" -1.84773
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/BIAS2" 0.54716
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/BIAS2" 5.82764
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx0x" 2.54482
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/GRAY_INx1x" -0.341106
+cap "adc_0/GRAY_INx2x" "adc_0/OUTx1x" 2.125
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/a_1720_n1450#" -0.00188537
+cap "adc_0/OUTx2x" "adc_0/VDD" 0.106822
+cap "adc_0/OUTx4x" "adc_0/VDD" 0.0069177
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx3x" 0.0289899
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx7x" -0.00015116
+cap "adc_0/OUTx1x" "adc_0/OUTx6x" -0.0244687
+cap "adc_0/OUTx1x" "adc_0/BIAS1" 7.08287
+cap "adc_0/GRAY_INx1x" "adc_0/VDD" 68.1305
+cap "adc_0/V_RAMP" "adc_0/BIAS1" -168.6
+cap "adc_0/BIAS2" "adc_0/GRAY_INx1x" 5.16337
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_sens_0/sens_amp_7/net1" 0.211299
+cap "adc_0/GND" "adc_0/GRAY_INx0x" -0.0424416
+cap "adc_0/OUTx1x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.648694
+cap "adc_0/OUTx3x" "adc_0/VDD" 0.10052
+cap "adc_0/OUTx1x" "adc_0/a_1870_n1400#" 0.351124
+cap "adc_0/a_1870_n1400#" "adc_0/V_RAMP" -0.138808
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx0x" 4.37088
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GND" -0.0870435
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx5x" 0.0222222
+cap "adc_0/GRAY_INx0x" "adc_0/OUTx2x" -0.00278237
+cap "adc_0/OUTx1x" "adc_0/VDD" 37.931
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/BIAS1" 2.71877
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS1" 1.62116
+cap "adc_0/OUTx4x" "adc_0/GRAY_INx0x" -0.00159611
cap "adc_0/OUTx1x" "adc_0/BIAS2" 2.42069
-cap "adc_0/OUTx6x" "adc_0/VDD" 0.0650559
-cap "adc_0/V_IN" "adc_0/VDD" 0.0861568
-cap "adc_0/VDD" "adc_0/GRAY_INx2x" 0.0352946
-cap "adc_0/VDD" "adc_0/OUTx6x" 0.435178
-cap "adc_0/GRAY_INx3x" "adc_0/VDD" 0.00770497
-cap "adc_0/OUTx1x" "adc_0/VDD" 0.0891085
-cap "adc_0/OUTx4x" "adc_0/VDD" 0.345473
-cap "adc_0/V_RAMP" "adc_0/VDD" 0.744138
-cap "adc_0/GND" "adc_0/VDD" 0.0020662
-cap "adc_0/OUTx3x" "adc_0/VDD" 0.378163
-cap "adc_0/a_1870_n1400#" "adc_0/VDD" 1.9288
-cap "adc_0/VDD" "adc_0/a_1720_n1450#" 0.243918
-cap "adc_0/a_1100_n1450#" "adc_0/VDD" 0.0315693
+cap "adc_0/GRAY_INx2x" "adc_0/VDD" 0.914055
+cap "adc_0/V_RAMP" "adc_0/VDD" 41.8575
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_sens_0/sens_amp_6/net1" 0.0887912
+cap "adc_0/OUTx1x" "adc_0/OUTx0x" 0.0267024
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx7x" -9.4198e-05
+cap "adc_0/a_1870_n1400#" "adc_0/BIAS1" 2.43712
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0957691
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/a_1000_n1450#" -0.000739431
+cap "adc_0/GRAY_INx3x" "adc_0/VDD" 1.0876
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx7x" -0.0468572
+cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx0x" -0.648975
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx2x" -0.000368924
+cap "adc_0/GND" "adc_0/GRAY_INx1x" -0.0298699
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx4x" -0.000240055
+cap "adc_0/BIAS1" "adc_0/VDD" -14.9879
+cap "adc_0/BIAS2" "adc_0/BIAS1" 2.29663
+cap "adc_0/OUTx0x" "adc_0/BIAS1" -0.19389
+cap "adc_0/OUTx7x" "adc_0/GRAY_INx1x" 0.031177
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx1x" 5.87334
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/VDD" 11.1423
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/BIAS2" 3.22123
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/VDD" 0.611897
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "adc_0/OUTx0x" 0.0796942
+cap "adc_0/8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "adc_0/BIAS2" 2.38282
+cap "adc_0/a_1870_n1400#" "adc_0/VDD" 14.0906
+cap "adc_0/a_1870_n1400#" "adc_0/BIAS2" 0.314414
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx3x" -0.000309981
+cap "adc_0/a_1870_n1400#" "adc_0/OUTx0x" 0.0383805
+cap "adc_0/OUTx1x" "adc_0/GRAY_INx0x" 3.62037
+cap "adc_0/V_RAMP" "adc_0/GRAY_INx0x" -6.4132
+cap "adc_0/OUTx1x" "adc_0/GND" 0.0702307
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/OUTx5x" -0.000222031
+cap "adc_0/GRAY_INx2x" "adc_0/GRAY_INx0x" -3.21709
+cap "adc_0/GRAY_INx5x" "adc_0/VDD" 0.0207213
+cap "adc_0/VDD" "adc_0/OUTx6x" 0.0650559
+cap "adc_0/VDD" "adc_0/V_IN" 0.0861568
+cap "adc_0/VDD" "adc_0/GND" 0.0020662
cap "adc_0/a_1000_n1450#" "adc_0/VDD" 4.26443
+cap "adc_0/VDD" "adc_0/OUTx2x" 0.10155
+cap "adc_0/VDD" "adc_0/GRAY_INx5x" 0.0184919
+cap "adc_0/VDD" "adc_0/a_1870_n1400#" 1.9288
+cap "adc_0/OUTx4x" "adc_0/VDD" 0.345473
cap "adc_0/VDD" "adc_0/BIAS1" 0.0621333
-cap "adc_0/V_IN" "adc_0/VDD" 0.177323
-cap "adc_0/GRAY_INx7x" "adc_0/VDD" 0.00511569
-cap "adc_0/OUTx2x" "adc_0/VDD" 0.10155
-cap "adc_0/GRAY_INx5x" "adc_0/VDD" 0.0184919
-cap "adc_0/V_RAMP" "adc_0/GRAY_INx0x" 1.00873
-cap "adc_0/GRAY_INx1x" "adc_0/GRAY_INx0x" 0.0130141
-cap "adc_0/BIAS1" "adc_0/VDD" -0.00247074
-cap "adc_0/BIAS1" "adc_0/GRAY_INx0x" 0.90487
-cap "adc_0/VDD" "adc_0/OUTx1x" 0.334081
-cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 0.655295
-cap "adc_0/BIAS2" "adc_0/GRAY_INx0x" 0.165109
-cap "adc_0/GRAY_INx0x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.64773
-cap "adc_0/GND" "adc_0/VDD" 0.00229578
-cap "adc_0/GRAY_INx0x" "adc_0/VDD" 66.3076
-cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.570974
+cap "adc_0/VDD" "adc_0/OUTx3x" 0.378163
+cap "adc_0/VDD" "adc_0/a_1100_n1450#" 0.0315693
+cap "adc_0/OUTx6x" "adc_0/VDD" 0.435178
+cap "adc_0/VDD" "adc_0/OUTx1x" 0.0891085
+cap "adc_0/VDD" "adc_0/GRAY_INx2x" 0.0352946
+cap "adc_0/VDD" "adc_0/V_IN" 0.177323
+cap "adc_0/VDD" "adc_0/GRAY_INx7x" 0.00511569
+cap "adc_0/VDD" "adc_0/a_1720_n1450#" 0.243918
+cap "adc_0/VDD" "adc_0/GRAY_INx3x" 0.00770497
+cap "adc_0/VDD" "adc_0/V_RAMP" 0.744138
cap "adc_0/V_RAMP" "adc_0/VDD" 0.0132055
+cap "adc_0/BIAS2" "adc_0/GRAY_INx0x" 0.165109
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/VDD" 0.655295
+cap "adc_0/GRAY_INx0x" "adc_0/BIAS1" 0.90487
+cap "adc_0/GRAY_INx0x" "adc_0/GRAY_INx1x" 0.0130141
+cap "adc_0/OUTx1x" "adc_0/VDD" 0.334081
+cap "adc_0/GRAY_INx0x" "adc_0/VDD" 66.3076
+cap "adc_0/GRAY_INx0x" "adc_0/V_RAMP" 1.00873
+cap "adc_0/BIAS1" "adc_0/VDD" -0.00247074
+cap "adc_0/a_1870_n1400#" "adc_0/VDD" 0.570974
+cap "adc_0/GND" "adc_0/VDD" 0.00229578
+cap "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "adc_0/GRAY_INx0x" 1.64773
cap "adc_0/VDD" "adc_0/GRAY_INx0x" 0.00886991
-cap "bias_cell_0/SF_IB" "bias_cell_0/GND" 0.256901
+cap "bias_cell_0/SF_IB" "bias_cell_0/VDD" 1.10134e-13
+cap "bias_cell_0/GND" "bias_cell_0/SF_IB" 0.256901
cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 6.33874
-cap "bias_cell_0/SF_IB" "bias_cell_0/GND" -140.721
-cap "bias_cell_0/GND" "bias_cell_0/NB1" 33.2328
-cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 6.25887
+cap "bias_cell_0/NB1" "bias_cell_0/GND" 33.2328
+cap "bias_cell_0/NB1" "bias_cell_0/SF_IB" 6.25887
+cap "bias_cell_0/GND" "bias_cell_0/SF_IB" -140.721
cap "bias_cell_0/NB2" "bias_cell_0/GND" 33.6137
cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" 34.4609
-cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/GND" -157.602
-cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 32.2337
-cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS1_OUT" -14.8202
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS2_OUT" -14.8202
-cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/GND" -146.696
-cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/SA_IREF_OUT" -8.93714
+cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 32.2337
+cap "bias_cell_0/GND" "bias_cell_0/BIAS2_OUT" -157.602
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -8.93714
-cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/GND" -169.728
+cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS1_OUT" -14.8202
+cap "bias_cell_0/GND" "bias_cell_0/BIAS1_OUT" -146.696
+cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/SA_IREF_OUT" -8.93714
+cap "bias_cell_0/GND" "bias_cell_0/SA_IREF_OUT" -169.728
cap "bias_cell_0/GND" "vssa2" 18.5439
-cap "bias_cell_0/GND" "vssa2" 9.56063
+cap "vssa2" "bias_cell_0/GND" 9.56063
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 4.81302
+cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 5.91555
+cap "bias_cell_0/SF_IB" "vssa2" 0.538961
cap "bias_cell_0/VDD" "bias_cell_0/GND" 0.792477
-cap "bias_cell_0/VDD" "bias_cell_0/SF_IB" 38.4234
-cap "vssa2" "bias_cell_0/SF_IB" 0.538961
-cap "bias_cell_0/NB1" "bias_cell_0/SF_IB" 5.91555
+cap "bias_cell_0/SF_IB" "bias_cell_0/VDD" 38.4234
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" 2.2669
cap "bias_cell_0/SF_IB" "bias_cell_0/GND" -37.6206
-cap "bias_cell_0/SF_IB" "vssa2" 3.22459
cap "bias_cell_0/SF_IB" "bias_cell_0/NB1" 5.55812
-cap "bias_cell_0/VDD" "vssa2" 0.0234239
-cap "bias_cell_0/VDD" "bias_cell_0/GND" -51.1204
-cap "bias_cell_0/NB2" "bias_cell_0/VDD" -4.74647
-cap "bias_cell_0/VDD" "bias_cell_0/NB1" -78.5225
-cap "bias_cell_0/GND" "bias_cell_0/NB1" 9.19156
-cap "vssa2" "bias_cell_0/NB1" 4.94416
cap "bias_cell_0/VDD" "bias_cell_0/SF_IB" 200.542
+cap "bias_cell_0/NB1" "vssa2" 4.94416
+cap "bias_cell_0/VDD" "vssa2" 0.0234239
+cap "bias_cell_0/VDD" "bias_cell_0/NB2" -4.74647
+cap "bias_cell_0/GND" "bias_cell_0/NB1" 9.19156
cap "bias_cell_0/VDD" "bias_cell_0/OUT_IB" 0.0172511
+cap "bias_cell_0/VDD" "bias_cell_0/NB1" -78.5225
+cap "bias_cell_0/VDD" "bias_cell_0/GND" -51.1204
+cap "bias_cell_0/SF_IB" "vssa2" 3.22459
cap "bias_cell_0/NB2" "vssa2" 6.07279
-cap "bias_cell_0/NB1" "bias_cell_0/OUT_IB" -1.17125
-cap "bias_cell_0/NB1" "bias_cell_0/NB2" -36.2581
-cap "bias_cell_0/GND" "bias_cell_0/NB1" 0.542014
+cap "vssa2" "bias_cell_0/NB1" 1.12863
+cap "bias_cell_0/OUT_IB" "bias_cell_0/NB1" -1.17125
cap "bias_cell_0/NB2" "bias_cell_0/OUT_IB" 10.6338
-cap "bias_cell_0/VDD" "bias_cell_0/OUT_IB" 0.0156279
+cap "bias_cell_0/NB2" "bias_cell_0/NB1" -36.2581
cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" 6.09794
-cap "bias_cell_0/NB1" "vssa2" 1.12863
-cap "vssa2" "bias_cell_0/OUT_IB" 42.3191
+cap "bias_cell_0/GND" "bias_cell_0/NB1" 0.542014
+cap "bias_cell_0/NB2" "bias_cell_0/GND" 10.5885
+cap "bias_cell_0/VDD" "bias_cell_0/OUT_IB" 0.0156279
cap "bias_cell_0/NB2" "bias_cell_0/VDD" -4.08557
-cap "bias_cell_0/GND" "bias_cell_0/NB2" 10.5885
-cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 0.66512
-cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" 2.69373
+cap "vssa2" "bias_cell_0/OUT_IB" 42.3191
+cap "bias_cell_0/OUT_IB" "bias_cell_0/GND" -16.3199
+cap "bias_cell_0/OUT_IB" "vssa2" 23.3593
+cap "bias_cell_0/OUT_IB" "bias_cell_0/AMP_IB" -3.28442
+cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" 0.66512
+cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 2.69373
cap "vssa2" "bias_cell_0/AMP_IB" 0.066909
cap "vssa2" "bias_cell_0/AMP_IB" 8.09548
-cap "bias_cell_0/AMP_IB" "bias_cell_0/OUT_IB" -3.28442
-cap "bias_cell_0/GND" "bias_cell_0/OUT_IB" -16.3199
-cap "vssa2" "bias_cell_0/OUT_IB" 23.3593
-cap "bias_cell_0/BIAS2" "bias_cell_0/AMP_IB" 5.74422
-cap "bias_cell_0/OUT_IB" "bias_cell_0/AMP_IB" -3.28442
-cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" -34.3506
-cap "bias_cell_0/ADC_ON" "bias_cell_0/AMP_IB" 36.8352
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/AMP_IB" 13.8897
+cap "bias_cell_0/ADC_ON" "bias_cell_0/AMP_IB" 36.8352
+cap "bias_cell_0/BIAS2" "bias_cell_0/AMP_IB" 5.74422
+cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" -34.3506
+cap "bias_cell_0/OUT_IB" "bias_cell_0/AMP_IB" -3.28442
cap "vssa2" "bias_cell_0/AMP_IB" 49.3466
-cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2_OUT" 11.6294
-cap "bias_cell_0/AMP_IB" "bias_cell_0/ADC_ON" 4.00333
cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 4.6525
-cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS2" 21.3879
-cap "bias_cell_0/BIAS2_OUT" "vssa2" 18.5098
+cap "bias_cell_0/AMP_IB" "bias_cell_0/GND" 17.5678
cap "bias_cell_0/AMP_IB" "vssa2" 9.22212
-cap "bias_cell_0/ADC_ON" "vssa2" 0.341618
-cap "bias_cell_0/GND" "bias_cell_0/BIAS2" 0.1402
-cap "bias_cell_0/GND" "bias_cell_0/BIAS2_OUT" -26.3677
-cap "bias_cell_0/GND" "bias_cell_0/AMP_IB" 17.5678
cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.00108548
-cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS1_OUT" -10.4056
-cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -6.14429
+cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS2" 21.3879
+cap "bias_cell_0/GND" "bias_cell_0/BIAS2_OUT" -26.3677
+cap "bias_cell_0/ADC_ON" "vssa2" 0.341618
+cap "vssa2" "bias_cell_0/BIAS2_OUT" 18.5098
+cap "bias_cell_0/AMP_IB" "bias_cell_0/ADC_ON" 4.00333
+cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2_OUT" 11.6294
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS2_OUT" -10.4056
-cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.0119403
-cap "bias_cell_0/BIAS1_OUT" "vssa2" 18.4787
-cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 0.0869176
+cap "bias_cell_0/GND" "bias_cell_0/BIAS2" 0.1402
+cap "bias_cell_0/GND" "bias_cell_0/BIAS1_OUT" -27.7692
cap "bias_cell_0/AMP_IB" "bias_cell_0/ADC_ON" 0.00352505
-cap "vssa2" "bias_cell_0/ADC_ON" 3.58664
-cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/GND" -27.7692
-cap "bias_cell_0/BIAS1" "bias_cell_0/GND" -0.233896
+cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.0119403
cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS1" 20.6427
+cap "vssa2" "bias_cell_0/BIAS1_OUT" 18.4787
+cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 0.0869176
+cap "vssa2" "bias_cell_0/ADC_ON" 3.58664
+cap "bias_cell_0/GND" "bias_cell_0/BIAS1" -0.233896
+cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS2_OUT" -10.4056
+cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/SA_IREF_OUT" -6.14429
+cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF_OUT" 47.842
cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/BIAS1_OUT" -6.14429
-cap "vssa2" "bias_cell_0/SA_IREF_OUT" 20.4287
-cap "vssa2" "bias_cell_0/ADC_ON" 27.4138
-cap "vssa2" "bias_cell_0/SA_IREF_OUT" 0.641032
-cap "bias_cell_0/SA_IREF" "bias_cell_0/SA_IREF_OUT" 14.3705
-cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" 92.588
-cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 2.09649
-cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/ADC_ON" 47.842
-cap "vssa2" "bias_cell_0/GND" 0.000288907
+cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/SA_IREF" 14.3705
+cap "bias_cell_0/ADC_ON" "bias_cell_0/GND" 0.435573
cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" 0.18249
-cap "bias_cell_0/GND" "bias_cell_0/SA_IREF_OUT" -37.4895
-cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 0.435573
-cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF_OUT" 59.7718
-cap "bias_cell_0/GND" "bias_cell_0/SA_IREF" 0.233775
-cap "bias_cell_0/ADC_ON" "bias_cell_0/GND" 16.9242
-cap "bias_cell_0/ADC_ON" "vssa2" 1.45503
-cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" 12.645
+cap "bias_cell_0/ADC_ON" "bias_cell_0/BIAS1" 2.09649
+cap "bias_cell_0/ADC_ON" "vssa2" 27.4138
+cap "bias_cell_0/SA_IREF_OUT" "vssa2" 0.641032
+cap "vssa2" "bias_cell_0/GND" 0.000288907
+cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/GND" -37.4895
+cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" 92.588
+cap "bias_cell_0/SA_IREF_OUT" "vssa2" 20.4287
+cap "vssa2" "bias_cell_0/ADC_ON" 1.45503
+cap "bias_cell_0/GND" "vssa2" 17.77
cap "bias_cell_0/SA_IREF_OUT" "vssa2" 1.50161
-cap "vssa2" "bias_cell_0/GND" 17.77
-cap "vssa2" "bias_cell_0/GND" 10.0505
+cap "bias_cell_0/GND" "bias_cell_0/ADC_ON" 16.9242
+cap "bias_cell_0/SA_IREF_OUT" "bias_cell_0/ADC_ON" 59.7718
+cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" 12.645
+cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" 0.233775
+cap "bias_cell_0/GND" "vssa2" 10.0505
cap "bias_cell_0/SF_IB" "vssa2" 0.0132899
cap "vssa2" "bias_cell_0/VDD" 1.23346
-cap "vssa2" "bias_cell_0/SF_IB" 3.00398
cap "vssa2" "bias_cell_0/VDD" 31.9333
+cap "vssa2" "bias_cell_0/SF_IB" 3.00398
+cap "vssa2" "bias_cell_0/NB1" 21.9783
cap "bias_cell_0/VDD" "bias_cell_0/NB2" 0.767235
-cap "bias_cell_0/NB1" "vssa2" 21.9783
-cap "bias_cell_0/SF_IB" "vssa2" 18.4645
-cap "bias_cell_0/VDD" "vssa2" 89.2973
cap "bias_cell_0/VDD" "bias_cell_0/NB1" 4.02895
-cap "bias_cell_0/OUT_IB" "vssa2" 63.8166
-cap "bias_cell_0/NB1" "vssa2" 3.00308
+cap "vssa2" "bias_cell_0/VDD" 89.2973
+cap "vssa2" "bias_cell_0/SF_IB" 18.4645
cap "bias_cell_0/NB2" "vssa2" 26.3678
+cap "bias_cell_0/OUT_IB" "vssa2" 63.8166
cap "bias_cell_0/VDD" "bias_cell_0/NB2" 0.905514
-cap "vssa2" "bias_cell_0/AMP_IB" 1.87345
-cap "vssa2" "bias_cell_0/AMP_IB" 8.86286
-cap "vssa2" "bias_cell_0/OUT_IB" 75.4627
-cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 37.7595
+cap "bias_cell_0/NB1" "vssa2" 3.00308
+cap "bias_cell_0/AMP_IB" "vssa2" 1.87345
+cap "bias_cell_0/OUT_IB" "vssa2" 75.4627
+cap "bias_cell_0/AMP_IB" "vssa2" 8.86286
cap "bias_cell_0/AMP_IB" "vssa2" 110.172
-cap "bias_cell_0/GND" "bias_cell_0/BIAS2" -0.693635
-cap "vssa2" "bias_cell_0/AMP_IB" 15.0888
-cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 46.2444
-cap "bias_cell_0/ADC_ON" "vssa2" 25.5775
+cap "bias_cell_0/BIAS2" "bias_cell_0/AMP_IB" 37.7595
+cap "bias_cell_0/BIAS2" "bias_cell_0/GND" -0.693635
+cap "vssa2" "bias_cell_0/ADC_ON" 25.5775
cap "bias_cell_0/BIAS2_OUT" "vssa2" 149.849
cap "bias_cell_0/BIAS2_OUT" "bias_cell_0/BIAS2" -0.421773
-cap "vssa2" "bias_cell_0/BIAS2" 356.305
-cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS2" -2.06618
-cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS1_OUT" -1.27181
-cap "bias_cell_0/BIAS1" "bias_cell_0/BIAS2" -2.06618
+cap "bias_cell_0/BIAS2" "vssa2" 356.305
+cap "bias_cell_0/AMP_IB" "vssa2" 15.0888
+cap "bias_cell_0/AMP_IB" "bias_cell_0/BIAS2" 46.2444
+cap "bias_cell_0/BIAS2" "bias_cell_0/BIAS1" -2.06618
cap "bias_cell_0/BIAS1" "bias_cell_0/SA_IREF" 4.30371
-cap "vssa2" "bias_cell_0/BIAS2_OUT" 0.223042
cap "vssa2" "bias_cell_0/ADC_ON" 35.1064
-cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 2.0004
-cap "bias_cell_0/BIAS1" "bias_cell_0/GND" -1.37507
-cap "vssa2" "bias_cell_0/BIAS1_OUT" 144.426
-cap "vssa2" "bias_cell_0/BIAS2" 4.80252
-cap "vssa2" "bias_cell_0/SA_IREF_OUT" 0.635558
-cap "vssa2" "bias_cell_0/SA_IREF" 25.7364
cap "vssa2" "bias_cell_0/BIAS1" 333.113
-cap "bias_cell_0/ADC_ON" "bias_cell_0/BIAS1" 7.04389
-cap "bias_cell_0/BIAS1" "bias_cell_0/SA_IREF" 78.741
-cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" 94.5125
-cap "bias_cell_0/SA_IREF_OUT" "vssa2" 143.895
-cap "bias_cell_0/ADC_ON" "vssa2" 72.9397
+cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 2.0004
+cap "bias_cell_0/BIAS2" "vssa2" 4.80252
+cap "bias_cell_0/BIAS1" "bias_cell_0/GND" -1.37507
+cap "bias_cell_0/SA_IREF_OUT" "vssa2" 0.635558
+cap "bias_cell_0/BIAS2" "bias_cell_0/BIAS1" -2.06618
+cap "vssa2" "bias_cell_0/BIAS2_OUT" 0.223042
+cap "bias_cell_0/BIAS1_OUT" "vssa2" 144.426
+cap "vssa2" "bias_cell_0/SA_IREF" 25.7364
+cap "bias_cell_0/BIAS1_OUT" "bias_cell_0/BIAS1" -1.27181
cap "vssa2" "bias_cell_0/SA_IREF" 314.086
-cap "bias_cell_0/GND" "bias_cell_0/SA_IREF" -3.20091
+cap "vssa2" "bias_cell_0/ADC_ON" 72.9397
+cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" 94.5125
+cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" -3.20091
+cap "bias_cell_0/BIAS1" "bias_cell_0/ADC_ON" 7.04389
+cap "bias_cell_0/BIAS1" "bias_cell_0/SA_IREF" 78.741
+cap "vssa2" "bias_cell_0/SA_IREF_OUT" 143.895
cap "bias_cell_0/SA_IREF" "bias_cell_0/GND" 0.507614
+cap "bias_cell_0/ADC_ON" "bias_cell_0/SA_IREF" -15.455
+cap "vssa2" "bias_cell_0/SA_IREF" 5.68434e-14
cap "bias_cell_0/ADC_ON" "vssa2" 4.43082
-cap "bias_cell_0/SA_IREF" "bias_cell_0/ADC_ON" -15.455
-cap "bias_cell_0/SA_IREF" "vssa2" 5.68434e-14
-merge "bias_cell_0/GND" "adc_0/GND" -25256.3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12092932 -46068 -1031481 -2893 -3028671 -7344 -21586463 -38390 0 0 0 0
+merge "bias_cell_0/GND" "adc_0/GND" -25228.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -12092932 -46068 -1031481 -2893 -3028671 -7344 -21586463 -38390 0 0 0 0
merge "adc_0/GND" "8bit_sens_0/VSUBS"
merge "8bit_sens_0/VSUBS" "VSUBS"
merge "VSUBS" "8bit_sens_0/sens_amp_7/GND"
merge "8bit_sens_0/sens_amp_7/GND" "8bit_sens_0/GND"
merge "8bit_sens_0/GND" "vssa2"
-merge "adc_0/GRAY_INx7x" "la_data_in[127]" -103.239 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
-merge "8bit_sens_0/OUTx7x" "la_data_out[1]" -181.166 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
-merge "adc_0/OUTx6x" "8bit_sens_0/INx6x" -499.999 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2680 -220 0 0 -4800 -280 0 0 0 0
+merge "adc_0/GRAY_INx7x" "la_data_in[127]" -103.401 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
+merge "8bit_sens_0/OUTx7x" "la_data_out[1]" -181.408 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
+merge "adc_0/OUTx6x" "8bit_sens_0/INx6x" -497.765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2680 -220 0 0 -4800 -280 0 0 0 0
merge "8bit_sens_0/INx6x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "m2_53493_202942#"
+merge "8bit_sens_0/VREF" "gpio_analog[13]" -69.5571 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4900 -280 0 0 0 0 0 0
merge "adc_0/OUTx7x" "8bit_sens_0/INx7x" -282.02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2500 -280 0 0 0 0 0 0 0 0
merge "8bit_sens_0/INx7x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "m2_53160_202790#"
merge "adc_0/GRAY_INx6x" "la_data_in[126]" -63.6356 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
merge "bias_cell_0/SA_IREF" "io_analog[3]" -625.112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -297970 -2692 0 0 0 0 0 0
-merge "adc_0/GRAY_INx5x" "la_data_in[125]" -68.8285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
+merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "adc_0/READ" -592.836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -8400 -400 0 0 0 0 0 0
+merge "adc_0/READ" "gpio_analog[12]"
+merge "adc_0/GRAY_INx5x" "la_data_in[125]" -68.9732 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx6x" "la_data_out[2]" -52.7968 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/GRAY_INx4x" "la_data_in[124]" -51.3026 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
-merge "bias_cell_0/BIAS1_OUT" "adc_0/BIAS1" -640.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -64800 -1780 -260460 -8862 0 0 0 0 0 0
+merge "bias_cell_0/BIAS1_OUT" "adc_0/BIAS1" -646.454 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -64800 -1780 -260460 -8862 0 0 0 0 0 0
merge "adc_0/BIAS1" "m2_33290_207480#"
merge "8bit_sens_0/OUTx5x" "la_data_out[3]" -39.5135 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "adc_0/VDD" "8bit_sens_0/sens_amp_7/VDD" -1916.98 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -172600 -4180 0 0 -21600 -530 0 0 0 0 0 0
merge "8bit_sens_0/sens_amp_7/VDD" "8bit_sens_0/VDD"
merge "8bit_sens_0/VDD" "vccd1"
-merge "adc_0/GRAY_INx3x" "la_data_in[123]" -56.4941 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
+merge "adc_0/GRAY_INx3x" "la_data_in[123]" -56.5273 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx4x" "la_data_out[4]" -29.9959 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
-merge "adc_0/OUTx2x" "8bit_sens_0/INx2x" -265.697 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2340 -200 0 0 -3600 -240 0 0 0 0
+merge "adc_0/OUTx2x" "8bit_sens_0/INx2x" -265.813 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2340 -200 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/INx2x" "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "m2_54833_202912#"
-merge "adc_0/OUTx4x" "8bit_sens_0/INx4x" -221.133 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3700 -280 0 0 -4200 -260 0 0 0 0
+merge "adc_0/OUTx4x" "8bit_sens_0/INx4x" -221.38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3700 -280 0 0 -4200 -260 0 0 0 0
merge "8bit_sens_0/INx4x" "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL"
merge "adc_0/8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "m2_54170_202730#"
merge "adc_0/GRAY_INx2x" "la_data_in[122]" -52.0208 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1600 -160 0 0 0 0 0 0 0 0
@@ -3895,7 +3923,6 @@
merge "adc_0/GRAY_INx0x" "la_data_in[120]" -105.319 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7600 -460 0 0 0 0 0 0 0 0
merge "8bit_sens_0/OUTx1x" "la_data_out[7]" -39.3084 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
merge "8bit_sens_0/OUTx0x" "la_data_out[8]" -107.04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0
-merge "8bit_sens_0/VREF" "m3_51655_199490#" -69.5571 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4900 -280 0 0 0 0 0 0
merge "bias_cell_0/ADC_ON" "gpio_analog[7]" -310.454 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -40000 -800 0 0 0 0 0 0
merge "bias_cell_0/SF_IB" "io_analog[10]" -991.29 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -911650 -2952 -76410 -1878 0 0 0 0 0 0
merge "io_analog[10]" "m3_26500_684896#"
diff --git a/mag/user_analog_project_wrapper.spice b/mag/user_analog_project_wrapper.spice
deleted file mode 100644
index 876ea8e..0000000
--- a/mag/user_analog_project_wrapper.spice
+++ /dev/null
@@ -1,318 +0,0 @@
-* SPICE3 file created from user_analog_project_wrapper.ext - technology: sky130B
-
-.subckt dram_cell storage WWL WBL RWL RBL VSUBS
-X0 RWL storage RBL VSUBS sky130_fd_pr__nfet_01v8 ad=3e+11p pd=2.6e+06u as=3.5e+11p ps=2.7e+06u w=1e+06u l=150000u
-X1 storage WWL WBL VSUBS sky130_fd_pr__nfet_01v8 ad=3.5e+11p pd=2.7e+06u as=3e+11p ps=2.6e+06u w=1e+06u l=150000u
-.ends
-
-.subckt dram_array dram_cell_1/WWL dram_cell_0/WBL dram_cell_1/RWL dram_cell_0/RBL
-+ dram_cell_1/WBL dram_cell_1/RBL VSUBS dram_cell_0/RWL
-Xdram_cell_0 dram_cell_0/storage dram_cell_1/WWL dram_cell_0/WBL dram_cell_0/RWL dram_cell_0/RBL
-+ VSUBS dram_cell
-Xdram_cell_1 dram_cell_1/storage dram_cell_1/WWL dram_cell_1/WBL dram_cell_1/RWL dram_cell_1/RBL
-+ VSUBS dram_cell
-.ends
-
-.subckt x4bit_dram dram_array_0/dram_cell_1/RBL dram_array_1/dram_cell_0/RWL dram_array_1/dram_cell_1/WWL
-+ dram_array_1/dram_cell_0/WBL dram_array_1/dram_cell_1/RWL dram_array_0/dram_cell_0/WBL
-+ dram_array_1/dram_cell_0/RBL dram_array_1/dram_cell_1/WBL dram_array_0/dram_cell_0/RBL
-+ dram_array_0/dram_cell_1/WBL dram_array_1/dram_cell_1/RBL VSUBS
-Xdram_array_0 dram_array_1/dram_cell_1/WWL dram_array_0/dram_cell_0/WBL dram_array_1/dram_cell_0/RWL
-+ dram_array_0/dram_cell_0/RBL dram_array_0/dram_cell_1/WBL dram_array_0/dram_cell_1/RBL
-+ VSUBS dram_array_1/dram_cell_0/RWL dram_array
-Xdram_array_1 dram_array_1/dram_cell_1/WWL dram_array_1/dram_cell_0/WBL dram_array_1/dram_cell_1/RWL
-+ dram_array_1/dram_cell_0/RBL dram_array_1/dram_cell_1/WBL dram_array_1/dram_cell_1/RBL
-+ VSUBS dram_array_1/dram_cell_0/RWL dram_array
-.ends
-
-.subckt x8bit_dram 4bit_dram_1/dram_array_1/dram_cell_1/RWL 4bit_dram_1/dram_array_0/dram_cell_0/WBL
-+ 4bit_dram_0/dram_array_1/dram_cell_0/WBL 4bit_dram_1/dram_array_1/dram_cell_0/RBL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/WBL 4bit_dram_0/dram_array_0/dram_cell_0/WBL
-+ 4bit_dram_1/dram_array_0/dram_cell_0/RBL 4bit_dram_0/dram_array_1/dram_cell_0/RBL
-+ 4bit_dram_1/dram_array_0/dram_cell_1/WBL 4bit_dram_0/dram_array_1/dram_cell_1/WBL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/RBL 4bit_dram_0/dram_array_0/dram_cell_0/RBL
-+ 4bit_dram_0/dram_array_0/dram_cell_1/WBL 4bit_dram_0/dram_array_1/dram_cell_1/RBL
-+ 4bit_dram_1/dram_array_0/dram_cell_1/RBL 4bit_dram_1/dram_array_1/dram_cell_1/WWL
-+ 4bit_dram_0/dram_array_0/dram_cell_1/RBL 4bit_dram_1/dram_array_1/dram_cell_0/WBL
-+ VSUBS
-X4bit_dram_1 4bit_dram_1/dram_array_0/dram_cell_1/RBL 4bit_dram_1/dram_array_1/dram_cell_1/RWL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/WWL 4bit_dram_1/dram_array_1/dram_cell_0/WBL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/RWL 4bit_dram_1/dram_array_0/dram_cell_0/WBL
-+ 4bit_dram_1/dram_array_1/dram_cell_0/RBL 4bit_dram_1/dram_array_1/dram_cell_1/WBL
-+ 4bit_dram_1/dram_array_0/dram_cell_0/RBL 4bit_dram_1/dram_array_0/dram_cell_1/WBL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/RBL VSUBS x4bit_dram
-X4bit_dram_0 4bit_dram_0/dram_array_0/dram_cell_1/RBL 4bit_dram_1/dram_array_1/dram_cell_1/RWL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/WWL 4bit_dram_0/dram_array_1/dram_cell_0/WBL
-+ 4bit_dram_1/dram_array_1/dram_cell_1/RWL 4bit_dram_0/dram_array_0/dram_cell_0/WBL
-+ 4bit_dram_0/dram_array_1/dram_cell_0/RBL 4bit_dram_0/dram_array_1/dram_cell_1/WBL
-+ 4bit_dram_0/dram_array_0/dram_cell_0/RBL 4bit_dram_0/dram_array_0/dram_cell_1/WBL
-+ 4bit_dram_0/dram_array_1/dram_cell_1/RBL VSUBS x4bit_dram
-.ends
-
-.subckt adc V_IN BIAS2 BIAS1 V_RAMP GRAY_INx1x GRAY_INx0x OUTx0x GRAY_INx2x GRAY_INx3x
-+ OUTx3x GRAY_INx4x GRAY_INx5x OUTx5x GRAY_INx6x GRAY_INx7x OUTx7x READ OUTx1x OUTx6x
-+ VDD GND OUTx4x OUTx2x
-X8bit_dram_0 READ GRAY_INx4x GRAY_INx2x OUTx6x GRAY_INx7x GRAY_INx0x OUTx4x OUTx2x
-+ GRAY_INx5x GRAY_INx3x OUTx7x OUTx0x GRAY_INx1x OUTx3x OUTx5x 8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL
-+ OUTx1x GRAY_INx6x GND x8bit_dram
-X0 VDD a_1000_n1450# a_1000_n1450# VDD sky130_fd_pr__pfet_01v8_lvt ad=1.45e+12p pd=1.09e+07u as=3.5e+11p ps=2.7e+06u w=1e+06u l=1e+06u
-X1 8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL a_1870_n1400# GND GND sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=2.5e+07p ps=5000u w=1e+06u l=150000u
-X2 a_1720_n1450# V_RAMP a_1100_n1450# GND sky130_fd_pr__nfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=8.8e+11p ps=7.1e+06u w=1e+06u l=150000u
-X3 a_1870_n1400# a_1720_n1450# VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=450000u
-X4 a_1100_n1450# V_IN a_1000_n1450# GND sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=3.5e+11p ps=2.7e+06u w=1e+06u l=150000u
-X5 8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL a_1870_n1400# VDD VDD sky130_fd_pr__pfet_01v8 ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=200000u
-X6 a_1100_n1450# BIAS1 GND GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=450000u l=1e+06u
-X7 a_1870_n1400# BIAS2 GND GND sky130_fd_pr__nfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=1e+06u
-X8 a_1720_n1450# a_1000_n1450# VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=1e+06u
-C0 VDD GND 2.71fF
-C1 8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL GND 2.33fF
-.ends
-
-.subckt bias_cell NB1 NB2 OUT_IB AMP_IB SF_IB BIAS1_OUT BIAS2_OUT ADC_ON BIAS1 BIAS2
-+ SA_IREF_OUT SA_IREF VDD GND
-X0 BIAS1 ADC_ON BIAS1_OUT GND sky130_fd_pr__nfet_01v8 ad=2.5e+12p pd=1.1e+07u as=5.9425e+12p ps=1.514e+07u w=5e+06u l=1e+06u
-X1 NB1 NB1 GND GND sky130_fd_pr__nfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=1.272e+13p ps=4.894e+07u w=1e+06u l=1.2e+06u
-X2 BIAS2_OUT BIAS2_OUT GND GND sky130_fd_pr__nfet_01v8_lvt ad=5.9725e+12p pd=1.52e+07u as=0p ps=0u w=1e+06u l=1e+06u
-X3 SA_IREF_OUT SA_IREF_OUT GND GND sky130_fd_pr__nfet_01v8 ad=5.9905e+12p pd=1.53e+07u as=0p ps=0u w=500000u l=1e+06u
-X4 NB2 NB2 GND GND sky130_fd_pr__nfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=1.2e+06u
-X5 BIAS2 ADC_ON BIAS2_OUT GND sky130_fd_pr__nfet_01v8 ad=2.5e+12p pd=1.1e+07u as=0p ps=0u w=5e+06u l=1e+06u
-X6 AMP_IB AMP_IB GND GND sky130_fd_pr__nfet_01v8_lvt ad=5.6e+12p pd=1.74e+07u as=0p ps=0u w=8e+06u l=2e+06u
-X7 OUT_IB OUT_IB GND GND sky130_fd_pr__nfet_01v8_lvt ad=5.6e+12p pd=1.74e+07u as=0p ps=0u w=8e+06u l=2e+06u
-X8 SA_IREF ADC_ON SA_IREF_OUT GND sky130_fd_pr__nfet_01v8 ad=2.5e+12p pd=1.1e+07u as=0p ps=0u w=5e+06u l=1e+06u
-X9 BIAS1_OUT BIAS1_OUT GND GND sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=420000u l=1e+06u
-X10 SF_IB SF_IB VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=5.5e+11p pd=3.1e+06u as=4.5e+11p ps=2.9e+06u w=1e+06u l=1e+06u
-C0 SA_IREF_OUT GND 2.47fF
-C1 BIAS1_OUT GND 2.00fF
-C2 AMP_IB GND 4.02fF
-C3 OUT_IB GND 4.01fF
-C4 BIAS2_OUT GND 2.10fF
-C5 ADC_ON GND 2.19fF
-C6 VDD GND 3.12fF
-.ends
-
-.subckt sens_amp V_IN SA_IREF OUT REF VDD GND
-X0 GN GN VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=1.8e+12p ps=1.22e+07u w=1e+06u l=500000u
-X1 net1 V_IN net2 GND sky130_fd_pr__nfet_01v8_lvt ad=1.4e+12p pd=8.7e+06u as=1.775e+12p ps=1.05e+07u w=4e+06u l=150000u
-X2 net2 REF GN GND sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=1.45e+12p ps=9.1e+06u w=4e+06u l=150000u
-X3 net1 GN VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=500000u
-X4 net2 SA_IREF GND GND sky130_fd_pr__nfet_01v8_lvt ad=0p pd=0u as=6e+11p ps=4.7e+06u w=500000u l=1e+06u
-X5 OUT net1 VDD VDD sky130_fd_pr__pfet_01v8_lvt ad=1.05e+12p pd=6.7e+06u as=0p ps=0u w=3e+06u l=350000u
-X6 OUT net1 GND GND sky130_fd_pr__nfet_01v8_lvt ad=3.5e+11p pd=2.7e+06u as=0p ps=0u w=1e+06u l=150000u
-C0 VDD GND 2.64fF
-.ends
-
-.subckt 8bit_sens INx1x INx0x INx2x INx3x INx4x INx5x INx6x INx7x OUTx7x OUTx6x OUTx5x
-+ OUTx4x OUTx3x OUTx2x OUTx1x OUTx0x SA_IREF VREF VDD GND
-Xsens_amp_2 INx5x SA_IREF OUTx5x VREF VDD GND sens_amp
-Xsens_amp_3 INx4x SA_IREF OUTx4x VREF VDD GND sens_amp
-Xsens_amp_4 INx3x SA_IREF OUTx3x VREF VDD GND sens_amp
-Xsens_amp_5 INx2x SA_IREF OUTx2x VREF VDD GND sens_amp
-Xsens_amp_6 INx1x SA_IREF OUTx1x VREF VDD GND sens_amp
-Xsens_amp_7 INx0x SA_IREF OUTx0x VREF VDD GND sens_amp
-Xsens_amp_0 INx7x SA_IREF OUTx7x VREF VDD GND sens_amp
-Xsens_amp_1 INx6x SA_IREF OUTx6x VREF VDD GND sens_amp
-C0 VDD GND 16.99fF
-C1 SA_IREF GND 6.02fF
-.ends
-
-.subckt user_analog_project_wrapper gpio_analog[0] gpio_analog[10] gpio_analog[11]
-+ gpio_analog[12] gpio_analog[13] gpio_analog[14] gpio_analog[15] gpio_analog[16]
-+ gpio_analog[17] gpio_analog[1] gpio_analog[2] gpio_analog[3] gpio_analog[4] gpio_analog[5]
-+ gpio_analog[6] gpio_analog[7] gpio_analog[8] gpio_analog[9] gpio_noesd[0] gpio_noesd[10]
-+ gpio_noesd[11] gpio_noesd[12] gpio_noesd[13] gpio_noesd[14] gpio_noesd[15] gpio_noesd[16]
-+ gpio_noesd[17] gpio_noesd[1] gpio_noesd[2] gpio_noesd[3] gpio_noesd[4] gpio_noesd[5]
-+ gpio_noesd[6] gpio_noesd[7] gpio_noesd[8] gpio_noesd[9] io_analog[0] io_analog[10]
-+ io_analog[1] io_analog[2] io_analog[3] io_analog[7] io_analog[8] io_analog[9] io_analog[4]
-+ io_analog[5] io_analog[6] io_clamp_high[0] io_clamp_high[1] io_clamp_high[2] io_clamp_low[0]
-+ io_clamp_low[1] io_clamp_low[2] io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
-+ io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
-+ io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[2] io_in[3] io_in[4] io_in[5]
-+ io_in[6] io_in[7] io_in[8] io_in[9] io_in_3v3[0] io_in_3v3[10] io_in_3v3[11] io_in_3v3[12]
-+ io_in_3v3[13] io_in_3v3[14] io_in_3v3[15] io_in_3v3[16] io_in_3v3[17] io_in_3v3[18]
-+ io_in_3v3[19] io_in_3v3[1] io_in_3v3[20] io_in_3v3[21] io_in_3v3[22] io_in_3v3[23]
-+ io_in_3v3[24] io_in_3v3[25] io_in_3v3[26] io_in_3v3[2] io_in_3v3[3] io_in_3v3[4]
-+ io_in_3v3[5] io_in_3v3[6] io_in_3v3[7] io_in_3v3[8] io_in_3v3[9] io_oeb[0] io_oeb[10]
-+ io_oeb[11] io_oeb[12] io_oeb[13] io_oeb[14] io_oeb[15] io_oeb[16] io_oeb[17] io_oeb[18]
-+ io_oeb[19] io_oeb[1] io_oeb[20] io_oeb[21] io_oeb[22] io_oeb[23] io_oeb[24] io_oeb[25]
-+ io_oeb[26] io_oeb[2] io_oeb[3] io_oeb[4] io_oeb[5] io_oeb[6] io_oeb[7] io_oeb[8]
-+ io_oeb[9] io_out[0] io_out[10] io_out[11] io_out[12] io_out[13] io_out[14] io_out[15]
-+ io_out[16] io_out[17] io_out[18] io_out[19] io_out[1] io_out[20] io_out[21] io_out[22]
-+ io_out[23] io_out[24] io_out[25] io_out[26] io_out[2] io_out[3] io_out[4] io_out[5]
-+ io_out[6] io_out[7] io_out[8] io_out[9] la_data_in[0] la_data_in[100] la_data_in[101]
-+ la_data_in[102] la_data_in[103] la_data_in[104] la_data_in[105] la_data_in[106]
-+ la_data_in[107] la_data_in[108] la_data_in[109] la_data_in[10] la_data_in[110] la_data_in[111]
-+ la_data_in[112] la_data_in[113] la_data_in[114] la_data_in[115] la_data_in[116]
-+ la_data_in[117] la_data_in[118] la_data_in[119] la_data_in[11] la_data_in[120] la_data_in[121]
-+ la_data_in[122] la_data_in[123] la_data_in[124] la_data_in[125] la_data_in[126]
-+ la_data_in[127] la_data_in[12] la_data_in[13] la_data_in[14] la_data_in[15] la_data_in[16]
-+ la_data_in[17] la_data_in[18] la_data_in[19] la_data_in[1] la_data_in[20] la_data_in[21]
-+ la_data_in[22] la_data_in[23] la_data_in[24] la_data_in[25] la_data_in[26] la_data_in[27]
-+ la_data_in[28] la_data_in[29] la_data_in[2] la_data_in[30] la_data_in[31] la_data_in[32]
-+ la_data_in[33] la_data_in[34] la_data_in[35] la_data_in[36] la_data_in[37] la_data_in[38]
-+ la_data_in[39] la_data_in[3] la_data_in[40] la_data_in[41] la_data_in[42] la_data_in[43]
-+ la_data_in[44] la_data_in[45] la_data_in[46] la_data_in[47] la_data_in[48] la_data_in[49]
-+ la_data_in[4] la_data_in[50] la_data_in[51] la_data_in[52] la_data_in[53] la_data_in[54]
-+ la_data_in[55] la_data_in[56] la_data_in[57] la_data_in[58] la_data_in[59] la_data_in[5]
-+ la_data_in[60] la_data_in[61] la_data_in[62] la_data_in[63] la_data_in[64] la_data_in[65]
-+ la_data_in[66] la_data_in[67] la_data_in[68] la_data_in[69] la_data_in[6] la_data_in[70]
-+ la_data_in[71] la_data_in[72] la_data_in[73] la_data_in[74] la_data_in[75] la_data_in[76]
-+ la_data_in[77] la_data_in[78] la_data_in[79] la_data_in[7] la_data_in[80] la_data_in[81]
-+ la_data_in[82] la_data_in[83] la_data_in[84] la_data_in[85] la_data_in[86] la_data_in[87]
-+ la_data_in[88] la_data_in[89] la_data_in[8] la_data_in[90] la_data_in[91] la_data_in[92]
-+ la_data_in[93] la_data_in[94] la_data_in[95] la_data_in[96] la_data_in[97] la_data_in[98]
-+ la_data_in[99] la_data_in[9] la_data_out[0] la_data_out[100] la_data_out[101] la_data_out[102]
-+ la_data_out[103] la_data_out[104] la_data_out[105] la_data_out[106] la_data_out[107]
-+ la_data_out[108] la_data_out[109] la_data_out[10] la_data_out[110] la_data_out[111]
-+ la_data_out[112] la_data_out[113] la_data_out[114] la_data_out[115] la_data_out[116]
-+ la_data_out[117] la_data_out[118] la_data_out[119] la_data_out[11] la_data_out[120]
-+ la_data_out[121] la_data_out[122] la_data_out[123] la_data_out[124] la_data_out[125]
-+ la_data_out[126] la_data_out[127] la_data_out[12] la_data_out[13] la_data_out[14]
-+ la_data_out[15] la_data_out[16] la_data_out[17] la_data_out[18] la_data_out[19]
-+ la_data_out[1] la_data_out[20] la_data_out[21] la_data_out[22] la_data_out[23] la_data_out[24]
-+ la_data_out[25] la_data_out[26] la_data_out[27] la_data_out[28] la_data_out[29]
-+ la_data_out[2] la_data_out[30] la_data_out[31] la_data_out[32] la_data_out[33] la_data_out[34]
-+ la_data_out[35] la_data_out[36] la_data_out[37] la_data_out[38] la_data_out[39]
-+ la_data_out[3] la_data_out[40] la_data_out[41] la_data_out[42] la_data_out[43] la_data_out[44]
-+ la_data_out[45] la_data_out[46] la_data_out[47] la_data_out[48] la_data_out[49]
-+ la_data_out[4] la_data_out[50] la_data_out[51] la_data_out[52] la_data_out[53] la_data_out[54]
-+ la_data_out[55] la_data_out[56] la_data_out[57] la_data_out[58] la_data_out[59]
-+ la_data_out[5] la_data_out[60] la_data_out[61] la_data_out[62] la_data_out[63] la_data_out[64]
-+ la_data_out[65] la_data_out[66] la_data_out[67] la_data_out[68] la_data_out[69]
-+ la_data_out[6] la_data_out[70] la_data_out[71] la_data_out[72] la_data_out[73] la_data_out[74]
-+ la_data_out[75] la_data_out[76] la_data_out[77] la_data_out[78] la_data_out[79]
-+ la_data_out[7] la_data_out[80] la_data_out[81] la_data_out[82] la_data_out[83] la_data_out[84]
-+ la_data_out[85] la_data_out[86] la_data_out[87] la_data_out[88] la_data_out[89]
-+ la_data_out[8] la_data_out[90] la_data_out[91] la_data_out[92] la_data_out[93] la_data_out[94]
-+ la_data_out[95] la_data_out[96] la_data_out[97] la_data_out[98] la_data_out[99]
-+ la_data_out[9] la_oenb[0] la_oenb[100] la_oenb[101] la_oenb[102] la_oenb[103] la_oenb[104]
-+ la_oenb[105] la_oenb[106] la_oenb[107] la_oenb[108] la_oenb[109] la_oenb[10] la_oenb[110]
-+ la_oenb[111] la_oenb[112] la_oenb[113] la_oenb[114] la_oenb[115] la_oenb[116] la_oenb[117]
-+ la_oenb[118] la_oenb[119] la_oenb[11] la_oenb[120] la_oenb[121] la_oenb[122] la_oenb[123]
-+ la_oenb[124] la_oenb[125] la_oenb[126] la_oenb[127] la_oenb[12] la_oenb[13] la_oenb[14]
-+ la_oenb[15] la_oenb[16] la_oenb[17] la_oenb[18] la_oenb[19] la_oenb[1] la_oenb[20]
-+ la_oenb[21] la_oenb[22] la_oenb[23] la_oenb[24] la_oenb[25] la_oenb[26] la_oenb[27]
-+ la_oenb[28] la_oenb[29] la_oenb[2] la_oenb[30] la_oenb[31] la_oenb[32] la_oenb[33]
-+ la_oenb[34] la_oenb[35] la_oenb[36] la_oenb[37] la_oenb[38] la_oenb[39] la_oenb[3]
-+ la_oenb[40] la_oenb[41] la_oenb[42] la_oenb[43] la_oenb[44] la_oenb[45] la_oenb[46]
-+ la_oenb[47] la_oenb[48] la_oenb[49] la_oenb[4] la_oenb[50] la_oenb[51] la_oenb[52]
-+ la_oenb[53] la_oenb[54] la_oenb[55] la_oenb[56] la_oenb[57] la_oenb[58] la_oenb[59]
-+ la_oenb[5] la_oenb[60] la_oenb[61] la_oenb[62] la_oenb[63] la_oenb[64] la_oenb[65]
-+ la_oenb[66] la_oenb[67] la_oenb[68] la_oenb[69] la_oenb[6] la_oenb[70] la_oenb[71]
-+ la_oenb[72] la_oenb[73] la_oenb[74] la_oenb[75] la_oenb[76] la_oenb[77] la_oenb[78]
-+ la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
-+ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
-+ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
-+ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
-+ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
-+ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
-+ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
-+ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
-+ wbs_adr_i[27] wbs_adr_i[28] wbs_adr_i[29] wbs_adr_i[2] wbs_adr_i[30] wbs_adr_i[31]
-+ wbs_adr_i[3] wbs_adr_i[4] wbs_adr_i[5] wbs_adr_i[6] wbs_adr_i[7] wbs_adr_i[8] wbs_adr_i[9]
-+ wbs_cyc_i wbs_dat_i[0] wbs_dat_i[10] wbs_dat_i[11] wbs_dat_i[12] wbs_dat_i[13] wbs_dat_i[14]
-+ wbs_dat_i[15] wbs_dat_i[16] wbs_dat_i[17] wbs_dat_i[18] wbs_dat_i[19] wbs_dat_i[1]
-+ wbs_dat_i[20] wbs_dat_i[21] wbs_dat_i[22] wbs_dat_i[23] wbs_dat_i[24] wbs_dat_i[25]
-+ wbs_dat_i[26] wbs_dat_i[27] wbs_dat_i[28] wbs_dat_i[29] wbs_dat_i[2] wbs_dat_i[30]
-+ wbs_dat_i[31] wbs_dat_i[3] wbs_dat_i[4] wbs_dat_i[5] wbs_dat_i[6] wbs_dat_i[7] wbs_dat_i[8]
-+ wbs_dat_i[9] wbs_dat_o[0] wbs_dat_o[10] wbs_dat_o[11] wbs_dat_o[12] wbs_dat_o[13]
-+ wbs_dat_o[14] wbs_dat_o[15] wbs_dat_o[16] wbs_dat_o[17] wbs_dat_o[18] wbs_dat_o[19]
-+ wbs_dat_o[1] wbs_dat_o[20] wbs_dat_o[21] wbs_dat_o[22] wbs_dat_o[23] wbs_dat_o[24]
-+ wbs_dat_o[25] wbs_dat_o[26] wbs_dat_o[27] wbs_dat_o[28] wbs_dat_o[29] wbs_dat_o[2]
-+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
-+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
-+ wbs_stb_i wbs_we_i
-Xadc_0 adc_0/V_IN adc_0/BIAS2 adc_0/BIAS1 io_analog[2] la_data_in[121] la_data_in[120]
-+ adc_0/OUTx0x la_data_in[122] la_data_in[123] adc_0/OUTx3x la_data_in[124] la_data_in[125]
-+ adc_0/OUTx5x la_data_in[126] la_data_in[127] adc_0/OUTx7x adc_0/READ adc_0/OUTx1x
-+ adc_0/OUTx6x vccd1 vssa2 adc_0/OUTx4x adc_0/OUTx2x adc
-Xbias_cell_0 io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[10] adc_0/BIAS1
-+ adc_0/BIAS2 gpio_analog[7] io_analog[4] io_analog[5] 8bit_sens_0/SA_IREF io_analog[3]
-+ vccd2 vssa2 bias_cell
-X8bit_sens_0 adc_0/OUTx1x adc_0/OUTx0x adc_0/OUTx2x adc_0/OUTx3x adc_0/OUTx4x adc_0/OUTx5x
-+ adc_0/OUTx6x adc_0/OUTx7x la_data_out[1] la_data_out[2] la_data_out[3] la_data_out[4]
-+ la_data_out[5] la_data_out[6] la_data_out[7] la_data_out[8] 8bit_sens_0/SA_IREF
-+ 8bit_sens_0/VREF vccd1 vssa2 8bit_sens
-C0 io_analog[8] io_analog[7] 3.50fF
-C1 io_analog[10] vccd2 13.80fF
-C2 io_analog[2] adc_0/BIAS1 2.53fF
-C3 vccd1 la_data_in[124] 2.16fF
-C4 io_analog[2] vccd2 10.71fF
-C5 la_data_in[120] vccd1 75.78fF
-C6 la_data_out[3] la_data_out[2] 23.11fF
-C7 la_data_out[2] la_data_out[1] 27.41fF
-C8 la_data_out[5] la_data_out[4] 41.43fF
-C9 vccd1 io_analog[2] 2.22fF
-C10 gpio_analog[7] 8bit_sens_0/SA_IREF 4.47fF
-C11 la_data_out[4] la_data_out[3] 43.18fF
-C12 la_data_in[121] la_data_in[122] 49.58fF
-C13 8bit_sens_0/SA_IREF adc_0/BIAS1 9.04fF
-C14 la_data_in[127] la_data_in[126] 27.40fF
-C15 la_data_out[6] la_data_out[7] 38.74fF
-C16 io_analog[4] io_analog[3] 14.51fF
-C17 la_data_in[125] la_data_in[126] 41.93fF
-C18 io_analog[6] io_analog[5] 5.39fF
-C19 la_data_in[123] la_data_in[122] 32.99fF
-C20 io_analog[6] vccd2 12.76fF
-C21 io_analog[7] io_analog[6] 2.42fF
-C22 io_analog[4] io_analog[5] 15.91fF
-C23 io_analog[5] vccd2 2.11fF
-C24 vccd1 la_data_in[121] 4.93fF
-C25 la_data_out[6] la_data_out[5] 40.26fF
-C26 io_analog[7] vccd2 10.12fF
-C27 vccd1 la_data_in[126] 2.17fF
-C28 vccd1 la_data_in[122] 2.54fF
-C29 vccd1 la_data_in[127] 2.11fF
-C30 la_data_in[120] la_data_in[121] 86.33fF
-C31 vccd1 la_data_in[123] 2.14fF
-C32 la_data_in[125] vccd1 2.10fF
-C33 la_data_in[123] la_data_in[124] 30.97fF
-C34 adc_0/BIAS2 adc_0/BIAS1 30.56fF
-C35 la_data_in[125] la_data_in[124] 40.36fF
-C36 la_data_out[7] la_data_out[8] 37.02fF
-C37 vssa1 vssa2 23.98fF
-C38 vssd1 vssa2 11.99fF
-C39 vssd2 vssa2 13.63fF
-C40 vdda1 vssa2 23.98fF
-C41 vdda2 vssa2 11.99fF
-C42 io_analog[0] vssa2 6.28fF
-C43 io_analog[1] vssa2 6.28fF
-C44 io_clamp_high[0] vssa2 2.62fF
-C45 io_clamp_low[0] vssa2 2.62fF
-C46 io_clamp_high[1] vssa2 2.62fF
-C47 io_clamp_low[1] vssa2 2.62fF
-C48 io_clamp_high[2] vssa2 2.62fF
-C49 io_clamp_low[2] vssa2 2.62fF
-C50 io_analog[10] vssa2 41.15fF
-C51 la_data_out[2] vssa2 47.84fF
-C52 la_data_out[1] vssa2 74.10fF
-C53 la_data_out[8] vssa2 88.64fF
-C54 vccd1 vssa2 2024.86fF
-C55 8bit_sens_0/SA_IREF vssa2 180.51fF
-C56 8bit_sens_0/VREF vssa2 2.04fF
-C57 la_data_out[7] vssa2 64.51fF
-C58 la_data_out[6] vssa2 62.06fF
-C59 la_data_out[5] vssa2 60.58fF
-C60 la_data_out[4] vssa2 55.08fF
-C61 la_data_out[3] vssa2 52.51fF
-C62 io_analog[8] vssa2 42.36fF
-C63 io_analog[9] vssa2 22.08fF
-C64 io_analog[6] vssa2 133.71fF
-C65 io_analog[7] vssa2 83.89fF
-C66 gpio_analog[7] vssa2 131.88fF
-C67 io_analog[3] vssa2 189.27fF
-C68 io_analog[4] vssa2 158.11fF
-C69 io_analog[5] vssa2 114.32fF
-C70 vccd2 vssa2 322.78fF
-C71 adc_0/BIAS2 vssa2 158.27fF
-C72 adc_0/BIAS1 vssa2 141.75fF
-C73 io_analog[2] vssa2 984.46fF
-C74 la_data_in[123] vssa2 281.79fF
-C75 la_data_in[122] vssa2 263.34fF
-C76 la_data_in[121] vssa2 237.68fF
-C77 la_data_in[120] vssa2 218.66fF
-C78 la_data_in[127] vssa2 318.43fF
-C79 la_data_in[126] vssa2 291.01fF
-C80 la_data_in[125] vssa2 274.61fF
-C81 la_data_in[124] vssa2 279.97fF
-.ends
-
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 876ea8e..9e229fd 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -50,7 +50,7 @@
.ends
.subckt adc V_IN BIAS2 BIAS1 V_RAMP GRAY_INx1x GRAY_INx0x OUTx0x GRAY_INx2x GRAY_INx3x
-+ OUTx3x GRAY_INx4x GRAY_INx5x OUTx5x GRAY_INx6x GRAY_INx7x OUTx7x READ OUTx1x OUTx6x
++ OUTx3x GRAY_INx4x GRAY_INx5x OUTx5x GRAY_INx6x GRAY_INx7x OUTx7x OUTx1x READ OUTx6x
+ VDD GND OUTx4x OUTx2x
X8bit_dram_0 READ GRAY_INx4x GRAY_INx2x OUTx6x GRAY_INx7x GRAY_INx0x OUTx4x OUTx2x
+ GRAY_INx5x GRAY_INx3x OUTx7x OUTx0x GRAY_INx1x OUTx3x OUTx5x 8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL
@@ -223,7 +223,7 @@
+ wbs_stb_i wbs_we_i
Xadc_0 adc_0/V_IN adc_0/BIAS2 adc_0/BIAS1 io_analog[2] la_data_in[121] la_data_in[120]
+ adc_0/OUTx0x la_data_in[122] la_data_in[123] adc_0/OUTx3x la_data_in[124] la_data_in[125]
-+ adc_0/OUTx5x la_data_in[126] la_data_in[127] adc_0/OUTx7x adc_0/READ adc_0/OUTx1x
++ adc_0/OUTx5x la_data_in[126] la_data_in[127] adc_0/OUTx7x adc_0/OUTx1x gpio_analog[12]
+ adc_0/OUTx6x vccd1 vssa2 adc_0/OUTx4x adc_0/OUTx2x adc
Xbias_cell_0 io_analog[9] io_analog[8] io_analog[7] io_analog[6] io_analog[10] adc_0/BIAS1
+ adc_0/BIAS2 gpio_analog[7] io_analog[4] io_analog[5] 8bit_sens_0/SA_IREF io_analog[3]
@@ -231,44 +231,44 @@
X8bit_sens_0 adc_0/OUTx1x adc_0/OUTx0x adc_0/OUTx2x adc_0/OUTx3x adc_0/OUTx4x adc_0/OUTx5x
+ adc_0/OUTx6x adc_0/OUTx7x la_data_out[1] la_data_out[2] la_data_out[3] la_data_out[4]
+ la_data_out[5] la_data_out[6] la_data_out[7] la_data_out[8] 8bit_sens_0/SA_IREF
-+ 8bit_sens_0/VREF vccd1 vssa2 8bit_sens
-C0 io_analog[8] io_analog[7] 3.50fF
-C1 io_analog[10] vccd2 13.80fF
-C2 io_analog[2] adc_0/BIAS1 2.53fF
-C3 vccd1 la_data_in[124] 2.16fF
-C4 io_analog[2] vccd2 10.71fF
-C5 la_data_in[120] vccd1 75.78fF
-C6 la_data_out[3] la_data_out[2] 23.11fF
-C7 la_data_out[2] la_data_out[1] 27.41fF
-C8 la_data_out[5] la_data_out[4] 41.43fF
-C9 vccd1 io_analog[2] 2.22fF
-C10 gpio_analog[7] 8bit_sens_0/SA_IREF 4.47fF
-C11 la_data_out[4] la_data_out[3] 43.18fF
-C12 la_data_in[121] la_data_in[122] 49.58fF
-C13 8bit_sens_0/SA_IREF adc_0/BIAS1 9.04fF
-C14 la_data_in[127] la_data_in[126] 27.40fF
-C15 la_data_out[6] la_data_out[7] 38.74fF
-C16 io_analog[4] io_analog[3] 14.51fF
-C17 la_data_in[125] la_data_in[126] 41.93fF
-C18 io_analog[6] io_analog[5] 5.39fF
-C19 la_data_in[123] la_data_in[122] 32.99fF
-C20 io_analog[6] vccd2 12.76fF
-C21 io_analog[7] io_analog[6] 2.42fF
-C22 io_analog[4] io_analog[5] 15.91fF
-C23 io_analog[5] vccd2 2.11fF
-C24 vccd1 la_data_in[121] 4.93fF
-C25 la_data_out[6] la_data_out[5] 40.26fF
-C26 io_analog[7] vccd2 10.12fF
-C27 vccd1 la_data_in[126] 2.17fF
-C28 vccd1 la_data_in[122] 2.54fF
-C29 vccd1 la_data_in[127] 2.11fF
-C30 la_data_in[120] la_data_in[121] 86.33fF
-C31 vccd1 la_data_in[123] 2.14fF
++ gpio_analog[13] vccd1 vssa2 8bit_sens
+C0 io_analog[3] io_analog[4] 14.51fF
+C1 la_data_out[7] la_data_out[6] 38.74fF
+C2 adc_0/BIAS1 8bit_sens_0/SA_IREF 9.04fF
+C3 io_analog[7] vccd2 10.12fF
+C4 io_analog[5] io_analog[6] 5.39fF
+C5 io_analog[2] vccd2 10.71fF
+C6 vccd1 la_data_in[124] 2.16fF
+C7 la_data_in[123] la_data_in[124] 30.97fF
+C8 la_data_in[122] vccd1 2.54fF
+C9 la_data_in[122] la_data_in[123] 32.99fF
+C10 io_analog[8] io_analog[7] 3.50fF
+C11 la_data_in[125] la_data_in[124] 40.36fF
+C12 la_data_in[120] vccd1 75.78fF
+C13 io_analog[7] io_analog[6] 2.42fF
+C14 la_data_in[126] la_data_in[127] 27.40fF
+C15 la_data_in[127] vccd1 2.11fF
+C16 io_analog[5] io_analog[4] 15.91fF
+C17 la_data_out[5] la_data_out[6] 40.26fF
+C18 la_data_out[3] la_data_out[2] 23.11fF
+C19 la_data_out[5] la_data_out[4] 41.43fF
+C20 la_data_in[121] vccd1 4.93fF
+C21 io_analog[2] vccd1 2.22fF
+C22 adc_0/BIAS1 adc_0/BIAS2 30.55fF
+C23 8bit_sens_0/SA_IREF gpio_analog[7] 4.47fF
+C24 la_data_out[1] la_data_out[2] 27.41fF
+C25 la_data_in[126] vccd1 2.17fF
+C26 adc_0/BIAS1 io_analog[2] 2.53fF
+C27 la_data_in[123] vccd1 2.14fF
+C28 io_analog[5] vccd2 2.11fF
+C29 io_analog[10] vccd2 13.80fF
+C30 vccd2 io_analog[6] 12.76fF
+C31 la_data_in[126] la_data_in[125] 41.93fF
C32 la_data_in[125] vccd1 2.10fF
-C33 la_data_in[123] la_data_in[124] 30.97fF
-C34 adc_0/BIAS2 adc_0/BIAS1 30.56fF
-C35 la_data_in[125] la_data_in[124] 40.36fF
-C36 la_data_out[7] la_data_out[8] 37.02fF
+C33 la_data_out[3] la_data_out[4] 43.18fF
+C34 la_data_in[122] la_data_in[121] 49.58fF
+C35 la_data_out[7] la_data_out[8] 37.02fF
+C36 la_data_in[121] la_data_in[120] 86.33fF
C37 vssa1 vssa2 23.98fF
C38 vssd1 vssa2 11.99fF
C39 vssd2 vssa2 13.63fF
@@ -286,9 +286,9 @@
C51 la_data_out[2] vssa2 47.84fF
C52 la_data_out[1] vssa2 74.10fF
C53 la_data_out[8] vssa2 88.64fF
-C54 vccd1 vssa2 2024.86fF
-C55 8bit_sens_0/SA_IREF vssa2 180.51fF
-C56 8bit_sens_0/VREF vssa2 2.04fF
+C54 vccd1 vssa2 2024.83fF
+C55 8bit_sens_0/SA_IREF vssa2 182.85fF
+C56 gpio_analog[13] vssa2 46.84fF
C57 la_data_out[7] vssa2 64.51fF
C58 la_data_out[6] vssa2 62.06fF
C59 la_data_out[5] vssa2 60.58fF
@@ -303,16 +303,17 @@
C68 io_analog[4] vssa2 158.11fF
C69 io_analog[5] vssa2 114.32fF
C70 vccd2 vssa2 322.78fF
-C71 adc_0/BIAS2 vssa2 158.27fF
-C72 adc_0/BIAS1 vssa2 141.75fF
+C71 adc_0/BIAS2 vssa2 161.84fF
+C72 adc_0/BIAS1 vssa2 141.59fF
C73 io_analog[2] vssa2 984.46fF
C74 la_data_in[123] vssa2 281.79fF
C75 la_data_in[122] vssa2 263.34fF
C76 la_data_in[121] vssa2 237.68fF
C77 la_data_in[120] vssa2 218.66fF
C78 la_data_in[127] vssa2 318.43fF
-C79 la_data_in[126] vssa2 291.01fF
-C80 la_data_in[125] vssa2 274.61fF
-C81 la_data_in[124] vssa2 279.97fF
+C79 gpio_analog[12] vssa2 56.91fF
+C80 la_data_in[126] vssa2 291.01fF
+C81 la_data_in[125] vssa2 274.61fF
+C82 la_data_in[124] vssa2 279.97fF
.ends
