| timestamp 1662180122 |
| version 8.3 |
| tech sky130B |
| style ngspice() |
| scale 1000 1 500000 |
| resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5 |
| use 8bit_dram 8bit_dram_0 -1 0 2469 0 -1 -1700 |
| parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__pfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd |
| port "GRAY_INx1x" 7 2340 -730 2340 -730 m4 |
| port "OUTx0x" 10 2150 -720 2150 -720 m4 |
| port "GRAY_INx3x" 12 1900 -720 1900 -720 m4 |
| port "OUTx2x" 14 1710 -720 1710 -720 m4 |
| port "GRAY_INx5x" 16 1470 -720 1470 -720 m4 |
| port "OUTx4x" 18 1280 -720 1280 -720 m4 |
| port "GRAY_INx7x" 20 1030 -700 1030 -700 m4 |
| port "OUTx6x" 22 840 -700 840 -700 m4 |
| port "READ" 23 570 -2290 570 -2290 m3 |
| port "GRAY_INx0x" 8 2430 -730 2430 -730 m2 |
| port "OUTx1x" 9 2260 -710 2260 -710 m2 |
| port "GRAY_INx2x" 11 1990 -720 1990 -720 m2 |
| port "OUTx3x" 13 1820 -720 1820 -720 m2 |
| port "GRAY_INx4x" 15 1560 -720 1560 -720 m2 |
| port "OUTx5x" 17 1390 -720 1390 -720 m2 |
| port "GRAY_INx6x" 19 1160 -720 1160 -720 m2 |
| port "OUTx7x" 21 950 -690 950 -690 m2 |
| port "BIAS2" 2 680 -1380 680 -1380 m1 |
| port "BIAS1" 4 2530 -1100 2530 -1100 m3 |
| port "V_IN" 1 830 -1150 830 -1150 li |
| port "V_RAMP" 6 2530 -930 2530 -930 m3 |
| port "VDD" 5 810 -770 810 -770 m1 |
| port "GND" 3 730 -1660 730 -1660 m1 |
| node "GRAY_INx1x" 1 171.962 2340 -730 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx0x" 1 35.7813 2150 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx3x" 1 33.2218 1900 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx2x" 1 29.0448 1710 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx5x" 1 31.2171 1470 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx4x" 1 37.3431 1280 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx7x" 1 45.7814 1030 -700 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63600 2240 0 0 0 0 |
| node "OUTx6x" 1 207.828 840 -700 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64200 2260 0 0 0 0 |
| node "READ" 2 627.336 570 -2290 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 117600 4040 0 0 0 0 0 0 |
| node "GRAY_INx0x" 4 209.62 2430 -730 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41120 2264 0 0 0 0 0 0 0 0 |
| node "OUTx1x" 5 67.8903 2260 -710 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33509 2296 0 0 0 0 0 0 0 0 |
| node "GRAY_INx2x" 3 48.1848 1990 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40800 2120 0 0 0 0 0 0 0 0 |
| node "OUTx3x" 4 33.0974 1820 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30150 2070 0 0 0 0 0 0 0 0 |
| node "GRAY_INx4x" 3 41.2646 1560 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40400 2100 0 0 0 0 0 0 0 0 |
| node "OUTx5x" 4 36.0708 1390 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30450 2090 0 0 0 0 0 0 0 0 |
| node "GRAY_INx6x" 3 52.8662 1160 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41840 2172 0 0 0 0 0 0 0 0 |
| node "OUTx7x" 4 196.809 950 -690 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32130 2202 0 0 0 0 0 0 0 0 |
| node "li_1640_n2140#" 54 84.507 1640 -2140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6800 420 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "li_764_n2030#" 56 84.0971 764 -2030 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7241 438 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "BIAS2" 150 975.355 680 -1380 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58300 1080 0 0 6900 340 120500 4280 0 0 0 0 0 0 0 0 0 0 |
| node "BIAS1" 92 589.902 2530 -1100 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43800 840 0 0 12600 500 9016 416 4888 284 128800 4410 0 0 0 0 0 0 |
| node "a_1100_n1450#" 1658 133.281 1100 -1450 ndif 0 0 0 0 0 0 0 0 35200 1420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47000 1780 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "V_IN" 666 353.895 830 -1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11874 794 0 0 48300 1520 3604 244 3328 232 0 0 0 0 0 0 0 0 |
| node "V_RAMP" 596 373.224 2530 -930 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14202 886 0 0 2550 218 3328 232 27120 838 105150 3590 0 0 0 0 0 0 |
| node "a_2260_n1450#" 979 472.536 2260 -1450 ndif 0 0 0 0 0 0 0 0 16000 560 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32400 1200 10944 424 8100 360 68400 1700 0 0 0 0 0 0 |
| node "a_1870_n1400#" 2261 279.113 1870 -1400 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28974 1774 0 0 42100 1500 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "a_1720_n1450#" 1349 160.364 1720 -1450 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28318 890 0 0 37562 1674 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "a_1000_n1450#" 1641 491.836 1000 -1450 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123000 2580 0 0 32662 1466 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "VDD" 7379 2707.25 810 -770 m1 0 0 0 0 612750 3710 0 0 20000 600 58000 2180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158400 4360 165600 3680 0 0 0 0 0 0 0 0 0 0 |
| substrate "GND" 0 0 730 -1660 m1 0 0 0 0 0 0 0 0 34800 1420 43200 860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92800 2820 220775 5250 0 0 0 0 0 0 0 0 0 0 |
| cap "GRAY_INx0x" "READ" 7.15514 |
| cap "li_1640_n2140#" "V_RAMP" 2.9373 |
| cap "READ" "a_1870_n1400#" 9.28674 |
| cap "a_1720_n1450#" "GRAY_INx2x" 10.8868 |
| cap "li_1640_n2140#" "BIAS2" 0.645755 |
| cap "a_1000_n1450#" "OUTx3x" 4.2456 |
| cap "GRAY_INx6x" "OUTx2x" 2.5129 |
| cap "a_1870_n1400#" "OUTx5x" 1.95799 |
| cap "READ" "OUTx3x" 4.99531 |
| cap "a_2260_n1450#" "GRAY_INx2x" 11.8436 |
| cap "GRAY_INx0x" "VDD" 18.0743 |
| cap "OUTx6x" "GRAY_INx2x" 0.95202 |
| cap "a_1870_n1400#" "VDD" 255.829 |
| cap "GRAY_INx6x" "V_IN" 52.7923 |
| cap "GRAY_INx0x" "OUTx4x" 0.938394 |
| cap "OUTx1x" "GRAY_INx1x" 2.11682 |
| cap "a_1100_n1450#" "GRAY_INx2x" 1.58509 |
| cap "VDD" "OUTx3x" 28.2014 |
| cap "a_1870_n1400#" "OUTx4x" 1.79508 |
| cap "BIAS2" "OUTx1x" 12.1398 |
| cap "GRAY_INx4x" "BIAS1" 17.4398 |
| cap "OUTx1x" "V_RAMP" 12.0116 |
| cap "GRAY_INx5x" "OUTx2x" 325.297 |
| cap "OUTx4x" "OUTx3x" 1.82953 |
| cap "GRAY_INx3x" "OUTx7x" 1.19038 |
| cap "GRAY_INx3x" "BIAS1" 21.7231 |
| cap "GRAY_INx5x" "V_IN" 1.57629 |
| cap "GRAY_INx4x" "a_1720_n1450#" 2.09698 |
| cap "GRAY_INx4x" "a_2260_n1450#" 8.06462 |
| cap "GRAY_INx7x" "BIAS2" 6.95009 |
| cap "GRAY_INx7x" "V_RAMP" 17.7634 |
| cap "BIAS2" "li_764_n2030#" 0.564727 |
| cap "GRAY_INx3x" "a_1720_n1450#" 4.46198 |
| cap "OUTx6x" "GRAY_INx4x" 1.5944 |
| cap "READ" "a_1000_n1450#" 15.1134 |
| cap "GRAY_INx3x" "a_2260_n1450#" 11.9736 |
| cap "GRAY_INx4x" "a_1100_n1450#" 3.82942 |
| cap "a_1000_n1450#" "OUTx5x" 6.77171 |
| cap "READ" "OUTx5x" 5.07725 |
| cap "OUTx7x" "GRAY_INx1x" 0.444584 |
| cap "a_1000_n1450#" "VDD" 247.849 |
| cap "GRAY_INx3x" "a_1100_n1450#" 1.61145 |
| cap "BIAS2" "OUTx7x" 9.94506 |
| cap "BIAS1" "GRAY_INx1x" 22.5419 |
| cap "OUTx0x" "V_IN" 0.983432 |
| cap "OUTx7x" "V_RAMP" 10.7191 |
| cap "READ" "VDD" 36.7718 |
| cap "BIAS1" "V_RAMP" 951.073 |
| cap "OUTx4x" "a_1000_n1450#" 7.0591 |
| cap "BIAS2" "BIAS1" 249.145 |
| cap "READ" "OUTx4x" 6.90673 |
| cap "GRAY_INx0x" "OUTx2x" 1.6556 |
| cap "OUTx5x" "VDD" 29.2456 |
| cap "a_1870_n1400#" "OUTx2x" 2.33939 |
| cap "a_1720_n1450#" "GRAY_INx1x" 2.17017 |
| cap "OUTx4x" "OUTx5x" 2.09868 |
| cap "GRAY_INx0x" "V_IN" 0.208384 |
| cap "OUTx2x" "OUTx3x" 2.10059 |
| cap "a_1870_n1400#" "V_IN" 0.649421 |
| cap "a_1720_n1450#" "V_RAMP" 38.9468 |
| cap "BIAS2" "a_1720_n1450#" 46.0978 |
| cap "a_2260_n1450#" "GRAY_INx1x" 72.3185 |
| cap "OUTx4x" "VDD" 20.7242 |
| cap "BIAS2" "a_2260_n1450#" 143.963 |
| cap "a_2260_n1450#" "V_RAMP" 16.315 |
| cap "GRAY_INx5x" "OUTx1x" 2.00008 |
| cap "GRAY_INx6x" "GRAY_INx7x" 2.72673 |
| cap "V_IN" "OUTx3x" 1.65111 |
| cap "OUTx6x" "V_RAMP" 5.03727 |
| cap "a_1100_n1450#" "GRAY_INx1x" 1.10963 |
| cap "OUTx6x" "BIAS2" 6.97704 |
| cap "a_1100_n1450#" "V_RAMP" 47.6242 |
| cap "BIAS2" "a_1100_n1450#" 94.6849 |
| cap "GRAY_INx4x" "GRAY_INx2x" 0.494937 |
| cap "GRAY_INx6x" "OUTx7x" 222.445 |
| cap "GRAY_INx6x" "BIAS1" 131.611 |
| cap "OUTx0x" "OUTx1x" 2.29046 |
| cap "GRAY_INx3x" "GRAY_INx2x" 2.60018 |
| cap "a_1000_n1450#" "OUTx2x" 7.40103 |
| cap "READ" "OUTx2x" 6.90673 |
| cap "GRAY_INx5x" "OUTx7x" 1.71934 |
| cap "GRAY_INx6x" "a_1720_n1450#" 2.81697 |
| cap "V_IN" "a_1000_n1450#" 137.415 |
| cap "OUTx2x" "OUTx5x" 2.04766 |
| cap "READ" "V_IN" 9.32086 |
| cap "GRAY_INx0x" "OUTx1x" 207.354 |
| cap "GRAY_INx6x" "a_2260_n1450#" 4.61361 |
| cap "OUTx2x" "VDD" 23.3622 |
| cap "GRAY_INx5x" "BIAS1" 24.1926 |
| cap "a_1870_n1400#" "OUTx1x" 10.9296 |
| cap "V_IN" "OUTx5x" 1.69338 |
| cap "GRAY_INx6x" "OUTx6x" 2.14881 |
| cap "GRAY_INx6x" "a_1100_n1450#" 6.84082 |
| cap "V_IN" "VDD" 23.2781 |
| cap "GRAY_INx5x" "a_1720_n1450#" 3.12953 |
| cap "V_IN" "OUTx4x" 2.29638 |
| cap "GRAY_INx0x" "GRAY_INx7x" 0.560837 |
| cap "GRAY_INx2x" "GRAY_INx1x" 2.41838 |
| cap "GRAY_INx5x" "a_2260_n1450#" 8.56734 |
| cap "GRAY_INx4x" "GRAY_INx3x" 2.11839 |
| cap "GRAY_INx7x" "a_1870_n1400#" 1.82615 |
| cap "BIAS2" "GRAY_INx2x" 14.8611 |
| cap "GRAY_INx2x" "V_RAMP" 12.8097 |
| cap "OUTx0x" "OUTx7x" 0.943415 |
| cap "GRAY_INx7x" "OUTx3x" 1.80441 |
| cap "OUTx0x" "BIAS1" 21.2679 |
| cap "li_1640_n2140#" "a_1000_n1450#" 1.66235 |
| cap "GRAY_INx5x" "a_1100_n1450#" 3.24316 |
| cap "li_1640_n2140#" "READ" 1.31957 |
| cap "a_1870_n1400#" "OUTx7x" 1.41969 |
| cap "OUTx0x" "a_1720_n1450#" 3.15324 |
| cap "li_1640_n2140#" "VDD" 2.22381 |
| cap "GRAY_INx0x" "BIAS1" 18.7682 |
| cap "a_1870_n1400#" "BIAS1" 16.0471 |
| cap "OUTx0x" "a_2260_n1450#" 11.074 |
| cap "GRAY_INx4x" "GRAY_INx1x" 1.63103 |
| cap "a_1000_n1450#" "OUTx1x" 3.63416 |
| cap "READ" "OUTx1x" 5.72333 |
| cap "BIAS1" "OUTx3x" 15.5267 |
| cap "GRAY_INx4x" "V_RAMP" 439.035 |
| cap "GRAY_INx4x" "BIAS2" 11.8688 |
| cap "GRAY_INx0x" "a_1720_n1450#" 2.76708 |
| cap "OUTx0x" "a_1100_n1450#" 1.88157 |
| cap "a_1870_n1400#" "a_1720_n1450#" 98.824 |
| cap "GRAY_INx0x" "a_2260_n1450#" 56.548 |
| cap "OUTx1x" "VDD" 31.2837 |
| cap "GRAY_INx3x" "V_RAMP" 17.5737 |
| cap "BIAS2" "GRAY_INx3x" 10.5669 |
| cap "a_1870_n1400#" "a_2260_n1450#" 29.2813 |
| cap "a_1720_n1450#" "OUTx3x" 4.22614 |
| cap "GRAY_INx0x" "OUTx6x" 0.0653327 |
| cap "GRAY_INx7x" "a_1000_n1450#" 10.5237 |
| cap "OUTx4x" "OUTx1x" 1.38352 |
| cap "V_IN" "OUTx2x" 1.80461 |
| cap "OUTx6x" "a_1870_n1400#" 0.931511 |
| cap "READ" "GRAY_INx7x" 6.92439 |
| cap "a_2260_n1450#" "OUTx3x" 7.54687 |
| cap "READ" "li_764_n2030#" 1.43022 |
| cap "GRAY_INx0x" "a_1100_n1450#" 1.09107 |
| cap "a_1870_n1400#" "a_1100_n1450#" 1.10176 |
| cap "OUTx6x" "OUTx3x" 1.24355 |
| cap "GRAY_INx7x" "OUTx5x" 2.35117 |
| cap "GRAY_INx7x" "VDD" 17.3693 |
| cap "li_764_n2030#" "VDD" 0.526083 |
| cap "a_1100_n1450#" "OUTx3x" 2.75922 |
| cap "GRAY_INx5x" "GRAY_INx2x" 2.29934 |
| cap "GRAY_INx7x" "OUTx4x" 325.297 |
| cap "a_1000_n1450#" "OUTx7x" 5.79683 |
| cap "READ" "OUTx7x" 5.09842 |
| cap "BIAS1" "a_1000_n1450#" 47.7762 |
| cap "BIAS2" "GRAY_INx1x" 6.62824 |
| cap "GRAY_INx1x" "V_RAMP" 20.4094 |
| cap "OUTx5x" "OUTx7x" 0.482716 |
| cap "READ" "BIAS1" 86.1959 |
| cap "BIAS2" "V_RAMP" 43.0991 |
| cap "VDD" "OUTx7x" 21.8656 |
| cap "BIAS1" "OUTx5x" 46.2606 |
| cap "a_1720_n1450#" "a_1000_n1450#" 23.7038 |
| cap "BIAS1" "VDD" 65.9299 |
| cap "READ" "a_1720_n1450#" 7.66535 |
| cap "GRAY_INx6x" "GRAY_INx3x" 1.81565 |
| cap "OUTx4x" "OUTx7x" 2.20559 |
| cap "a_2260_n1450#" "a_1000_n1450#" 4.33884 |
| cap "OUTx4x" "BIAS1" 44.2571 |
| cap "a_1720_n1450#" "OUTx5x" 2.26137 |
| cap "OUTx0x" "GRAY_INx2x" 3.02989 |
| cap "READ" "a_2260_n1450#" 25.7735 |
| cap "OUTx6x" "a_1000_n1450#" 4.54127 |
| cap "OUTx6x" "READ" 7.02901 |
| cap "GRAY_INx5x" "GRAY_INx4x" 2.52547 |
| cap "a_1720_n1450#" "VDD" 278.914 |
| cap "OUTx2x" "OUTx1x" 2.02055 |
| cap "a_2260_n1450#" "OUTx5x" 5.16631 |
| cap "a_1000_n1450#" "a_1100_n1450#" 106.971 |
| cap "OUTx6x" "OUTx5x" 1.8448 |
| cap "READ" "a_1100_n1450#" 9.26602 |
| cap "a_2260_n1450#" "VDD" 121.765 |
| cap "a_1720_n1450#" "OUTx4x" 2.14051 |
| cap "OUTx6x" "VDD" 12.5851 |
| cap "V_IN" "OUTx1x" 0.756156 |
| cap "a_1100_n1450#" "OUTx5x" 3.46536 |
| cap "a_1870_n1400#" "GRAY_INx2x" 5.87446 |
| cap "OUTx4x" "a_2260_n1450#" 5.58034 |
| cap "a_1100_n1450#" "VDD" 86.1236 |
| cap "GRAY_INx2x" "OUTx3x" 291.078 |
| cap "GRAY_INx6x" "GRAY_INx1x" 1.00188 |
| cap "OUTx4x" "a_1100_n1450#" 3.09895 |
| cap "GRAY_INx6x" "BIAS2" 10.0223 |
| cap "GRAY_INx6x" "V_RAMP" 13.3188 |
| cap "GRAY_INx4x" "OUTx0x" 2.31071 |
| cap "GRAY_INx7x" "V_IN" 4.71705 |
| cap "li_764_n2030#" "V_IN" 0.887306 |
| cap "GRAY_INx3x" "OUTx0x" 325.297 |
| cap "OUTx2x" "OUTx7x" 1.73276 |
| cap "GRAY_INx5x" "V_RAMP" 18.4046 |
| cap "GRAY_INx5x" "BIAS2" 8.06454 |
| cap "GRAY_INx4x" "a_1870_n1400#" 2.20436 |
| cap "BIAS1" "OUTx2x" 23.6154 |
| cap "V_IN" "OUTx7x" 37.2457 |
| cap "GRAY_INx0x" "GRAY_INx3x" 2.31575 |
| cap "GRAY_INx4x" "OUTx3x" 113.22 |
| cap "V_IN" "BIAS1" 77.8114 |
| cap "a_1870_n1400#" "GRAY_INx3x" 4.75807 |
| cap "a_1720_n1450#" "OUTx2x" 3.7551 |
| cap "a_1000_n1450#" "GRAY_INx2x" 3.48582 |
| cap "READ" "GRAY_INx2x" 6.8245 |
| cap "GRAY_INx3x" "OUTx3x" 1.73851 |
| cap "li_1640_n2140#" "li_764_n2030#" 5.40359 |
| cap "a_2260_n1450#" "OUTx2x" 9.14974 |
| cap "a_1720_n1450#" "V_IN" 0.626756 |
| cap "OUTx0x" "GRAY_INx1x" 462.923 |
| cap "OUTx5x" "GRAY_INx2x" 0.342982 |
| cap "BIAS2" "OUTx0x" 8.38834 |
| cap "OUTx0x" "V_RAMP" 18.0102 |
| cap "a_1100_n1450#" "OUTx2x" 2.5382 |
| cap "VDD" "GRAY_INx2x" 26.2571 |
| cap "V_IN" "a_2260_n1450#" 3.49524 |
| cap "OUTx6x" "V_IN" 9.39569 |
| cap "OUTx4x" "GRAY_INx2x" 1.64187 |
| cap "GRAY_INx7x" "OUTx1x" 1.19818 |
| cap "GRAY_INx0x" "GRAY_INx1x" 10.213 |
| cap "V_IN" "a_1100_n1450#" 2.02691 |
| cap "a_1870_n1400#" "GRAY_INx1x" 2.57237 |
| cap "li_1640_n2140#" "BIAS1" 0.336809 |
| cap "GRAY_INx0x" "BIAS2" 10.6761 |
| cap "GRAY_INx0x" "V_RAMP" 14.9889 |
| cap "GRAY_INx6x" "GRAY_INx5x" 2.29742 |
| cap "a_1870_n1400#" "V_RAMP" 15.4114 |
| cap "a_1870_n1400#" "BIAS2" 46.5525 |
| cap "OUTx3x" "GRAY_INx1x" 1.53177 |
| cap "GRAY_INx4x" "a_1000_n1450#" 11.5747 |
| cap "READ" "GRAY_INx4x" 6.71497 |
| cap "OUTx3x" "V_RAMP" 68.8925 |
| cap "BIAS2" "OUTx3x" 15.4895 |
| cap "GRAY_INx4x" "OUTx5x" 292.526 |
| cap "GRAY_INx3x" "a_1000_n1450#" 3.44566 |
| cap "OUTx1x" "OUTx7x" 0.766667 |
| cap "READ" "GRAY_INx3x" 6.90673 |
| cap "GRAY_INx4x" "VDD" 26.0297 |
| cap "BIAS1" "OUTx1x" 15.155 |
| cap "GRAY_INx3x" "OUTx5x" 1.56864 |
| cap "GRAY_INx4x" "OUTx4x" 1.973 |
| cap "GRAY_INx3x" "VDD" 22.4013 |
| cap "li_1640_n2140#" "a_1100_n1450#" 2.90863 |
| cap "GRAY_INx6x" "OUTx0x" 1.68938 |
| cap "a_1720_n1450#" "OUTx1x" 3.14372 |
| cap "GRAY_INx7x" "OUTx7x" 2.22841 |
| cap "GRAY_INx7x" "BIAS1" 28.581 |
| cap "a_2260_n1450#" "OUTx1x" 65.0779 |
| cap "OUTx6x" "OUTx1x" 0.542456 |
| cap "OUTx2x" "GRAY_INx2x" 2.04545 |
| cap "a_1000_n1450#" "GRAY_INx1x" 2.09814 |
| cap "READ" "GRAY_INx1x" 6.90673 |
| cap "a_1100_n1450#" "OUTx1x" 1.86307 |
| cap "GRAY_INx6x" "a_1870_n1400#" 2.23358 |
| cap "a_1000_n1450#" "V_RAMP" 82.448 |
| cap "BIAS2" "a_1000_n1450#" 33.71 |
| cap "READ" "V_RAMP" 6.42899 |
| cap "GRAY_INx7x" "a_1720_n1450#" 2.41228 |
| cap "OUTx5x" "GRAY_INx1x" 1.07973 |
| cap "READ" "BIAS2" 29.5835 |
| cap "V_IN" "GRAY_INx2x" 0.916992 |
| cap "GRAY_INx7x" "a_2260_n1450#" 3.62213 |
| cap "VDD" "GRAY_INx1x" 15.8419 |
| cap "BIAS2" "OUTx5x" 8.61245 |
| cap "BIAS1" "OUTx7x" 19.3486 |
| cap "OUTx5x" "V_RAMP" 10.5099 |
| cap "OUTx6x" "GRAY_INx7x" 481.077 |
| cap "BIAS2" "VDD" 209.153 |
| cap "VDD" "V_RAMP" 172.457 |
| cap "GRAY_INx5x" "GRAY_INx0x" 1.58022 |
| cap "GRAY_INx7x" "a_1100_n1450#" 2.37737 |
| cap "GRAY_INx5x" "a_1870_n1400#" 2.83315 |
| cap "BIAS2" "OUTx4x" 6.50189 |
| cap "OUTx4x" "V_RAMP" 16.8079 |
| cap "a_1720_n1450#" "OUTx7x" 2.00937 |
| cap "GRAY_INx5x" "OUTx3x" 2.34351 |
| cap "GRAY_INx4x" "OUTx2x" 2.6947 |
| cap "a_1720_n1450#" "BIAS1" 16.6903 |
| cap "a_2260_n1450#" "OUTx7x" 1.87057 |
| cap "OUTx6x" "OUTx7x" 7.82061 |
| cap "BIAS1" "a_2260_n1450#" 197.986 |
| cap "GRAY_INx4x" "V_IN" 1.44758 |
| cap "GRAY_INx3x" "OUTx2x" 462.923 |
| cap "a_1100_n1450#" "OUTx7x" 2.09281 |
| cap "OUTx6x" "BIAS1" 11.7322 |
| cap "GRAY_INx0x" "OUTx0x" 2.07348 |
| cap "BIAS1" "a_1100_n1450#" 106.672 |
| cap "GRAY_INx3x" "V_IN" 1.09308 |
| cap "a_1720_n1450#" "a_2260_n1450#" 7.93385 |
| cap "a_1870_n1400#" "OUTx0x" 3.57482 |
| cap "GRAY_INx6x" "a_1000_n1450#" 14.3784 |
| cap "GRAY_INx6x" "READ" 7.46657 |
| cap "OUTx6x" "a_1720_n1450#" 1.45785 |
| cap "OUTx0x" "OUTx3x" 2.01523 |
| cap "OUTx1x" "GRAY_INx2x" 192.307 |
| cap "GRAY_INx6x" "OUTx5x" 178.794 |
| cap "a_1720_n1450#" "a_1100_n1450#" 76.4086 |
| cap "OUTx6x" "a_2260_n1450#" 1.0819 |
| cap "GRAY_INx6x" "VDD" 28.1456 |
| cap "GRAY_INx0x" "a_1870_n1400#" 2.90887 |
| cap "a_2260_n1450#" "a_1100_n1450#" 9.60873 |
| cap "GRAY_INx5x" "a_1000_n1450#" 5.34977 |
| cap "GRAY_INx5x" "READ" 6.90673 |
| cap "GRAY_INx6x" "OUTx4x" 2.87958 |
| cap "OUTx6x" "a_1100_n1450#" 1.58234 |
| cap "a_1870_n1400#" "OUTx3x" 2.41406 |
| cap "OUTx2x" "V_RAMP" 22.5584 |
| cap "GRAY_INx5x" "OUTx5x" 1.76895 |
| cap "BIAS2" "OUTx2x" 7.64112 |
| cap "GRAY_INx7x" "GRAY_INx2x" 1.58547 |
| cap "V_IN" "GRAY_INx1x" 0.411883 |
| cap "GRAY_INx5x" "VDD" 25.1198 |
| cap "V_IN" "V_RAMP" 4.58473 |
| cap "BIAS2" "V_IN" 69.2601 |
| cap "GRAY_INx5x" "OUTx4x" 462.923 |
| cap "OUTx0x" "a_1000_n1450#" 3.7793 |
| cap "READ" "OUTx0x" 6.90673 |
| cap "GRAY_INx3x" "OUTx1x" 2.56716 |
| cap "BIAS1" "GRAY_INx2x" 17.4273 |
| cap "OUTx0x" "OUTx5x" 1.60549 |
| cap "GRAY_INx7x" "GRAY_INx4x" 2.2334 |
| cap "OUTx0x" "VDD" 21.5291 |
| cap "a_1870_n1400#" "a_1000_n1450#" 5.67061 |
| cap "GRAY_INx0x" "a_1000_n1450#" 2.39003 |
| device msubckt sky130_fd_pr__nfet_01v8 2230 -1450 2231 -1449 l=30 w=200 "GND" "a_1870_n1400#" 60 0 "GND" 200 0 "a_2260_n1450#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1870 -1600 1871 -1599 l=200 w=200 "GND" "BIAS2" 400 0 "GND" 200 0 "a_1870_n1400#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1690 -1450 1691 -1449 l=30 w=200 "GND" "V_RAMP" 60 0 "a_1100_n1450#" 200 0 "a_1720_n1450#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8 1330 -1620 1331 -1619 l=200 w=90 "GND" "BIAS1" 400 0 "GND" 90 0 "a_1100_n1450#" 90 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1070 -1450 1071 -1449 l=30 w=200 "GND" "V_IN" 60 0 "a_1000_n1450#" 200 0 "a_1100_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8 2220 -1110 2221 -1109 l=40 w=200 "VDD" "a_1870_n1400#" 80 0 "VDD" 200 0 "a_2260_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1930 -1060 1931 -1059 l=90 w=200 "VDD" "a_1720_n1450#" 180 0 "VDD" 200 0 "a_1870_n1400#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1520 -1060 1521 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "VDD" 200 0 "a_1720_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1070 -1060 1071 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "a_1000_n1450#" 200 0 "VDD" 200 0 |
| cap "a_1100_n1450#" "GND" 0.933335 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 5.50563 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.6079 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0617132 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -3.62012 |
| cap "BIAS1" "V_IN" -2.51738 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 5.73964 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "GND" 70.5412 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -8.54424e-05 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 11.0576 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.116761 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 1.83905 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS2" 1.55813 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.053718 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 61.6339 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.27527 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 3.28011 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0674668 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_RAMP" 7.86714 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0105251 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" -6.39044 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0904769 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0291227 |
| cap "a_1000_n1450#" "BIAS1" -1.35379 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "VDD" 0.491866 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.000238699 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.579418 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0201137 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.61617 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 46.2224 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 25.2816 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "V_IN" 59.479 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -27.536 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0930028 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.63021 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 11.6531 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.139468 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.670312 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 1.22872 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.425348 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0284849 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.098269 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0453317 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0540618 |
| cap "BIAS2" "a_1000_n1450#" 0.838693 |
| cap "a_1100_n1450#" "V_RAMP" -0.645355 |
| cap "BIAS1" "GND" -6.48079 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.3092 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 6.49388 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.000891146 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.247468 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 4.69954 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0370006 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.98823 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.629186 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "GND" 0.366462 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0498302 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -2.03677 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "VDD" 0.383609 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00752321 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.19679 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.13413 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 18.0666 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 0.231145 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.159674 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.76928 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.9653 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6832 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 8.2221 |
| cap "BIAS2" "GND" -0.719256 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 2.705 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.33393 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.66447 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00402917 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0406008 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "GND" 9.37596 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 4.27689 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.0895 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.195592 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.117289 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0262757 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "BIAS1" 1.88344 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.25736 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0285071 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_IN" 1.72248 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.239186 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00034688 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0621439 |
| cap "BIAS1" "V_RAMP" -2.66289 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390295 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.43642 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0544076 |
| cap "BIAS1" "VDD" -2.52254 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.27511 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.350496 |
| cap "a_1720_n1450#" "GND" 0.26344 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "GND" 6.37813 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.060956 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.00114193 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.51707 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.39337 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.30688 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 136.959 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.201761 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.000282779 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.42538 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0872739 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.171491 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS1" -42.7637 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -2.76043e-06 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.00155291 |
| cap "BIAS2" "V_RAMP" -0.117922 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00292971 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 1.37728 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.118638 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "GND" 9.58327 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.0549252 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -19.1352 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.123171 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "VDD" 1.55184 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0373118 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 17.3813 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.00200893 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00102381 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "GND" 43.6867 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0920516 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1000_n1450#" 1.59878 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.482716 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0945249 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.919416 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 3.26809 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0344911 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0603412 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.29099 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.582232 |
| cap "a_1100_n1450#" "BIAS1" -2.52094 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.098269 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.189831 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.0883216 |
| cap "a_1720_n1450#" "VDD" 0.025356 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -2.48678e-05 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS1" 0.0382438 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "VDD" 3.74098 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0100182 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.27401 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.132554 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 3.45146 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.16663 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "GND" 5.77192 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 8.52831 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 1.57514 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -14.4815 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.33301 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0013419 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.29528 |
| cap "BIAS2" "a_1100_n1450#" 0.135131 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -14.4815 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0374578 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.95524 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "VDD" 3.17851 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 2.20076 |
| cap "V_IN" "GND" -0.416424 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 2.17953 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.00083711 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "GND" 0.159169 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.0297725 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.94269 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.09253 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.45589 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 3.93281 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.12477 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "VDD" 0.103655 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.110951 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.210274 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 4.78653 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.516809 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.44085 |
| cap "a_1000_n1450#" "GND" 1.12119 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -6.09724e-05 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 3.58449 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.30023 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -6.51667 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.92947 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.30843 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "GND" 63.7693 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.200635 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.437278 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 7.73301 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.421328 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.0760366 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -3.78622e-06 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "GND" 15.2831 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "VDD" 0.708582 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -27.2308 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.0222617 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0510678 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.17502 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_IN" 3.1249 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0315754 |
| cap "BIAS2" "BIAS1" -5.14804 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.57981 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.00148064 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.384583 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "GND" 19.7181 |
| cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 10.0248 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "BIAS1" 2.27313 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.108546 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 7.61082 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.6232 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.00020449 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.52962 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.56957 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 10.3286 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.57324 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 33.4171 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -19.1351 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.444991 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0341316 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.353732 |
| cap "a_1000_n1450#" "V_RAMP" 0.604532 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_IN" -3.50669 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.154608 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -0.000193271 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.85005 |
| cap "a_1000_n1450#" "VDD" 3.45671 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -7.65029 |
| cap "a_1720_n1450#" "BIAS1" -2.04805 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0181359 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.132846 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.8276 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.249042 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "GND" 41.0969 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "BIAS1" 9.97982 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.146022 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "VDD" 9.40824 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 29.7137 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.291584 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "GND" 7.82349 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.125115 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -8.5 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1100_n1450#" 2.0457 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "VDD" 5.19873 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.992231 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.618264 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0790654 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.074722 |
| cap "V_RAMP" "GND" -0.254294 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.99029 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.302044 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.830892 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0388643 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.139468 |
| cap "BIAS2" "a_1720_n1450#" 0.869605 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.85671 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.744596 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0225169 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.29199 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "VDD" 10.9194 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "VDD" 2.49487 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.041835 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -3.71821 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "GND" 772.763 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS1" 0.687434 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_IN" 4.85972 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.00796 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.345858 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0125795 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 4.26772 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.405984 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "GND" 92.3 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -2.69828 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -3.92544 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.00176326 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 2.58365 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "GND" 7.5 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.0474576 |
| cap "a_1000_n1450#" "a_1100_n1450#" 1.56068 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.439002 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0919385 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0666906 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "VDD" 3.60539 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 6.11521 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.66447 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.0608144 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.329795 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "VDD" 0.601185 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS1" 2.0609 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.8546 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0577865 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.187347 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.60978 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "GND" 5.54063 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.117404 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0020125 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.01343 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -5.59752 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.063849 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1720_n1450#" 10.1643 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -8.89594e-05 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.247468 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.08821 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0134903 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00161877 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.140948 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.10399 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0532087 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 2.80202 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 14.3091 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -8.89594e-05 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -5.79259 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.76761 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.6698 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "GND" 3.26588 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "a_1870_n1400#" 1.46628 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.294791 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.2807 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.060956 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.83823 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "VDD" 3.58915 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1720_n1450#" 6.82222 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GND" 4.83645 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -1.23879e-06 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.058652 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000177049 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 7.42581 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "VDD" 0.706079 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0453581 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -19.9654 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 3.15379 |
| cap "BIAS2" "GND" 3.7066 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0703315 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.061489 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000401671 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 1.04623 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.23441 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.696885 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 3.89719 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "V_RAMP" 1.56834 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.41616 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 6.44193 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.62635 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 1.93821 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" -0.0332521 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "BIAS2" 37.38 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1870_n1400#" 0.598216 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.383079 |
| cap "a_1870_n1400#" "a_1720_n1450#" 0.692513 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0702659 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000684837 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.802502 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0628071 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.0723097 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -3.20043 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0379485 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.826992 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0432799 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.631024 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.00848554 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0176446 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.18676 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS2" 9.80977 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.174367 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0207214 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.28709 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "BIAS2" 3.85367 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "BIAS1" 1.40716 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0896117 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 7.31129 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.44828e-05 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1720_n1450#" 0.814251 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 2.60769 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00773872 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0424989 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.472353 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.291548 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.73757 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.042945 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -6.51667 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.210823 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "a_1870_n1400#" 1.56722 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0296036 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0552098 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "GND" 388.424 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.562213 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.022966 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1870_n1400#" 2.35246 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 51.3778 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 4.78199 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.000851373 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.042945 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0271561 |
| cap "BIAS2" "a_1870_n1400#" 2.05056 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.000117457 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 7.0193 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -3.78622e-06 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.00735648 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.565274 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0511651 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.000755933 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.323989 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_RAMP" 0.372723 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0985772 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 21.4123 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0460312 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -9.35 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.16819 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.87215 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "VDD" 8.61722 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.0110033 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "VDD" 0.0175938 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0701304 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.254349 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00059708 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.69566 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.2317 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 3.15098 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1720_n1450#" 2.02989 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00380833 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0296036 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.93592 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000522601 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0472786 |
| cap "BIAS2" "a_1720_n1450#" 3.1891 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.70523 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000319715 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0109873 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 9.46478 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0113908 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000153749 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "GND" 7.67288 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 26.6425 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 6.032 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.000224931 |
| cap "a_1870_n1400#" "GND" 1.92409 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 48.0744 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.44828e-05 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0880644 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 19.875 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 51.2959 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.077983 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0281068 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0443803 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.0882335 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.0220217 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 9.91911 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.0760366 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.29458 |
| cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.9402 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 1.99018 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 4.91548 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1870_n1400#" 16.0201 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 15.0376 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 4.08514 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.08172 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0104909 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0157989 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "BIAS2" 4.39505 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000266492 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS1" 4.36287 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "GND" 1.43665 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.74027 |
| cap "GND" "a_1720_n1450#" 1.21244 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "BIAS2" 5.30455 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000112148 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0302549 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.377527 |
| cap "VDD" "a_1720_n1450#" 0.109424 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390765 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -19.1351 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000180329 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 4.1577 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.116079 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0393076 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0790691 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 5.78299 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -21.5657 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1870_n1400#" 5.34153 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.0347718 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.171491 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -27.2308 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.723246 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.629827 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 4.35076 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.946276 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 3.44589 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.946276 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0124444 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.126567 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 1.06702 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "VDD" 1.78021 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.274985 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 2.08846 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.665406 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.629827 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.82762 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.000785002 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "V_RAMP" 1.39549 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.157699 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.116892 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_RAMP" 0.79349 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "V_RAMP" 0.304511 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.909122 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.837499 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 1.22803 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.765508 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.16434 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 2.67915 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.00900749 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 3.44799 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.250446 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.634132 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.582219 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00459401 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.54101 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.75744 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1000_n1450#" 1.80077 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 1.32252 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.00495499 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.013366 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.42616 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 0.14231 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 1.46409 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.386156 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 8.02498 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" 6.25991 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.69157 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.307507 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.67125 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.355936 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.0959047 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 2.47329 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.0143353 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 5.43565 |
| cap "VDD" "a_1720_n1450#" 5.25775 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 1.03607 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.0782307 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.00785 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00448159 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.484979 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.156473 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000268858 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.14017 |
| cap "BIAS1" "VDD" 0.769393 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.619119 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 2.50816 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.14259 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 4.63311 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.946276 |
| cap "V_RAMP" "VDD" 0.798811 |
| cap "VDD" "a_1870_n1400#" 6.73852 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1720_n1450#" 0.978212 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.75744 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 3.68865 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.679031 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.252891 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.320955 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 7.10139 |
| cap "VDD" "BIAS2" 7.44072 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 3.38334 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.212311 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.634132 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.131148 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.662542 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "VDD" 1.96995 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.274985 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1720_n1450#" -0.000573118 |
| cap "GND" "VDD" 3.37587 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 2.1684e-19 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0212796 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.482735 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 0.124726 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 0.00847102 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 3.51812 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.69157 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.946276 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 1.94462 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GRAY_INx3x" -46.2737 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "OUTx2x" -40.0623 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "GRAY_INx5x" -42.7679 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/VSUBS" "GND" -1219.55 0 0 0 0 0 0 0 0 -34800 -1420 -43200 -860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -92800 -2820 -220775 -5250 0 0 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "OUTx4x" -45.5742 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "GRAY_INx0x" -19.9181 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -800 -120 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "GRAY_INx7x" -66.5398 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "OUTx6x" -97.7241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4200 -260 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GRAY_INx2x" -24.7836 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2400 -200 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "GRAY_INx4x" -20.7858 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -180 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "READ" -815.703 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -13524 -848 0 0 0 0 -106560 -3672 0 0 0 0 0 0 |
| merge "READ" "li_1640_n2140#" |
| merge "li_1640_n2140#" "li_764_n2030#" |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "GRAY_INx6x" -26.0352 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -180 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "OUTx1x" -28.0989 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "OUTx7x" -55.1902 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "OUTx5x" -23.4717 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GRAY_INx1x" -40.0565 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_2260_n1450#" -776.684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5040 -288 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "OUTx3x" -20.2527 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1350 -150 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "OUTx0x" -36.2133 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
