| timestamp 1662014509 |
| version 8.3 |
| tech sky130A |
| style ngspice() |
| scale 1000 1 500000 |
| resistclasses 4400000 2200000 950000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12800 125 125 47 47 29 5 |
| use 8bit_dram 8bit_dram_0 -1 0 2469 0 -1 -1700 |
| parameters sky130_fd_pr__nfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__pfet_01v8 l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__pfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd |
| parameters sky130_fd_pr__nfet_01v8_lvt l=l w=w a1=as p1=ps a2=ad p2=pd |
| port "GRAY_INx1x" 7 2340 -730 2340 -730 m4 |
| port "OUTx0x" 10 2150 -720 2150 -720 m4 |
| port "GRAY_INx3x" 12 1900 -720 1900 -720 m4 |
| port "OUTx2x" 14 1710 -720 1710 -720 m4 |
| port "GRAY_INx5x" 16 1470 -720 1470 -720 m4 |
| port "OUTx4x" 18 1280 -720 1280 -720 m4 |
| port "GRAY_INx7x" 20 1030 -700 1030 -700 m4 |
| port "OUTx6x" 22 840 -700 840 -700 m4 |
| port "READ" 23 570 -2290 570 -2290 m3 |
| port "GRAY_INx0x" 8 2430 -730 2430 -730 m2 |
| port "OUTx1x" 9 2260 -710 2260 -710 m2 |
| port "GRAY_INx2x" 11 1990 -720 1990 -720 m2 |
| port "OUTx3x" 13 1820 -720 1820 -720 m2 |
| port "GRAY_INx4x" 15 1560 -720 1560 -720 m2 |
| port "OUTx5x" 17 1390 -720 1390 -720 m2 |
| port "GRAY_INx6x" 19 1160 -720 1160 -720 m2 |
| port "OUTx7x" 21 950 -690 950 -690 m2 |
| port "BIAS2" 2 680 -1380 680 -1380 m1 |
| port "BIAS1" 4 2530 -1100 2530 -1100 m3 |
| port "V_IN" 1 830 -1150 830 -1150 li |
| port "V_RAMP" 6 2530 -930 2530 -930 m3 |
| port "VDD" 5 810 -770 810 -770 m1 |
| port "GND" 3 730 -1660 730 -1660 m1 |
| node "GRAY_INx1x" 1 184.777 2340 -730 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx0x" 1 38.774 2150 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx3x" 1 35.9961 1900 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx2x" 1 31.5083 1710 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx5x" 1 33.8566 1470 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "OUTx4x" 1 40.3987 1280 -720 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 61200 2160 0 0 0 0 |
| node "GRAY_INx7x" 1 49.466 1030 -700 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63600 2240 0 0 0 0 |
| node "OUTx6x" 1 223.487 840 -700 m4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64200 2260 0 0 0 0 |
| node "READ" 2 703.065 570 -2290 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 117600 4040 0 0 0 0 0 0 |
| node "GRAY_INx0x" 4 242.346 2430 -730 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41120 2264 0 0 0 0 0 0 0 0 |
| node "OUTx1x" 5 85.2688 2260 -710 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33509 2296 0 0 0 0 0 0 0 0 |
| node "GRAY_INx2x" 3 63.0632 1990 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40800 2120 0 0 0 0 0 0 0 0 |
| node "OUTx3x" 4 44.9101 1820 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30150 2070 0 0 0 0 0 0 0 0 |
| node "GRAY_INx4x" 3 55.5821 1560 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40400 2100 0 0 0 0 0 0 0 0 |
| node "OUTx5x" 4 48.1585 1390 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30450 2090 0 0 0 0 0 0 0 0 |
| node "GRAY_INx6x" 3 71.0784 1160 -720 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41840 2172 0 0 0 0 0 0 0 0 |
| node "OUTx7x" 4 234.498 950 -690 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32130 2202 0 0 0 0 0 0 0 0 |
| node "li_1640_n2140#" 54 84.507 1640 -2140 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6800 420 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "li_764_n2030#" 56 84.0971 764 -2030 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7241 438 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "BIAS2" 150 975.355 680 -1380 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58300 1080 0 0 6900 340 120500 4280 0 0 0 0 0 0 0 0 0 0 |
| node "BIAS1" 92 612.702 2530 -1100 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43800 840 0 0 12600 500 9016 416 4888 284 128800 4410 0 0 0 0 0 0 |
| node "a_1100_n1450#" 1658 133.281 1100 -1450 ndif 0 0 0 0 0 0 0 0 35200 1420 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47000 1780 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "V_IN" 666 354.3 830 -1150 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11874 794 0 0 48300 1520 3604 244 3328 232 0 0 0 0 0 0 0 0 |
| node "V_RAMP" 596 403.912 2530 -930 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14202 886 0 0 2550 218 3328 232 27120 838 105150 3590 0 0 0 0 0 0 |
| node "a_2260_n1450#" 979 499.414 2260 -1450 ndif 0 0 0 0 0 0 0 0 16000 560 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32400 1200 10944 424 8100 360 68400 1700 0 0 0 0 0 0 |
| node "a_1870_n1400#" 2261 279.113 1870 -1400 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28974 1774 0 0 42100 1500 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "a_1720_n1450#" 1349 160.364 1720 -1450 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28318 890 0 0 37562 1674 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "a_1000_n1450#" 1641 491.836 1000 -1450 ndif 0 0 0 0 0 0 0 0 14000 540 14000 540 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123000 2580 0 0 32662 1466 0 0 0 0 0 0 0 0 0 0 0 0 |
| node "VDD" 7379 2707.25 810 -770 m1 0 0 0 0 612750 3710 0 0 20000 600 58000 2180 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 158400 4360 165600 3680 0 0 0 0 0 0 0 0 0 0 |
| substrate "GND" 0 0 730 -1660 m1 0 0 0 0 0 0 0 0 34800 1420 43200 860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 92800 2820 220775 5250 0 0 0 0 0 0 0 0 0 0 |
| cap "V_RAMP" "a_1000_n1450#" 88.7003 |
| cap "VDD" "GRAY_INx2x" 41.6052 |
| cap "BIAS2" "OUTx4x" 7.27168 |
| cap "a_1720_n1450#" "OUTx2x" 4.1624 |
| cap "OUTx7x" "GRAY_INx5x" 1.71934 |
| cap "a_1100_n1450#" "GRAY_INx0x" 1.36195 |
| cap "GRAY_INx7x" "BIAS1" 28.8608 |
| cap "READ" "OUTx2x" 6.90673 |
| cap "GRAY_INx4x" "OUTx2x" 2.6947 |
| cap "GRAY_INx6x" "a_1100_n1450#" 8.7962 |
| cap "OUTx3x" "VDD" 42.8711 |
| cap "BIAS1" "OUTx1x" 15.8435 |
| cap "a_1870_n1400#" "OUTx2x" 2.54833 |
| cap "a_2260_n1450#" "V_IN" 3.90699 |
| cap "OUTx6x" "GRAY_INx0x" 0.0653327 |
| cap "GRAY_INx1x" "a_2260_n1450#" 72.7961 |
| cap "GRAY_INx6x" "OUTx6x" 2.14881 |
| cap "V_RAMP" "GRAY_INx0x" 15.2236 |
| cap "BIAS2" "GRAY_INx5x" 9.00405 |
| cap "GRAY_INx6x" "OUTx5x" 178.794 |
| cap "GRAY_INx6x" "V_RAMP" 13.8624 |
| cap "a_1720_n1450#" "OUTx4x" 2.33247 |
| cap "a_1000_n1450#" "OUTx2x" 8.03429 |
| cap "OUTx3x" "GRAY_INx2x" 291.078 |
| cap "a_1100_n1450#" "VDD" 86.1236 |
| cap "OUTx0x" "BIAS1" 21.4666 |
| cap "OUTx7x" "BIAS1" 20.1839 |
| cap "GRAY_INx3x" "BIAS1" 21.9167 |
| cap "READ" "OUTx4x" 6.90673 |
| cap "GRAY_INx4x" "OUTx4x" 1.973 |
| cap "li_764_n2030#" "VDD" 0.526083 |
| cap "OUTx6x" "VDD" 13.9643 |
| cap "GRAY_INx7x" "V_IN" 5.11739 |
| cap "a_1870_n1400#" "OUTx4x" 1.95568 |
| cap "VDD" "OUTx5x" 44.0235 |
| cap "a_1100_n1450#" "GRAY_INx2x" 1.98084 |
| cap "V_RAMP" "VDD" 199.045 |
| cap "OUTx1x" "V_IN" 1.01725 |
| cap "GRAY_INx1x" "OUTx1x" 2.11682 |
| cap "BIAS2" "BIAS1" 261.571 |
| cap "a_1720_n1450#" "GRAY_INx5x" 3.4089 |
| cap "OUTx6x" "GRAY_INx2x" 0.95202 |
| cap "a_1000_n1450#" "OUTx4x" 7.66685 |
| cap "GRAY_INx0x" "OUTx2x" 1.6556 |
| cap "OUTx5x" "GRAY_INx2x" 0.342982 |
| cap "OUTx3x" "a_1100_n1450#" 3.43884 |
| cap "V_RAMP" "GRAY_INx2x" 13.1731 |
| cap "READ" "GRAY_INx5x" 6.90673 |
| cap "OUTx0x" "V_IN" 1.07202 |
| cap "GRAY_INx4x" "GRAY_INx5x" 2.52547 |
| cap "GRAY_INx6x" "OUTx2x" 2.5129 |
| cap "OUTx7x" "V_IN" 40.2586 |
| cap "GRAY_INx1x" "OUTx0x" 462.923 |
| cap "GRAY_INx1x" "OUTx7x" 0.444584 |
| cap "a_1870_n1400#" "GRAY_INx5x" 3.08599 |
| cap "OUTx6x" "OUTx3x" 1.24355 |
| cap "GRAY_INx3x" "V_IN" 1.19271 |
| cap "V_RAMP" "OUTx3x" 69.2213 |
| cap "a_1720_n1450#" "BIAS1" 19.0822 |
| cap "a_1000_n1450#" "GRAY_INx5x" 5.81106 |
| cap "VDD" "OUTx2x" 25.6172 |
| cap "BIAS2" "V_IN" 70.1169 |
| cap "GRAY_INx0x" "OUTx4x" 0.938394 |
| cap "OUTx6x" "a_1100_n1450#" 1.72508 |
| cap "BIAS2" "GRAY_INx1x" 7.39874 |
| cap "READ" "BIAS1" 87.8398 |
| cap "a_1100_n1450#" "OUTx5x" 4.38213 |
| cap "GRAY_INx4x" "BIAS1" 18.3357 |
| cap "GRAY_INx6x" "OUTx4x" 2.87958 |
| cap "GRAY_INx7x" "a_2260_n1450#" 3.71407 |
| cap "V_RAMP" "a_1100_n1450#" 49.1359 |
| cap "a_1870_n1400#" "BIAS1" 18.3431 |
| cap "OUTx2x" "GRAY_INx2x" 2.04545 |
| cap "OUTx6x" "OUTx5x" 1.8448 |
| cap "OUTx1x" "a_2260_n1450#" 66.156 |
| cap "V_RAMP" "OUTx6x" 5.10783 |
| cap "V_RAMP" "OUTx5x" 10.9416 |
| cap "a_1000_n1450#" "BIAS1" 52.7231 |
| cap "VDD" "OUTx4x" 22.793 |
| cap "GRAY_INx0x" "GRAY_INx5x" 1.58022 |
| cap "OUTx3x" "OUTx2x" 2.10059 |
| cap "a_1720_n1450#" "V_IN" 0.626756 |
| cap "GRAY_INx1x" "a_1720_n1450#" 2.3629 |
| cap "OUTx0x" "a_2260_n1450#" 11.2776 |
| cap "OUTx7x" "a_2260_n1450#" 2.13267 |
| cap "GRAY_INx6x" "GRAY_INx5x" 2.29742 |
| cap "GRAY_INx3x" "a_2260_n1450#" 12.2247 |
| cap "BIAS2" "li_1640_n2140#" 0.645755 |
| cap "READ" "V_IN" 10.726 |
| cap "GRAY_INx1x" "READ" 6.90673 |
| cap "GRAY_INx7x" "OUTx1x" 1.19818 |
| cap "OUTx4x" "GRAY_INx2x" 1.64187 |
| cap "GRAY_INx4x" "V_IN" 1.9393 |
| cap "a_1870_n1400#" "V_IN" 0.649498 |
| cap "GRAY_INx1x" "GRAY_INx4x" 1.63103 |
| cap "GRAY_INx1x" "a_1870_n1400#" 2.79976 |
| cap "a_1100_n1450#" "OUTx2x" 2.77675 |
| cap "VDD" "GRAY_INx5x" 27.5532 |
| cap "BIAS2" "a_2260_n1450#" 153.252 |
| cap "GRAY_INx0x" "BIAS1" 19.1949 |
| cap "OUTx3x" "OUTx4x" 1.82953 |
| cap "a_1000_n1450#" "V_IN" 138.065 |
| cap "OUTx2x" "OUTx5x" 2.04766 |
| cap "OUTx7x" "GRAY_INx7x" 2.22841 |
| cap "GRAY_INx6x" "BIAS1" 132.509 |
| cap "GRAY_INx1x" "a_1000_n1450#" 2.2784 |
| cap "V_RAMP" "OUTx2x" 22.8754 |
| cap "OUTx0x" "OUTx1x" 2.29046 |
| cap "GRAY_INx5x" "GRAY_INx2x" 2.29934 |
| cap "OUTx7x" "OUTx1x" 0.766667 |
| cap "GRAY_INx3x" "OUTx1x" 2.56716 |
| cap "a_1100_n1450#" "OUTx4x" 3.38674 |
| cap "VDD" "BIAS1" 74.4704 |
| cap "li_1640_n2140#" "READ" 1.54214 |
| cap "BIAS2" "GRAY_INx7x" 7.77531 |
| cap "a_1720_n1450#" "a_2260_n1450#" 8.5591 |
| cap "OUTx3x" "GRAY_INx5x" 2.34351 |
| cap "OUTx0x" "OUTx7x" 0.943415 |
| cap "OUTx4x" "OUTx5x" 2.09868 |
| cap "BIAS2" "OUTx1x" 22.8615 |
| cap "OUTx0x" "GRAY_INx3x" 325.297 |
| cap "GRAY_INx0x" "V_IN" 0.287702 |
| cap "OUTx7x" "GRAY_INx3x" 1.19038 |
| cap "V_RAMP" "OUTx4x" 16.9007 |
| cap "GRAY_INx1x" "GRAY_INx0x" 10.213 |
| cap "READ" "a_2260_n1450#" 26.8399 |
| cap "GRAY_INx4x" "a_2260_n1450#" 8.71811 |
| cap "BIAS1" "GRAY_INx2x" 18.1537 |
| cap "GRAY_INx6x" "V_IN" 53.2927 |
| cap "a_1870_n1400#" "a_2260_n1450#" 30.7884 |
| cap "a_1000_n1450#" "li_1640_n2140#" 1.66235 |
| cap "GRAY_INx6x" "GRAY_INx1x" 1.00188 |
| cap "a_1100_n1450#" "GRAY_INx5x" 3.54516 |
| cap "BIAS2" "OUTx0x" 9.35658 |
| cap "BIAS2" "OUTx7x" 19.7885 |
| cap "OUTx3x" "BIAS1" 16.5314 |
| cap "a_1720_n1450#" "GRAY_INx7x" 2.62787 |
| cap "BIAS2" "GRAY_INx3x" 11.7136 |
| cap "a_1000_n1450#" "a_2260_n1450#" 4.5779 |
| cap "GRAY_INx5x" "OUTx5x" 1.76895 |
| cap "VDD" "V_IN" 24.4939 |
| cap "GRAY_INx1x" "VDD" 17.4329 |
| cap "V_RAMP" "GRAY_INx5x" 18.5199 |
| cap "a_1720_n1450#" "OUTx1x" 3.88148 |
| cap "READ" "GRAY_INx7x" 6.92439 |
| cap "GRAY_INx4x" "GRAY_INx7x" 2.2334 |
| cap "a_1870_n1400#" "GRAY_INx7x" 1.98952 |
| cap "READ" "OUTx1x" 5.72333 |
| cap "a_1100_n1450#" "BIAS1" 110.104 |
| cap "GRAY_INx2x" "V_IN" 1.23269 |
| cap "a_1870_n1400#" "OUTx1x" 13.2124 |
| cap "GRAY_INx1x" "GRAY_INx2x" 2.41838 |
| cap "OUTx0x" "a_1720_n1450#" 3.43287 |
| cap "OUTx7x" "a_1720_n1450#" 2.49351 |
| cap "OUTx6x" "BIAS1" 11.943 |
| cap "a_1000_n1450#" "GRAY_INx7x" 11.5464 |
| cap "a_1720_n1450#" "GRAY_INx3x" 4.86797 |
| cap "OUTx5x" "BIAS1" 47.7109 |
| cap "GRAY_INx0x" "a_2260_n1450#" 58.0178 |
| cap "V_RAMP" "BIAS1" 952.34 |
| cap "OUTx0x" "READ" 6.90673 |
| cap "OUTx3x" "V_IN" 2.20876 |
| cap "a_1000_n1450#" "OUTx1x" 4.40371 |
| cap "GRAY_INx1x" "OUTx3x" 1.53177 |
| cap "OUTx0x" "GRAY_INx4x" 2.31071 |
| cap "OUTx7x" "READ" 5.09842 |
| cap "a_1870_n1400#" "OUTx0x" 3.89079 |
| cap "GRAY_INx6x" "a_2260_n1450#" 5.1632 |
| cap "a_1870_n1400#" "OUTx7x" 1.76354 |
| cap "READ" "GRAY_INx3x" 6.90673 |
| cap "GRAY_INx4x" "GRAY_INx3x" 2.11839 |
| cap "GRAY_INx5x" "OUTx2x" 325.297 |
| cap "li_1640_n2140#" "VDD" 2.22381 |
| cap "a_1870_n1400#" "GRAY_INx3x" 5.19831 |
| cap "BIAS2" "a_1720_n1450#" 46.0978 |
| cap "a_1000_n1450#" "OUTx0x" 4.1044 |
| cap "a_1000_n1450#" "OUTx7x" 7.09683 |
| cap "a_1100_n1450#" "V_IN" 2.08603 |
| cap "GRAY_INx1x" "a_1100_n1450#" 1.20962 |
| cap "VDD" "a_2260_n1450#" 124.565 |
| cap "BIAS2" "READ" 35.8582 |
| cap "BIAS2" "GRAY_INx4x" 22.2655 |
| cap "BIAS2" "a_1870_n1400#" 46.5525 |
| cap "a_1000_n1450#" "GRAY_INx3x" 3.74404 |
| cap "GRAY_INx0x" "GRAY_INx7x" 0.560837 |
| cap "li_764_n2030#" "V_IN" 0.887306 |
| cap "OUTx6x" "V_IN" 10.3138 |
| cap "OUTx5x" "V_IN" 2.23728 |
| cap "GRAY_INx0x" "OUTx1x" 207.354 |
| cap "GRAY_INx6x" "GRAY_INx7x" 2.72673 |
| cap "GRAY_INx1x" "OUTx5x" 1.07973 |
| cap "V_RAMP" "V_IN" 4.78064 |
| cap "V_RAMP" "GRAY_INx1x" 20.4664 |
| cap "OUTx4x" "GRAY_INx5x" 462.923 |
| cap "GRAY_INx2x" "a_2260_n1450#" 13.0247 |
| cap "OUTx2x" "BIAS1" 23.8801 |
| cap "BIAS2" "a_1000_n1450#" 33.71 |
| cap "OUTx0x" "GRAY_INx0x" 2.07348 |
| cap "a_1720_n1450#" "READ" 8.73457 |
| cap "VDD" "GRAY_INx7x" 19.1504 |
| cap "a_1720_n1450#" "GRAY_INx4x" 2.60029 |
| cap "OUTx3x" "a_2260_n1450#" 8.33541 |
| cap "a_1870_n1400#" "a_1720_n1450#" 98.824 |
| cap "GRAY_INx0x" "GRAY_INx3x" 2.31575 |
| cap "GRAY_INx6x" "OUTx0x" 1.68938 |
| cap "GRAY_INx6x" "OUTx7x" 222.445 |
| cap "VDD" "OUTx1x" 48.3944 |
| cap "li_1640_n2140#" "a_1100_n1450#" 2.90863 |
| cap "GRAY_INx6x" "GRAY_INx3x" 1.81565 |
| cap "GRAY_INx4x" "READ" 6.71497 |
| cap "OUTx4x" "BIAS1" 44.7368 |
| cap "a_1870_n1400#" "READ" 10.5842 |
| cap "GRAY_INx7x" "GRAY_INx2x" 1.58547 |
| cap "li_764_n2030#" "li_1640_n2140#" 5.40359 |
| cap "a_1870_n1400#" "GRAY_INx4x" 2.74258 |
| cap "a_1000_n1450#" "a_1720_n1450#" 23.7038 |
| cap "BIAS2" "GRAY_INx0x" 20.6004 |
| cap "a_1100_n1450#" "a_2260_n1450#" 10.7525 |
| cap "OUTx2x" "V_IN" 1.96935 |
| cap "GRAY_INx2x" "OUTx1x" 192.307 |
| cap "OUTx0x" "VDD" 23.6379 |
| cap "V_RAMP" "li_1640_n2140#" 3.40785 |
| cap "OUTx7x" "VDD" 36.7556 |
| cap "GRAY_INx6x" "BIAS2" 19.6738 |
| cap "a_1000_n1450#" "READ" 17.0833 |
| cap "OUTx3x" "GRAY_INx7x" 1.80441 |
| cap "OUTx6x" "a_2260_n1450#" 1.11518 |
| cap "VDD" "GRAY_INx3x" 24.6125 |
| cap "a_1870_n1400#" "a_1000_n1450#" 5.67061 |
| cap "a_1000_n1450#" "GRAY_INx4x" 13.9603 |
| cap "OUTx5x" "a_2260_n1450#" 5.72281 |
| cap "V_RAMP" "a_2260_n1450#" 18.4897 |
| cap "OUTx0x" "GRAY_INx2x" 3.02989 |
| cap "GRAY_INx5x" "BIAS1" 24.4994 |
| cap "BIAS2" "VDD" 209.153 |
| cap "GRAY_INx3x" "GRAY_INx2x" 2.60018 |
| cap "a_1720_n1450#" "GRAY_INx0x" 3.4198 |
| cap "a_1100_n1450#" "GRAY_INx7x" 2.59133 |
| cap "OUTx4x" "V_IN" 2.50719 |
| cap "OUTx3x" "OUTx0x" 2.01523 |
| cap "GRAY_INx6x" "a_1720_n1450#" 3.49704 |
| cap "a_1100_n1450#" "OUTx1x" 2.3223 |
| cap "OUTx6x" "GRAY_INx7x" 481.077 |
| cap "GRAY_INx0x" "READ" 7.15514 |
| cap "OUTx3x" "GRAY_INx3x" 1.73851 |
| cap "GRAY_INx7x" "OUTx5x" 2.35117 |
| cap "BIAS2" "GRAY_INx2x" 25.5155 |
| cap "OUTx6x" "OUTx1x" 0.542456 |
| cap "V_RAMP" "GRAY_INx7x" 17.86 |
| cap "a_1870_n1400#" "GRAY_INx0x" 3.59726 |
| cap "GRAY_INx6x" "READ" 7.46657 |
| cap "GRAY_INx6x" "a_1870_n1400#" 2.77277 |
| cap "V_RAMP" "OUTx1x" 12.3496 |
| cap "a_1720_n1450#" "VDD" 278.914 |
| cap "OUTx0x" "a_1100_n1450#" 2.05081 |
| cap "OUTx7x" "a_1100_n1450#" 2.61042 |
| cap "OUTx2x" "a_2260_n1450#" 9.32428 |
| cap "BIAS2" "OUTx3x" 28.9685 |
| cap "GRAY_INx5x" "V_IN" 1.721 |
| cap "a_1000_n1450#" "GRAY_INx0x" 2.88768 |
| cap "a_1100_n1450#" "GRAY_INx3x" 1.75683 |
| cap "OUTx6x" "OUTx7x" 7.82061 |
| cap "OUTx0x" "OUTx5x" 1.60549 |
| cap "VDD" "READ" 41.8096 |
| cap "GRAY_INx6x" "a_1000_n1450#" 17.3653 |
| cap "OUTx7x" "OUTx5x" 0.482716 |
| cap "VDD" "GRAY_INx4x" 42.2021 |
| cap "V_RAMP" "OUTx0x" 18.0902 |
| cap "a_1720_n1450#" "GRAY_INx2x" 13.1692 |
| cap "a_1870_n1400#" "VDD" 255.829 |
| cap "V_RAMP" "OUTx7x" 11.0997 |
| cap "GRAY_INx3x" "OUTx5x" 1.56864 |
| cap "BIAS2" "a_1100_n1450#" 94.6849 |
| cap "V_RAMP" "GRAY_INx3x" 17.6435 |
| cap "READ" "GRAY_INx2x" 6.8245 |
| cap "GRAY_INx4x" "GRAY_INx2x" 0.494937 |
| cap "BIAS2" "li_764_n2030#" 0.564727 |
| cap "OUTx4x" "a_2260_n1450#" 5.6942 |
| cap "BIAS2" "OUTx6x" 7.8356 |
| cap "a_1000_n1450#" "VDD" 247.849 |
| cap "BIAS1" "V_IN" 81.0472 |
| cap "a_1870_n1400#" "GRAY_INx2x" 7.44938 |
| cap "OUTx3x" "a_1720_n1450#" 5.32351 |
| cap "BIAS2" "OUTx5x" 16.5431 |
| cap "GRAY_INx1x" "BIAS1" 22.6675 |
| cap "OUTx2x" "OUTx1x" 2.02055 |
| cap "V_RAMP" "BIAS2" 47.6033 |
| cap "OUTx3x" "READ" 4.99531 |
| cap "OUTx3x" "GRAY_INx4x" 113.22 |
| cap "a_1870_n1400#" "OUTx3x" 2.99219 |
| cap "a_1000_n1450#" "GRAY_INx2x" 4.24501 |
| cap "a_1720_n1450#" "a_1100_n1450#" 76.4086 |
| cap "OUTx7x" "OUTx2x" 1.73276 |
| cap "GRAY_INx5x" "a_2260_n1450#" 8.75574 |
| cap "OUTx4x" "GRAY_INx7x" 325.297 |
| cap "OUTx6x" "a_1720_n1450#" 1.58885 |
| cap "GRAY_INx3x" "OUTx2x" 462.923 |
| cap "OUTx3x" "a_1000_n1450#" 5.16403 |
| cap "a_1100_n1450#" "READ" 10.629 |
| cap "GRAY_INx0x" "VDD" 29.896 |
| cap "a_1720_n1450#" "OUTx5x" 2.80745 |
| cap "a_1100_n1450#" "GRAY_INx4x" 4.86325 |
| cap "OUTx4x" "OUTx1x" 1.38352 |
| cap "a_1870_n1400#" "a_1100_n1450#" 1.10176 |
| cap "V_RAMP" "a_1720_n1450#" 40.9563 |
| cap "GRAY_INx6x" "VDD" 44.5773 |
| cap "GRAY_INx1x" "V_IN" 0.448377 |
| cap "OUTx6x" "READ" 7.02901 |
| cap "li_1640_n2140#" "BIAS1" 0.393635 |
| cap "li_764_n2030#" "READ" 1.67146 |
| cap "OUTx6x" "GRAY_INx4x" 1.5944 |
| cap "READ" "OUTx5x" 5.07725 |
| cap "BIAS2" "OUTx2x" 8.54233 |
| cap "OUTx6x" "a_1870_n1400#" 1.01522 |
| cap "GRAY_INx4x" "OUTx5x" 292.526 |
| cap "a_1870_n1400#" "OUTx5x" 2.4291 |
| cap "V_RAMP" "READ" 6.81949 |
| cap "V_RAMP" "GRAY_INx4x" 439.501 |
| cap "V_RAMP" "a_1870_n1400#" 16.9413 |
| cap "a_1000_n1450#" "a_1100_n1450#" 106.971 |
| cap "OUTx7x" "OUTx4x" 2.20559 |
| cap "BIAS1" "a_2260_n1450#" 201.352 |
| cap "OUTx6x" "a_1000_n1450#" 4.94143 |
| cap "GRAY_INx5x" "OUTx1x" 2.00008 |
| cap "a_1000_n1450#" "OUTx5x" 8.22985 |
| device msubckt sky130_fd_pr__nfet_01v8 2230 -1450 2231 -1449 l=30 w=200 "GND" "a_1870_n1400#" 60 0 "GND" 200 0 "a_2260_n1450#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1870 -1600 1871 -1599 l=200 w=200 "GND" "BIAS2" 400 0 "GND" 200 0 "a_1870_n1400#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1690 -1450 1691 -1449 l=30 w=200 "GND" "V_RAMP" 60 0 "a_1100_n1450#" 200 0 "a_1720_n1450#" 200 0 |
| device msubckt sky130_fd_pr__nfet_01v8 1330 -1620 1331 -1619 l=200 w=90 "GND" "BIAS1" 400 0 "GND" 90 0 "a_1100_n1450#" 90 0 |
| device msubckt sky130_fd_pr__nfet_01v8_lvt 1070 -1450 1071 -1449 l=30 w=200 "GND" "V_IN" 60 0 "a_1000_n1450#" 200 0 "a_1100_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8 2220 -1110 2221 -1109 l=40 w=200 "VDD" "a_1870_n1400#" 80 0 "VDD" 200 0 "a_2260_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1930 -1060 1931 -1059 l=90 w=200 "VDD" "a_1720_n1450#" 180 0 "VDD" 200 0 "a_1870_n1400#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1520 -1060 1521 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "VDD" 200 0 "a_1720_n1450#" 200 0 |
| device msubckt sky130_fd_pr__pfet_01v8_lvt 1070 -1060 1071 -1059 l=200 w=200 "VDD" "a_1000_n1450#" 400 0 "a_1000_n1450#" 200 0 "VDD" 200 0 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.0444459 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.03479 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.513009 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS1" 0.0425883 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "BIAS1" 12.9682 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -7.33879 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0666906 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0225169 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 5.16854 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0335693 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.150892 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS2" 3.63989 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "GND" 8.51595 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "GND" 61.0704 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "GND" 7.50022 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 5.89423 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -14.4815 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0997777 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.0200105 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.457096 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.0669658 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 11.1432 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0558424 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "a_1000_n1450#" 2.17953 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.146126 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.396852 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 22.4133 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.751696 |
| cap "a_1000_n1450#" "GND" 1.12119 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.197571 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "BIAS1" 7.23411 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.289366 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.491866 |
| cap "V_IN" "GND" -0.0125575 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1000_n1450#" 1.70561 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 19.5409 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.19325 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 4.84302 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.749855 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 3.66694 |
| cap "V_RAMP" "GND" -0.393327 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -0.00523592 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.0680415 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS2" 25.2816 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.57794 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0692814 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.104811 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 4.62897 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.345858 |
| cap "a_1100_n1450#" "BIAS2" 0.135131 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "GND" 45.337 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390295 |
| cap "VDD" "a_1000_n1450#" 3.45671 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 9.84859 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.950197 |
| cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 9.37618 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "GND" 3.28022 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.00162157 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 140.454 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.882379 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1000_n1450#" -1.66252 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "BIAS2" 2.29199 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0389779 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -4.11245 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 2.30843 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 9.69594 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.9653 |
| cap "a_1720_n1450#" "BIAS2" 0.869605 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0181359 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS1" 2.59813 |
| cap "BIAS2" "BIAS1" -6.47474 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.54947 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.96578 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0203005 |
| cap "a_1100_n1450#" "BIAS1" -3.19363 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.564882 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "GND" 0.436537 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.55184 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 2.76928 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -5.32566 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0477943 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.175806 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.101903 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.917355 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.322711 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "GND" 80.6403 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.570272 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "GND" 17.5806 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.129069 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0188897 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "BIAS1" 10.5067 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.098269 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 2.10772 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.154608 |
| cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 13.9996 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1000_n1450#" 1.75357 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.0540618 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -6.51667 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -8.5 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "a_1000_n1450#" 0.302044 |
| cap "a_1720_n1450#" "BIAS1" -2.34683 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 1.91648 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 2.8276 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.00752321 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" 0.0831988 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0312458 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" 0.0340443 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.120614 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.552049 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.61029 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 5.77708 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.17505 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 5.02491 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.110951 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -2.61846 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -1.2355 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.80106 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 0.220415 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.19925 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.0677976 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.00636744 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.217583 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0696619 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.237288 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.77653 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "GND" 22.3974 |
| cap "V_RAMP" "a_1000_n1450#" 0.661926 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.942353 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.125115 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "BIAS2" 4.41021 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.00891474 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GND" 1.92687 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.596107 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.00102381 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0125319 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "a_1000_n1450#" 8.30415 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.00245157 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1000_n1450#" 0.329795 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.688566 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.629186 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 8.73114 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 59.479 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0790654 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.102313 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 12.879 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.501082 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.118638 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 0.469721 |
| cap "GND" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 779.113 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 0.155555 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.074722 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0341316 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.19345 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.0642071 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.81619 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.57677 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 5.34318 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -14.4864 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.482716 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "BIAS1" 3.59087 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.041835 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "BIAS2" 2.98823 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0982371 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0763942 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -1.01329 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -2.47637 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "GND" 3.93292 |
| cap "BIAS2" "GND" -0.719256 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 6.11521 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.138026 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "BIAS2" 2.21812 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "a_1000_n1450#" 2.32019 |
| cap "a_1100_n1450#" "GND" 0.933335 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 70.0967 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0201137 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" 5.54019 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1100_n1450#" 1.69597 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.50589 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 1.42777 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 0.306059 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "GND" 6.37832 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "BIAS1" 47.006 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 2.6491 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0262757 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0920516 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.150892 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 10.3286 |
| cap "a_1720_n1450#" "GND" 0.26344 |
| cap "BIAS1" "GND" -8.07555 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.247468 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -27.5754 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -19.1351 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.362795 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS2" -0.175198 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -1.85885e-05 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "BIAS1" 2.09415 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 1.18639 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.00692931 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.146022 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 8.21583 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -19.1462 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 3.74098 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0674668 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "a_1000_n1450#" 3.75935 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.70965 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.168444 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.34856 |
| cap "VDD" "a_1720_n1450#" 0.025356 |
| cap "VDD" "BIAS1" -2.78928 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0344911 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0100182 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -2.62434 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0304196 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.862207 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS1" -41.374 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0162089 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 7.39062 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS2" 2.30404 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS2" 2.33899 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -0.00246803 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "BIAS2" 2.29099 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.116761 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.0237598 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1100_n1450#" 2.33398 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 32.6631 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0567128 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0603412 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0373118 |
| cap "V_IN" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 37.2525 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0282257 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "GND" 0.159192 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 1.37391 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.15011 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 11.779 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "GND" 7.77631 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 0.428653 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1000_n1450#" 1.27401 |
| cap "BIAS2" "a_1000_n1450#" 0.838693 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0135668 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "BIAS1" 2.27139 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "BIAS1" 0.70532 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GND" 0.00114081 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.2854 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "BIAS1" 1.57332 |
| cap "a_1100_n1450#" "a_1000_n1450#" 1.56068 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0498302 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.0265004 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0285071 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.998443 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 5.68138 |
| cap "V_RAMP" "BIAS2" -0.246774 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -27.2336 |
| cap "V_RAMP" "a_1100_n1450#" -0.791557 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "a_1000_n1450#" 1.0895 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 6.17592 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" 3.09335 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0315754 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0577315 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 1.40587 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0342549 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.112021 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "BIAS2" 2.76072 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0949153 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "GND" 0.739008 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS2" 2.94269 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.85005 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 3.95005 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "GND" 63.7695 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.102299 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.175527 |
| cap "BIAS1" "a_1000_n1450#" -1.63506 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 3.61617 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0406008 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.201761 |
| cap "V_IN" "BIAS1" -2.86028 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0427294 |
| cap "V_RAMP" "BIAS1" -2.91147 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "GND" 11.5117 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.6698 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.95805 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 4.16334 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "BIAS1" 4.78955 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 1.17502 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" 9.40824 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS1" 1.32717 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.60121 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.212224 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "BIAS2" 2.70881 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "BIAS2" 2.70432 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.0857416 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -7.66627 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0872739 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0558637 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 0.231168 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.00839695 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" 0.629368 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.33899 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" 3.11382 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "GND" 86.9315 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0577865 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0125795 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -3.28149 |
| cap "a_1100_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 2.90913 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -2.54941e-05 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" 0.261616 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.654152 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "V_RAMP" 1.73898 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -3.82247 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "VDD" 19.875 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.117951 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 56.8164 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00848554 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -9.35 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.00735648 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0157989 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" -4.03532 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0511651 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "BIAS2" 4.91548 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -4.18527 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0271561 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.140948 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "GND" 1.43665 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.00059708 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0985772 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1720_n1450#" 2.16421 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" -0.0346649 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.294791 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0742261 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -8.34399e-06 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0443803 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS2" 3.49732 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -13.6154 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1720_n1450#" 7.38621 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" 4.01716 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "BIAS2" 6.15141 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -22.3664 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" -0.00489773 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.047547 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.210823 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 2.5268 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.97131 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "BIAS2" 5.83287 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GND" 5.89088 |
| cap "BIAS2" "a_1720_n1450#" 3.1891 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -19.1351 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 4.39505 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 10.5615 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -27.2308 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.116135 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1720_n1450#" 10.7348 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GND" 23.4211 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 4.29715 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" -0.0173336 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GND" 0.426263 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.35665 |
| cap "BIAS2" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 5.65142 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 1.73757 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.171491 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" -0.0757928 |
| cap "BIAS2" "GND" 3.7066 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 9.90605 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 2.01058 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.231453 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "BIAS1" -19.6778 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" 0.0669658 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1870_n1400#" 2.68618 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.058652 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0424989 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0472786 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "GND" 392.431 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "GND" 48.0744 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" -0.0346649 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "BIAS1" 3.3369 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "a_1870_n1400#" 2.7431 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.0296036 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.114306 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0104909 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.00773872 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.189766 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "BIAS1" 2.8619 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.0911615 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS2" 2.93592 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 2.6698 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.60401 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" -0.0453581 |
| cap "a_1870_n1400#" "a_1720_n1450#" 0.692513 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 1.56722 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" -0.0173336 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0379485 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "V_RAMP" 0.40325 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" 1.69613 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" -2.65192 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.0781327 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "V_RAMP" 0.335303 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.174367 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0854932 |
| cap "BIAS1" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 3.22682 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "VDD" 4.83863 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.57333 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0480093 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.0794719 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "BIAS2" 7.44046 |
| cap "a_1870_n1400#" "GND" 1.92409 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "VDD" 0.0234468 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0701304 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.0302549 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.102199 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" -0.0457694 |
| cap "VDD" "a_1720_n1450#" 0.109424 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0532087 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "VDD" 3.58915 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 6.56251 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS2" 11.6818 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.000869098 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.00380833 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "BIAS2" 8.36975 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 5.73187 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "BIAS1" 0.794558 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.306017 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1870_n1400#" 0.598216 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 28.7488 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.00115532 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 6.69123 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -2.91378 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0460312 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "a_1720_n1450#" 2.16819 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0281068 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0126324 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -3.67026 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "BIAS2" 7.0193 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "BIAS2" 40.9923 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" -0.303379 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "a_1720_n1450#" -1.45247 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -5.79259 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0291122 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 15.7155 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" -0.0702659 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" -0.0896117 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.737187 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0790691 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "BIAS1" 2.72919 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.0128628 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "GND" 14.3091 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1870_n1400#" 2.64381 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.377527 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" -0.0134903 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -3.64927 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "BIAS1" 4.65534 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" -2.54941e-05 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "a_1870_n1400#" 5.92407 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 1.1668 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.247468 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "GND" 0.671238 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "BIAS1" 4.47709 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -6.51667 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "GND" 5.19872 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0552098 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" -0.0393076 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0390765 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.042945 |
| cap "a_1870_n1400#" "BIAS2" 2.05056 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.516278 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.0831988 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" -0.0347718 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" -0.0880644 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "VDD" 0.749015 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" -0.0628071 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "BIAS1" 3.2089 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "BIAS1" 52.099 |
| cap "GND" "a_1720_n1450#" 1.21244 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" -0.0250056 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "a_1870_n1400#" 7.42581 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 17.5677 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "GND" 3.26588 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" -0.15121 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "V_RAMP" 0.829018 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "VDD" 10.2882 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" -0.042945 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "V_RAMP" 0.67954 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" -0.061489 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" -0.0207214 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0296036 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "VDD" 3.64969 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" -0.022966 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" 0.0220217 |
| cap "GND" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 8.81055 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" -0.0113908 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1720_n1450#" 0.814251 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00189117 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.420848 |
| cap "VDD" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 2.67125 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "V_RAMP" 0.722922 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "a_1000_n1450#" 0.013366 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 9.33004 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "VDD" 0.723246 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "a_1000_n1450#" 0.133141 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.14231 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "VDD" 2.32754 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" 6.37078 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 1.02185 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_1000_n1450#" 1.64654 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "a_1000_n1450#" 0.142085 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.38864 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 1.80899 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "V_RAMP" 0.312353 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.65339 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "VDD" 1.63206 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "VDD" 4.35076 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.00599073 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" 1.02185 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "V_RAMP" 0.00551788 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "a_1000_n1450#" 0.278586 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.0163894 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/storage" "a_1000_n1450#" 0.0959047 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.132345 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 3.86603 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" 0.00102367 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 0.407168 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" 0.805949 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "V_RAMP" 0.814017 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.65339 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "VDD" 2.31577 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.346716 |
| cap "a_1000_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" 0.837499 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "VDD" 1.32252 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "VDD" 2.1185 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.61017 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.187358 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "V_RAMP" 0.720466 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.896146 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "a_1000_n1450#" 0.641382 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/storage" "a_1000_n1450#" 0.00900749 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "VDD" 1.24617 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "VDD" 2.98369 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.307507 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "VDD" 4.08751 |
| cap "VDD" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/storage" 2.82762 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "a_1000_n1450#" 0.915612 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "VDD" 3.07703 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "VDD" 1.81833 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "V_RAMP" 0.694302 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" 0.366288 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000303582 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.00584413 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.499903 |
| cap "GND" "VDD" 3.37587 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" -0.000647137 |
| cap "V_RAMP" "VDD" 0.933804 |
| cap "BIAS1" "VDD" 0.899414 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.131148 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "VDD" 4.4073 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "VDD" 7.7395 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "VDD" 2.26995 |
| cap "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "VDD" 3.75796 |
| cap "a_1720_n1450#" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 0.994081 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.805949 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 1.31635 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "VDD" 2.82886 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 1.02185 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "VDD" 0.679031 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 0.549607 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "a_1720_n1450#" 0.093961 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.279616 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" "VDD" 5.43565 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "VDD" 1.64322 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "VDD" 5.068 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" 0.720466 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.0212796 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/storage" "V_RAMP" 0.178164 |
| cap "BIAS2" "VDD" 7.44072 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "VDD" 4.54657 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.722922 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "V_RAMP" 0.686105 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" 1.02185 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/storage" 0.102015 |
| cap "a_1870_n1400#" "VDD" 6.73852 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.0114952 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "V_RAMP" 0.642682 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" 0.0203746 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" 2.1684e-19 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" "VDD" 1.00785 |
| cap "a_1720_n1450#" "VDD" 5.25775 |
| cap "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/storage" "VDD" 1.94462 |
| cap "V_RAMP" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/storage" 0.312353 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" 0.29663 |
| cap "a_1870_n1400#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" 0.151767 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/WBL" "GRAY_INx3x" -50.5551 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/RBL" "OUTx2x" -44.6832 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/WBL" "GRAY_INx5x" -46.8643 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/VSUBS" "GND" -1219.55 0 0 0 0 0 0 0 0 -34800 -1420 -43200 -860 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -92800 -2820 -220775 -5250 0 0 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/RBL" "OUTx4x" -50.0953 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/WBL" "GRAY_INx0x" -22.9252 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -800 -120 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RWL" "READ" -859.42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4854 -556 0 0 0 0 -106560 -3672 0 0 0 0 0 0 |
| merge "READ" "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RWL" |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RWL" "li_1640_n2140#" |
| merge "li_1640_n2140#" "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RWL" "li_764_n2030#" |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WBL" "GRAY_INx7x" -71.7607 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/RBL" "OUTx6x" -109.381 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4200 -260 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_0/WBL" "GRAY_INx2x" -28.1937 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2400 -200 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_0/WBL" "GRAY_INx4x" -23.9202 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -180 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_0/WBL" "GRAY_INx6x" -29.786 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2000 -180 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/RBL" "OUTx1x" -32.1148 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/RBL" "OUTx7x" -64.9353 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_0/dram_cell_1/RBL" "OUTx5x" -27.0017 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1650 -170 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_1/WBL" "GRAY_INx1x" -44.0615 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_1/dram_array_1/dram_cell_1/WWL" "a_2260_n1450#" -826.075 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -5040 -288 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_1/dram_cell_1/RBL" "OUTx3x" -23.7896 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1350 -150 0 0 0 0 0 0 0 0 |
| merge "8bit_dram_0/4bit_dram_0/dram_array_0/dram_cell_0/RBL" "OUTx0x" -39.444 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3600 -240 0 0 0 0 |
