| commit | f4d92bf2d5dbda8fe5d04d051879691524dcebd0 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Tue Oct 12 15:49:11 2021 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Tue Oct 12 15:49:11 2021 -0400 |
| tree | 68f876891a7484bdfc6d109398c74461ed6d0bfa | |
| parent | 00336fefcbe85ba1859b311b66fa1b68f7d2bf46 [diff] |
Additional corrections to the analog wrapper testbench schematic to properly quote net names with brackets, and to name a net that is referenced in the plot command but hadn't been named in the schematic.
| :exclamation: Important Note |
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| :warning: | Use this sample project for analog user projects. |
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Refer to README for this sample project documentation.