| commit | 3efd3e2ed083bd3dafd91c6fd16fc43e2bcc94d6 | [log] [tgz] |
|---|---|---|
| author | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 07:45:32 2022 -0400 |
| committer | Po-Chun Huang <hpcalex@terpmail.umd.edu> | Thu Jul 14 07:45:32 2022 -0400 |
| tree | e87048ff9fd21e050ac6bf4aaca2df3dad2630d7 | |
| parent | eeb2fe507976a1cdaf10fb06407ae40939d55201 [diff] |
changed readme
This project contains array of various sizes of 1T1R devices and a 1T1R 256x256 ReRAM module for device performance characterization, e.g. I-V, transient, R-ratio, and variations, and ReRAM simulation model verification. The goal is to design a low power ReRAM controller optimized for write/read latency, endurance, and power consumption based on the actual measurement results of sky130 ReRAM devices.
Refer to README for this sample project documentation. ~