Merge pull request #83 from efabless/litex_integration_GL
GL simulation tb updates
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index d151b60..43a4149 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -34,7 +34,7 @@
clean: ${PATTERNS}
for i in ${PATTERNS}; do \
- ( cd $$i && make clean ) ; \
+ ( cd $$i && \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe ) ; \
done
rm -rf *.log
diff --git a/verilog/dv/io_ports/io_ports.c b/verilog/dv/io_ports/io_ports.c
index aa111ef..d204e4a 100644
--- a/verilog/dv/io_ports/io_ports.c
+++ b/verilog/dv/io_ports/io_ports.c
@@ -71,6 +71,5 @@
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
-
}
diff --git a/verilog/dv/io_ports/io_ports_tb.v b/verilog/dv/io_ports/io_ports_tb.v
index 4e526ba..cf66d3f 100644
--- a/verilog/dv/io_ports/io_ports_tb.v
+++ b/verilog/dv/io_ports/io_ports_tb.v
@@ -17,10 +17,6 @@
`timescale 1 ns / 1 ps
-// `include "uprj_netlists.v"
-// `include "caravel_netlists.v"
-// `include "spiflash.v"
-
module io_ports_tb;
reg clock;
reg RSTB;
@@ -35,8 +31,8 @@
assign mprj_io_0 = mprj_io[7:0];
// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
- // assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
- // assign mprj_io[3] = CSB;
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+ // assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -95,7 +91,7 @@
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
- #170000;
+ #300000;
CSB = 1'b0; // CSB can be released
end
diff --git a/verilog/dv/la_test1/la_test1.c b/verilog/dv/la_test1/la_test1.c
index 96b56bd..cad69d1 100644
--- a/verilog/dv/la_test1/la_test1.c
+++ b/verilog/dv/la_test1/la_test1.c
@@ -124,7 +124,7 @@
}
}
print("\n");
- print("Monitor: Test 2 Passed\n\n"); // Makes simulation very long!
+ print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
reg_mprj_datal = 0xAB510000;
}
diff --git a/verilog/dv/la_test1/la_test1_tb.v b/verilog/dv/la_test1/la_test1_tb.v
index 81a4e32..e0fff24 100644
--- a/verilog/dv/la_test1/la_test1_tb.v
+++ b/verilog/dv/la_test1/la_test1_tb.v
@@ -17,11 +17,6 @@
`timescale 1 ns / 1 ps
-// `include "uprj_netlists.v"
-// `include "caravel_netlists.v"
-// `include "spiflash.v"
-// `include "tbuart.v"
-
module la_test1_tb;
reg clock;
reg RSTB;
diff --git a/verilog/dv/la_test2/la_test2_tb.v b/verilog/dv/la_test2/la_test2_tb.v
index 168664b..6ef965d 100644
--- a/verilog/dv/la_test2/la_test2_tb.v
+++ b/verilog/dv/la_test2/la_test2_tb.v
@@ -17,10 +17,6 @@
`timescale 1 ns / 1 ps
-// `include "uprj_netlists.v"
-// `include "caravel_netlists.v"
-// `include "spiflash.v"
-
module la_test2_tb;
reg clock;
reg RSTB;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index 65633bc..d049848 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -34,11 +34,6 @@
uint32_t testval;
- reg_spi_enable = 0;
-
- // reg_spimaster_cs = 0x00000000; // Shut off the housekeeping SPI,
- // so we can use the pins.
-
reg_mprj_datal = 0x00000000;
reg_mprj_datah = 0x00000000;
@@ -57,7 +52,7 @@
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -97,9 +92,9 @@
// Configure LA probes [31:0], [127:64] as inputs to the cpu
// Configure LA probes [63:32] as outputs from the cpu
reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
- reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
- reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
- reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
+ reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+ reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
// Flag start of the test
reg_mprj_datal = 0xAB400000;
@@ -108,7 +103,7 @@
reg_la1_data = 0x00000000;
// Configure LA probes from [63:32] as inputs to disable counter write
- reg_la1_oenb = reg_la1_iena = 0x00000000;
+ reg_la1_oenb = reg_la1_iena = 0x00000000;
reg_mprj_datal = 0xAB410000;
reg_mprj_datah = 0x00000000;
@@ -137,4 +132,3 @@
// Flag end of the test
reg_mprj_datal = 0xAB510000;
}
-
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 1f956a3..68addd0 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -17,18 +17,12 @@
`timescale 1 ns / 1 ps
-// `include "uprj_netlists.v"
-// `include "caravel_netlists.v"
-// `include "spiflash.v"
-// `include "tbuart.v"
-
module mprj_stimulus_tb;
// Signals declaration
reg clock;
reg RSTB;
- reg CSB;
reg power1, power2;
-
+ reg CSB;
wire gpio;
wire [37:0] mprj_io;
wire [15:0] checkbits;
@@ -38,10 +32,7 @@
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
-
- // Force CSB high until simulation is underway
- // Note: The CSB GPIO pin default needs to be set to a pull-up. . .
- assign mprj_io[3] = CSB;
+ assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
always #12.5 clock <= (clock === 1'b0);
@@ -54,11 +45,15 @@
$dumpvars(0, mprj_stimulus_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (70) begin
+ repeat (100) begin
repeat (1000) @(posedge clock);
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Project IO Stimulus (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Project IO Stimulus (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -68,14 +63,12 @@
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
-
- // Values reflect copying user-controlled outputs to memory and back
- // to management-controlled outputs. Note that there is a slight
- // discrepancy in timing when using gate level simulation; either
- // of the specified values is okay.
- wait(checkbits == 16'h198F);
- wait(checkbits == 16'h1DDC);
+ // Values reflect copying user-controlled outputs to memory and back
+ // to management-controlled outputs.
+ wait(checkbits == 16'h1968 || checkbits == 16'h1969); // They're off because the difference between GL and RTL
+ wait(checkbits == 16'h1DCD || checkbits == 16'h1DCE); // They're off because the difference between GL and RTL
+
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
@@ -84,11 +77,12 @@
// Reset Operation
initial begin
+ CSB <= 1'b1;
RSTB <= 1'b0;
- CSB <= 1'b1;
- #1000;
- RSTB <= 1'b1; // Release reset
#2000;
+ RSTB <= 1'b1; // Release reset
+ #1000000;
+ CSB <= 1'b0; // Stop driving CSB
end
initial begin // Power-up sequence
@@ -110,7 +104,7 @@
wire VSS = 1'b0;
caravel uut (
- .vddio (VDD3V3),
+ .vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
@@ -151,4 +145,4 @@
);
endmodule
-`default_nettype wire
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 60529dc..d5c2983 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -17,10 +17,6 @@
`timescale 1 ns / 1 ps
-// `include "uprj_netlists.v"
-// `include "caravel_netlists.v"
-// `include "spiflash.v"
-
module wb_port_tb;
reg clock;
reg RSTB;
@@ -35,7 +31,7 @@
assign checkbits = mprj_io[31:16];
- // assign mprj_io[3] = CSB;
+ assign mprj_io[3] = 1'b1;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
@@ -52,7 +48,7 @@
$dumpvars(0, wb_port_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (50) begin
+ repeat (70) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
@@ -83,7 +79,7 @@
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
- #170000;
+ #100000;
CSB = 1'b0; // CSB can be released
end
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
new file mode 100644
index 0000000..284a97c
--- /dev/null
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -0,0 +1,3 @@
+// Caravel user project includes
+$USER_PROJECT_VERILOG/gl/user_project_wrapper.v
+$USER_PROJECT_VERILOG/gl/user_proj_example.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
new file mode 100644
index 0000000..f5047d5
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -0,0 +1,3 @@
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
new file mode 100644
index 0000000..31ab09b
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -0,0 +1,5 @@
+# Caravel user project includes
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+
+
\ No newline at end of file
