| /root/in_memory_computing_sram/openlane/user_project_wrapper/config.json |
| /root/in_memory_computing_sram/verilog/includes/includes.gl+sdf.caravel_user_project |
| /root/in_memory_computing_sram/verilog/includes/includes.gl.caravel_user_project |
| /root/in_memory_computing_sram/verilog/includes/includes.rtl.caravel_user_project |
| /root/in_memory_computing_sram/verilog/rtl/SRAM_Wrapper_top.v |
| /root/in_memory_computing_sram/verilog/rtl/files/FIFO.v |
| /root/in_memory_computing_sram/verilog/rtl/files/Integrated_bitcell_with_dummy_cells.v |
| /root/in_memory_computing_sram/verilog/rtl/files/SA_OB_mux.v |
| /root/in_memory_computing_sram/verilog/rtl/files/controller_3.v |
| /root/in_memory_computing_sram/verilog/rtl/files/controller_4.v |
| /root/in_memory_computing_sram/verilog/rtl/files/top.v |
| /root/in_memory_computing_sram/verilog/rtl/files/wb_rd_wr_buf.v |
