first_V2
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds new file mode 100644 index 0000000..22909fb --- /dev/null +++ b/gds/user_project_wrapper.gds Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz deleted file mode 100644 index 06dcb34..0000000 --- a/gds/user_project_wrapper.gds.gz +++ /dev/null Binary files differ
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json deleted file mode 100644 index 370d74c..0000000 --- a/openlane/user_proj_example/config.json +++ /dev/null
@@ -1,45 +0,0 @@ -{ - "DESIGN_NAME": "user_proj_example", - "DESIGN_IS_CORE": 0, - "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v"], - "CLOCK_PERIOD": 10, - "CLOCK_PORT": "wb_clk_i", - "CLOCK_NET": "counter.clk", - "FP_SIZING": "absolute", - "DIE_AREA": "0 0 900 600", - "FP_PIN_ORDER_CFG": "dir::pin_order.cfg", - "PL_BASIC_PLACEMENT": 0, - "PL_TARGET_DENSITY": 0.55, - "VDD_NETS": ["vccd1"], - "GND_NETS": ["vssd1"], - "DIODE_INSERTION_STRATEGY": 4, - "RUN_CVC": 1, - "pdk::sky130*": { - "FP_CORE_UTIL": 45, - "RT_MAX_LAYER": "met4", - "scl::sky130_fd_sc_hd": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hdll": { - "CLOCK_PERIOD": 10 - }, - "scl::sky130_fd_sc_hs": { - "CLOCK_PERIOD": 8 - }, - "scl::sky130_fd_sc_ls": { - "CLOCK_PERIOD": 10, - "SYNTH_MAX_FANOUT": 5 - }, - "scl::sky130_fd_sc_ms": { - "CLOCK_PERIOD": 10 - } - }, - "pdk::gf180mcuC": { - "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0", - "CLOCK_PERIOD": 24.0, - "FP_CORE_UTIL": 40, - "RT_MAX_LAYER": "Metal4", - "SYNTH_MAX_FANOUT": 4, - "PL_TARGET_DENSITY": 0.45 - } -} \ No newline at end of file
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg deleted file mode 100644 index 2fda806..0000000 --- a/openlane/user_proj_example/pin_order.cfg +++ /dev/null
@@ -1,10 +0,0 @@ -#BUS_SORT - -#S -wb_.* -wbs_.* -la_.* -irq.* - -#N -io_.*