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sky130
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mpw-007
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slot-024
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af2b669a4e1cc3892bdc8f38686e78a443237a8a
commit
af2b669a4e1cc3892bdc8f38686e78a443237a8a
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author
Deepak42074 <deepakvermamathura@gmail.com>
Sun Dec 04 00:50:02 2022 +0530
committer
Deepak42074 <deepakvermamathura@gmail.com>
Sun Dec 04 00:50:02 2022 +0530
tree
819381cc7e743b04d8efb7d0e031445ad2806587
parent
df65f7392008d16005f089db11d4b79299a51cfc
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first_V2
README.md
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def/user_proj_example.def
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def/user_project_wrapper.def
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docs/Makefile
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docs/environment.yml
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docs/requirements.txt
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docs/source/_static/counter_32.png
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docs/source/_static/empty.png
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docs/source/_static/layout.png
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docs/source/_static/option1.png
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docs/source/_static/option2.png
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docs/source/_static/option3.png
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docs/source/_static/pitch.png
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docs/source/_static/wrapper.png
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docs/source/conf.py
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docs/source/index.rst
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docs/source/quickstart.rst
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gds/Integrated_bitcell_with_dummy_cells.gds
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gds/SRAM_Wrapper_top.gds
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gds/user_proj_example.gds
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lef/Integrated_bitcell_with_dummy_cells.lef
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lef/SRAM_Wrapper_top.lef
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lef/user_proj_example.lef
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lef/user_project_wrapper.lef
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mag/user_proj_example.mag
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mag/user_project_wrapper.mag
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maglef/user_proj_example.mag
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maglef/user_project_wrapper.mag
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signoff/user_proj_example/OPENLANE_VERSION
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signoff/user_proj_example/PDK_SOURCES
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signoff/user_project_wrapper/OPENLANE_VERSION
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signoff/user_project_wrapper/PDK_SOURCES
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signoff/user_project_wrapper/metrics.csv
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spi/lvs/user_proj_example.spice
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spi/lvs/user_project_wrapper.spice
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verilog/dv/Makefile
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verilog/dv/README.md
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verilog/dv/io_ports/Makefile
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verilog/dv/io_ports/io_ports.c
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verilog/dv/io_ports/io_ports_tb.v
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verilog/dv/la_test1/Makefile
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verilog/dv/la_test1/la_test1.c
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verilog/dv/la_test1/la_test1_tb.v
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verilog/dv/la_test2/Makefile
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verilog/dv/la_test2/la_test2.c
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verilog/dv/la_test2/la_test2_tb.v
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verilog/dv/local-install.md
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verilog/dv/mprj_stimulus/Makefile
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verilog/dv/mprj_stimulus/mprj_stimulus.c
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verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
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verilog/dv/wb_port/Makefile
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verilog/dv/wb_port/wb_port.c
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verilog/dv/wb_port/wb_port_tb.v
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verilog/gl/user_proj_example.v
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verilog/gl/user_project_wrapper.nl.v
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verilog/gl/user_project_wrapper.v
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verilog/includes/includes.gl+sdf.caravel_user_project
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verilog/includes/includes.gl.caravel_user_project
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verilog/includes/includes.rtl.caravel_user_project
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verilog/rtl/SRAM_Wrapper_top.v
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verilog/rtl/defines.v
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verilog/rtl/files/FIFO.v
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verilog/rtl/files/Integrated_bitcell_with_dummy_cells.v
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verilog/rtl/files/SA_OB_mux.v
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verilog/rtl/files/controller_3.v
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verilog/rtl/files/controller_4.v
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verilog/rtl/files/top.v
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verilog/rtl/files/wb_rd_wr_buf.v
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verilog/rtl/uprj_netlists.v
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verilog/rtl/user_defines.v
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verilog/rtl/user_project_wrapper.v
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71 files changed
tree: 819381cc7e743b04d8efb7d0e031445ad2806587
.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
signoff/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md
README.md
SRAM IMC
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