leaf openlane config

openlane/leaf_chip/config.tcl

diff --git a/openlane/leaf_chip/config.tcl b/openlane/leaf_chip/config.tcl
new file mode 100755
index 0000000..8ad4333
--- /dev/null
+++ b/openlane/leaf_chip/config.tcl
@@ -0,0 +1,34 @@
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) leaf_chip
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/leaf_chip.v"
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clk"
+# set ::env(CLOCK_NET) "counter.clk"
+set ::env(CLOCK_PERIOD) "20"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 1400 1400"
+
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.15
+
+# set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(RT_MAX_LAYER) {met4}
+
+set ::env(VDD_NETS) [list {vccd1}]
+set ::env(GND_NETS) [list {vssd1}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4 
+set ::env(RUN_CVC) 1

openlane/leaf_chip/pin_order.cfg

diff --git a/openlane/leaf_chip/pin_order.cfg b/openlane/leaf_chip/pin_order.cfg
new file mode 100644
index 0000000..c868ef4
--- /dev/null
+++ b/openlane/leaf_chip/pin_order.cfg
@@ -0,0 +1,7 @@
+#S
+clk
+reset
+
+#N
+rx
+tx
\ No newline at end of file