chip-level static timing analysis update
diff --git a/Makefile b/Makefile index 6f8e5b8..3862fec 100644 --- a/Makefile +++ b/Makefile
@@ -15,23 +15,26 @@ # SPDX-License-Identifier: Apache-2.0 MAKEFLAGS+=--warn-undefined-variables -CARAVEL_ROOT?=$(PWD)/caravel +export CARAVEL_ROOT?=$(PWD)/caravel PRECHECK_ROOT?=${HOME}/mpw_precheck -MCW_ROOT?=$(PWD)/mgmt_core_wrapper +export MCW_ROOT?=$(PWD)/mgmt_core_wrapper SIM?=RTL -export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb -export OPEN_PDKS_COMMIT?=7519dfb04400f224f140749cda44ee7de6f5e095 -export PDK_MAGIC_COMMIT=7d601628e4e05fd17fcb80c3552dacb64e9f6e7b -export OPENLANE_TAG=2022.02.23_02.50.41 -export MISMATCHES_OK=1 -export PDKPATH?=$(PDK_ROOT)/sky130A -export PDK?=sky130A - # Install lite version of caravel, (1): caravel-lite, (0): caravel CARAVEL_LITE?=1 -MPW_TAG ?= mpw-6c +# PDK switch varient +export PDK?=sky130A +#export PDK?=gf180mcuC +export PDKPATH?=$(PDK_ROOT)/$(PDK) + + + +ifeq ($(PDK),sky130A) + SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + MPW_TAG ?= mpw-8c ifeq ($(CARAVEL_LITE),1) CARAVEL_NAME := caravel-lite @@ -43,6 +46,38 @@ CARAVEL_TAG := $(MPW_TAG) endif +endif + +ifeq ($(PDK),sky130B) + SKYWATER_COMMIT=f70d8ca46961ff92719d8870a18a076370b85f6c + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + MPW_TAG ?= mpw-8c + +ifeq ($(CARAVEL_LITE),1) + CARAVEL_NAME := caravel-lite + CARAVEL_REPO := https://github.com/efabless/caravel-lite + CARAVEL_TAG := $(MPW_TAG) +else + CARAVEL_NAME := caravel + CARAVEL_REPO := https://github.com/efabless/caravel + CARAVEL_TAG := $(MPW_TAG) +endif + +endif + +ifeq ($(PDK),gf180mcuC) + + MPW_TAG ?= gfmpw-0b + CARAVEL_NAME := caravel + CARAVEL_REPO := https://github.com/efabless/caravel-gf180mcu + CARAVEL_TAG := $(MPW_TAG) + #OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9 + export OPEN_PDKS_COMMIT?=0059588eebfc704681dc2368bd1d33d96281d10f + export OPENLANE_TAG?=2022.11.19 + +endif + # Include Caravel Makefile Targets .PHONY: % : check-caravel %: @@ -60,16 +95,16 @@ # Install DV setup .PHONY: simenv simenv: - docker pull efabless/dv_setup:latest + docker pull efabless/dv:latest .PHONY: setup -setup: install check-env install_mcw openlane pdk-with-volare +setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts # Openlane blocks=$(shell cd openlane && find * -maxdepth 0 -type d) .PHONY: $(blocks) $(blocks): % : - export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $* + $(MAKE) -C openlane $* dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d) dv-targets-rtl=$(dv_patterns:%=verify-%-rtl) @@ -77,20 +112,21 @@ dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf) TARGET_PATH=$(shell pwd) -verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make" +verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make" dv_base_dependencies=simenv docker_run_verify=\ docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ -e CARAVEL_ROOT=${CARAVEL_ROOT} \ - -e TOOLS=/opt/riscv32i \ + -e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \ -e DESIGNS=$(TARGET_PATH) \ + -e USER_PROJECT_VERILOG=$(TARGET_PATH)/verilog \ -e PDK=$(PDK) \ -e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \ - -e GCC_PREFIX=riscv32-unknown-elf \ + -e CARAVEL_VERILOG_PATH=$(TARGET_PATH)/caravel/verilog \ -e MCW_ROOT=$(MCW_ROOT) \ - -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv_setup:latest \ + -u $$(id -u $$USER):$$(id -g $$USER) efabless/dv:latest \ sh -c $(verify_command) .PHONY: harden @@ -140,6 +176,11 @@ # Install Openlane .PHONY: openlane openlane: + @if [ "$$(realpath $${OPENLANE_ROOT})" = "$$(realpath $$(pwd)/openlane)" ]; then\ + echo "OPENLANE_ROOT is set to '$$(pwd)/openlane' which contains openlane config files"; \ + echo "Please set it to a different directory"; \ + exit 1; \ + fi cd openlane && $(MAKE) openlane #### Not sure if the targets following are of any use @@ -183,10 +224,11 @@ -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \ -v $(PDK_ROOT):$(PDK_ROOT) \ -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \ + -e PDK_PATH=$(PDK_ROOT)/$(PDK) \ -e PDK_ROOT=$(PDK_ROOT) \ -e PDKPATH=$(PDKPATH) \ -u $(shell id -u $(USER)):$(shell id -g $(USER)) \ - efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)" + efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)" @@ -219,3 +261,81 @@ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' +export CUP_ROOT=$(shell pwd) +export TIMING_ROOT?=$(shell pwd)/deps/timing-scripts +export PROJECT_ROOT=$(CUP_ROOT) +timing-scripts-repo=https://github.com/efabless/timing-scripts.git + +$(TIMING_ROOT): + @mkdir -p $(CUP_ROOT)/deps + @git clone $(timing-scripts-repo) $(TIMING_ROOT) + +.PHONY: setup-timing-scripts +setup-timing-scripts: $(TIMING_ROOT) + @( cd $(TIMING_ROOT) && git pull ) + @#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); ) + +./verilog/gl/user_project_wrapper.v: + $(error you don't have $@) + +./env/spef-mapping.tcl: + @echo "run the following:" + @echo "make extract-parasitics" + @echo "make create-spef-mapping" + exit 1 + +.PHONY: create-spef-mapping +create-spef-mapping: ./verilog/gl/user_project_wrapper.v + docker run \ + --rm \ + -u $$(id -u $$USER):$$(id -g $$USER) \ + -v $(PDK_ROOT):$(PDK_ROOT) \ + -v $(CUP_ROOT):$(CUP_ROOT) \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -v $(TIMING_ROOT):$(TIMING_ROOT) \ + -w $(shell pwd) \ + efabless/timing-scripts:latest \ + python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \ + -i ./verilog/gl/user_project_wrapper.v \ + -o ./env/spef-mapping.tcl \ + --pdk-path $(PDK_ROOT)/$(PDK) \ + --macro-parent mprj \ + --project-root "$(CUP_ROOT)" + +.PHONY: extract-parasitics +extract-parasitics: ./verilog/gl/user_project_wrapper.v + docker run \ + --rm \ + -u $$(id -u $$USER):$$(id -g $$USER) \ + -v $(PDK_ROOT):$(PDK_ROOT) \ + -v $(CUP_ROOT):$(CUP_ROOT) \ + -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ + -v $(MCW_ROOT):$(MCW_ROOT) \ + -v $(TIMING_ROOT):$(TIMING_ROOT) \ + -w $(shell pwd) \ + efabless/timing-scripts:latest \ + python3 $(TIMING_ROOT)/scripts/get_macros.py \ + -i ./verilog/gl/user_project_wrapper.v \ + -o ./tmp-macros-list \ + --project-root "$(CUP_ROOT)" \ + --pdk-path $(PDK_ROOT)/$(PDK) + @cat ./tmp-macros-list | cut -d " " -f2 \ + | xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \ + -f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'" + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper + @cat ./tmp-macros-list + @rm ./tmp-macros-list + +.PHONY: caravel-sta +caravel-sta: ./env/spef-mapping.tcl + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast + @$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow + @echo =================================================Summary================================================= + @find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff -name "*-summary.rpt" | head -n1 \ + | xargs tail -n2 | head -n1 + @find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff -name "*-summary.rpt" \ + | xargs -I {} tail -n1 "{}" + @echo ========================================================================================================= + @echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
diff --git a/caravel b/caravel index 192a5b1..1e3103f 160000 --- a/caravel +++ b/caravel
@@ -1 +1 @@ -Subproject commit 192a5b1fe5cd068c3a8a7b30aee8458ca738f73b +Subproject commit 1e3103fd5ffa56f72e2b38e804c9c7bb2738e32a
diff --git a/deps/timing-scripts b/deps/timing-scripts new file mode 160000 index 0000000..72bdbdc --- /dev/null +++ b/deps/timing-scripts
@@ -0,0 +1 @@ +Subproject commit 72bdbdcc7837fa377814a97d3227b570b60dc17d
diff --git a/mgmt_core_wrapper b/mgmt_core_wrapper index ca8f316..453e4cc 160000 --- a/mgmt_core_wrapper +++ b/mgmt_core_wrapper
@@ -1 +1 @@ -Subproject commit ca8f31620b55ef8b10a750a0c570e400e07cd9f8 +Subproject commit 453e4cca7d165db005492cd1a93a3a8aed710e2b