final gds oasis
106 files changed
tree: 80717252258276d49299aeaa24792c3a8802cf95
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. mpw_precheck/
  9. openlane/
  10. sdc/
  11. sdf/
  12. signoff/
  13. spef/
  14. spi/
  15. tapeout/
  16. verilog/
  17. .gitignore
  18. LICENSE
  19. Makefile
  20. README.md
README.md

WARP-V

WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.