| commit | 48a7b14ce82bad2637992a38a0c6c927cbe1567a | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 11:12:41 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 11:12:41 2022 -0800 |
| tree | 80717252258276d49299aeaa24792c3a8802cf95 | |
| parent | ab4419d3cf2667ce8c012a4e8aac94a6344ca4e7 [diff] |
final gds oasis
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.
