| commit | f1113c5f682ce0da598ea9022f4f6be8d6c6fff3 | [log] [tgz] |
|---|---|---|
| author | Ali Imran <59641896+ALI11-2000@users.noreply.github.com> | Mon Dec 05 15:29:42 2022 +0000 |
| committer | Ali Imran <59641896+ALI11-2000@users.noreply.github.com> | Mon Dec 05 15:29:42 2022 +0000 |
| tree | 2a33d16e1ae54e3e8fe22f4ba5cb011bc76ddf8c | |
| parent | 78d60aed9b67196e8c5f104a7a8ab10b1c97f49f [diff] |
Updated Files
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.