commit ee2712b0e8695985fbe9a6f408e4cad9c2b1b052
author Ali Imran <59641896+ALI11-2000@users.noreply.github.com> Sun Aug 14 21:07:56 2022 +0500
committer GitHub <noreply@github.com> Sun Aug 14 21:07:56 2022 +0500
tree 867b91e8a31804dbb552e06b79294c82c704c426
parent f6b317fb1c1988ff04bcbfb7720702d1be4cc1ba

SRAM updaed

verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v

diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index b1f95b0..19337a3 100644
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -33,7 +33,7 @@
       input [NUM_WMASKS-1:0]   wmask0; // write mask

       input [ADDR_WIDTH-1:0]  addr0;

       input [DATA_WIDTH-1:0]  din0;

-      output [DATA_WIDTH-1:0] dout0;

+      output reg [DATA_WIDTH-1:0] dout0;

       input  clk1; // clock

       input   csb1; // active low chip select

       input [ADDR_WIDTH-1:0]  addr1;

@@ -44,7 +44,6 @@
       reg [NUM_WMASKS-1:0]   wmask0_reg;

       reg [ADDR_WIDTH-1:0]  addr0_reg;

       reg [DATA_WIDTH-1:0]  din0_reg;

-      reg [DATA_WIDTH-1:0]  dout0;

     

       // All inputs are registers

       always @(posedge clk0)