|author||Ali Imran <59641896+ALI11firstname.lastname@example.org>||Mon Dec 05 15:29:59 2022 +0000|
|committer||Ali Imran <59641896+ALI11email@example.com>||Mon Dec 05 15:29:59 2022 +0000|
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.