| commit | aa11ae4ad72ef24c71c83445270aa7cc854bd4e4 | [log] [tgz] |
|---|---|---|
| author | Ali Imran <59641896+ALI11-2000@users.noreply.github.com> | Sun Aug 28 23:14:08 2022 +0500 |
| committer | GitHub <noreply@github.com> | Sun Aug 28 23:14:08 2022 +0500 |
| tree | 8158056ab96b9af8b1b8fead229bd6179d97731e | |
| parent | f2d682bf481bc07efa189ad4b0e1bef05959deb6 [diff] |
Update README.md
WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging “transaction-level design” methodology. It can implement a single-stage, low-power microcontroller or a mid-range 7-stage CPU. Even the instruction-set architectures (ISAs) is configurable. WARP-V is an evolving library of CPU components as well as various compositions of them. It is driven by a community interested in transforming the silicon industry through open-source hardware and revolutionary design methodology.