commit	5e5d9ffc8cded36d4147e42122b199b1be6085fb	[log] [tgz]
author	Ali Imran <ali1120001@outlook.com>	Sun Aug 28 19:25:45 2022 +0500
committer	Ali Imran <ali1120001@outlook.com>	Sun Aug 28 19:25:45 2022 +0500
tree	a3aac1b9839e044a10d005a8545d398ae7098e48
parent	84d90d6d07ead30f36ccf349929713a892f150b4 [diff]

Processor Design Updated

Makefile[diff]
def/user_project_wrapper.def[diff]
gds/user_project_wrapper.gds[diff]
lef/user_project_wrapper.lef[diff]
mag/user_project_wrapper.mag[diff]
maglef/user_project_wrapper.mag[diff]
sdc/user_project_wrapper.sdc[diff]
sdf/user_project_wrapper.sdf[diff]
signoff/user_project_wrapper/metrics.csv[diff]
spef/user_project_wrapper.spef[diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/io_ports/Makefile[Deleted - diff]
verilog/dv/io_ports/io_ports.c[Deleted - diff]
verilog/dv/io_ports/io_ports_tb.v[Deleted - diff]
verilog/dv/la_test1/Makefile[Deleted - diff]
verilog/dv/la_test1/la_test1.c[Deleted - diff]
verilog/dv/la_test1/la_test1_tb.v[Deleted - diff]
verilog/dv/la_test2/Makefile[Deleted - diff]
verilog/dv/la_test2/la_test2.c[Deleted - diff]
verilog/dv/la_test2/la_test2_tb.v[Deleted - diff]
verilog/dv/mprj_stimulus/Makefile[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Deleted - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Deleted - diff]
verilog/dv/wb_port/wb_port.c[diff]
verilog/dv/wb_port/wb_port_tb.v[diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/rtl/user_project_wrapper.v[diff]

27 files changed

tree: a3aac1b9839e044a10d005a8545d398ae7098e48

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.