SRAM Updated
diff --git a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
index 78fd6bc..79721fb 100644
--- a/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
+++ b/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8.v
@@ -98,7 +98,7 @@
always @ (negedge clk0)
begin : MEM_READ0
if (!csb0_reg && web0_reg)
- dout0 <= #(DELAY) mem[addr0_reg];
+ dout0 <= mem[addr0_reg];
end
// Memory Read Block Port 1
@@ -106,7 +106,7 @@
always @ (negedge clk1)
begin : MEM_READ1
if (!csb1_reg)
- dout1 <= #(DELAY) mem[addr1_reg];
+ dout1 <= mem[addr1_reg];
end
initial begin
